xref: /freebsd/contrib/ofed/libirdma/irdma_uk.c (revision 643ac419fafba89f5adda0e0ea75b538727453fb)
1 /*-
2  * SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB
3  *
4  * Copyright (c) 2015 - 2022 Intel Corporation
5  *
6  * This software is available to you under a choice of one of two
7  * licenses.  You may choose to be licensed under the terms of the GNU
8  * General Public License (GPL) Version 2, available from the file
9  * COPYING in the main directory of this source tree, or the
10  * OpenFabrics.org BSD license below:
11  *
12  *   Redistribution and use in source and binary forms, with or
13  *   without modification, are permitted provided that the following
14  *   conditions are met:
15  *
16  *    - Redistributions of source code must retain the above
17  *	copyright notice, this list of conditions and the following
18  *	disclaimer.
19  *
20  *    - Redistributions in binary form must reproduce the above
21  *	copyright notice, this list of conditions and the following
22  *	disclaimer in the documentation and/or other materials
23  *	provided with the distribution.
24  *
25  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
26  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
27  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
28  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
29  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
30  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
31  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
32  * SOFTWARE.
33  */
34 /*$FreeBSD$*/
35 
36 #include "osdep.h"
37 #include "irdma_defs.h"
38 #include "irdma_user.h"
39 #include "irdma.h"
40 
41 /**
42  * irdma_set_fragment - set fragment in wqe
43  * @wqe: wqe for setting fragment
44  * @offset: offset value
45  * @sge: sge length and stag
46  * @valid: The wqe valid
47  */
48 static void
49 irdma_set_fragment(__le64 * wqe, u32 offset, struct irdma_sge *sge,
50 		   u8 valid)
51 {
52 	if (sge) {
53 		set_64bit_val(wqe, offset,
54 			      LS_64(sge->tag_off, IRDMAQPSQ_FRAG_TO));
55 		set_64bit_val(wqe, offset + IRDMA_BYTE_8,
56 			      LS_64(valid, IRDMAQPSQ_VALID) |
57 			      LS_64(sge->len, IRDMAQPSQ_FRAG_LEN) |
58 			      LS_64(sge->stag, IRDMAQPSQ_FRAG_STAG));
59 	} else {
60 		set_64bit_val(wqe, offset, 0);
61 		set_64bit_val(wqe, offset + IRDMA_BYTE_8,
62 			      LS_64(valid, IRDMAQPSQ_VALID));
63 	}
64 }
65 
66 /**
67  * irdma_set_fragment_gen_1 - set fragment in wqe
68  * @wqe: wqe for setting fragment
69  * @offset: offset value
70  * @sge: sge length and stag
71  * @valid: wqe valid flag
72  */
73 static void
74 irdma_set_fragment_gen_1(__le64 * wqe, u32 offset,
75 			 struct irdma_sge *sge, u8 valid)
76 {
77 	if (sge) {
78 		set_64bit_val(wqe, offset,
79 			      LS_64(sge->tag_off, IRDMAQPSQ_FRAG_TO));
80 		set_64bit_val(wqe, offset + IRDMA_BYTE_8,
81 			      LS_64(sge->len, IRDMAQPSQ_GEN1_FRAG_LEN) |
82 			      LS_64(sge->stag, IRDMAQPSQ_GEN1_FRAG_STAG));
83 	} else {
84 		set_64bit_val(wqe, offset, 0);
85 		set_64bit_val(wqe, offset + IRDMA_BYTE_8, 0);
86 	}
87 }
88 
89 /**
90  * irdma_nop_1 - insert a NOP wqe
91  * @qp: hw qp ptr
92  */
93 static int
94 irdma_nop_1(struct irdma_qp_uk *qp)
95 {
96 	u64 hdr;
97 	__le64 *wqe;
98 	u32 wqe_idx;
99 	bool signaled = false;
100 
101 	if (!qp->sq_ring.head)
102 		return EINVAL;
103 
104 	wqe_idx = IRDMA_RING_CURRENT_HEAD(qp->sq_ring);
105 	wqe = qp->sq_base[wqe_idx].elem;
106 
107 	qp->sq_wrtrk_array[wqe_idx].quanta = IRDMA_QP_WQE_MIN_QUANTA;
108 
109 	set_64bit_val(wqe, IRDMA_BYTE_0, 0);
110 	set_64bit_val(wqe, IRDMA_BYTE_8, 0);
111 	set_64bit_val(wqe, IRDMA_BYTE_16, 0);
112 
113 	hdr = LS_64(IRDMAQP_OP_NOP, IRDMAQPSQ_OPCODE) |
114 	    LS_64(signaled, IRDMAQPSQ_SIGCOMPL) |
115 	    LS_64(qp->swqe_polarity, IRDMAQPSQ_VALID);
116 
117 	/* make sure WQE is written before valid bit is set */
118 	udma_to_device_barrier();
119 
120 	set_64bit_val(wqe, IRDMA_BYTE_24, hdr);
121 
122 	return 0;
123 }
124 
125 /**
126  * irdma_clr_wqes - clear next 128 sq entries
127  * @qp: hw qp ptr
128  * @qp_wqe_idx: wqe_idx
129  */
130 void
131 irdma_clr_wqes(struct irdma_qp_uk *qp, u32 qp_wqe_idx)
132 {
133 	__le64 *wqe;
134 	u32 wqe_idx;
135 
136 	if (!(qp_wqe_idx & 0x7F)) {
137 		wqe_idx = (qp_wqe_idx + 128) % qp->sq_ring.size;
138 		wqe = qp->sq_base[wqe_idx].elem;
139 		if (wqe_idx)
140 			memset(wqe, qp->swqe_polarity ? 0 : 0xFF, 0x1000);
141 		else
142 			memset(wqe, qp->swqe_polarity ? 0xFF : 0, 0x1000);
143 	}
144 }
145 
146 /**
147  * irdma_uk_qp_post_wr - ring doorbell
148  * @qp: hw qp ptr
149  */
150 void
151 irdma_uk_qp_post_wr(struct irdma_qp_uk *qp)
152 {
153 	u64 temp;
154 	u32 hw_sq_tail;
155 	u32 sw_sq_head;
156 
157 	/* valid bit is written and loads completed before reading shadow */
158 	atomic_thread_fence(memory_order_seq_cst);
159 
160 	/* read the doorbell shadow area */
161 	get_64bit_val(qp->shadow_area, IRDMA_BYTE_0, &temp);
162 
163 	hw_sq_tail = (u32)RS_64(temp, IRDMA_QP_DBSA_HW_SQ_TAIL);
164 	sw_sq_head = IRDMA_RING_CURRENT_HEAD(qp->sq_ring);
165 	if (sw_sq_head != qp->initial_ring.head) {
166 		if (qp->push_dropped) {
167 			db_wr32(qp->qp_id, qp->wqe_alloc_db);
168 			qp->push_dropped = false;
169 		} else if (sw_sq_head != hw_sq_tail) {
170 			if (sw_sq_head > qp->initial_ring.head) {
171 				if (hw_sq_tail >= qp->initial_ring.head &&
172 				    hw_sq_tail < sw_sq_head)
173 					db_wr32(qp->qp_id, qp->wqe_alloc_db);
174 			} else {
175 				if (hw_sq_tail >= qp->initial_ring.head ||
176 				    hw_sq_tail < sw_sq_head)
177 					db_wr32(qp->qp_id, qp->wqe_alloc_db);
178 			}
179 		}
180 	}
181 
182 	qp->initial_ring.head = qp->sq_ring.head;
183 }
184 
185 /**
186  * irdma_qp_ring_push_db -  ring qp doorbell
187  * @qp: hw qp ptr
188  * @wqe_idx: wqe index
189  */
190 static void
191 irdma_qp_ring_push_db(struct irdma_qp_uk *qp, u32 wqe_idx)
192 {
193 	set_32bit_val(qp->push_db, 0,
194 		      LS_32(wqe_idx >> 3, IRDMA_WQEALLOC_WQE_DESC_INDEX) | qp->qp_id);
195 	qp->initial_ring.head = qp->sq_ring.head;
196 	qp->push_mode = true;
197 	qp->push_dropped = false;
198 }
199 
200 void
201 irdma_qp_push_wqe(struct irdma_qp_uk *qp, __le64 * wqe, u16 quanta,
202 		  u32 wqe_idx, bool post_sq)
203 {
204 	__le64 *push;
205 
206 	if (IRDMA_RING_CURRENT_HEAD(qp->initial_ring) !=
207 	    IRDMA_RING_CURRENT_TAIL(qp->sq_ring) &&
208 	    !qp->push_mode) {
209 		if (post_sq)
210 			irdma_uk_qp_post_wr(qp);
211 	} else {
212 		push = (__le64 *) ((uintptr_t)qp->push_wqe +
213 				   (wqe_idx & 0x7) * 0x20);
214 		irdma_memcpy(push, wqe, quanta * IRDMA_QP_WQE_MIN_SIZE);
215 		irdma_qp_ring_push_db(qp, wqe_idx);
216 	}
217 }
218 
219 /**
220  * irdma_qp_get_next_send_wqe - pad with NOP if needed, return where next WR should go
221  * @qp: hw qp ptr
222  * @wqe_idx: return wqe index
223  * @quanta: size of WR in quanta
224  * @total_size: size of WR in bytes
225  * @info: info on WR
226  */
227 __le64 *
228 irdma_qp_get_next_send_wqe(struct irdma_qp_uk *qp, u32 *wqe_idx,
229 			   u16 quanta, u32 total_size,
230 			   struct irdma_post_sq_info *info)
231 {
232 	__le64 *wqe;
233 	__le64 *wqe_0 = NULL;
234 	u32 nop_wqe_idx;
235 	u16 avail_quanta;
236 	u16 i;
237 
238 	avail_quanta = qp->uk_attrs->max_hw_sq_chunk -
239 	    (IRDMA_RING_CURRENT_HEAD(qp->sq_ring) %
240 	     qp->uk_attrs->max_hw_sq_chunk);
241 	if (quanta <= avail_quanta) {
242 		/* WR fits in current chunk */
243 		if (quanta > IRDMA_SQ_RING_FREE_QUANTA(qp->sq_ring))
244 			return NULL;
245 	} else {
246 		/* Need to pad with NOP */
247 		if (quanta + avail_quanta >
248 		    IRDMA_SQ_RING_FREE_QUANTA(qp->sq_ring))
249 			return NULL;
250 
251 		nop_wqe_idx = IRDMA_RING_CURRENT_HEAD(qp->sq_ring);
252 		for (i = 0; i < avail_quanta; i++) {
253 			irdma_nop_1(qp);
254 			IRDMA_RING_MOVE_HEAD_NOCHECK(qp->sq_ring);
255 		}
256 		if (qp->push_db && info->push_wqe)
257 			irdma_qp_push_wqe(qp, qp->sq_base[nop_wqe_idx].elem,
258 					  avail_quanta, nop_wqe_idx, true);
259 	}
260 
261 	*wqe_idx = IRDMA_RING_CURRENT_HEAD(qp->sq_ring);
262 	if (!*wqe_idx)
263 		qp->swqe_polarity = !qp->swqe_polarity;
264 
265 	IRDMA_RING_MOVE_HEAD_BY_COUNT_NOCHECK(qp->sq_ring, quanta);
266 
267 	wqe = qp->sq_base[*wqe_idx].elem;
268 	if (qp->uk_attrs->hw_rev == IRDMA_GEN_1 && quanta == 1 &&
269 	    (IRDMA_RING_CURRENT_HEAD(qp->sq_ring) & 1)) {
270 		wqe_0 = qp->sq_base[IRDMA_RING_CURRENT_HEAD(qp->sq_ring)].elem;
271 		wqe_0[3] = htole64(LS_64(!qp->swqe_polarity, IRDMAQPSQ_VALID));
272 	}
273 	qp->sq_wrtrk_array[*wqe_idx].wrid = info->wr_id;
274 	qp->sq_wrtrk_array[*wqe_idx].wr_len = total_size;
275 	qp->sq_wrtrk_array[*wqe_idx].quanta = quanta;
276 	qp->sq_wrtrk_array[*wqe_idx].signaled = info->signaled;
277 
278 	return wqe;
279 }
280 
281 /**
282  * irdma_qp_get_next_recv_wqe - get next qp's rcv wqe
283  * @qp: hw qp ptr
284  * @wqe_idx: return wqe index
285  */
286 __le64 *
287 irdma_qp_get_next_recv_wqe(struct irdma_qp_uk *qp, u32 *wqe_idx)
288 {
289 	__le64 *wqe;
290 	int ret_code;
291 
292 	if (IRDMA_RING_FULL_ERR(qp->rq_ring))
293 		return NULL;
294 
295 	IRDMA_ATOMIC_RING_MOVE_HEAD(qp->rq_ring, *wqe_idx, ret_code);
296 	if (ret_code)
297 		return NULL;
298 
299 	if (!*wqe_idx)
300 		qp->rwqe_polarity = !qp->rwqe_polarity;
301 	/* rq_wqe_size_multiplier is no of 32 byte quanta in one rq wqe */
302 	wqe = qp->rq_base[*wqe_idx * qp->rq_wqe_size_multiplier].elem;
303 
304 	return wqe;
305 }
306 
307 /**
308  * irdma_uk_rdma_write - rdma write operation
309  * @qp: hw qp ptr
310  * @info: post sq information
311  * @post_sq: flag to post sq
312  */
313 int
314 irdma_uk_rdma_write(struct irdma_qp_uk *qp, struct irdma_post_sq_info *info,
315 		    bool post_sq)
316 {
317 	u64 hdr;
318 	__le64 *wqe;
319 	struct irdma_rdma_write *op_info;
320 	u32 i, wqe_idx;
321 	u32 total_size = 0, byte_off;
322 	int ret_code;
323 	u32 frag_cnt, addl_frag_cnt;
324 	bool read_fence = false;
325 	u16 quanta;
326 
327 	info->push_wqe = qp->push_db ? true : false;
328 
329 	op_info = &info->op.rdma_write;
330 	if (op_info->num_lo_sges > qp->max_sq_frag_cnt)
331 		return EINVAL;
332 
333 	for (i = 0; i < op_info->num_lo_sges; i++)
334 		total_size += op_info->lo_sg_list[i].len;
335 
336 	read_fence |= info->read_fence;
337 
338 	if (info->imm_data_valid)
339 		frag_cnt = op_info->num_lo_sges + 1;
340 	else
341 		frag_cnt = op_info->num_lo_sges;
342 	addl_frag_cnt = frag_cnt > 1 ? (frag_cnt - 1) : 0;
343 	ret_code = irdma_fragcnt_to_quanta_sq(frag_cnt, &quanta);
344 	if (ret_code)
345 		return ret_code;
346 
347 	wqe = irdma_qp_get_next_send_wqe(qp, &wqe_idx, quanta, total_size,
348 					 info);
349 	if (!wqe)
350 		return ENOSPC;
351 
352 	irdma_clr_wqes(qp, wqe_idx);
353 
354 	qp->sq_wrtrk_array[wqe_idx].signaled = info->signaled;
355 	set_64bit_val(wqe, IRDMA_BYTE_16,
356 		      LS_64(op_info->rem_addr.tag_off, IRDMAQPSQ_FRAG_TO));
357 
358 	if (info->imm_data_valid) {
359 		set_64bit_val(wqe, IRDMA_BYTE_0,
360 			      LS_64(info->imm_data, IRDMAQPSQ_IMMDATA));
361 		i = 0;
362 	} else {
363 		qp->wqe_ops.iw_set_fragment(wqe, IRDMA_BYTE_0,
364 					    op_info->lo_sg_list,
365 					    qp->swqe_polarity);
366 		i = 1;
367 	}
368 
369 	for (byte_off = IRDMA_BYTE_32; i < op_info->num_lo_sges; i++) {
370 		qp->wqe_ops.iw_set_fragment(wqe, byte_off,
371 					    &op_info->lo_sg_list[i],
372 					    qp->swqe_polarity);
373 		byte_off += 16;
374 	}
375 
376 	/* if not an odd number set valid bit in next fragment */
377 	if (qp->uk_attrs->hw_rev >= IRDMA_GEN_2 && !(frag_cnt & 0x01) &&
378 	    frag_cnt) {
379 		qp->wqe_ops.iw_set_fragment(wqe, byte_off, NULL,
380 					    qp->swqe_polarity);
381 		if (qp->uk_attrs->hw_rev == IRDMA_GEN_2)
382 			++addl_frag_cnt;
383 	}
384 
385 	if (!op_info->rem_addr.stag && !total_size)
386 		op_info->rem_addr.stag = 0x1234;
387 	hdr = LS_64(op_info->rem_addr.stag, IRDMAQPSQ_REMSTAG) |
388 	    LS_64(info->op_type, IRDMAQPSQ_OPCODE) |
389 	    LS_64((info->imm_data_valid ? 1 : 0), IRDMAQPSQ_IMMDATAFLAG) |
390 	    LS_64((info->report_rtt ? 1 : 0), IRDMAQPSQ_REPORTRTT) |
391 	    LS_64(addl_frag_cnt, IRDMAQPSQ_ADDFRAGCNT) |
392 	    LS_64((info->push_wqe ? 1 : 0), IRDMAQPSQ_PUSHWQE) |
393 	    LS_64(read_fence, IRDMAQPSQ_READFENCE) |
394 	    LS_64(info->local_fence, IRDMAQPSQ_LOCALFENCE) |
395 	    LS_64(info->signaled, IRDMAQPSQ_SIGCOMPL) |
396 	    LS_64(qp->swqe_polarity, IRDMAQPSQ_VALID);
397 
398 	udma_to_device_barrier();	/* make sure WQE is populated before valid bit is set */
399 
400 	set_64bit_val(wqe, IRDMA_BYTE_24, hdr);
401 	if (info->push_wqe) {
402 		irdma_qp_push_wqe(qp, wqe, quanta, wqe_idx, post_sq);
403 	} else {
404 		if (post_sq)
405 			irdma_uk_qp_post_wr(qp);
406 	}
407 
408 	return 0;
409 }
410 
411 /**
412  * irdma_uk_rdma_read - rdma read command
413  * @qp: hw qp ptr
414  * @info: post sq information
415  * @inv_stag: flag for inv_stag
416  * @post_sq: flag to post sq
417  */
418 int
419 irdma_uk_rdma_read(struct irdma_qp_uk *qp, struct irdma_post_sq_info *info,
420 		   bool inv_stag, bool post_sq)
421 {
422 	struct irdma_rdma_read *op_info;
423 	int ret_code;
424 	u32 i, byte_off, total_size = 0;
425 	bool local_fence = false;
426 	bool ord_fence = false;
427 	u32 addl_frag_cnt;
428 	__le64 *wqe;
429 	u32 wqe_idx;
430 	u16 quanta;
431 	u64 hdr;
432 
433 	info->push_wqe = qp->push_db ? true : false;
434 
435 	op_info = &info->op.rdma_read;
436 	if (qp->max_sq_frag_cnt < op_info->num_lo_sges)
437 		return EINVAL;
438 
439 	for (i = 0; i < op_info->num_lo_sges; i++)
440 		total_size += op_info->lo_sg_list[i].len;
441 
442 	ret_code = irdma_fragcnt_to_quanta_sq(op_info->num_lo_sges, &quanta);
443 	if (ret_code)
444 		return ret_code;
445 
446 	wqe = irdma_qp_get_next_send_wqe(qp, &wqe_idx, quanta, total_size,
447 					 info);
448 	if (!wqe)
449 		return ENOSPC;
450 
451 	if (qp->rd_fence_rate && (qp->ord_cnt++ == qp->rd_fence_rate)) {
452 		ord_fence = true;
453 		qp->ord_cnt = 0;
454 	}
455 
456 	irdma_clr_wqes(qp, wqe_idx);
457 
458 	qp->sq_wrtrk_array[wqe_idx].signaled = info->signaled;
459 	addl_frag_cnt = op_info->num_lo_sges > 1 ?
460 	    (op_info->num_lo_sges - 1) : 0;
461 	local_fence |= info->local_fence;
462 
463 	qp->wqe_ops.iw_set_fragment(wqe, IRDMA_BYTE_0, op_info->lo_sg_list,
464 				    qp->swqe_polarity);
465 	for (i = 1, byte_off = IRDMA_BYTE_32; i < op_info->num_lo_sges; ++i) {
466 		qp->wqe_ops.iw_set_fragment(wqe, byte_off,
467 					    &op_info->lo_sg_list[i],
468 					    qp->swqe_polarity);
469 		byte_off += IRDMA_BYTE_16;
470 	}
471 
472 	/* if not an odd number set valid bit in next fragment */
473 	if (qp->uk_attrs->hw_rev >= IRDMA_GEN_2 &&
474 	    !(op_info->num_lo_sges & 0x01) && op_info->num_lo_sges) {
475 		qp->wqe_ops.iw_set_fragment(wqe, byte_off, NULL,
476 					    qp->swqe_polarity);
477 		if (qp->uk_attrs->hw_rev == IRDMA_GEN_2)
478 			++addl_frag_cnt;
479 	}
480 	set_64bit_val(wqe, IRDMA_BYTE_16,
481 		      LS_64(op_info->rem_addr.tag_off, IRDMAQPSQ_FRAG_TO));
482 	hdr = LS_64(op_info->rem_addr.stag, IRDMAQPSQ_REMSTAG) |
483 	    LS_64((info->report_rtt ? 1 : 0), IRDMAQPSQ_REPORTRTT) |
484 	    LS_64(addl_frag_cnt, IRDMAQPSQ_ADDFRAGCNT) |
485 	    LS_64((inv_stag ? IRDMAQP_OP_RDMA_READ_LOC_INV : IRDMAQP_OP_RDMA_READ),
486 		  IRDMAQPSQ_OPCODE) |
487 	    LS_64((info->push_wqe ? 1 : 0), IRDMAQPSQ_PUSHWQE) |
488 	    LS_64(info->read_fence || qp->force_fence || ord_fence ? 1 : 0,
489 		  IRDMAQPSQ_READFENCE) |
490 	    LS_64(local_fence, IRDMAQPSQ_LOCALFENCE) |
491 	    LS_64(info->signaled, IRDMAQPSQ_SIGCOMPL) |
492 	    LS_64(qp->swqe_polarity, IRDMAQPSQ_VALID);
493 
494 	udma_to_device_barrier();	/* make sure WQE is populated before valid bit is set */
495 
496 	set_64bit_val(wqe, IRDMA_BYTE_24, hdr);
497 	if (info->push_wqe) {
498 		irdma_qp_push_wqe(qp, wqe, quanta, wqe_idx, post_sq);
499 	} else {
500 		if (post_sq)
501 			irdma_uk_qp_post_wr(qp);
502 	}
503 
504 	return 0;
505 }
506 
507 /**
508  * irdma_uk_send - rdma send command
509  * @qp: hw qp ptr
510  * @info: post sq information
511  * @post_sq: flag to post sq
512  */
513 int
514 irdma_uk_send(struct irdma_qp_uk *qp, struct irdma_post_sq_info *info,
515 	      bool post_sq)
516 {
517 	__le64 *wqe;
518 	struct irdma_post_send *op_info;
519 	u64 hdr;
520 	u32 i, wqe_idx, total_size = 0, byte_off;
521 	int ret_code;
522 	u32 frag_cnt, addl_frag_cnt;
523 	bool read_fence = false;
524 	u16 quanta;
525 
526 	info->push_wqe = qp->push_db ? true : false;
527 
528 	op_info = &info->op.send;
529 	if (qp->max_sq_frag_cnt < op_info->num_sges)
530 		return EINVAL;
531 
532 	for (i = 0; i < op_info->num_sges; i++)
533 		total_size += op_info->sg_list[i].len;
534 
535 	if (info->imm_data_valid)
536 		frag_cnt = op_info->num_sges + 1;
537 	else
538 		frag_cnt = op_info->num_sges;
539 	ret_code = irdma_fragcnt_to_quanta_sq(frag_cnt, &quanta);
540 	if (ret_code)
541 		return ret_code;
542 
543 	wqe = irdma_qp_get_next_send_wqe(qp, &wqe_idx, quanta, total_size,
544 					 info);
545 	if (!wqe)
546 		return ENOSPC;
547 
548 	irdma_clr_wqes(qp, wqe_idx);
549 
550 	read_fence |= info->read_fence;
551 	addl_frag_cnt = frag_cnt > 1 ? (frag_cnt - 1) : 0;
552 	if (info->imm_data_valid) {
553 		set_64bit_val(wqe, IRDMA_BYTE_0,
554 			      LS_64(info->imm_data, IRDMAQPSQ_IMMDATA));
555 		i = 0;
556 	} else {
557 		qp->wqe_ops.iw_set_fragment(wqe, IRDMA_BYTE_0, op_info->sg_list,
558 					    qp->swqe_polarity);
559 		i = 1;
560 	}
561 
562 	for (byte_off = IRDMA_BYTE_32; i < op_info->num_sges; i++) {
563 		qp->wqe_ops.iw_set_fragment(wqe, byte_off, &op_info->sg_list[i],
564 					    qp->swqe_polarity);
565 		byte_off += IRDMA_BYTE_16;
566 	}
567 
568 	/* if not an odd number set valid bit in next fragment */
569 	if (qp->uk_attrs->hw_rev >= IRDMA_GEN_2 && !(frag_cnt & 0x01) &&
570 	    frag_cnt) {
571 		qp->wqe_ops.iw_set_fragment(wqe, byte_off, NULL,
572 					    qp->swqe_polarity);
573 		if (qp->uk_attrs->hw_rev == IRDMA_GEN_2)
574 			++addl_frag_cnt;
575 	}
576 
577 	set_64bit_val(wqe, IRDMA_BYTE_16,
578 		      LS_64(op_info->qkey, IRDMAQPSQ_DESTQKEY) |
579 		      LS_64(op_info->dest_qp, IRDMAQPSQ_DESTQPN));
580 	hdr = LS_64(info->stag_to_inv, IRDMAQPSQ_REMSTAG) |
581 	    LS_64(op_info->ah_id, IRDMAQPSQ_AHID) |
582 	    LS_64((info->imm_data_valid ? 1 : 0), IRDMAQPSQ_IMMDATAFLAG) |
583 	    LS_64((info->report_rtt ? 1 : 0), IRDMAQPSQ_REPORTRTT) |
584 	    LS_64(info->op_type, IRDMAQPSQ_OPCODE) |
585 	    LS_64(addl_frag_cnt, IRDMAQPSQ_ADDFRAGCNT) |
586 	    LS_64((info->push_wqe ? 1 : 0), IRDMAQPSQ_PUSHWQE) |
587 	    LS_64(read_fence, IRDMAQPSQ_READFENCE) |
588 	    LS_64(info->local_fence, IRDMAQPSQ_LOCALFENCE) |
589 	    LS_64(info->signaled, IRDMAQPSQ_SIGCOMPL) |
590 	    LS_64(info->udp_hdr, IRDMAQPSQ_UDPHEADER) |
591 	    LS_64(info->l4len, IRDMAQPSQ_L4LEN) |
592 	    LS_64(qp->swqe_polarity, IRDMAQPSQ_VALID);
593 
594 	udma_to_device_barrier();	/* make sure WQE is populated before valid bit is set */
595 
596 	set_64bit_val(wqe, IRDMA_BYTE_24, hdr);
597 	if (info->push_wqe) {
598 		irdma_qp_push_wqe(qp, wqe, quanta, wqe_idx, post_sq);
599 	} else {
600 		if (post_sq)
601 			irdma_uk_qp_post_wr(qp);
602 	}
603 
604 	return 0;
605 }
606 
607 /**
608  * irdma_set_mw_bind_wqe_gen_1 - set mw bind wqe
609  * @wqe: wqe for setting fragment
610  * @op_info: info for setting bind wqe values
611  */
612 static void
613 irdma_set_mw_bind_wqe_gen_1(__le64 * wqe,
614 			    struct irdma_bind_window *op_info)
615 {
616 	set_64bit_val(wqe, IRDMA_BYTE_0, (uintptr_t)op_info->va);
617 	set_64bit_val(wqe, IRDMA_BYTE_8,
618 		      LS_64(op_info->mw_stag, IRDMAQPSQ_PARENTMRSTAG) |
619 		      LS_64(op_info->mr_stag, IRDMAQPSQ_MWSTAG));
620 	set_64bit_val(wqe, IRDMA_BYTE_16, op_info->bind_len);
621 }
622 
623 /**
624  * irdma_copy_inline_data_gen_1 - Copy inline data to wqe
625  * @dest: pointer to wqe
626  * @src: pointer to inline data
627  * @len: length of inline data to copy
628  * @polarity: compatibility parameter
629  */
630 static void
631 irdma_copy_inline_data_gen_1(u8 *dest, u8 *src, u32 len,
632 			     u8 polarity)
633 {
634 	if (len <= IRDMA_BYTE_16) {
635 		irdma_memcpy(dest, src, len);
636 	} else {
637 		irdma_memcpy(dest, src, IRDMA_BYTE_16);
638 		src += IRDMA_BYTE_16;
639 		dest = dest + IRDMA_BYTE_32;
640 		irdma_memcpy(dest, src, len - IRDMA_BYTE_16);
641 	}
642 }
643 
644 /**
645  * irdma_inline_data_size_to_quanta_gen_1 - based on inline data, quanta
646  * @data_size: data size for inline
647  *
648  * Gets the quanta based on inline and immediate data.
649  */
650 static inline u16 irdma_inline_data_size_to_quanta_gen_1(u32 data_size) {
651 	return data_size <= 16 ? IRDMA_QP_WQE_MIN_QUANTA : 2;
652 }
653 
654 /**
655  * irdma_set_mw_bind_wqe - set mw bind in wqe
656  * @wqe: wqe for setting mw bind
657  * @op_info: info for setting wqe values
658  */
659 static void
660 irdma_set_mw_bind_wqe(__le64 * wqe,
661 		      struct irdma_bind_window *op_info)
662 {
663 	set_64bit_val(wqe, IRDMA_BYTE_0, (uintptr_t)op_info->va);
664 	set_64bit_val(wqe, IRDMA_BYTE_8,
665 		      LS_64(op_info->mr_stag, IRDMAQPSQ_PARENTMRSTAG) |
666 		      LS_64(op_info->mw_stag, IRDMAQPSQ_MWSTAG));
667 	set_64bit_val(wqe, IRDMA_BYTE_16, op_info->bind_len);
668 }
669 
670 /**
671  * irdma_copy_inline_data - Copy inline data to wqe
672  * @dest: pointer to wqe
673  * @src: pointer to inline data
674  * @len: length of inline data to copy
675  * @polarity: polarity of wqe valid bit
676  */
677 static void
678 irdma_copy_inline_data(u8 *dest, u8 *src, u32 len, u8 polarity)
679 {
680 	u8 inline_valid = polarity << IRDMA_INLINE_VALID_S;
681 	u32 copy_size;
682 
683 	dest += IRDMA_BYTE_8;
684 	if (len <= IRDMA_BYTE_8) {
685 		irdma_memcpy(dest, src, len);
686 		return;
687 	}
688 
689 	*((u64 *)dest) = *((u64 *)src);
690 	len -= IRDMA_BYTE_8;
691 	src += IRDMA_BYTE_8;
692 	dest += IRDMA_BYTE_24;	/* point to additional 32 byte quanta */
693 
694 	while (len) {
695 		copy_size = len < 31 ? len : 31;
696 		irdma_memcpy(dest, src, copy_size);
697 		*(dest + 31) = inline_valid;
698 		len -= copy_size;
699 		dest += IRDMA_BYTE_32;
700 		src += copy_size;
701 	}
702 }
703 
704 /**
705  * irdma_inline_data_size_to_quanta - based on inline data, quanta
706  * @data_size: data size for inline
707  *
708  * Gets the quanta based on inline and immediate data.
709  */
710 static u16 irdma_inline_data_size_to_quanta(u32 data_size) {
711 	if (data_size <= 8)
712 		return IRDMA_QP_WQE_MIN_QUANTA;
713 	else if (data_size <= 39)
714 		return 2;
715 	else if (data_size <= 70)
716 		return 3;
717 	else if (data_size <= 101)
718 		return 4;
719 	else if (data_size <= 132)
720 		return 5;
721 	else if (data_size <= 163)
722 		return 6;
723 	else if (data_size <= 194)
724 		return 7;
725 	else
726 		return 8;
727 }
728 
729 /**
730  * irdma_uk_inline_rdma_write - inline rdma write operation
731  * @qp: hw qp ptr
732  * @info: post sq information
733  * @post_sq: flag to post sq
734  */
735 int
736 irdma_uk_inline_rdma_write(struct irdma_qp_uk *qp,
737 			   struct irdma_post_sq_info *info, bool post_sq)
738 {
739 	__le64 *wqe;
740 	struct irdma_inline_rdma_write *op_info;
741 	u64 hdr = 0;
742 	u32 wqe_idx;
743 	bool read_fence = false;
744 	u16 quanta;
745 
746 	info->push_wqe = qp->push_db ? true : false;
747 	op_info = &info->op.inline_rdma_write;
748 
749 	if (op_info->len > qp->max_inline_data)
750 		return EINVAL;
751 
752 	quanta = qp->wqe_ops.iw_inline_data_size_to_quanta(op_info->len);
753 	wqe = irdma_qp_get_next_send_wqe(qp, &wqe_idx, quanta, op_info->len,
754 					 info);
755 	if (!wqe)
756 		return ENOSPC;
757 
758 	irdma_clr_wqes(qp, wqe_idx);
759 
760 	qp->sq_wrtrk_array[wqe_idx].signaled = info->signaled;
761 	read_fence |= info->read_fence;
762 	set_64bit_val(wqe, IRDMA_BYTE_16,
763 		      LS_64(op_info->rem_addr.tag_off, IRDMAQPSQ_FRAG_TO));
764 
765 	hdr = LS_64(op_info->rem_addr.stag, IRDMAQPSQ_REMSTAG) |
766 	    LS_64(info->op_type, IRDMAQPSQ_OPCODE) |
767 	    LS_64(op_info->len, IRDMAQPSQ_INLINEDATALEN) |
768 	    LS_64(info->report_rtt ? 1 : 0, IRDMAQPSQ_REPORTRTT) |
769 	    LS_64(1, IRDMAQPSQ_INLINEDATAFLAG) |
770 	    LS_64(info->imm_data_valid ? 1 : 0, IRDMAQPSQ_IMMDATAFLAG) |
771 	    LS_64(info->push_wqe ? 1 : 0, IRDMAQPSQ_PUSHWQE) |
772 	    LS_64(read_fence, IRDMAQPSQ_READFENCE) |
773 	    LS_64(info->local_fence, IRDMAQPSQ_LOCALFENCE) |
774 	    LS_64(info->signaled, IRDMAQPSQ_SIGCOMPL) |
775 	    LS_64(qp->swqe_polarity, IRDMAQPSQ_VALID);
776 
777 	if (info->imm_data_valid)
778 		set_64bit_val(wqe, IRDMA_BYTE_0,
779 			      LS_64(info->imm_data, IRDMAQPSQ_IMMDATA));
780 
781 	qp->wqe_ops.iw_copy_inline_data((u8 *)wqe, op_info->data, op_info->len,
782 					qp->swqe_polarity);
783 	udma_to_device_barrier();	/* make sure WQE is populated before valid bit is set */
784 
785 	set_64bit_val(wqe, IRDMA_BYTE_24, hdr);
786 
787 	if (info->push_wqe) {
788 		irdma_qp_push_wqe(qp, wqe, quanta, wqe_idx, post_sq);
789 	} else {
790 		if (post_sq)
791 			irdma_uk_qp_post_wr(qp);
792 	}
793 
794 	return 0;
795 }
796 
797 /**
798  * irdma_uk_inline_send - inline send operation
799  * @qp: hw qp ptr
800  * @info: post sq information
801  * @post_sq: flag to post sq
802  */
803 int
804 irdma_uk_inline_send(struct irdma_qp_uk *qp,
805 		     struct irdma_post_sq_info *info, bool post_sq)
806 {
807 	__le64 *wqe;
808 	struct irdma_post_inline_send *op_info;
809 	u64 hdr;
810 	u32 wqe_idx;
811 	bool read_fence = false;
812 	u16 quanta;
813 
814 	info->push_wqe = qp->push_db ? true : false;
815 	op_info = &info->op.inline_send;
816 
817 	if (op_info->len > qp->max_inline_data)
818 		return EINVAL;
819 
820 	quanta = qp->wqe_ops.iw_inline_data_size_to_quanta(op_info->len);
821 	wqe = irdma_qp_get_next_send_wqe(qp, &wqe_idx, quanta, op_info->len,
822 					 info);
823 	if (!wqe)
824 		return ENOSPC;
825 
826 	irdma_clr_wqes(qp, wqe_idx);
827 
828 	set_64bit_val(wqe, IRDMA_BYTE_16,
829 		      LS_64(op_info->qkey, IRDMAQPSQ_DESTQKEY) |
830 		      LS_64(op_info->dest_qp, IRDMAQPSQ_DESTQPN));
831 
832 	read_fence |= info->read_fence;
833 	hdr = LS_64(info->stag_to_inv, IRDMAQPSQ_REMSTAG) |
834 	    LS_64(op_info->ah_id, IRDMAQPSQ_AHID) |
835 	    LS_64(info->op_type, IRDMAQPSQ_OPCODE) |
836 	    LS_64(op_info->len, IRDMAQPSQ_INLINEDATALEN) |
837 	    LS_64((info->imm_data_valid ? 1 : 0), IRDMAQPSQ_IMMDATAFLAG) |
838 	    LS_64((info->report_rtt ? 1 : 0), IRDMAQPSQ_REPORTRTT) |
839 	    LS_64(1, IRDMAQPSQ_INLINEDATAFLAG) |
840 	    LS_64((info->push_wqe ? 1 : 0), IRDMAQPSQ_PUSHWQE) |
841 	    LS_64(read_fence, IRDMAQPSQ_READFENCE) |
842 	    LS_64(info->local_fence, IRDMAQPSQ_LOCALFENCE) |
843 	    LS_64(info->signaled, IRDMAQPSQ_SIGCOMPL) |
844 	    LS_64(info->udp_hdr, IRDMAQPSQ_UDPHEADER) |
845 	    LS_64(info->l4len, IRDMAQPSQ_L4LEN) |
846 	    LS_64(qp->swqe_polarity, IRDMAQPSQ_VALID);
847 
848 	if (info->imm_data_valid)
849 		set_64bit_val(wqe, IRDMA_BYTE_0,
850 			      LS_64(info->imm_data, IRDMAQPSQ_IMMDATA));
851 	qp->wqe_ops.iw_copy_inline_data((u8 *)wqe, op_info->data, op_info->len,
852 					qp->swqe_polarity);
853 
854 	udma_to_device_barrier();	/* make sure WQE is populated before valid bit is set */
855 
856 	set_64bit_val(wqe, IRDMA_BYTE_24, hdr);
857 
858 	if (info->push_wqe) {
859 		irdma_qp_push_wqe(qp, wqe, quanta, wqe_idx, post_sq);
860 	} else {
861 		if (post_sq)
862 			irdma_uk_qp_post_wr(qp);
863 	}
864 
865 	return 0;
866 }
867 
868 /**
869  * irdma_uk_stag_local_invalidate - stag invalidate operation
870  * @qp: hw qp ptr
871  * @info: post sq information
872  * @post_sq: flag to post sq
873  */
874 int
875 irdma_uk_stag_local_invalidate(struct irdma_qp_uk *qp,
876 			       struct irdma_post_sq_info *info,
877 			       bool post_sq)
878 {
879 	__le64 *wqe;
880 	struct irdma_inv_local_stag *op_info;
881 	u64 hdr;
882 	u32 wqe_idx;
883 	bool local_fence = false;
884 	struct irdma_sge sge = {0};
885 
886 	info->push_wqe = qp->push_db ? true : false;
887 	op_info = &info->op.inv_local_stag;
888 	local_fence = info->local_fence;
889 
890 	wqe = irdma_qp_get_next_send_wqe(qp, &wqe_idx, IRDMA_QP_WQE_MIN_QUANTA,
891 					 0, info);
892 	if (!wqe)
893 		return ENOSPC;
894 
895 	irdma_clr_wqes(qp, wqe_idx);
896 
897 	sge.stag = op_info->target_stag;
898 	qp->wqe_ops.iw_set_fragment(wqe, IRDMA_BYTE_0, &sge, 0);
899 
900 	set_64bit_val(wqe, IRDMA_BYTE_16, 0);
901 
902 	hdr = LS_64(IRDMA_OP_TYPE_INV_STAG, IRDMAQPSQ_OPCODE) |
903 	    LS_64((info->push_wqe ? 1 : 0), IRDMAQPSQ_PUSHWQE) |
904 	    LS_64(info->read_fence, IRDMAQPSQ_READFENCE) |
905 	    LS_64(local_fence, IRDMAQPSQ_LOCALFENCE) |
906 	    LS_64(info->signaled, IRDMAQPSQ_SIGCOMPL) |
907 	    LS_64(qp->swqe_polarity, IRDMAQPSQ_VALID);
908 
909 	udma_to_device_barrier();	/* make sure WQE is populated before valid bit is set */
910 
911 	set_64bit_val(wqe, IRDMA_BYTE_24, hdr);
912 
913 	if (info->push_wqe) {
914 		irdma_qp_push_wqe(qp, wqe, IRDMA_QP_WQE_MIN_QUANTA, wqe_idx,
915 				  post_sq);
916 	} else {
917 		if (post_sq)
918 			irdma_uk_qp_post_wr(qp);
919 	}
920 
921 	return 0;
922 }
923 
924 /**
925  * irdma_uk_mw_bind - bind Memory Window
926  * @qp: hw qp ptr
927  * @info: post sq information
928  * @post_sq: flag to post sq
929  */
930 int
931 irdma_uk_mw_bind(struct irdma_qp_uk *qp, struct irdma_post_sq_info *info,
932 		 bool post_sq)
933 {
934 	__le64 *wqe;
935 	struct irdma_bind_window *op_info;
936 	u64 hdr;
937 	u32 wqe_idx;
938 	bool local_fence;
939 
940 	info->push_wqe = qp->push_db ? true : false;
941 	op_info = &info->op.bind_window;
942 	local_fence = info->local_fence;
943 
944 	wqe = irdma_qp_get_next_send_wqe(qp, &wqe_idx, IRDMA_QP_WQE_MIN_QUANTA,
945 					 0, info);
946 	if (!wqe)
947 		return ENOSPC;
948 
949 	irdma_clr_wqes(qp, wqe_idx);
950 
951 	qp->wqe_ops.iw_set_mw_bind_wqe(wqe, op_info);
952 
953 	hdr = LS_64(IRDMA_OP_TYPE_BIND_MW, IRDMAQPSQ_OPCODE) |
954 	    LS_64(((op_info->ena_reads << 2) | (op_info->ena_writes << 3)),
955 		  IRDMAQPSQ_STAGRIGHTS) |
956 	    LS_64((op_info->addressing_type == IRDMA_ADDR_TYPE_VA_BASED ? 1 : 0),
957 		  IRDMAQPSQ_VABASEDTO) |
958 	    LS_64((op_info->mem_window_type_1 ? 1 : 0),
959 		  IRDMAQPSQ_MEMWINDOWTYPE) |
960 	    LS_64((info->push_wqe ? 1 : 0), IRDMAQPSQ_PUSHWQE) |
961 	    LS_64(info->read_fence, IRDMAQPSQ_READFENCE) |
962 	    LS_64(local_fence, IRDMAQPSQ_LOCALFENCE) |
963 	    LS_64(info->signaled, IRDMAQPSQ_SIGCOMPL) |
964 	    LS_64(qp->swqe_polarity, IRDMAQPSQ_VALID);
965 
966 	udma_to_device_barrier();	/* make sure WQE is populated before valid bit is set */
967 
968 	set_64bit_val(wqe, IRDMA_BYTE_24, hdr);
969 
970 	if (info->push_wqe) {
971 		irdma_qp_push_wqe(qp, wqe, IRDMA_QP_WQE_MIN_QUANTA, wqe_idx,
972 				  post_sq);
973 	} else {
974 		if (post_sq)
975 			irdma_uk_qp_post_wr(qp);
976 	}
977 
978 	return 0;
979 }
980 
981 /**
982  * irdma_uk_post_receive - post receive wqe
983  * @qp: hw qp ptr
984  * @info: post rq information
985  */
986 int
987 irdma_uk_post_receive(struct irdma_qp_uk *qp,
988 		      struct irdma_post_rq_info *info)
989 {
990 	u32 wqe_idx, i, byte_off;
991 	u32 addl_frag_cnt;
992 	__le64 *wqe;
993 	u64 hdr;
994 
995 	if (qp->max_rq_frag_cnt < info->num_sges)
996 		return EINVAL;
997 
998 	wqe = irdma_qp_get_next_recv_wqe(qp, &wqe_idx);
999 	if (!wqe)
1000 		return ENOSPC;
1001 
1002 	qp->rq_wrid_array[wqe_idx] = info->wr_id;
1003 	addl_frag_cnt = info->num_sges > 1 ? (info->num_sges - 1) : 0;
1004 	qp->wqe_ops.iw_set_fragment(wqe, IRDMA_BYTE_0, info->sg_list,
1005 				    qp->rwqe_polarity);
1006 
1007 	for (i = 1, byte_off = IRDMA_BYTE_32; i < info->num_sges; i++) {
1008 		qp->wqe_ops.iw_set_fragment(wqe, byte_off, &info->sg_list[i],
1009 					    qp->rwqe_polarity);
1010 		byte_off += 16;
1011 	}
1012 
1013 	/* if not an odd number set valid bit in next fragment */
1014 	if (qp->uk_attrs->hw_rev >= IRDMA_GEN_2 && !(info->num_sges & 0x01) &&
1015 	    info->num_sges) {
1016 		qp->wqe_ops.iw_set_fragment(wqe, byte_off, NULL,
1017 					    qp->rwqe_polarity);
1018 		if (qp->uk_attrs->hw_rev == IRDMA_GEN_2)
1019 			++addl_frag_cnt;
1020 	}
1021 
1022 	set_64bit_val(wqe, IRDMA_BYTE_16, 0);
1023 	hdr = LS_64(addl_frag_cnt, IRDMAQPSQ_ADDFRAGCNT) |
1024 	    LS_64(qp->rwqe_polarity, IRDMAQPSQ_VALID);
1025 
1026 	udma_to_device_barrier();	/* make sure WQE is populated before valid bit is set */
1027 
1028 	set_64bit_val(wqe, IRDMA_BYTE_24, hdr);
1029 
1030 	return 0;
1031 }
1032 
1033 /**
1034  * irdma_uk_cq_resize - reset the cq buffer info
1035  * @cq: cq to resize
1036  * @cq_base: new cq buffer addr
1037  * @cq_size: number of cqes
1038  */
1039 void
1040 irdma_uk_cq_resize(struct irdma_cq_uk *cq, void *cq_base, int cq_size)
1041 {
1042 	cq->cq_base = cq_base;
1043 	cq->cq_size = cq_size;
1044 	IRDMA_RING_INIT(cq->cq_ring, cq->cq_size);
1045 	cq->polarity = 1;
1046 }
1047 
1048 /**
1049  * irdma_uk_cq_set_resized_cnt - record the count of the resized buffers
1050  * @cq: cq to resize
1051  * @cq_cnt: the count of the resized cq buffers
1052  */
1053 void
1054 irdma_uk_cq_set_resized_cnt(struct irdma_cq_uk *cq, u16 cq_cnt)
1055 {
1056 	u64 temp_val;
1057 	u16 sw_cq_sel;
1058 	u8 arm_next_se;
1059 	u8 arm_next;
1060 	u8 arm_seq_num;
1061 
1062 	get_64bit_val(cq->shadow_area, 32, &temp_val);
1063 
1064 	sw_cq_sel = (u16)RS_64(temp_val, IRDMA_CQ_DBSA_SW_CQ_SELECT);
1065 	sw_cq_sel += cq_cnt;
1066 
1067 	arm_seq_num = (u8)RS_64(temp_val, IRDMA_CQ_DBSA_ARM_SEQ_NUM);
1068 	arm_next_se = (u8)RS_64(temp_val, IRDMA_CQ_DBSA_ARM_NEXT_SE);
1069 	arm_next = (u8)RS_64(temp_val, IRDMA_CQ_DBSA_ARM_NEXT);
1070 
1071 	temp_val = LS_64(arm_seq_num, IRDMA_CQ_DBSA_ARM_SEQ_NUM) |
1072 	    LS_64(sw_cq_sel, IRDMA_CQ_DBSA_SW_CQ_SELECT) |
1073 	    LS_64(arm_next_se, IRDMA_CQ_DBSA_ARM_NEXT_SE) |
1074 	    LS_64(arm_next, IRDMA_CQ_DBSA_ARM_NEXT);
1075 
1076 	set_64bit_val(cq->shadow_area, 32, temp_val);
1077 }
1078 
1079 /**
1080  * irdma_uk_cq_request_notification - cq notification request (door bell)
1081  * @cq: hw cq
1082  * @cq_notify: notification type
1083  */
1084 void
1085 irdma_uk_cq_request_notification(struct irdma_cq_uk *cq,
1086 				 enum irdma_cmpl_notify cq_notify)
1087 {
1088 	u64 temp_val;
1089 	u16 sw_cq_sel;
1090 	u8 arm_next_se = 0;
1091 	u8 arm_next = 0;
1092 	u8 arm_seq_num;
1093 
1094 	cq->armed = true;
1095 	get_64bit_val(cq->shadow_area, IRDMA_BYTE_32, &temp_val);
1096 	arm_seq_num = (u8)RS_64(temp_val, IRDMA_CQ_DBSA_ARM_SEQ_NUM);
1097 	arm_seq_num++;
1098 	sw_cq_sel = (u16)RS_64(temp_val, IRDMA_CQ_DBSA_SW_CQ_SELECT);
1099 	arm_next_se = (u8)RS_64(temp_val, IRDMA_CQ_DBSA_ARM_NEXT_SE);
1100 	arm_next_se |= 1;
1101 	if (cq_notify == IRDMA_CQ_COMPL_EVENT)
1102 		arm_next = 1;
1103 	temp_val = LS_64(arm_seq_num, IRDMA_CQ_DBSA_ARM_SEQ_NUM) |
1104 	    LS_64(sw_cq_sel, IRDMA_CQ_DBSA_SW_CQ_SELECT) |
1105 	    LS_64(arm_next_se, IRDMA_CQ_DBSA_ARM_NEXT_SE) |
1106 	    LS_64(arm_next, IRDMA_CQ_DBSA_ARM_NEXT);
1107 
1108 	set_64bit_val(cq->shadow_area, IRDMA_BYTE_32, temp_val);
1109 
1110 	udma_to_device_barrier();	/* make sure WQE is populated before valid bit is set */
1111 
1112 	db_wr32(cq->cq_id, cq->cqe_alloc_db);
1113 }
1114 
1115 static void
1116 irdma_copy_quanta(__le64 * dst, __le64 * src, u32 offset, bool flip,
1117 		  bool barrier)
1118 {
1119 	__le64 val;
1120 
1121 	get_64bit_val(src, offset, &val);
1122 	set_64bit_val(dst, offset, val);
1123 
1124 	get_64bit_val(src, offset + 8, &val);
1125 	if (flip)
1126 		val ^= IRDMAQPSQ_VALID_M;
1127 	set_64bit_val(dst, offset + 8, val);
1128 
1129 	get_64bit_val(src, offset + 24, &val);
1130 	if (flip)
1131 		val ^= IRDMAQPSQ_VALID_M;
1132 	if (barrier)
1133 		udma_to_device_barrier();	/* make sure WQE is populated before valid bit is set */
1134 	set_64bit_val(dst, offset + 24, val);
1135 }
1136 
1137 static void
1138 irdma_copy_wqe(__le64 * dst, __le64 * src, u8 wqe_quanta,
1139 	       bool flip_polarity)
1140 {
1141 	u32 offset;
1142 
1143 	offset = 32;
1144 	while (--wqe_quanta) {
1145 		irdma_copy_quanta(dst, src, offset, flip_polarity, false);
1146 		offset += 32;
1147 	}
1148 
1149 	irdma_copy_quanta(dst, src, 0, flip_polarity, true);
1150 }
1151 
1152 static void
1153 irdma_repost_rq_wqes(struct irdma_qp_uk *qp, u32 start_idx,
1154 		     u32 end_idx)
1155 {
1156 	__le64 *dst_wqe, *src_wqe;
1157 	u32 wqe_idx;
1158 	u8 wqe_quanta = qp->rq_wqe_size_multiplier;
1159 	bool flip_polarity;
1160 	u64 val;
1161 
1162 	libirdma_debug("reposting_wqes: from start_idx=%d to end_idx = %d\n", start_idx, end_idx);
1163 	pthread_spin_lock(qp->lock);
1164 	while (start_idx != end_idx) {
1165 		IRDMA_RING_SET_TAIL(qp->rq_ring, start_idx + 1);
1166 		src_wqe = qp->rq_base[start_idx * qp->rq_wqe_size_multiplier].elem;
1167 		dst_wqe = irdma_qp_get_next_recv_wqe(qp, &wqe_idx);
1168 
1169 		/* Check to see if polarity has changed */
1170 		get_64bit_val(src_wqe, 24, &val);
1171 		if (RS_64(val, IRDMAQPSQ_VALID) != qp->rwqe_polarity)
1172 			flip_polarity = true;
1173 		else
1174 			flip_polarity = false;
1175 
1176 		qp->rq_wrid_array[wqe_idx] = qp->rq_wrid_array[start_idx];
1177 		irdma_copy_wqe(dst_wqe, src_wqe, wqe_quanta, flip_polarity);
1178 
1179 		start_idx = (start_idx + 1) % qp->rq_size;
1180 	}
1181 
1182 	pthread_spin_unlock(qp->lock);
1183 }
1184 
1185 static int
1186 irdma_check_rq_cqe(struct irdma_qp_uk *qp, u32 *array_idx)
1187 {
1188 	u32 exp_idx = (qp->last_rx_cmpl_idx + 1) % qp->rq_size;
1189 
1190 	if (*array_idx != exp_idx) {
1191 		if (qp->uk_attrs->feature_flags & IRDMA_FEATURE_RELAX_RQ_ORDER) {
1192 			irdma_repost_rq_wqes(qp, exp_idx, *array_idx);
1193 			qp->last_rx_cmpl_idx = *array_idx;
1194 
1195 			return 0;
1196 		}
1197 
1198 		*array_idx = exp_idx;
1199 		qp->last_rx_cmpl_idx = exp_idx;
1200 
1201 		return -1;
1202 	}
1203 
1204 	qp->last_rx_cmpl_idx = *array_idx;
1205 
1206 	return 0;
1207 }
1208 
1209 /**
1210  * irdma_skip_duplicate_flush_cmpl - check last cmpl and update wqe if needed
1211  *
1212  * @ring: sq/rq ring
1213  * @flush_seen: information if flush for specific ring was already seen
1214  * @comp_status: completion status
1215  * @wqe_idx: new value of WQE index returned if there is more work on ring
1216  */
1217 static inline int
1218 irdma_skip_duplicate_flush_cmpl(struct irdma_ring ring, u8 flush_seen,
1219 				enum irdma_cmpl_status comp_status,
1220 				u32 *wqe_idx)
1221 {
1222 	if (flush_seen) {
1223 		if (IRDMA_RING_MORE_WORK(ring))
1224 			*wqe_idx = ring.tail;
1225 		else
1226 			return ENOENT;
1227 	}
1228 
1229 	return 0;
1230 }
1231 
1232 /**
1233  * irdma_uk_cq_poll_cmpl - get cq completion info
1234  * @cq: hw cq
1235  * @info: cq poll information returned
1236  */
1237 int
1238 irdma_uk_cq_poll_cmpl(struct irdma_cq_uk *cq,
1239 		      struct irdma_cq_poll_info *info)
1240 {
1241 	u64 comp_ctx, qword0, qword2, qword3;
1242 	__le64 *cqe;
1243 	struct irdma_qp_uk *qp;
1244 	struct irdma_ring *pring = NULL;
1245 	u32 wqe_idx, q_type;
1246 	int ret_code;
1247 	bool move_cq_head = true;
1248 	u8 polarity;
1249 	bool ext_valid;
1250 	__le64 *ext_cqe;
1251 
1252 	if (cq->avoid_mem_cflct)
1253 		cqe = IRDMA_GET_CURRENT_EXTENDED_CQ_ELEM(cq);
1254 	else
1255 		cqe = IRDMA_GET_CURRENT_CQ_ELEM(cq);
1256 
1257 	get_64bit_val(cqe, IRDMA_BYTE_24, &qword3);
1258 	polarity = (u8)RS_64(qword3, IRDMA_CQ_VALID);
1259 	if (polarity != cq->polarity)
1260 		return ENOENT;
1261 
1262 	/* Ensure CQE contents are read after valid bit is checked */
1263 	udma_from_device_barrier();
1264 
1265 	ext_valid = (bool)RS_64(qword3, IRDMA_CQ_EXTCQE);
1266 	if (ext_valid) {
1267 		u64 qword6, qword7;
1268 		u32 peek_head;
1269 
1270 		if (cq->avoid_mem_cflct) {
1271 			ext_cqe = (__le64 *) ((u8 *)cqe + 32);
1272 			get_64bit_val(ext_cqe, IRDMA_BYTE_24, &qword7);
1273 			polarity = (u8)RS_64(qword7, IRDMA_CQ_VALID);
1274 		} else {
1275 			peek_head = (cq->cq_ring.head + 1) % cq->cq_ring.size;
1276 			ext_cqe = cq->cq_base[peek_head].buf;
1277 			get_64bit_val(ext_cqe, IRDMA_BYTE_24, &qword7);
1278 			polarity = (u8)RS_64(qword7, IRDMA_CQ_VALID);
1279 			if (!peek_head)
1280 				polarity ^= 1;
1281 		}
1282 		if (polarity != cq->polarity)
1283 			return ENOENT;
1284 
1285 		/* Ensure ext CQE contents are read after ext valid bit is checked */
1286 		udma_from_device_barrier();
1287 
1288 		info->imm_valid = (bool)RS_64(qword7, IRDMA_CQ_IMMVALID);
1289 		if (info->imm_valid) {
1290 			u64 qword4;
1291 
1292 			get_64bit_val(ext_cqe, IRDMA_BYTE_0, &qword4);
1293 			info->imm_data = (u32)RS_64(qword4, IRDMA_CQ_IMMDATALOW32);
1294 		}
1295 		info->ud_smac_valid = (bool)RS_64(qword7, IRDMA_CQ_UDSMACVALID);
1296 		info->ud_vlan_valid = (bool)RS_64(qword7, IRDMA_CQ_UDVLANVALID);
1297 		if (info->ud_smac_valid || info->ud_vlan_valid) {
1298 			get_64bit_val(ext_cqe, IRDMA_BYTE_16, &qword6);
1299 			if (info->ud_vlan_valid)
1300 				info->ud_vlan = (u16)RS_64(qword6, IRDMA_CQ_UDVLAN);
1301 			if (info->ud_smac_valid) {
1302 				info->ud_smac[5] = qword6 & 0xFF;
1303 				info->ud_smac[4] = (qword6 >> 8) & 0xFF;
1304 				info->ud_smac[3] = (qword6 >> 16) & 0xFF;
1305 				info->ud_smac[2] = (qword6 >> 24) & 0xFF;
1306 				info->ud_smac[1] = (qword6 >> 32) & 0xFF;
1307 				info->ud_smac[0] = (qword6 >> 40) & 0xFF;
1308 			}
1309 		}
1310 	} else {
1311 		info->imm_valid = false;
1312 		info->ud_smac_valid = false;
1313 		info->ud_vlan_valid = false;
1314 	}
1315 
1316 	q_type = (u8)RS_64(qword3, IRDMA_CQ_SQ);
1317 	info->error = (bool)RS_64(qword3, IRDMA_CQ_ERROR);
1318 	info->push_dropped = (bool)RS_64(qword3, IRDMACQ_PSHDROP);
1319 	info->ipv4 = (bool)RS_64(qword3, IRDMACQ_IPV4);
1320 	if (info->error) {
1321 		info->major_err = RS_64(qword3, IRDMA_CQ_MAJERR);
1322 		info->minor_err = RS_64(qword3, IRDMA_CQ_MINERR);
1323 		if (info->major_err == IRDMA_FLUSH_MAJOR_ERR) {
1324 			info->comp_status = IRDMA_COMPL_STATUS_FLUSHED;
1325 			/* Set the min error to standard flush error code for remaining cqes */
1326 			if (info->minor_err != FLUSH_GENERAL_ERR) {
1327 				qword3 &= ~IRDMA_CQ_MINERR_M;
1328 				qword3 |= LS_64(FLUSH_GENERAL_ERR, IRDMA_CQ_MINERR);
1329 				set_64bit_val(cqe, IRDMA_BYTE_24, qword3);
1330 			}
1331 		} else {
1332 			info->comp_status = IRDMA_COMPL_STATUS_UNKNOWN;
1333 		}
1334 	} else {
1335 		info->comp_status = IRDMA_COMPL_STATUS_SUCCESS;
1336 	}
1337 
1338 	get_64bit_val(cqe, IRDMA_BYTE_0, &qword0);
1339 	get_64bit_val(cqe, IRDMA_BYTE_16, &qword2);
1340 
1341 	info->tcp_seq_num_rtt = (u32)RS_64(qword0, IRDMACQ_TCPSEQNUMRTT);
1342 	info->qp_id = (u32)RS_64(qword2, IRDMACQ_QPID);
1343 	info->ud_src_qpn = (u32)RS_64(qword2, IRDMACQ_UDSRCQPN);
1344 
1345 	get_64bit_val(cqe, IRDMA_BYTE_8, &comp_ctx);
1346 
1347 	info->solicited_event = (bool)RS_64(qword3, IRDMACQ_SOEVENT);
1348 	qp = (struct irdma_qp_uk *)(irdma_uintptr) comp_ctx;
1349 	if (!qp || qp->destroy_pending) {
1350 		ret_code = EFAULT;
1351 		goto exit;
1352 	}
1353 	wqe_idx = (u32)RS_64(qword3, IRDMA_CQ_WQEIDX);
1354 	info->qp_handle = (irdma_qp_handle) (irdma_uintptr) qp;
1355 
1356 	if (q_type == IRDMA_CQE_QTYPE_RQ) {
1357 		u32 array_idx;
1358 
1359 		ret_code = irdma_skip_duplicate_flush_cmpl(qp->rq_ring,
1360 							   qp->rq_flush_seen,
1361 							   info->comp_status,
1362 							   &wqe_idx);
1363 		if (ret_code != 0)
1364 			goto exit;
1365 
1366 		array_idx = wqe_idx / qp->rq_wqe_size_multiplier;
1367 
1368 		if (info->comp_status == IRDMA_COMPL_STATUS_FLUSHED ||
1369 		    info->comp_status == IRDMA_COMPL_STATUS_UNKNOWN) {
1370 			if (!IRDMA_RING_MORE_WORK(qp->rq_ring)) {
1371 				ret_code = ENOENT;
1372 				goto exit;
1373 			}
1374 
1375 			info->wr_id = qp->rq_wrid_array[qp->rq_ring.tail];
1376 			info->signaled = 1;
1377 			array_idx = qp->rq_ring.tail;
1378 		} else {
1379 			info->wr_id = qp->rq_wrid_array[array_idx];
1380 			info->signaled = 1;
1381 			if (irdma_check_rq_cqe(qp, &array_idx)) {
1382 				info->wr_id = qp->rq_wrid_array[array_idx];
1383 				info->comp_status = IRDMA_COMPL_STATUS_UNKNOWN;
1384 				IRDMA_RING_SET_TAIL(qp->rq_ring, array_idx + 1);
1385 				return 0;
1386 			}
1387 		}
1388 
1389 		info->bytes_xfered = (u32)RS_64(qword0, IRDMACQ_PAYLDLEN);
1390 
1391 		if (info->imm_valid)
1392 			info->op_type = IRDMA_OP_TYPE_REC_IMM;
1393 		else
1394 			info->op_type = IRDMA_OP_TYPE_REC;
1395 
1396 		if (qword3 & IRDMACQ_STAG_M) {
1397 			info->stag_invalid_set = true;
1398 			info->inv_stag = (u32)RS_64(qword2, IRDMACQ_INVSTAG);
1399 		} else {
1400 			info->stag_invalid_set = false;
1401 		}
1402 		IRDMA_RING_SET_TAIL(qp->rq_ring, array_idx + 1);
1403 		if (info->comp_status == IRDMA_COMPL_STATUS_FLUSHED) {
1404 			qp->rq_flush_seen = true;
1405 			if (!IRDMA_RING_MORE_WORK(qp->rq_ring))
1406 				qp->rq_flush_complete = true;
1407 			else
1408 				move_cq_head = false;
1409 		}
1410 		pring = &qp->rq_ring;
1411 	} else {		/* q_type is IRDMA_CQE_QTYPE_SQ */
1412 		if (qp->first_sq_wq) {
1413 			if (wqe_idx + 1 >= qp->conn_wqes)
1414 				qp->first_sq_wq = false;
1415 
1416 			if (wqe_idx < qp->conn_wqes && qp->sq_ring.head == qp->sq_ring.tail) {
1417 				IRDMA_RING_MOVE_HEAD_NOCHECK(cq->cq_ring);
1418 				IRDMA_RING_MOVE_TAIL(cq->cq_ring);
1419 				set_64bit_val(cq->shadow_area, IRDMA_BYTE_0,
1420 					      IRDMA_RING_CURRENT_HEAD(cq->cq_ring));
1421 				memset(info, 0,
1422 				       sizeof(struct irdma_cq_poll_info));
1423 				return irdma_uk_cq_poll_cmpl(cq, info);
1424 			}
1425 		}
1426 		/* cease posting push mode on push drop */
1427 		if (info->push_dropped) {
1428 			qp->push_mode = false;
1429 			qp->push_dropped = true;
1430 		}
1431 		ret_code = irdma_skip_duplicate_flush_cmpl(qp->sq_ring,
1432 							   qp->sq_flush_seen,
1433 							   info->comp_status,
1434 							   &wqe_idx);
1435 		if (ret_code != 0)
1436 			goto exit;
1437 		if (info->comp_status != IRDMA_COMPL_STATUS_FLUSHED) {
1438 			info->wr_id = qp->sq_wrtrk_array[wqe_idx].wrid;
1439 			info->signaled = qp->sq_wrtrk_array[wqe_idx].signaled;
1440 			if (!info->comp_status)
1441 				info->bytes_xfered = qp->sq_wrtrk_array[wqe_idx].wr_len;
1442 			info->op_type = (u8)RS_64(qword3, IRDMACQ_OP);
1443 			IRDMA_RING_SET_TAIL(qp->sq_ring,
1444 					    wqe_idx + qp->sq_wrtrk_array[wqe_idx].quanta);
1445 		} else {
1446 			if (!IRDMA_RING_MORE_WORK(qp->sq_ring)) {
1447 				ret_code = ENOENT;
1448 				goto exit;
1449 			}
1450 
1451 			do {
1452 				__le64 *sw_wqe;
1453 				u64 wqe_qword;
1454 				u8 op_type;
1455 				u32 tail;
1456 
1457 				tail = qp->sq_ring.tail;
1458 				sw_wqe = qp->sq_base[tail].elem;
1459 				get_64bit_val(sw_wqe, IRDMA_BYTE_24,
1460 					      &wqe_qword);
1461 				op_type = (u8)RS_64(wqe_qword, IRDMAQPSQ_OPCODE);
1462 				info->op_type = op_type;
1463 				IRDMA_RING_SET_TAIL(qp->sq_ring,
1464 						    tail + qp->sq_wrtrk_array[tail].quanta);
1465 				if (op_type != IRDMAQP_OP_NOP) {
1466 					info->wr_id = qp->sq_wrtrk_array[tail].wrid;
1467 					info->signaled = qp->sq_wrtrk_array[tail].signaled;
1468 					info->bytes_xfered = qp->sq_wrtrk_array[tail].wr_len;
1469 					break;
1470 				}
1471 			} while (1);
1472 			qp->sq_flush_seen = true;
1473 			if (!IRDMA_RING_MORE_WORK(qp->sq_ring))
1474 				qp->sq_flush_complete = true;
1475 		}
1476 		pring = &qp->sq_ring;
1477 	}
1478 
1479 	ret_code = 0;
1480 
1481 exit:
1482 	if (!ret_code && info->comp_status == IRDMA_COMPL_STATUS_FLUSHED)
1483 		if (pring && IRDMA_RING_MORE_WORK(*pring))
1484 			move_cq_head = false;
1485 
1486 	if (move_cq_head) {
1487 		IRDMA_RING_MOVE_HEAD_NOCHECK(cq->cq_ring);
1488 		if (!IRDMA_RING_CURRENT_HEAD(cq->cq_ring))
1489 			cq->polarity ^= 1;
1490 
1491 		if (ext_valid && !cq->avoid_mem_cflct) {
1492 			IRDMA_RING_MOVE_HEAD_NOCHECK(cq->cq_ring);
1493 			if (!IRDMA_RING_CURRENT_HEAD(cq->cq_ring))
1494 				cq->polarity ^= 1;
1495 		}
1496 
1497 		IRDMA_RING_MOVE_TAIL(cq->cq_ring);
1498 		if (!cq->avoid_mem_cflct && ext_valid)
1499 			IRDMA_RING_MOVE_TAIL(cq->cq_ring);
1500 		set_64bit_val(cq->shadow_area, IRDMA_BYTE_0,
1501 			      IRDMA_RING_CURRENT_HEAD(cq->cq_ring));
1502 	} else {
1503 		qword3 &= ~IRDMA_CQ_WQEIDX_M;
1504 		qword3 |= LS_64(pring->tail, IRDMA_CQ_WQEIDX);
1505 		set_64bit_val(cqe, IRDMA_BYTE_24, qword3);
1506 	}
1507 
1508 	return ret_code;
1509 }
1510 
1511 /**
1512  * irdma_qp_round_up - return round up qp wq depth
1513  * @wqdepth: wq depth in quanta to round up
1514  */
1515 static int
1516 irdma_qp_round_up(u32 wqdepth)
1517 {
1518 	int scount = 1;
1519 
1520 	for (wqdepth--; scount <= 16; scount *= 2)
1521 		wqdepth |= wqdepth >> scount;
1522 
1523 	return ++wqdepth;
1524 }
1525 
1526 /**
1527  * irdma_get_wqe_shift - get shift count for maximum wqe size
1528  * @uk_attrs: qp HW attributes
1529  * @sge: Maximum Scatter Gather Elements wqe
1530  * @inline_data: Maximum inline data size
1531  * @shift: Returns the shift needed based on sge
1532  *
1533  * Shift can be used to left shift the wqe size based on number of SGEs and inlind data size.
1534  * For 1 SGE or inline data <= 8, shift = 0 (wqe size of 32
1535  * bytes). For 2 or 3 SGEs or inline data <= 39, shift = 1 (wqe
1536  * size of 64 bytes).
1537  * For 4-7 SGE's and inline <= 101 Shift of 2 otherwise (wqe
1538  * size of 256 bytes).
1539  */
1540 void
1541 irdma_get_wqe_shift(struct irdma_uk_attrs *uk_attrs, u32 sge,
1542 		    u32 inline_data, u8 *shift)
1543 {
1544 	*shift = 0;
1545 	if (uk_attrs->hw_rev >= IRDMA_GEN_2) {
1546 		if (sge > 1 || inline_data > 8) {
1547 			if (sge < 4 && inline_data <= 39)
1548 				*shift = 1;
1549 			else if (sge < 8 && inline_data <= 101)
1550 				*shift = 2;
1551 			else
1552 				*shift = 3;
1553 		}
1554 	} else if (sge > 1 || inline_data > 16) {
1555 		*shift = (sge < 4 && inline_data <= 48) ? 1 : 2;
1556 	}
1557 }
1558 
1559 /*
1560  * irdma_get_sqdepth - get SQ depth (quanta) @max_hw_wq_quanta: HW SQ size limit @sq_size: SQ size @shift: shift which
1561  * determines size of WQE @sqdepth: depth of SQ
1562  */
1563 int
1564 irdma_get_sqdepth(u32 max_hw_wq_quanta, u32 sq_size, u8 shift, u32 *sqdepth)
1565 {
1566 	*sqdepth = irdma_qp_round_up((sq_size << shift) + IRDMA_SQ_RSVD);
1567 
1568 	if (*sqdepth < (IRDMA_QP_SW_MIN_WQSIZE << shift))
1569 		*sqdepth = IRDMA_QP_SW_MIN_WQSIZE << shift;
1570 	else if (*sqdepth > max_hw_wq_quanta)
1571 		return EINVAL;
1572 
1573 	return 0;
1574 }
1575 
1576 /*
1577  * irdma_get_rqdepth - get RQ/SRQ depth (quanta) @max_hw_rq_quanta: HW RQ/SRQ size limit @rq_size: RQ/SRQ size @shift:
1578  * shift which determines size of WQE @rqdepth: depth of RQ/SRQ
1579  */
1580 int
1581 irdma_get_rqdepth(u32 max_hw_rq_quanta, u32 rq_size, u8 shift, u32 *rqdepth)
1582 {
1583 	*rqdepth = irdma_qp_round_up((rq_size << shift) + IRDMA_RQ_RSVD);
1584 
1585 	if (*rqdepth < (IRDMA_QP_SW_MIN_WQSIZE << shift))
1586 		*rqdepth = IRDMA_QP_SW_MIN_WQSIZE << shift;
1587 	else if (*rqdepth > max_hw_rq_quanta)
1588 		return EINVAL;
1589 
1590 	return 0;
1591 }
1592 
1593 static const struct irdma_wqe_uk_ops iw_wqe_uk_ops = {
1594 	.iw_copy_inline_data = irdma_copy_inline_data,
1595 	.iw_inline_data_size_to_quanta = irdma_inline_data_size_to_quanta,
1596 	.iw_set_fragment = irdma_set_fragment,
1597 	.iw_set_mw_bind_wqe = irdma_set_mw_bind_wqe,
1598 };
1599 
1600 static const struct irdma_wqe_uk_ops iw_wqe_uk_ops_gen_1 = {
1601 	.iw_copy_inline_data = irdma_copy_inline_data_gen_1,
1602 	.iw_inline_data_size_to_quanta = irdma_inline_data_size_to_quanta_gen_1,
1603 	.iw_set_fragment = irdma_set_fragment_gen_1,
1604 	.iw_set_mw_bind_wqe = irdma_set_mw_bind_wqe_gen_1,
1605 };
1606 
1607 /**
1608  * irdma_setup_connection_wqes - setup WQEs necessary to complete
1609  * connection.
1610  * @qp: hw qp (user and kernel)
1611  * @info: qp initialization info
1612  */
1613 static void
1614 irdma_setup_connection_wqes(struct irdma_qp_uk *qp,
1615 			    struct irdma_qp_uk_init_info *info)
1616 {
1617 	u16 move_cnt = 1;
1618 
1619 	if (qp->uk_attrs->feature_flags & IRDMA_FEATURE_RTS_AE)
1620 		move_cnt = 3;
1621 
1622 	qp->conn_wqes = move_cnt;
1623 	IRDMA_RING_MOVE_HEAD_BY_COUNT_NOCHECK(qp->sq_ring, move_cnt);
1624 	IRDMA_RING_MOVE_TAIL_BY_COUNT(qp->sq_ring, move_cnt);
1625 	IRDMA_RING_MOVE_HEAD_BY_COUNT_NOCHECK(qp->initial_ring, move_cnt);
1626 }
1627 
1628 /**
1629  * irdma_uk_qp_init - initialize shared qp
1630  * @qp: hw qp (user and kernel)
1631  * @info: qp initialization info
1632  *
1633  * initializes the vars used in both user and kernel mode.
1634  * size of the wqe depends on numbers of max. fragements
1635  * allowed. Then size of wqe * the number of wqes should be the
1636  * amount of memory allocated for sq and rq.
1637  */
1638 int
1639 irdma_uk_qp_init(struct irdma_qp_uk *qp, struct irdma_qp_uk_init_info *info)
1640 {
1641 	int ret_code = 0;
1642 	u32 sq_ring_size;
1643 	u8 sqshift, rqshift;
1644 
1645 	qp->uk_attrs = info->uk_attrs;
1646 	if (info->max_sq_frag_cnt > qp->uk_attrs->max_hw_wq_frags ||
1647 	    info->max_rq_frag_cnt > qp->uk_attrs->max_hw_wq_frags)
1648 		return EINVAL;
1649 
1650 	irdma_get_wqe_shift(qp->uk_attrs, info->max_rq_frag_cnt, 0, &rqshift);
1651 	if (qp->uk_attrs->hw_rev == IRDMA_GEN_1) {
1652 		irdma_get_wqe_shift(qp->uk_attrs, info->max_sq_frag_cnt,
1653 				    info->max_inline_data, &sqshift);
1654 		if (info->abi_ver > 4)
1655 			rqshift = IRDMA_MAX_RQ_WQE_SHIFT_GEN1;
1656 	} else {
1657 		irdma_get_wqe_shift(qp->uk_attrs, info->max_sq_frag_cnt + 1,
1658 				    info->max_inline_data, &sqshift);
1659 	}
1660 	qp->qp_caps = info->qp_caps;
1661 	qp->sq_base = info->sq;
1662 	qp->rq_base = info->rq;
1663 	qp->qp_type = info->type ? info->type : IRDMA_QP_TYPE_IWARP;
1664 	qp->shadow_area = info->shadow_area;
1665 	qp->sq_wrtrk_array = info->sq_wrtrk_array;
1666 
1667 	qp->rq_wrid_array = info->rq_wrid_array;
1668 	qp->wqe_alloc_db = info->wqe_alloc_db;
1669 	qp->last_rx_cmpl_idx = 0xffffffff;
1670 	qp->rd_fence_rate = info->rd_fence_rate;
1671 	qp->qp_id = info->qp_id;
1672 	qp->sq_size = info->sq_size;
1673 	qp->push_mode = false;
1674 	qp->max_sq_frag_cnt = info->max_sq_frag_cnt;
1675 	sq_ring_size = qp->sq_size << sqshift;
1676 	IRDMA_RING_INIT(qp->sq_ring, sq_ring_size);
1677 	IRDMA_RING_INIT(qp->initial_ring, sq_ring_size);
1678 	if (info->first_sq_wq) {
1679 		irdma_setup_connection_wqes(qp, info);
1680 		qp->swqe_polarity = 1;
1681 		qp->first_sq_wq = true;
1682 	} else {
1683 		qp->swqe_polarity = 0;
1684 	}
1685 	qp->swqe_polarity_deferred = 1;
1686 	qp->rwqe_polarity = 0;
1687 	qp->rq_size = info->rq_size;
1688 	qp->max_rq_frag_cnt = info->max_rq_frag_cnt;
1689 	qp->max_inline_data = info->max_inline_data;
1690 	qp->rq_wqe_size = rqshift;
1691 	IRDMA_RING_INIT(qp->rq_ring, qp->rq_size);
1692 	qp->rq_wqe_size_multiplier = 1 << rqshift;
1693 	if (qp->uk_attrs->hw_rev == IRDMA_GEN_1)
1694 		qp->wqe_ops = iw_wqe_uk_ops_gen_1;
1695 	else
1696 		qp->wqe_ops = iw_wqe_uk_ops;
1697 	return ret_code;
1698 }
1699 
1700 /**
1701  * irdma_uk_cq_init - initialize shared cq (user and kernel)
1702  * @cq: hw cq
1703  * @info: hw cq initialization info
1704  */
1705 int
1706 irdma_uk_cq_init(struct irdma_cq_uk *cq, struct irdma_cq_uk_init_info *info)
1707 {
1708 	cq->cq_base = info->cq_base;
1709 	cq->cq_id = info->cq_id;
1710 	cq->cq_size = info->cq_size;
1711 	cq->cqe_alloc_db = info->cqe_alloc_db;
1712 	cq->cq_ack_db = info->cq_ack_db;
1713 	cq->shadow_area = info->shadow_area;
1714 	cq->avoid_mem_cflct = info->avoid_mem_cflct;
1715 	IRDMA_RING_INIT(cq->cq_ring, cq->cq_size);
1716 	cq->polarity = 1;
1717 
1718 	return 0;
1719 }
1720 
1721 /**
1722  * irdma_uk_clean_cq - clean cq entries
1723  * @q: completion context
1724  * @cq: cq to clean
1725  */
1726 int
1727 irdma_uk_clean_cq(void *q, struct irdma_cq_uk *cq)
1728 {
1729 	__le64 *cqe;
1730 	u64 qword3, comp_ctx;
1731 	u32 cq_head;
1732 	u8 polarity, temp;
1733 
1734 	cq_head = cq->cq_ring.head;
1735 	temp = cq->polarity;
1736 	do {
1737 		if (cq->avoid_mem_cflct)
1738 			cqe = ((struct irdma_extended_cqe *)(cq->cq_base))[cq_head].buf;
1739 		else
1740 			cqe = cq->cq_base[cq_head].buf;
1741 		get_64bit_val(cqe, IRDMA_BYTE_24, &qword3);
1742 		polarity = (u8)RS_64(qword3, IRDMA_CQ_VALID);
1743 
1744 		if (polarity != temp)
1745 			break;
1746 
1747 		get_64bit_val(cqe, IRDMA_BYTE_8, &comp_ctx);
1748 		if ((void *)(irdma_uintptr) comp_ctx == q)
1749 			set_64bit_val(cqe, IRDMA_BYTE_8, 0);
1750 
1751 		cq_head = (cq_head + 1) % cq->cq_ring.size;
1752 		if (!cq_head)
1753 			temp ^= 1;
1754 	} while (true);
1755 	return 0;
1756 }
1757 
1758 /**
1759  * irdma_nop - post a nop
1760  * @qp: hw qp ptr
1761  * @wr_id: work request id
1762  * @signaled: signaled for completion
1763  * @post_sq: ring doorbell
1764  */
1765 int
1766 irdma_nop(struct irdma_qp_uk *qp, u64 wr_id, bool signaled, bool post_sq)
1767 {
1768 	__le64 *wqe;
1769 	u64 hdr;
1770 	u32 wqe_idx;
1771 	struct irdma_post_sq_info info = {0};
1772 
1773 	info.push_wqe = false;
1774 	info.wr_id = wr_id;
1775 	wqe = irdma_qp_get_next_send_wqe(qp, &wqe_idx, IRDMA_QP_WQE_MIN_QUANTA,
1776 					 0, &info);
1777 	if (!wqe)
1778 		return ENOSPC;
1779 
1780 	irdma_clr_wqes(qp, wqe_idx);
1781 
1782 	set_64bit_val(wqe, IRDMA_BYTE_0, 0);
1783 	set_64bit_val(wqe, IRDMA_BYTE_8, 0);
1784 	set_64bit_val(wqe, IRDMA_BYTE_16, 0);
1785 
1786 	hdr = LS_64(IRDMAQP_OP_NOP, IRDMAQPSQ_OPCODE) |
1787 	    LS_64(signaled, IRDMAQPSQ_SIGCOMPL) |
1788 	    LS_64(qp->swqe_polarity, IRDMAQPSQ_VALID);
1789 
1790 	udma_to_device_barrier();	/* make sure WQE is populated before valid bit is set */
1791 
1792 	set_64bit_val(wqe, IRDMA_BYTE_24, hdr);
1793 	if (post_sq)
1794 		irdma_uk_qp_post_wr(qp);
1795 
1796 	return 0;
1797 }
1798 
1799 /**
1800  * irdma_fragcnt_to_quanta_sq - calculate quanta based on fragment count for SQ
1801  * @frag_cnt: number of fragments
1802  * @quanta: quanta for frag_cnt
1803  */
1804 int
1805 irdma_fragcnt_to_quanta_sq(u32 frag_cnt, u16 *quanta)
1806 {
1807 	switch (frag_cnt) {
1808 	case 0:
1809 	case 1:
1810 		*quanta = IRDMA_QP_WQE_MIN_QUANTA;
1811 		break;
1812 	case 2:
1813 	case 3:
1814 		*quanta = 2;
1815 		break;
1816 	case 4:
1817 	case 5:
1818 		*quanta = 3;
1819 		break;
1820 	case 6:
1821 	case 7:
1822 		*quanta = 4;
1823 		break;
1824 	case 8:
1825 	case 9:
1826 		*quanta = 5;
1827 		break;
1828 	case 10:
1829 	case 11:
1830 		*quanta = 6;
1831 		break;
1832 	case 12:
1833 	case 13:
1834 		*quanta = 7;
1835 		break;
1836 	case 14:
1837 	case 15:		/* when immediate data is present */
1838 		*quanta = 8;
1839 		break;
1840 	default:
1841 		return EINVAL;
1842 	}
1843 
1844 	return 0;
1845 }
1846 
1847 /**
1848  * irdma_fragcnt_to_wqesize_rq - calculate wqe size based on fragment count for RQ
1849  * @frag_cnt: number of fragments
1850  * @wqe_size: size in bytes given frag_cnt
1851  */
1852 int
1853 irdma_fragcnt_to_wqesize_rq(u32 frag_cnt, u16 *wqe_size)
1854 {
1855 	switch (frag_cnt) {
1856 	case 0:
1857 	case 1:
1858 		*wqe_size = 32;
1859 		break;
1860 	case 2:
1861 	case 3:
1862 		*wqe_size = 64;
1863 		break;
1864 	case 4:
1865 	case 5:
1866 	case 6:
1867 	case 7:
1868 		*wqe_size = 128;
1869 		break;
1870 	case 8:
1871 	case 9:
1872 	case 10:
1873 	case 11:
1874 	case 12:
1875 	case 13:
1876 	case 14:
1877 		*wqe_size = 256;
1878 		break;
1879 	default:
1880 		return EINVAL;
1881 	}
1882 
1883 	return 0;
1884 }
1885