1 /*- 2 * SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB 3 * 4 * Copyright (c) 2017 - 2022 Intel Corporation 5 * 6 * This software is available to you under a choice of one of two 7 * licenses. You may choose to be licensed under the terms of the GNU 8 * General Public License (GPL) Version 2, available from the file 9 * COPYING in the main directory of this source tree, or the 10 * OpenFabrics.org BSD license below: 11 * 12 * Redistribution and use in source and binary forms, with or 13 * without modification, are permitted provided that the following 14 * conditions are met: 15 * 16 * - Redistributions of source code must retain the above 17 * copyright notice, this list of conditions and the following 18 * disclaimer. 19 * 20 * - Redistributions in binary form must reproduce the above 21 * copyright notice, this list of conditions and the following 22 * disclaimer in the documentation and/or other materials 23 * provided with the distribution. 24 * 25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 32 * SOFTWARE. 33 */ 34 35 #ifndef IRDMA_H 36 #define IRDMA_H 37 38 #define RDMA_BIT2(type, a) ((u##type) 1UL << a) 39 #define RDMA_MASK3(type, mask, shift) ((u##type) mask << shift) 40 #define MAKEMASK(m, s) ((m) << (s)) 41 42 #define IRDMA_WQEALLOC_WQE_DESC_INDEX_S 20 43 #define IRDMA_WQEALLOC_WQE_DESC_INDEX GENMASK(31, 20) 44 45 enum irdma_vers { 46 IRDMA_GEN_RSVD = 0, 47 IRDMA_GEN_1 = 1, 48 IRDMA_GEN_2 = 2, 49 }; 50 51 struct irdma_uk_attrs { 52 u64 feature_flags; 53 u32 max_hw_wq_frags; 54 u32 max_hw_read_sges; 55 u32 max_hw_inline; 56 u32 max_hw_rq_quanta; 57 u32 max_hw_wq_quanta; 58 u32 min_hw_cq_size; 59 u32 max_hw_cq_size; 60 u16 max_hw_sq_chunk; 61 u16 min_hw_wq_size; 62 u8 hw_rev; 63 }; 64 65 struct irdma_hw_attrs { 66 struct irdma_uk_attrs uk_attrs; 67 u64 max_hw_outbound_msg_size; 68 u64 max_hw_inbound_msg_size; 69 u64 max_mr_size; 70 u64 page_size_cap; 71 u32 min_hw_qp_id; 72 u32 min_hw_aeq_size; 73 u32 max_hw_aeq_size; 74 u32 min_hw_ceq_size; 75 u32 max_hw_ceq_size; 76 u32 max_hw_device_pages; 77 u32 max_hw_vf_fpm_id; 78 u32 first_hw_vf_fpm_id; 79 u32 max_hw_ird; 80 u32 max_hw_ord; 81 u32 max_hw_wqes; 82 u32 max_hw_pds; 83 u32 max_hw_ena_vf_count; 84 u32 max_qp_wr; 85 u32 max_pe_ready_count; 86 u32 max_done_count; 87 u32 max_sleep_count; 88 u32 max_cqp_compl_wait_time_ms; 89 u16 max_stat_inst; 90 u16 max_stat_idx; 91 }; 92 93 #endif /* IRDMA_H*/ 94