1 /* 2 * Copyright (c) 2024, Broadcom. All rights reserved. The term 3 * Broadcom refers to Broadcom Limited and/or its subsidiaries. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in 13 * the documentation and/or other materials provided with the 14 * distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 18 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 23 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE 25 * OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN 26 * IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #ifndef __BNXT_RE_ABI_H__ 30 #define __BNXT_RE_ABI_H__ 31 32 #include <sys/types.h> 33 #include <sys/mman.h> 34 #include <sys/stat.h> 35 36 #include <infiniband/kern-abi.h> 37 38 #include <errno.h> 39 #include <fcntl.h> 40 #include <limits.h> 41 #include <pthread.h> 42 #include <stdio.h> 43 #include <stdlib.h> 44 #include <string.h> 45 #include <unistd.h> 46 47 #define __aligned_u64 __attribute__((aligned(8))) u64 48 49 #define BNXT_RE_ABI_VERSION 6 50 #define BNXT_RE_MAX_INLINE_SIZE 0x60 51 #define BNXT_RE_MAX_INLINE_SIZE_VAR_WQE 0x1E0 52 #define BNXT_RE_MAX_PUSH_SIZE_VAR_WQE 0xD0 53 #define BNXT_RE_FULL_FLAG_DELTA 0x00 54 55 enum bnxt_re_wr_opcode { 56 BNXT_RE_WR_OPCD_SEND = 0x00, 57 BNXT_RE_WR_OPCD_SEND_IMM = 0x01, 58 BNXT_RE_WR_OPCD_SEND_INVAL = 0x02, 59 BNXT_RE_WR_OPCD_RDMA_WRITE = 0x04, 60 BNXT_RE_WR_OPCD_RDMA_WRITE_IMM = 0x05, 61 BNXT_RE_WR_OPCD_RDMA_READ = 0x06, 62 BNXT_RE_WR_OPCD_ATOMIC_CS = 0x08, 63 BNXT_RE_WR_OPCD_ATOMIC_FA = 0x0B, 64 BNXT_RE_WR_OPCD_LOC_INVAL = 0x0C, 65 BNXT_RE_WR_OPCD_BIND = 0x0E, 66 BNXT_RE_WR_OPCD_RECV = 0x80, 67 BNXT_RE_WR_OPCD_INVAL = 0xFF 68 }; 69 70 enum bnxt_re_wr_flags { 71 BNXT_RE_WR_FLAGS_INLINE = 0x10, 72 BNXT_RE_WR_FLAGS_SE = 0x08, 73 BNXT_RE_WR_FLAGS_UC_FENCE = 0x04, 74 BNXT_RE_WR_FLAGS_RD_FENCE = 0x02, 75 BNXT_RE_WR_FLAGS_SIGNALED = 0x01 76 }; 77 78 #define BNXT_RE_MEMW_TYPE_2 0x02 79 #define BNXT_RE_MEMW_TYPE_1 0x00 80 enum bnxt_re_wr_bind_acc { 81 BNXT_RE_WR_BIND_ACC_LWR = 0x01, 82 BNXT_RE_WR_BIND_ACC_RRD = 0x02, 83 BNXT_RE_WR_BIND_ACC_RWR = 0x04, 84 BNXT_RE_WR_BIND_ACC_RAT = 0x08, 85 BNXT_RE_WR_BIND_ACC_MWB = 0x10, 86 BNXT_RE_WR_BIND_ACC_ZBVA = 0x01, 87 BNXT_RE_WR_BIND_ACC_SHIFT = 0x10 88 }; 89 90 enum bnxt_re_wc_type { 91 BNXT_RE_WC_TYPE_SEND = 0x00, 92 BNXT_RE_WC_TYPE_RECV_RC = 0x01, 93 BNXT_RE_WC_TYPE_RECV_UD = 0x02, 94 BNXT_RE_WC_TYPE_RECV_RAW = 0x03, 95 BNXT_RE_WC_TYPE_TERM = 0x0E, 96 BNXT_RE_WC_TYPE_COFF = 0x0F 97 }; 98 99 #define BNXT_RE_WC_OPCD_RECV 0x80 100 enum bnxt_re_req_wc_status { 101 BNXT_RE_REQ_ST_OK = 0x00, 102 BNXT_RE_REQ_ST_BAD_RESP = 0x01, 103 BNXT_RE_REQ_ST_LOC_LEN = 0x02, 104 BNXT_RE_REQ_ST_LOC_QP_OP = 0x03, 105 BNXT_RE_REQ_ST_PROT = 0x04, 106 BNXT_RE_REQ_ST_MEM_OP = 0x05, 107 BNXT_RE_REQ_ST_REM_INVAL = 0x06, 108 BNXT_RE_REQ_ST_REM_ACC = 0x07, 109 BNXT_RE_REQ_ST_REM_OP = 0x08, 110 BNXT_RE_REQ_ST_RNR_NAK_XCED = 0x09, 111 BNXT_RE_REQ_ST_TRNSP_XCED = 0x0A, 112 BNXT_RE_REQ_ST_WR_FLUSH = 0x0B 113 }; 114 115 enum bnxt_re_rsp_wc_status { 116 BNXT_RE_RSP_ST_OK = 0x00, 117 BNXT_RE_RSP_ST_LOC_ACC = 0x01, 118 BNXT_RE_RSP_ST_LOC_LEN = 0x02, 119 BNXT_RE_RSP_ST_LOC_PROT = 0x03, 120 BNXT_RE_RSP_ST_LOC_QP_OP = 0x04, 121 BNXT_RE_RSP_ST_MEM_OP = 0x05, 122 BNXT_RE_RSP_ST_REM_INVAL = 0x06, 123 BNXT_RE_RSP_ST_WR_FLUSH = 0x07, 124 BNXT_RE_RSP_ST_HW_FLUSH = 0x08 125 }; 126 127 enum bnxt_re_hdr_offset { 128 BNXT_RE_HDR_WT_MASK = 0xFF, 129 BNXT_RE_HDR_FLAGS_MASK = 0xFF, 130 BNXT_RE_HDR_FLAGS_SHIFT = 0x08, 131 BNXT_RE_HDR_WS_MASK = 0xFF, 132 BNXT_RE_HDR_WS_SHIFT = 0x10 133 }; 134 135 enum bnxt_re_db_que_type { 136 BNXT_RE_QUE_TYPE_SQ = 0x00, 137 BNXT_RE_QUE_TYPE_RQ = 0x01, 138 BNXT_RE_QUE_TYPE_SRQ = 0x02, 139 BNXT_RE_QUE_TYPE_SRQ_ARM = 0x03, 140 BNXT_RE_QUE_TYPE_CQ = 0x04, 141 BNXT_RE_QUE_TYPE_CQ_ARMSE = 0x05, 142 BNXT_RE_QUE_TYPE_CQ_ARMALL = 0x06, 143 BNXT_RE_QUE_TYPE_CQ_ARMENA = 0x07, 144 BNXT_RE_QUE_TYPE_SRQ_ARMENA = 0x08, 145 BNXT_RE_QUE_TYPE_CQ_CUT_ACK = 0x09, 146 BNXT_RE_PUSH_TYPE_START = 0x0C, 147 BNXT_RE_PUSH_TYPE_END = 0x0D, 148 BNXT_RE_QUE_TYPE_NULL = 0x0F 149 }; 150 151 enum bnxt_re_db_mask { 152 BNXT_RE_DB_INDX_MASK = 0xFFFFFFUL, 153 BNXT_RE_DB_PILO_MASK = 0x0FFUL, 154 BNXT_RE_DB_PILO_SHIFT = 0x18, 155 BNXT_RE_DB_QID_MASK = 0xFFFFFUL, 156 BNXT_RE_DB_PIHI_MASK = 0xF00UL, 157 BNXT_RE_DB_PIHI_SHIFT = 0x0C, /* Because mask is 0xF00 */ 158 BNXT_RE_DB_TYP_MASK = 0x0FUL, 159 BNXT_RE_DB_TYP_SHIFT = 0x1C, 160 BNXT_RE_DB_VALID_SHIFT = 0x1A, 161 BNXT_RE_DB_EPOCH_SHIFT = 0x18, 162 BNXT_RE_DB_TOGGLE_SHIFT = 0x19, 163 164 }; 165 166 enum bnxt_re_psns_mask { 167 BNXT_RE_PSNS_SPSN_MASK = 0xFFFFFF, 168 BNXT_RE_PSNS_OPCD_MASK = 0xFF, 169 BNXT_RE_PSNS_OPCD_SHIFT = 0x18, 170 BNXT_RE_PSNS_NPSN_MASK = 0xFFFFFF, 171 BNXT_RE_PSNS_FLAGS_MASK = 0xFF, 172 BNXT_RE_PSNS_FLAGS_SHIFT = 0x18 173 }; 174 175 enum bnxt_re_msns_mask { 176 BNXT_RE_SQ_MSN_SEARCH_START_PSN_MASK = 0xFFFFFFUL, 177 BNXT_RE_SQ_MSN_SEARCH_START_PSN_SHIFT = 0, 178 BNXT_RE_SQ_MSN_SEARCH_NEXT_PSN_MASK = 0xFFFFFF000000ULL, 179 BNXT_RE_SQ_MSN_SEARCH_NEXT_PSN_SHIFT = 0x18, 180 BNXT_RE_SQ_MSN_SEARCH_START_IDX_MASK = 0xFFFF000000000000ULL, 181 BNXT_RE_SQ_MSN_SEARCH_START_IDX_SHIFT = 0x30 182 }; 183 184 enum bnxt_re_bcqe_mask { 185 BNXT_RE_BCQE_PH_MASK = 0x01, 186 BNXT_RE_BCQE_TYPE_MASK = 0x0F, 187 BNXT_RE_BCQE_TYPE_SHIFT = 0x01, 188 BNXT_RE_BCQE_STATUS_MASK = 0xFF, 189 BNXT_RE_BCQE_STATUS_SHIFT = 0x08, 190 BNXT_RE_BCQE_FLAGS_MASK = 0xFFFFU, 191 BNXT_RE_BCQE_FLAGS_SHIFT = 0x10, 192 BNXT_RE_BCQE_RWRID_MASK = 0xFFFFFU, 193 BNXT_RE_BCQE_SRCQP_MASK = 0xFF, 194 BNXT_RE_BCQE_SRCQP_SHIFT = 0x18 195 }; 196 197 enum bnxt_re_rc_flags_mask { 198 BNXT_RE_RC_FLAGS_SRQ_RQ_MASK = 0x01, 199 BNXT_RE_RC_FLAGS_IMM_MASK = 0x02, 200 BNXT_RE_RC_FLAGS_IMM_SHIFT = 0x01, 201 BNXT_RE_RC_FLAGS_INV_MASK = 0x04, 202 BNXT_RE_RC_FLAGS_INV_SHIFT = 0x02, 203 BNXT_RE_RC_FLAGS_RDMA_MASK = 0x08, 204 BNXT_RE_RC_FLAGS_RDMA_SHIFT = 0x03 205 }; 206 207 enum bnxt_re_ud_flags_mask { 208 BNXT_RE_UD_FLAGS_SRQ_RQ_MASK = 0x01, 209 BNXT_RE_UD_FLAGS_SRQ_RQ_SFT = 0x00, 210 BNXT_RE_UD_FLAGS_IMM_MASK = 0x02, 211 BNXT_RE_UD_FLAGS_IMM_SFT = 0x01, 212 BNXT_RE_UD_FLAGS_IP_VER_MASK = 0x30, 213 BNXT_RE_UD_FLAGS_IP_VER_SFT = 0x4, 214 BNXT_RE_UD_FLAGS_META_MASK = 0x3C0, 215 BNXT_RE_UD_FLAGS_META_SFT = 0x6, 216 BNXT_RE_UD_FLAGS_EXT_META_MASK = 0xC00, 217 BNXT_RE_UD_FLAGS_EXT_META_SFT = 0x10, 218 }; 219 220 enum bnxt_re_ud_cqe_mask { 221 BNXT_RE_UD_CQE_MAC_MASK = 0xFFFFFFFFFFFFULL, 222 BNXT_RE_UD_CQE_SRCQPLO_MASK = 0xFFFF, 223 BNXT_RE_UD_CQE_SRCQPLO_SHIFT = 0x30, 224 BNXT_RE_UD_CQE_LEN_MASK = 0x3FFFU 225 }; 226 227 enum bnxt_re_shpg_offt { 228 BNXT_RE_SHPG_BEG_RESV_OFFT = 0x00, 229 BNXT_RE_SHPG_AVID_OFFT = 0x10, 230 BNXT_RE_SHPG_AVID_SIZE = 0x04, 231 BNXT_RE_SHPG_END_RESV_OFFT = 0xFF0 232 }; 233 234 enum bnxt_re_que_flags_mask { 235 BNXT_RE_FLAG_EPOCH_TAIL_SHIFT = 0x0UL, 236 BNXT_RE_FLAG_EPOCH_HEAD_SHIFT = 0x1UL, 237 BNXT_RE_FLAG_EPOCH_TAIL_MASK = 0x1UL, 238 BNXT_RE_FLAG_EPOCH_HEAD_MASK = 0x2UL, 239 }; 240 241 enum bnxt_re_db_epoch_flag_shift { 242 BNXT_RE_DB_EPOCH_TAIL_SHIFT = BNXT_RE_DB_EPOCH_SHIFT, 243 BNXT_RE_DB_EPOCH_HEAD_SHIFT = (BNXT_RE_DB_EPOCH_SHIFT - 1) 244 }; 245 246 enum bnxt_re_ppp_st_en_mask { 247 BNXT_RE_PPP_ENABLED_MASK = 0x1UL, 248 BNXT_RE_PPP_STATE_MASK = 0x2UL, 249 }; 250 251 enum bnxt_re_ppp_st_shift { 252 BNXT_RE_PPP_ST_SHIFT = 0x1UL 253 }; 254 255 struct bnxt_re_db_hdr { 256 __u64 typ_qid_indx; /* typ: 4, qid:20, indx:24 */ 257 }; 258 259 #define BNXT_RE_CHIP_ID0_CHIP_NUM_SFT 0x00 260 #define BNXT_RE_CHIP_ID0_CHIP_REV_SFT 0x10 261 #define BNXT_RE_CHIP_ID0_CHIP_MET_SFT 0x18 262 263 enum { 264 BNXT_RE_COMP_MASK_UCNTX_WC_DPI_ENABLED = 0x01, 265 BNXT_RE_COMP_MASK_UCNTX_POW2_DISABLED = 0x02, 266 BNXT_RE_COMP_MASK_UCNTX_RSVD_WQE_DISABLED = 0x04, 267 BNXT_RE_COMP_MASK_UCNTX_MQP_EX_SUPPORTED = 0x8, 268 BNXT_RE_COMP_MASK_UCNTX_DBR_PACING_ENABLED = 0x10, 269 BNXT_RE_COMP_MASK_UCNTX_DBR_RECOVERY_ENABLED = 0x20, 270 BNXT_RE_COMP_MASK_UCNTX_HW_RETX_ENABLED = 0x40 271 }; 272 273 enum bnxt_re_req_to_drv { 274 BNXT_RE_COMP_MASK_REQ_UCNTX_POW2_SUPPORT = 0x01, 275 BNXT_RE_COMP_MASK_REQ_UCNTX_RSVD_WQE = 0x02 276 }; 277 278 #define BNXT_RE_WQE_MODES_WQE_MODE_MASK 0x01 279 /* bit wise modes can be extended here. */ 280 enum bnxt_re_modes { 281 BNXT_RE_WQE_MODE_STATIC = 0x00, 282 BNXT_RE_WQE_MODE_VARIABLE = 0x01 283 /* Other modes can be here */ 284 }; 285 286 struct bnxt_re_cntx_req { 287 struct ibv_get_context cmd; 288 __aligned_u64 comp_mask; 289 }; 290 291 struct bnxt_re_cntx_resp { 292 struct ibv_get_context_resp resp; 293 __u32 dev_id; 294 __u32 max_qp; /* To allocate qp-table */ 295 __u32 pg_size; 296 __u32 cqe_size; 297 __u32 max_cqd; 298 __u32 chip_id0; 299 __u32 chip_id1; 300 __u32 modes; 301 __aligned_u64 comp_mask; 302 } __attribute__((packed)); 303 304 enum { 305 BNXT_RE_COMP_MASK_PD_HAS_WC_DPI = 0x01, 306 BNXT_RE_COMP_MASK_PD_HAS_DBR_BAR_ADDR = 0x02, 307 }; 308 309 struct bnxt_re_pd_resp { 310 struct ibv_alloc_pd_resp resp; 311 __u32 pdid; 312 __u32 dpi; 313 __u64 dbr; 314 __u64 comp_mask; 315 __u32 wcdpi; 316 __u64 dbr_bar_map; 317 } __attribute__((packed)); 318 319 struct bnxt_re_mr_resp { 320 struct ibv_reg_mr_resp resp; 321 } __attribute__((packed)); 322 323 /* CQ */ 324 enum { 325 BNXT_RE_COMP_MASK_CQ_HAS_DB_INFO = 0x01, 326 BNXT_RE_COMP_MASK_CQ_HAS_WC_DPI = 0x02, 327 BNXT_RE_COMP_MASK_CQ_HAS_CQ_PAGE = 0x04 328 }; 329 330 enum { 331 BNXT_RE_COMP_MASK_CQ_REQ_HAS_CAP_MASK = 0x1 332 }; 333 334 enum { 335 BNXT_RE_COMP_MASK_CQ_REQ_CAP_DBR_RECOVERY = 0x1 336 }; 337 338 struct bnxt_re_cq_req { 339 struct ibv_create_cq cmd; 340 __u64 cq_va; 341 __u64 cq_handle; 342 __aligned_u64 comp_mask; 343 __u16 cq_capab; 344 } __attribute__((packed)); 345 346 struct bnxt_re_cq_resp { 347 struct ibv_create_cq_resp resp; 348 __u32 cqid; 349 __u32 tail; 350 __u32 phase; 351 __u32 rsvd; 352 __aligned_u64 comp_mask; 353 __u32 dpi; 354 __u64 dbr; 355 __u32 wcdpi; 356 __u64 cq_page; 357 } __attribute__((packed)); 358 359 struct bnxt_re_resize_cq_req { 360 struct ibv_resize_cq cmd; 361 __u64 cq_va; 362 } __attribute__((packed)); 363 364 struct bnxt_re_bcqe { 365 __u32 flg_st_typ_ph; 366 __u32 qphi_rwrid; 367 } __attribute__((packed)); 368 369 struct bnxt_re_req_cqe { 370 __u64 qp_handle; 371 __u32 con_indx; /* 16 bits valid. */ 372 __u32 rsvd1; 373 __u64 rsvd2; 374 } __attribute__((packed)); 375 376 struct bnxt_re_rc_cqe { 377 __u32 length; 378 __u32 imm_key; 379 __u64 qp_handle; 380 __u64 mr_handle; 381 } __attribute__((packed)); 382 383 struct bnxt_re_ud_cqe { 384 __u32 length; /* 14 bits */ 385 __u32 immd; 386 __u64 qp_handle; 387 __u64 qplo_mac; /* 16:48*/ 388 } __attribute__((packed)); 389 390 struct bnxt_re_term_cqe { 391 __u64 qp_handle; 392 __u32 rq_sq_cidx; 393 __u32 rsvd; 394 __u64 rsvd1; 395 } __attribute__((packed)); 396 397 struct bnxt_re_cutoff_cqe { 398 __u64 rsvd1; 399 __u64 rsvd2; 400 __u64 rsvd3; 401 __u8 cqe_type_toggle; 402 __u8 status; 403 __u16 rsvd4; 404 __u32 rsvd5; 405 } __attribute__((packed)); 406 407 /* QP */ 408 struct bnxt_re_qp_req { 409 struct ibv_create_qp cmd; 410 __u64 qpsva; 411 __u64 qprva; 412 __u64 qp_handle; 413 } __attribute__((packed)); 414 415 struct bnxt_re_qp_resp { 416 struct ibv_create_qp_resp resp; 417 __u32 qpid; 418 } __attribute__((packed)); 419 420 enum bnxt_re_modify_ex_mask { 421 BNXT_RE_MQP_PPP_REQ_EN_MASK = 0x1UL, 422 BNXT_RE_MQP_PPP_REQ_EN = 0x1UL, 423 BNXT_RE_MQP_PATH_MTU_MASK = 0x2UL, 424 BNXT_RE_MQP_PPP_IDX_MASK = 0x7UL, 425 BNXT_RE_MQP_PPP_STATE = 0x10UL 426 }; 427 428 /* Modify QP */ 429 struct bnxt_re_modify_ex_req { 430 struct ibv_modify_qp_ex cmd; 431 __aligned_u64 comp_mask; 432 __u32 dpi; 433 __u32 rsvd; 434 }; 435 436 struct bnxt_re_modify_ex_resp { 437 struct ibv_modify_qp_resp_ex resp; 438 __aligned_u64 comp_mask; 439 __u32 ppp_st_idx; 440 __u32 path_mtu; 441 }; 442 443 union lower_shdr { 444 __u64 qkey_len; 445 __u64 lkey_plkey; 446 __u64 rva; 447 }; 448 449 struct bnxt_re_bsqe { 450 __u32 rsv_ws_fl_wt; 451 __u32 key_immd; 452 union lower_shdr lhdr; 453 } __attribute__((packed)); 454 455 struct bnxt_re_psns_ext { 456 __u32 opc_spsn; 457 __u32 flg_npsn; 458 __u16 st_slot_idx; 459 __u16 rsvd0; 460 __u32 rsvd1; 461 } __attribute__((packed)); 462 463 /* sq_msn_search (size:64b/8B) */ 464 struct bnxt_re_msns { 465 __u64 start_idx_next_psn_start_psn; 466 } __attribute__((packed)); 467 468 struct bnxt_re_psns { 469 __u32 opc_spsn; 470 __u32 flg_npsn; 471 } __attribute__((packed)); 472 473 struct bnxt_re_sge { 474 __u64 pa; 475 __u32 lkey; 476 __u32 length; 477 } __attribute__((packed)); 478 479 struct bnxt_re_send { 480 __u32 dst_qp; 481 __u32 avid; 482 __u64 rsvd; 483 } __attribute__((packed)); 484 485 struct bnxt_re_raw { 486 __u32 cfa_meta; 487 __u32 rsvd2; 488 __u64 rsvd3; 489 } __attribute__((packed)); 490 491 struct bnxt_re_rdma { 492 __u64 rva; 493 __u32 rkey; 494 __u32 rsvd2; 495 } __attribute__((packed)); 496 497 struct bnxt_re_atomic { 498 __u64 swp_dt; 499 __u64 cmp_dt; 500 } __attribute__((packed)); 501 502 struct bnxt_re_inval { 503 __u64 rsvd[2]; 504 } __attribute__((packed)); 505 506 struct bnxt_re_bind { 507 __u64 va; 508 __u64 len; /* only 40 bits are valid */ 509 } __attribute__((packed)); 510 511 struct bnxt_re_brqe { 512 __u32 rsv_ws_fl_wt; 513 __u32 rsvd; 514 __u32 wrid; 515 __u32 rsvd1; 516 } __attribute__((packed)); 517 518 struct bnxt_re_rqe { 519 __u64 rsvd[2]; 520 } __attribute__((packed)); 521 522 /* SRQ */ 523 struct bnxt_re_srq_req { 524 struct ibv_create_srq cmd; 525 __u64 srqva; 526 __u64 srq_handle; 527 } __attribute__((packed)); 528 529 struct bnxt_re_srq_resp { 530 struct ibv_create_srq_resp resp; 531 __u32 srqid; 532 } __attribute__((packed)); 533 534 struct bnxt_re_srqe { 535 __u64 rsvd[2]; 536 } __attribute__((packed)); 537 538 struct bnxt_re_push_wqe { 539 __u64 addr[32]; 540 } __attribute__((packed));; 541 542 #endif 543