1 //===- X86RecognizableInstr.h - Disassembler instruction spec ----*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file is part of the X86 Disassembler Emitter. 10 // It contains the interface of a single recognizable instruction. 11 // Documentation for the disassembler emitter in general can be found in 12 // X86DisassemblerEmitter.h. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #ifndef LLVM_UTILS_TABLEGEN_X86RECOGNIZABLEINSTR_H 17 #define LLVM_UTILS_TABLEGEN_X86RECOGNIZABLEINSTR_H 18 19 #include "CodeGenInstruction.h" 20 #include "llvm/Support/DataTypes.h" 21 #include "llvm/Support/X86DisassemblerDecoderCommon.h" 22 23 struct InstructionSpecifier; 24 25 namespace llvm { 26 27 class Record; 28 29 #define X86_INSTR_MRM_MAPPING \ 30 MAP(C0, 64) \ 31 MAP(C1, 65) \ 32 MAP(C2, 66) \ 33 MAP(C3, 67) \ 34 MAP(C4, 68) \ 35 MAP(C5, 69) \ 36 MAP(C6, 70) \ 37 MAP(C7, 71) \ 38 MAP(C8, 72) \ 39 MAP(C9, 73) \ 40 MAP(CA, 74) \ 41 MAP(CB, 75) \ 42 MAP(CC, 76) \ 43 MAP(CD, 77) \ 44 MAP(CE, 78) \ 45 MAP(CF, 79) \ 46 MAP(D0, 80) \ 47 MAP(D1, 81) \ 48 MAP(D2, 82) \ 49 MAP(D3, 83) \ 50 MAP(D4, 84) \ 51 MAP(D5, 85) \ 52 MAP(D6, 86) \ 53 MAP(D7, 87) \ 54 MAP(D8, 88) \ 55 MAP(D9, 89) \ 56 MAP(DA, 90) \ 57 MAP(DB, 91) \ 58 MAP(DC, 92) \ 59 MAP(DD, 93) \ 60 MAP(DE, 94) \ 61 MAP(DF, 95) \ 62 MAP(E0, 96) \ 63 MAP(E1, 97) \ 64 MAP(E2, 98) \ 65 MAP(E3, 99) \ 66 MAP(E4, 100) \ 67 MAP(E5, 101) \ 68 MAP(E6, 102) \ 69 MAP(E7, 103) \ 70 MAP(E8, 104) \ 71 MAP(E9, 105) \ 72 MAP(EA, 106) \ 73 MAP(EB, 107) \ 74 MAP(EC, 108) \ 75 MAP(ED, 109) \ 76 MAP(EE, 110) \ 77 MAP(EF, 111) \ 78 MAP(F0, 112) \ 79 MAP(F1, 113) \ 80 MAP(F2, 114) \ 81 MAP(F3, 115) \ 82 MAP(F4, 116) \ 83 MAP(F5, 117) \ 84 MAP(F6, 118) \ 85 MAP(F7, 119) \ 86 MAP(F8, 120) \ 87 MAP(F9, 121) \ 88 MAP(FA, 122) \ 89 MAP(FB, 123) \ 90 MAP(FC, 124) \ 91 MAP(FD, 125) \ 92 MAP(FE, 126) \ 93 MAP(FF, 127) 94 95 // A clone of X86 since we can't depend on something that is generated. 96 namespace X86Local { 97 enum { 98 Pseudo = 0, 99 RawFrm = 1, 100 AddRegFrm = 2, 101 RawFrmMemOffs = 3, 102 RawFrmSrc = 4, 103 RawFrmDst = 5, 104 RawFrmDstSrc = 6, 105 RawFrmImm8 = 7, 106 RawFrmImm16 = 8, 107 AddCCFrm = 9, 108 PrefixByte = 10, 109 MRMDestMem4VOp3CC = 20, 110 MRMr0 = 21, 111 MRMSrcMemFSIB = 22, 112 MRMDestMemFSIB = 23, 113 MRMDestMem = 24, 114 MRMSrcMem = 25, 115 MRMSrcMem4VOp3 = 26, 116 MRMSrcMemOp4 = 27, 117 MRMSrcMemCC = 28, 118 MRMXmCC = 30, MRMXm = 31, 119 MRM0m = 32, MRM1m = 33, MRM2m = 34, MRM3m = 35, 120 MRM4m = 36, MRM5m = 37, MRM6m = 38, MRM7m = 39, 121 MRMDestReg = 40, 122 MRMSrcReg = 41, 123 MRMSrcReg4VOp3 = 42, 124 MRMSrcRegOp4 = 43, 125 MRMSrcRegCC = 44, 126 MRMXrCC = 46, MRMXr = 47, 127 MRM0r = 48, MRM1r = 49, MRM2r = 50, MRM3r = 51, 128 MRM4r = 52, MRM5r = 53, MRM6r = 54, MRM7r = 55, 129 MRM0X = 56, MRM1X = 57, MRM2X = 58, MRM3X = 59, 130 MRM4X = 60, MRM5X = 61, MRM6X = 62, MRM7X = 63, 131 #define MAP(from, to) MRM_##from = to, 132 X86_INSTR_MRM_MAPPING 133 #undef MAP 134 }; 135 136 enum { 137 OB = 0, TB = 1, T8 = 2, TA = 3, XOP8 = 4, XOP9 = 5, XOPA = 6, ThreeDNow = 7, 138 T_MAP5 = 8, T_MAP6 = 9 139 }; 140 141 enum { 142 PD = 1, XS = 2, XD = 3, PS = 4 143 }; 144 145 enum { 146 VEX = 1, XOP = 2, EVEX = 3 147 }; 148 149 enum { 150 OpSize16 = 1, OpSize32 = 2 151 }; 152 153 enum { 154 AdSize16 = 1, AdSize32 = 2, AdSize64 = 3 155 }; 156 } 157 158 namespace X86Disassembler { 159 160 class DisassemblerTables; 161 162 /// Extract common fields of a single X86 instruction from a CodeGenInstruction 163 struct RecognizableInstrBase { 164 /// The OpPrefix field from the record 165 uint8_t OpPrefix; 166 /// The OpMap field from the record 167 uint8_t OpMap; 168 /// The opcode field from the record; this is the opcode used in the Intel 169 /// encoding and therefore distinct from the UID 170 uint8_t Opcode; 171 /// The form field from the record 172 uint8_t Form; 173 // The encoding field from the record 174 uint8_t Encoding; 175 /// The OpSize field from the record 176 uint8_t OpSize; 177 /// The AdSize field from the record 178 uint8_t AdSize; 179 /// The hasREX_W field from the record 180 bool HasREX_W; 181 /// The hasVEX_4V field from the record 182 bool HasVEX_4V; 183 /// The HasVEX_WPrefix field from the record 184 bool HasVEX_W; 185 /// The IgnoresVEX_W field from the record 186 bool IgnoresVEX_W; 187 /// The hasVEX_L field from the record 188 bool HasVEX_L; 189 /// The ignoreVEX_L field from the record 190 bool IgnoresVEX_L; 191 /// The hasEVEX_L2Prefix field from the record 192 bool HasEVEX_L2; 193 /// The hasEVEX_K field from the record 194 bool HasEVEX_K; 195 /// The hasEVEX_KZ field from the record 196 bool HasEVEX_KZ; 197 /// The hasEVEX_B field from the record 198 bool HasEVEX_B; 199 /// Indicates that the instruction uses the L and L' fields for RC. 200 bool EncodeRC; 201 /// The isCodeGenOnly field from the record 202 bool IsCodeGenOnly; 203 /// The isAsmParserOnly field from the record 204 bool IsAsmParserOnly; 205 /// The ForceDisassemble field from the record 206 bool ForceDisassemble; 207 // The CD8_Scale field from the record 208 uint8_t CD8_Scale; 209 /// \param insn The CodeGenInstruction to extract information from. 210 RecognizableInstrBase(const CodeGenInstruction &insn); 211 /// \returns true if this instruction should be emitted 212 bool shouldBeEmitted() const; 213 }; 214 215 /// RecognizableInstr - Encapsulates all information required to decode a single 216 /// instruction, as extracted from the LLVM instruction tables. Has methods 217 /// to interpret the information available in the LLVM tables, and to emit the 218 /// instruction into DisassemblerTables. 219 class RecognizableInstr : public RecognizableInstrBase { 220 private: 221 /// The record from the .td files corresponding to this instruction 222 const Record* Rec; 223 /// The instruction name as listed in the tables 224 std::string Name; 225 // Whether the instruction has the predicate "In32BitMode" 226 bool Is32Bit; 227 // Whether the instruction has the predicate "In64BitMode" 228 bool Is64Bit; 229 /// The operands of the instruction, as listed in the CodeGenInstruction. 230 /// They are not one-to-one with operands listed in the MCInst; for example, 231 /// memory operands expand to 5 operands in the MCInst 232 const std::vector<CGIOperandList::OperandInfo>* Operands; 233 234 /// The opcode of the instruction, as used in an MCInst 235 InstrUID UID; 236 /// The description of the instruction that is emitted into the instruction 237 /// info table 238 InstructionSpecifier* Spec; 239 240 /// insnContext - Returns the primary context in which the instruction is 241 /// valid. 242 /// 243 /// @return - The context in which the instruction is valid. 244 InstructionContext insnContext() const; 245 246 /// typeFromString - Translates an operand type from the string provided in 247 /// the LLVM tables to an OperandType for use in the operand specifier. 248 /// 249 /// @param s - The string, as extracted by calling Rec->getName() 250 /// on a CodeGenInstruction::OperandInfo. 251 /// @param hasREX_W - Indicates whether the instruction has a REX.W 252 /// prefix. If it does, 32-bit register operands stay 253 /// 32-bit regardless of the operand size. 254 /// @param OpSize Indicates the operand size of the instruction. 255 /// If register size does not match OpSize, then 256 /// register sizes keep their size. 257 /// @return - The operand's type. 258 static OperandType typeFromString(const std::string& s, 259 bool hasREX_W, uint8_t OpSize); 260 261 /// immediateEncodingFromString - Translates an immediate encoding from the 262 /// string provided in the LLVM tables to an OperandEncoding for use in 263 /// the operand specifier. 264 /// 265 /// @param s - See typeFromString(). 266 /// @param OpSize - Indicates whether this is an OpSize16 instruction. 267 /// If it is not, then 16-bit immediate operands stay 16-bit. 268 /// @return - The operand's encoding. 269 static OperandEncoding immediateEncodingFromString(const std::string &s, 270 uint8_t OpSize); 271 272 /// rmRegisterEncodingFromString - Like immediateEncodingFromString, but 273 /// handles operands that are in the REG field of the ModR/M byte. 274 static OperandEncoding rmRegisterEncodingFromString(const std::string &s, 275 uint8_t OpSize); 276 277 /// rmRegisterEncodingFromString - Like immediateEncodingFromString, but 278 /// handles operands that are in the REG field of the ModR/M byte. 279 static OperandEncoding roRegisterEncodingFromString(const std::string &s, 280 uint8_t OpSize); 281 static OperandEncoding memoryEncodingFromString(const std::string &s, 282 uint8_t OpSize); 283 static OperandEncoding relocationEncodingFromString(const std::string &s, 284 uint8_t OpSize); 285 static OperandEncoding opcodeModifierEncodingFromString(const std::string &s, 286 uint8_t OpSize); 287 static OperandEncoding vvvvRegisterEncodingFromString(const std::string &s, 288 uint8_t OpSize); 289 static OperandEncoding writemaskRegisterEncodingFromString(const std::string &s, 290 uint8_t OpSize); 291 292 /// Adjust the encoding type for an operand based on the instruction. 293 void adjustOperandEncoding(OperandEncoding &encoding); 294 295 /// handleOperand - Converts a single operand from the LLVM table format to 296 /// the emitted table format, handling any duplicate operands it encounters 297 /// and then one non-duplicate. 298 /// 299 /// @param optional - Determines whether to assert that the 300 /// operand exists. 301 /// @param operandIndex - The index into the generated operand table. 302 /// Incremented by this function one or more 303 /// times to reflect possible duplicate 304 /// operands). 305 /// @param physicalOperandIndex - The index of the current operand into the 306 /// set of non-duplicate ('physical') operands. 307 /// Incremented by this function once. 308 /// @param numPhysicalOperands - The number of non-duplicate operands in the 309 /// instructions. 310 /// @param operandMapping - The operand mapping, which has an entry for 311 /// each operand that indicates whether it is a 312 /// duplicate, and of what. 313 void handleOperand(bool optional, 314 unsigned &operandIndex, 315 unsigned &physicalOperandIndex, 316 unsigned numPhysicalOperands, 317 const unsigned *operandMapping, 318 OperandEncoding (*encodingFromString) 319 (const std::string&, 320 uint8_t OpSize)); 321 322 /// emitInstructionSpecifier - Loads the instruction specifier for the current 323 /// instruction into a DisassemblerTables. 324 /// 325 void emitInstructionSpecifier(); 326 327 /// emitDecodePath - Populates the proper fields in the decode tables 328 /// corresponding to the decode paths for this instruction. 329 /// 330 /// \param tables The DisassemblerTables to populate with the decode 331 /// decode information for the current instruction. 332 void emitDecodePath(DisassemblerTables &tables) const; 333 334 public: 335 /// Constructor - Initializes a RecognizableInstr with the appropriate fields 336 /// from a CodeGenInstruction. 337 /// 338 /// \param tables The DisassemblerTables that the specifier will be added to. 339 /// \param insn The CodeGenInstruction to extract information from. 340 /// \param uid The unique ID of the current instruction. 341 RecognizableInstr(DisassemblerTables &tables, 342 const CodeGenInstruction &insn, 343 InstrUID uid); 344 /// processInstr - Accepts a CodeGenInstruction and loads decode information 345 /// for it into a DisassemblerTables if appropriate. 346 /// 347 /// \param tables The DiassemblerTables to be populated with decode 348 /// information. 349 /// \param insn The CodeGenInstruction to be used as a source for this 350 /// information. 351 /// \param uid The unique ID of the instruction. 352 static void processInstr(DisassemblerTables &tables, 353 const CodeGenInstruction &insn, 354 InstrUID uid); 355 }; 356 357 std::string getMnemonic(const CodeGenInstruction *I, unsigned Variant); 358 bool isRegisterOperand(const Record *Rec); 359 bool isMemoryOperand(const Record *Rec); 360 bool isImmediateOperand(const Record *Rec); 361 unsigned getRegOperandSize(const Record *RegRec); 362 unsigned getMemOperandSize(const Record *MemRec); 363 } // namespace X86Disassembler 364 365 } // namespace llvm 366 367 #endif 368