1 //===- X86RecognizableInstr.h - Disassembler instruction spec ----*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file is part of the X86 Disassembler Emitter. 10 // It contains the interface of a single recognizable instruction. 11 // Documentation for the disassembler emitter in general can be found in 12 // X86DisassemblerEmitter.h. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #ifndef LLVM_UTILS_TABLEGEN_X86RECOGNIZABLEINSTR_H 17 #define LLVM_UTILS_TABLEGEN_X86RECOGNIZABLEINSTR_H 18 19 #include "CodeGenInstruction.h" 20 #include "llvm/Support/DataTypes.h" 21 #include "llvm/Support/X86DisassemblerDecoderCommon.h" 22 23 struct InstructionSpecifier; 24 25 namespace llvm { 26 27 class Record; 28 29 #define X86_INSTR_MRM_MAPPING \ 30 MAP(C0, 64) \ 31 MAP(C1, 65) \ 32 MAP(C2, 66) \ 33 MAP(C3, 67) \ 34 MAP(C4, 68) \ 35 MAP(C5, 69) \ 36 MAP(C6, 70) \ 37 MAP(C7, 71) \ 38 MAP(C8, 72) \ 39 MAP(C9, 73) \ 40 MAP(CA, 74) \ 41 MAP(CB, 75) \ 42 MAP(CC, 76) \ 43 MAP(CD, 77) \ 44 MAP(CE, 78) \ 45 MAP(CF, 79) \ 46 MAP(D0, 80) \ 47 MAP(D1, 81) \ 48 MAP(D2, 82) \ 49 MAP(D3, 83) \ 50 MAP(D4, 84) \ 51 MAP(D5, 85) \ 52 MAP(D6, 86) \ 53 MAP(D7, 87) \ 54 MAP(D8, 88) \ 55 MAP(D9, 89) \ 56 MAP(DA, 90) \ 57 MAP(DB, 91) \ 58 MAP(DC, 92) \ 59 MAP(DD, 93) \ 60 MAP(DE, 94) \ 61 MAP(DF, 95) \ 62 MAP(E0, 96) \ 63 MAP(E1, 97) \ 64 MAP(E2, 98) \ 65 MAP(E3, 99) \ 66 MAP(E4, 100) \ 67 MAP(E5, 101) \ 68 MAP(E6, 102) \ 69 MAP(E7, 103) \ 70 MAP(E8, 104) \ 71 MAP(E9, 105) \ 72 MAP(EA, 106) \ 73 MAP(EB, 107) \ 74 MAP(EC, 108) \ 75 MAP(ED, 109) \ 76 MAP(EE, 110) \ 77 MAP(EF, 111) \ 78 MAP(F0, 112) \ 79 MAP(F1, 113) \ 80 MAP(F2, 114) \ 81 MAP(F3, 115) \ 82 MAP(F4, 116) \ 83 MAP(F5, 117) \ 84 MAP(F6, 118) \ 85 MAP(F7, 119) \ 86 MAP(F8, 120) \ 87 MAP(F9, 121) \ 88 MAP(FA, 122) \ 89 MAP(FB, 123) \ 90 MAP(FC, 124) \ 91 MAP(FD, 125) \ 92 MAP(FE, 126) \ 93 MAP(FF, 127) 94 95 // A clone of X86 since we can't depend on something that is generated. 96 namespace X86Local { 97 enum { 98 Pseudo = 0, 99 RawFrm = 1, 100 AddRegFrm = 2, 101 RawFrmMemOffs = 3, 102 RawFrmSrc = 4, 103 RawFrmDst = 5, 104 RawFrmDstSrc = 6, 105 RawFrmImm8 = 7, 106 RawFrmImm16 = 8, 107 AddCCFrm = 9, 108 PrefixByte = 10, 109 MRMr0 = 21, 110 MRMSrcMemFSIB = 22, 111 MRMDestMemFSIB = 23, 112 MRMDestMem = 24, 113 MRMSrcMem = 25, 114 MRMSrcMem4VOp3 = 26, 115 MRMSrcMemOp4 = 27, 116 MRMSrcMemCC = 28, 117 MRMXmCC = 30, MRMXm = 31, 118 MRM0m = 32, MRM1m = 33, MRM2m = 34, MRM3m = 35, 119 MRM4m = 36, MRM5m = 37, MRM6m = 38, MRM7m = 39, 120 MRMDestReg = 40, 121 MRMSrcReg = 41, 122 MRMSrcReg4VOp3 = 42, 123 MRMSrcRegOp4 = 43, 124 MRMSrcRegCC = 44, 125 MRMXrCC = 46, MRMXr = 47, 126 MRM0r = 48, MRM1r = 49, MRM2r = 50, MRM3r = 51, 127 MRM4r = 52, MRM5r = 53, MRM6r = 54, MRM7r = 55, 128 MRM0X = 56, MRM1X = 57, MRM2X = 58, MRM3X = 59, 129 MRM4X = 60, MRM5X = 61, MRM6X = 62, MRM7X = 63, 130 #define MAP(from, to) MRM_##from = to, 131 X86_INSTR_MRM_MAPPING 132 #undef MAP 133 }; 134 135 enum { 136 OB = 0, TB = 1, T8 = 2, TA = 3, XOP8 = 4, XOP9 = 5, XOPA = 6, ThreeDNow = 7, 137 T_MAP5 = 8, T_MAP6 = 9 138 }; 139 140 enum { 141 PD = 1, XS = 2, XD = 3, PS = 4 142 }; 143 144 enum { 145 VEX = 1, XOP = 2, EVEX = 3 146 }; 147 148 enum { 149 OpSize16 = 1, OpSize32 = 2 150 }; 151 152 enum { 153 AdSize16 = 1, AdSize32 = 2, AdSize64 = 3 154 }; 155 } 156 157 namespace X86Disassembler { 158 159 class DisassemblerTables; 160 161 /// Extract common fields of a single X86 instruction from a CodeGenInstruction 162 struct RecognizableInstrBase { 163 /// The OpPrefix field from the record 164 uint8_t OpPrefix; 165 /// The OpMap field from the record 166 uint8_t OpMap; 167 /// The opcode field from the record; this is the opcode used in the Intel 168 /// encoding and therefore distinct from the UID 169 uint8_t Opcode; 170 /// The form field from the record 171 uint8_t Form; 172 // The encoding field from the record 173 uint8_t Encoding; 174 /// The OpSize field from the record 175 uint8_t OpSize; 176 /// The AdSize field from the record 177 uint8_t AdSize; 178 /// The hasREX_W field from the record 179 bool HasREX_W; 180 /// The hasVEX_4V field from the record 181 bool HasVEX_4V; 182 /// The HasVEX_WPrefix field from the record 183 bool HasVEX_W; 184 /// The IgnoresVEX_W field from the record 185 bool IgnoresVEX_W; 186 /// The hasVEX_L field from the record 187 bool HasVEX_L; 188 /// The ignoreVEX_L field from the record 189 bool IgnoresVEX_L; 190 /// The hasEVEX_L2Prefix field from the record 191 bool HasEVEX_L2; 192 /// The hasEVEX_K field from the record 193 bool HasEVEX_K; 194 /// The hasEVEX_KZ field from the record 195 bool HasEVEX_KZ; 196 /// The hasEVEX_B field from the record 197 bool HasEVEX_B; 198 /// Indicates that the instruction uses the L and L' fields for RC. 199 bool EncodeRC; 200 /// The isCodeGenOnly field from the record 201 bool IsCodeGenOnly; 202 /// The isAsmParserOnly field from the record 203 bool IsAsmParserOnly; 204 /// The ForceDisassemble field from the record 205 bool ForceDisassemble; 206 // The CD8_Scale field from the record 207 uint8_t CD8_Scale; 208 /// \param insn The CodeGenInstruction to extract information from. 209 RecognizableInstrBase(const CodeGenInstruction &insn); 210 /// \returns true if this instruction should be emitted 211 bool shouldBeEmitted() const; 212 }; 213 214 /// RecognizableInstr - Encapsulates all information required to decode a single 215 /// instruction, as extracted from the LLVM instruction tables. Has methods 216 /// to interpret the information available in the LLVM tables, and to emit the 217 /// instruction into DisassemblerTables. 218 class RecognizableInstr : public RecognizableInstrBase { 219 private: 220 /// The record from the .td files corresponding to this instruction 221 const Record* Rec; 222 /// The instruction name as listed in the tables 223 std::string Name; 224 // Whether the instruction has the predicate "In32BitMode" 225 bool Is32Bit; 226 // Whether the instruction has the predicate "In64BitMode" 227 bool Is64Bit; 228 /// The operands of the instruction, as listed in the CodeGenInstruction. 229 /// They are not one-to-one with operands listed in the MCInst; for example, 230 /// memory operands expand to 5 operands in the MCInst 231 const std::vector<CGIOperandList::OperandInfo>* Operands; 232 233 /// The opcode of the instruction, as used in an MCInst 234 InstrUID UID; 235 /// The description of the instruction that is emitted into the instruction 236 /// info table 237 InstructionSpecifier* Spec; 238 239 /// insnContext - Returns the primary context in which the instruction is 240 /// valid. 241 /// 242 /// @return - The context in which the instruction is valid. 243 InstructionContext insnContext() const; 244 245 /// typeFromString - Translates an operand type from the string provided in 246 /// the LLVM tables to an OperandType for use in the operand specifier. 247 /// 248 /// @param s - The string, as extracted by calling Rec->getName() 249 /// on a CodeGenInstruction::OperandInfo. 250 /// @param hasREX_W - Indicates whether the instruction has a REX.W 251 /// prefix. If it does, 32-bit register operands stay 252 /// 32-bit regardless of the operand size. 253 /// @param OpSize Indicates the operand size of the instruction. 254 /// If register size does not match OpSize, then 255 /// register sizes keep their size. 256 /// @return - The operand's type. 257 static OperandType typeFromString(const std::string& s, 258 bool hasREX_W, uint8_t OpSize); 259 260 /// immediateEncodingFromString - Translates an immediate encoding from the 261 /// string provided in the LLVM tables to an OperandEncoding for use in 262 /// the operand specifier. 263 /// 264 /// @param s - See typeFromString(). 265 /// @param OpSize - Indicates whether this is an OpSize16 instruction. 266 /// If it is not, then 16-bit immediate operands stay 16-bit. 267 /// @return - The operand's encoding. 268 static OperandEncoding immediateEncodingFromString(const std::string &s, 269 uint8_t OpSize); 270 271 /// rmRegisterEncodingFromString - Like immediateEncodingFromString, but 272 /// handles operands that are in the REG field of the ModR/M byte. 273 static OperandEncoding rmRegisterEncodingFromString(const std::string &s, 274 uint8_t OpSize); 275 276 /// rmRegisterEncodingFromString - Like immediateEncodingFromString, but 277 /// handles operands that are in the REG field of the ModR/M byte. 278 static OperandEncoding roRegisterEncodingFromString(const std::string &s, 279 uint8_t OpSize); 280 static OperandEncoding memoryEncodingFromString(const std::string &s, 281 uint8_t OpSize); 282 static OperandEncoding relocationEncodingFromString(const std::string &s, 283 uint8_t OpSize); 284 static OperandEncoding opcodeModifierEncodingFromString(const std::string &s, 285 uint8_t OpSize); 286 static OperandEncoding vvvvRegisterEncodingFromString(const std::string &s, 287 uint8_t OpSize); 288 static OperandEncoding writemaskRegisterEncodingFromString(const std::string &s, 289 uint8_t OpSize); 290 291 /// Adjust the encoding type for an operand based on the instruction. 292 void adjustOperandEncoding(OperandEncoding &encoding); 293 294 /// handleOperand - Converts a single operand from the LLVM table format to 295 /// the emitted table format, handling any duplicate operands it encounters 296 /// and then one non-duplicate. 297 /// 298 /// @param optional - Determines whether to assert that the 299 /// operand exists. 300 /// @param operandIndex - The index into the generated operand table. 301 /// Incremented by this function one or more 302 /// times to reflect possible duplicate 303 /// operands). 304 /// @param physicalOperandIndex - The index of the current operand into the 305 /// set of non-duplicate ('physical') operands. 306 /// Incremented by this function once. 307 /// @param numPhysicalOperands - The number of non-duplicate operands in the 308 /// instructions. 309 /// @param operandMapping - The operand mapping, which has an entry for 310 /// each operand that indicates whether it is a 311 /// duplicate, and of what. 312 void handleOperand(bool optional, 313 unsigned &operandIndex, 314 unsigned &physicalOperandIndex, 315 unsigned numPhysicalOperands, 316 const unsigned *operandMapping, 317 OperandEncoding (*encodingFromString) 318 (const std::string&, 319 uint8_t OpSize)); 320 321 /// emitInstructionSpecifier - Loads the instruction specifier for the current 322 /// instruction into a DisassemblerTables. 323 /// 324 void emitInstructionSpecifier(); 325 326 /// emitDecodePath - Populates the proper fields in the decode tables 327 /// corresponding to the decode paths for this instruction. 328 /// 329 /// \param tables The DisassemblerTables to populate with the decode 330 /// decode information for the current instruction. 331 void emitDecodePath(DisassemblerTables &tables) const; 332 333 public: 334 /// Constructor - Initializes a RecognizableInstr with the appropriate fields 335 /// from a CodeGenInstruction. 336 /// 337 /// \param tables The DisassemblerTables that the specifier will be added to. 338 /// \param insn The CodeGenInstruction to extract information from. 339 /// \param uid The unique ID of the current instruction. 340 RecognizableInstr(DisassemblerTables &tables, 341 const CodeGenInstruction &insn, 342 InstrUID uid); 343 /// processInstr - Accepts a CodeGenInstruction and loads decode information 344 /// for it into a DisassemblerTables if appropriate. 345 /// 346 /// \param tables The DiassemblerTables to be populated with decode 347 /// information. 348 /// \param insn The CodeGenInstruction to be used as a source for this 349 /// information. 350 /// \param uid The unique ID of the instruction. 351 static void processInstr(DisassemblerTables &tables, 352 const CodeGenInstruction &insn, 353 InstrUID uid); 354 }; 355 356 std::string getMnemonic(const CodeGenInstruction *I, unsigned Variant); 357 bool isRegisterOperand(const Record *Rec); 358 bool isMemoryOperand(const Record *Rec); 359 bool isImmediateOperand(const Record *Rec); 360 unsigned getRegOperandSize(const Record *RegRec); 361 unsigned getMemOperandSize(const Record *MemRec); 362 } // namespace X86Disassembler 363 364 } // namespace llvm 365 366 #endif 367