1 //===- X86RecognizableInstr.h - Disassembler instruction spec ----*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file is part of the X86 Disassembler Emitter. 10 // It contains the interface of a single recognizable instruction. 11 // Documentation for the disassembler emitter in general can be found in 12 // X86DisassemblerEmitter.h. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #ifndef LLVM_UTILS_TABLEGEN_X86RECOGNIZABLEINSTR_H 17 #define LLVM_UTILS_TABLEGEN_X86RECOGNIZABLEINSTR_H 18 19 #include "CodeGenInstruction.h" 20 #include "llvm/Support/DataTypes.h" 21 #include "llvm/Support/X86DisassemblerDecoderCommon.h" 22 23 struct InstructionSpecifier; 24 25 namespace llvm { 26 27 class Record; 28 29 #define X86_INSTR_MRM_MAPPING \ 30 MAP(C0, 64) \ 31 MAP(C1, 65) \ 32 MAP(C2, 66) \ 33 MAP(C3, 67) \ 34 MAP(C4, 68) \ 35 MAP(C5, 69) \ 36 MAP(C6, 70) \ 37 MAP(C7, 71) \ 38 MAP(C8, 72) \ 39 MAP(C9, 73) \ 40 MAP(CA, 74) \ 41 MAP(CB, 75) \ 42 MAP(CC, 76) \ 43 MAP(CD, 77) \ 44 MAP(CE, 78) \ 45 MAP(CF, 79) \ 46 MAP(D0, 80) \ 47 MAP(D1, 81) \ 48 MAP(D2, 82) \ 49 MAP(D3, 83) \ 50 MAP(D4, 84) \ 51 MAP(D5, 85) \ 52 MAP(D6, 86) \ 53 MAP(D7, 87) \ 54 MAP(D8, 88) \ 55 MAP(D9, 89) \ 56 MAP(DA, 90) \ 57 MAP(DB, 91) \ 58 MAP(DC, 92) \ 59 MAP(DD, 93) \ 60 MAP(DE, 94) \ 61 MAP(DF, 95) \ 62 MAP(E0, 96) \ 63 MAP(E1, 97) \ 64 MAP(E2, 98) \ 65 MAP(E3, 99) \ 66 MAP(E4, 100) \ 67 MAP(E5, 101) \ 68 MAP(E6, 102) \ 69 MAP(E7, 103) \ 70 MAP(E8, 104) \ 71 MAP(E9, 105) \ 72 MAP(EA, 106) \ 73 MAP(EB, 107) \ 74 MAP(EC, 108) \ 75 MAP(ED, 109) \ 76 MAP(EE, 110) \ 77 MAP(EF, 111) \ 78 MAP(F0, 112) \ 79 MAP(F1, 113) \ 80 MAP(F2, 114) \ 81 MAP(F3, 115) \ 82 MAP(F4, 116) \ 83 MAP(F5, 117) \ 84 MAP(F6, 118) \ 85 MAP(F7, 119) \ 86 MAP(F8, 120) \ 87 MAP(F9, 121) \ 88 MAP(FA, 122) \ 89 MAP(FB, 123) \ 90 MAP(FC, 124) \ 91 MAP(FD, 125) \ 92 MAP(FE, 126) \ 93 MAP(FF, 127) 94 95 // A clone of X86 since we can't depend on something that is generated. 96 namespace X86Local { 97 enum { 98 Pseudo = 0, 99 RawFrm = 1, 100 AddRegFrm = 2, 101 RawFrmMemOffs = 3, 102 RawFrmSrc = 4, 103 RawFrmDst = 5, 104 RawFrmDstSrc = 6, 105 RawFrmImm8 = 7, 106 RawFrmImm16 = 8, 107 AddCCFrm = 9, 108 PrefixByte = 10, 109 MRMr0 = 21, 110 MRMSrcMemFSIB = 22, 111 MRMDestMemFSIB = 23, 112 MRMDestMem = 24, 113 MRMSrcMem = 25, 114 MRMSrcMem4VOp3 = 26, 115 MRMSrcMemOp4 = 27, 116 MRMSrcMemCC = 28, 117 MRMXmCC = 30, MRMXm = 31, 118 MRM0m = 32, MRM1m = 33, MRM2m = 34, MRM3m = 35, 119 MRM4m = 36, MRM5m = 37, MRM6m = 38, MRM7m = 39, 120 MRMDestReg = 40, 121 MRMSrcReg = 41, 122 MRMSrcReg4VOp3 = 42, 123 MRMSrcRegOp4 = 43, 124 MRMSrcRegCC = 44, 125 MRMXrCC = 46, MRMXr = 47, 126 MRM0r = 48, MRM1r = 49, MRM2r = 50, MRM3r = 51, 127 MRM4r = 52, MRM5r = 53, MRM6r = 54, MRM7r = 55, 128 MRM0X = 56, MRM1X = 57, MRM2X = 58, MRM3X = 59, 129 MRM4X = 60, MRM5X = 61, MRM6X = 62, MRM7X = 63, 130 #define MAP(from, to) MRM_##from = to, 131 X86_INSTR_MRM_MAPPING 132 #undef MAP 133 }; 134 135 enum { 136 OB = 0, TB = 1, T8 = 2, TA = 3, XOP8 = 4, XOP9 = 5, XOPA = 6, ThreeDNow = 7, 137 T_MAP5 = 8, T_MAP6 = 9 138 }; 139 140 enum { 141 PD = 1, XS = 2, XD = 3, PS = 4 142 }; 143 144 enum { 145 VEX = 1, XOP = 2, EVEX = 3 146 }; 147 148 enum { 149 OpSize16 = 1, OpSize32 = 2 150 }; 151 152 enum { 153 AdSize16 = 1, AdSize32 = 2, AdSize64 = 3 154 }; 155 } 156 157 namespace X86Disassembler { 158 159 class DisassemblerTables; 160 161 /// RecognizableInstr - Encapsulates all information required to decode a single 162 /// instruction, as extracted from the LLVM instruction tables. Has methods 163 /// to interpret the information available in the LLVM tables, and to emit the 164 /// instruction into DisassemblerTables. 165 class RecognizableInstr { 166 private: 167 /// The opcode of the instruction, as used in an MCInst 168 InstrUID UID; 169 /// The record from the .td files corresponding to this instruction 170 const Record* Rec; 171 /// The OpPrefix field from the record 172 uint8_t OpPrefix; 173 /// The OpMap field from the record 174 uint8_t OpMap; 175 /// The opcode field from the record; this is the opcode used in the Intel 176 /// encoding and therefore distinct from the UID 177 uint8_t Opcode; 178 /// The form field from the record 179 uint8_t Form; 180 // The encoding field from the record 181 uint8_t Encoding; 182 /// The OpSize field from the record 183 uint8_t OpSize; 184 /// The AdSize field from the record 185 uint8_t AdSize; 186 /// The hasREX_WPrefix field from the record 187 bool HasREX_WPrefix; 188 /// The hasVEX_4V field from the record 189 bool HasVEX_4V; 190 /// The HasVEX_WPrefix field from the record 191 bool HasVEX_W; 192 /// The IgnoresVEX_W field from the record 193 bool IgnoresVEX_W; 194 /// Inferred from the operands; indicates whether the L bit in the VEX prefix is set 195 bool HasVEX_LPrefix; 196 /// The ignoreVEX_L field from the record 197 bool IgnoresVEX_L; 198 /// The hasEVEX_L2Prefix field from the record 199 bool HasEVEX_L2Prefix; 200 /// The hasEVEX_K field from the record 201 bool HasEVEX_K; 202 /// The hasEVEX_KZ field from the record 203 bool HasEVEX_KZ; 204 /// The hasEVEX_B field from the record 205 bool HasEVEX_B; 206 /// Indicates that the instruction uses the L and L' fields for RC. 207 bool EncodeRC; 208 /// The isCodeGenOnly field from the record 209 bool IsCodeGenOnly; 210 /// The ForceDisassemble field from the record 211 bool ForceDisassemble; 212 // The CD8_Scale field from the record 213 uint8_t CD8_Scale; 214 // Whether the instruction has the predicate "In64BitMode" 215 bool Is64Bit; 216 // Whether the instruction has the predicate "In32BitMode" 217 bool Is32Bit; 218 219 /// The instruction name as listed in the tables 220 std::string Name; 221 222 /// Indicates whether the instruction should be emitted into the decode 223 /// tables; regardless, it will be emitted into the instruction info table 224 bool ShouldBeEmitted; 225 226 /// The operands of the instruction, as listed in the CodeGenInstruction. 227 /// They are not one-to-one with operands listed in the MCInst; for example, 228 /// memory operands expand to 5 operands in the MCInst 229 const std::vector<CGIOperandList::OperandInfo>* Operands; 230 231 /// The description of the instruction that is emitted into the instruction 232 /// info table 233 InstructionSpecifier* Spec; 234 235 /// insnContext - Returns the primary context in which the instruction is 236 /// valid. 237 /// 238 /// @return - The context in which the instruction is valid. 239 InstructionContext insnContext() const; 240 241 /// typeFromString - Translates an operand type from the string provided in 242 /// the LLVM tables to an OperandType for use in the operand specifier. 243 /// 244 /// @param s - The string, as extracted by calling Rec->getName() 245 /// on a CodeGenInstruction::OperandInfo. 246 /// @param hasREX_WPrefix - Indicates whether the instruction has a REX.W 247 /// prefix. If it does, 32-bit register operands stay 248 /// 32-bit regardless of the operand size. 249 /// @param OpSize Indicates the operand size of the instruction. 250 /// If register size does not match OpSize, then 251 /// register sizes keep their size. 252 /// @return - The operand's type. 253 static OperandType typeFromString(const std::string& s, 254 bool hasREX_WPrefix, uint8_t OpSize); 255 256 /// immediateEncodingFromString - Translates an immediate encoding from the 257 /// string provided in the LLVM tables to an OperandEncoding for use in 258 /// the operand specifier. 259 /// 260 /// @param s - See typeFromString(). 261 /// @param OpSize - Indicates whether this is an OpSize16 instruction. 262 /// If it is not, then 16-bit immediate operands stay 16-bit. 263 /// @return - The operand's encoding. 264 static OperandEncoding immediateEncodingFromString(const std::string &s, 265 uint8_t OpSize); 266 267 /// rmRegisterEncodingFromString - Like immediateEncodingFromString, but 268 /// handles operands that are in the REG field of the ModR/M byte. 269 static OperandEncoding rmRegisterEncodingFromString(const std::string &s, 270 uint8_t OpSize); 271 272 /// rmRegisterEncodingFromString - Like immediateEncodingFromString, but 273 /// handles operands that are in the REG field of the ModR/M byte. 274 static OperandEncoding roRegisterEncodingFromString(const std::string &s, 275 uint8_t OpSize); 276 static OperandEncoding memoryEncodingFromString(const std::string &s, 277 uint8_t OpSize); 278 static OperandEncoding relocationEncodingFromString(const std::string &s, 279 uint8_t OpSize); 280 static OperandEncoding opcodeModifierEncodingFromString(const std::string &s, 281 uint8_t OpSize); 282 static OperandEncoding vvvvRegisterEncodingFromString(const std::string &s, 283 uint8_t OpSize); 284 static OperandEncoding writemaskRegisterEncodingFromString(const std::string &s, 285 uint8_t OpSize); 286 287 /// Adjust the encoding type for an operand based on the instruction. 288 void adjustOperandEncoding(OperandEncoding &encoding); 289 290 /// handleOperand - Converts a single operand from the LLVM table format to 291 /// the emitted table format, handling any duplicate operands it encounters 292 /// and then one non-duplicate. 293 /// 294 /// @param optional - Determines whether to assert that the 295 /// operand exists. 296 /// @param operandIndex - The index into the generated operand table. 297 /// Incremented by this function one or more 298 /// times to reflect possible duplicate 299 /// operands). 300 /// @param physicalOperandIndex - The index of the current operand into the 301 /// set of non-duplicate ('physical') operands. 302 /// Incremented by this function once. 303 /// @param numPhysicalOperands - The number of non-duplicate operands in the 304 /// instructions. 305 /// @param operandMapping - The operand mapping, which has an entry for 306 /// each operand that indicates whether it is a 307 /// duplicate, and of what. 308 void handleOperand(bool optional, 309 unsigned &operandIndex, 310 unsigned &physicalOperandIndex, 311 unsigned numPhysicalOperands, 312 const unsigned *operandMapping, 313 OperandEncoding (*encodingFromString) 314 (const std::string&, 315 uint8_t OpSize)); 316 317 /// shouldBeEmitted - Returns the shouldBeEmitted field. Although filter() 318 /// filters out many instructions, at various points in decoding we 319 /// determine that the instruction should not actually be decodable. In 320 /// particular, MMX MOV instructions aren't emitted, but they're only 321 /// identified during operand parsing. 322 /// 323 /// @return - true if at this point we believe the instruction should be 324 /// emitted; false if not. This will return false if filter() returns false 325 /// once emitInstructionSpecifier() has been called. 326 bool shouldBeEmitted() const { 327 return ShouldBeEmitted; 328 } 329 330 /// emitInstructionSpecifier - Loads the instruction specifier for the current 331 /// instruction into a DisassemblerTables. 332 /// 333 void emitInstructionSpecifier(); 334 335 /// emitDecodePath - Populates the proper fields in the decode tables 336 /// corresponding to the decode paths for this instruction. 337 /// 338 /// \param tables The DisassemblerTables to populate with the decode 339 /// decode information for the current instruction. 340 void emitDecodePath(DisassemblerTables &tables) const; 341 342 /// Constructor - Initializes a RecognizableInstr with the appropriate fields 343 /// from a CodeGenInstruction. 344 /// 345 /// \param tables The DisassemblerTables that the specifier will be added to. 346 /// \param insn The CodeGenInstruction to extract information from. 347 /// \param uid The unique ID of the current instruction. 348 RecognizableInstr(DisassemblerTables &tables, 349 const CodeGenInstruction &insn, 350 InstrUID uid); 351 public: 352 /// processInstr - Accepts a CodeGenInstruction and loads decode information 353 /// for it into a DisassemblerTables if appropriate. 354 /// 355 /// \param tables The DiassemblerTables to be populated with decode 356 /// information. 357 /// \param insn The CodeGenInstruction to be used as a source for this 358 /// information. 359 /// \param uid The unique ID of the instruction. 360 static void processInstr(DisassemblerTables &tables, 361 const CodeGenInstruction &insn, 362 InstrUID uid); 363 }; 364 365 } // namespace X86Disassembler 366 367 } // namespace llvm 368 369 #endif 370