1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file is part of the X86 Disassembler Emitter. 10 // It contains the implementation of a single recognizable instruction. 11 // Documentation for the disassembler emitter in general can be found in 12 // X86DisassemblerEmitter.h. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #include "X86RecognizableInstr.h" 17 #include "X86DisassemblerShared.h" 18 #include "X86DisassemblerTables.h" 19 #include "X86ModRMFilters.h" 20 #include "llvm/Support/ErrorHandling.h" 21 #include "llvm/TableGen/Record.h" 22 #include <string> 23 24 using namespace llvm; 25 using namespace X86Disassembler; 26 27 std::string X86Disassembler::getMnemonic(const CodeGenInstruction *I, 28 unsigned Variant) { 29 std::string AsmString = I->FlattenAsmStringVariants(I->AsmString, Variant); 30 StringRef Mnemonic(AsmString); 31 // Extract a mnemonic assuming it's separated by \t 32 Mnemonic = Mnemonic.take_until([](char C) { return C == '\t'; }); 33 34 // Special case: CMOVCC, JCC, SETCC have "${cond}" in mnemonic. 35 // Replace it with "CC" in-place. 36 size_t CondPos = Mnemonic.find("${cond}"); 37 if (CondPos != StringRef::npos) 38 Mnemonic = AsmString.replace(CondPos, StringRef::npos, "CC"); 39 return Mnemonic.upper(); 40 } 41 42 bool X86Disassembler::isRegisterOperand(const Record *Rec) { 43 return Rec->isSubClassOf("RegisterClass") || 44 Rec->isSubClassOf("RegisterOperand"); 45 } 46 47 bool X86Disassembler::isMemoryOperand(const Record *Rec) { 48 return Rec->isSubClassOf("Operand") && 49 Rec->getValueAsString("OperandType") == "OPERAND_MEMORY"; 50 } 51 52 bool X86Disassembler::isImmediateOperand(const Record *Rec) { 53 return Rec->isSubClassOf("Operand") && 54 Rec->getValueAsString("OperandType") == "OPERAND_IMMEDIATE"; 55 } 56 57 unsigned X86Disassembler::getRegOperandSize(const Record *RegRec) { 58 if (RegRec->isSubClassOf("RegisterClass")) 59 return RegRec->getValueAsInt("Alignment"); 60 if (RegRec->isSubClassOf("RegisterOperand")) 61 return RegRec->getValueAsDef("RegClass")->getValueAsInt("Alignment"); 62 63 llvm_unreachable("Register operand's size not known!"); 64 } 65 66 unsigned X86Disassembler::getMemOperandSize(const Record *MemRec) { 67 if (MemRec->isSubClassOf("X86MemOperand")) 68 return MemRec->getValueAsInt("Size"); 69 70 llvm_unreachable("Memory operand's size not known!"); 71 } 72 73 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit. 74 /// Useful for switch statements and the like. 75 /// 76 /// @param init - A reference to the BitsInit to be decoded. 77 /// @return - The field, with the first bit in the BitsInit as the lowest 78 /// order bit. 79 static uint8_t byteFromBitsInit(BitsInit &init) { 80 int width = init.getNumBits(); 81 82 assert(width <= 8 && "Field is too large for uint8_t!"); 83 84 int index; 85 uint8_t mask = 0x01; 86 87 uint8_t ret = 0; 88 89 for (index = 0; index < width; index++) { 90 if (cast<BitInit>(init.getBit(index))->getValue()) 91 ret |= mask; 92 93 mask <<= 1; 94 } 95 96 return ret; 97 } 98 99 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the 100 /// name of the field. 101 /// 102 /// @param rec - The record from which to extract the value. 103 /// @param name - The name of the field in the record. 104 /// @return - The field, as translated by byteFromBitsInit(). 105 static uint8_t byteFromRec(const Record *rec, StringRef name) { 106 BitsInit *bits = rec->getValueAsBitsInit(name); 107 return byteFromBitsInit(*bits); 108 } 109 110 RecognizableInstrBase::RecognizableInstrBase(const CodeGenInstruction &insn) { 111 const Record *Rec = insn.TheDef; 112 assert(Rec->isSubClassOf("X86Inst") && "Not a X86 Instruction"); 113 OpPrefix = byteFromRec(Rec, "OpPrefixBits"); 114 OpMap = byteFromRec(Rec, "OpMapBits"); 115 Opcode = byteFromRec(Rec, "Opcode"); 116 Form = byteFromRec(Rec, "FormBits"); 117 Encoding = byteFromRec(Rec, "OpEncBits"); 118 OpSize = byteFromRec(Rec, "OpSizeBits"); 119 AdSize = byteFromRec(Rec, "AdSizeBits"); 120 HasREX_W = Rec->getValueAsBit("hasREX_W"); 121 HasVEX_4V = Rec->getValueAsBit("hasVEX_4V"); 122 IgnoresW = Rec->getValueAsBit("IgnoresW"); 123 IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L"); 124 HasEVEX_L2 = Rec->getValueAsBit("hasEVEX_L2"); 125 HasEVEX_K = Rec->getValueAsBit("hasEVEX_K"); 126 HasEVEX_KZ = Rec->getValueAsBit("hasEVEX_Z"); 127 HasEVEX_B = Rec->getValueAsBit("hasEVEX_B"); 128 IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly"); 129 IsAsmParserOnly = Rec->getValueAsBit("isAsmParserOnly"); 130 ForceDisassemble = Rec->getValueAsBit("ForceDisassemble"); 131 CD8_Scale = byteFromRec(Rec, "CD8_Scale"); 132 HasVEX_L = Rec->getValueAsBit("hasVEX_L"); 133 ExplicitREX2Prefix = 134 byteFromRec(Rec, "explicitOpPrefixBits") == X86Local::ExplicitREX2; 135 136 EncodeRC = HasEVEX_B && 137 (Form == X86Local::MRMDestReg || Form == X86Local::MRMSrcReg); 138 } 139 140 bool RecognizableInstrBase::shouldBeEmitted() const { 141 return Form != X86Local::Pseudo && (!IsCodeGenOnly || ForceDisassemble) && 142 !IsAsmParserOnly; 143 } 144 145 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables, 146 const CodeGenInstruction &insn, 147 InstrUID uid) 148 : RecognizableInstrBase(insn), Rec(insn.TheDef), Name(Rec->getName().str()), 149 Is32Bit(false), Is64Bit(false), Operands(&insn.Operands.OperandList), 150 UID(uid), Spec(&tables.specForUID(uid)) { 151 // Check for 64-bit inst which does not require REX 152 // FIXME: Is there some better way to check for In64BitMode? 153 std::vector<Record *> Predicates = Rec->getValueAsListOfDefs("Predicates"); 154 for (unsigned i = 0, e = Predicates.size(); i != e; ++i) { 155 if (Predicates[i]->getName().contains("Not64Bit") || 156 Predicates[i]->getName().contains("In32Bit")) { 157 Is32Bit = true; 158 break; 159 } 160 if (Predicates[i]->getName().contains("In64Bit")) { 161 Is64Bit = true; 162 break; 163 } 164 } 165 } 166 167 void RecognizableInstr::processInstr(DisassemblerTables &tables, 168 const CodeGenInstruction &insn, 169 InstrUID uid) { 170 if (!insn.TheDef->isSubClassOf("X86Inst")) 171 return; 172 RecognizableInstr recogInstr(tables, insn, uid); 173 174 if (!recogInstr.shouldBeEmitted()) 175 return; 176 recogInstr.emitInstructionSpecifier(); 177 recogInstr.emitDecodePath(tables); 178 } 179 180 #define EVEX_KB(n) \ 181 (HasEVEX_KZ && HasEVEX_B \ 182 ? n##_KZ_B \ 183 : (HasEVEX_K && HasEVEX_B \ 184 ? n##_K_B \ 185 : (HasEVEX_KZ ? n##_KZ \ 186 : (HasEVEX_K ? n##_K : (HasEVEX_B ? n##_B : n))))) 187 188 InstructionContext RecognizableInstr::insnContext() const { 189 InstructionContext insnContext; 190 191 if (Encoding == X86Local::EVEX) { 192 if (HasVEX_L && HasEVEX_L2) { 193 errs() << "Don't support VEX.L if EVEX_L2 is enabled: " << Name << "\n"; 194 llvm_unreachable("Don't support VEX.L if EVEX_L2 is enabled"); 195 } 196 // VEX_L & VEX_W 197 if (!EncodeRC && HasVEX_L && HasREX_W) { 198 if (OpPrefix == X86Local::PD) 199 insnContext = EVEX_KB(IC_EVEX_L_W_OPSIZE); 200 else if (OpPrefix == X86Local::XS) 201 insnContext = EVEX_KB(IC_EVEX_L_W_XS); 202 else if (OpPrefix == X86Local::XD) 203 insnContext = EVEX_KB(IC_EVEX_L_W_XD); 204 else if (OpPrefix == X86Local::PS) 205 insnContext = EVEX_KB(IC_EVEX_L_W); 206 else { 207 errs() << "Instruction does not use a prefix: " << Name << "\n"; 208 llvm_unreachable("Invalid prefix"); 209 } 210 } else if (!EncodeRC && HasVEX_L) { 211 // VEX_L 212 if (OpPrefix == X86Local::PD) 213 insnContext = EVEX_KB(IC_EVEX_L_OPSIZE); 214 else if (OpPrefix == X86Local::XS) 215 insnContext = EVEX_KB(IC_EVEX_L_XS); 216 else if (OpPrefix == X86Local::XD) 217 insnContext = EVEX_KB(IC_EVEX_L_XD); 218 else if (OpPrefix == X86Local::PS) 219 insnContext = EVEX_KB(IC_EVEX_L); 220 else { 221 errs() << "Instruction does not use a prefix: " << Name << "\n"; 222 llvm_unreachable("Invalid prefix"); 223 } 224 } else if (!EncodeRC && HasEVEX_L2 && HasREX_W) { 225 // EVEX_L2 & VEX_W 226 if (OpPrefix == X86Local::PD) 227 insnContext = EVEX_KB(IC_EVEX_L2_W_OPSIZE); 228 else if (OpPrefix == X86Local::XS) 229 insnContext = EVEX_KB(IC_EVEX_L2_W_XS); 230 else if (OpPrefix == X86Local::XD) 231 insnContext = EVEX_KB(IC_EVEX_L2_W_XD); 232 else if (OpPrefix == X86Local::PS) 233 insnContext = EVEX_KB(IC_EVEX_L2_W); 234 else { 235 errs() << "Instruction does not use a prefix: " << Name << "\n"; 236 llvm_unreachable("Invalid prefix"); 237 } 238 } else if (!EncodeRC && HasEVEX_L2) { 239 // EVEX_L2 240 if (OpPrefix == X86Local::PD) 241 insnContext = EVEX_KB(IC_EVEX_L2_OPSIZE); 242 else if (OpPrefix == X86Local::XD) 243 insnContext = EVEX_KB(IC_EVEX_L2_XD); 244 else if (OpPrefix == X86Local::XS) 245 insnContext = EVEX_KB(IC_EVEX_L2_XS); 246 else if (OpPrefix == X86Local::PS) 247 insnContext = EVEX_KB(IC_EVEX_L2); 248 else { 249 errs() << "Instruction does not use a prefix: " << Name << "\n"; 250 llvm_unreachable("Invalid prefix"); 251 } 252 } else if (HasREX_W) { 253 // VEX_W 254 if (OpPrefix == X86Local::PD) 255 insnContext = EVEX_KB(IC_EVEX_W_OPSIZE); 256 else if (OpPrefix == X86Local::XS) 257 insnContext = EVEX_KB(IC_EVEX_W_XS); 258 else if (OpPrefix == X86Local::XD) 259 insnContext = EVEX_KB(IC_EVEX_W_XD); 260 else if (OpPrefix == X86Local::PS) 261 insnContext = EVEX_KB(IC_EVEX_W); 262 else { 263 errs() << "Instruction does not use a prefix: " << Name << "\n"; 264 llvm_unreachable("Invalid prefix"); 265 } 266 } 267 // No L, no W 268 else if (OpPrefix == X86Local::PD) { 269 if (AdSize == X86Local::AdSize32) 270 insnContext = IC_EVEX_OPSIZE_ADSIZE; 271 else 272 insnContext = EVEX_KB(IC_EVEX_OPSIZE); 273 } else if (OpPrefix == X86Local::XD) 274 insnContext = EVEX_KB(IC_EVEX_XD); 275 else if (OpPrefix == X86Local::XS) 276 insnContext = EVEX_KB(IC_EVEX_XS); 277 else if (OpPrefix == X86Local::PS) 278 insnContext = EVEX_KB(IC_EVEX); 279 else { 280 errs() << "Instruction does not use a prefix: " << Name << "\n"; 281 llvm_unreachable("Invalid prefix"); 282 } 283 /// eof EVEX 284 } else if (Encoding == X86Local::VEX || Encoding == X86Local::XOP) { 285 if (HasVEX_L && HasREX_W) { 286 if (OpPrefix == X86Local::PD) 287 insnContext = IC_VEX_L_W_OPSIZE; 288 else if (OpPrefix == X86Local::XS) 289 insnContext = IC_VEX_L_W_XS; 290 else if (OpPrefix == X86Local::XD) 291 insnContext = IC_VEX_L_W_XD; 292 else if (OpPrefix == X86Local::PS) 293 insnContext = IC_VEX_L_W; 294 else { 295 errs() << "Instruction does not use a prefix: " << Name << "\n"; 296 llvm_unreachable("Invalid prefix"); 297 } 298 } else if (OpPrefix == X86Local::PD && HasVEX_L) 299 insnContext = IC_VEX_L_OPSIZE; 300 else if (OpPrefix == X86Local::PD && HasREX_W) 301 insnContext = IC_VEX_W_OPSIZE; 302 else if (OpPrefix == X86Local::PD) 303 insnContext = IC_VEX_OPSIZE; 304 else if (HasVEX_L && OpPrefix == X86Local::XS) 305 insnContext = IC_VEX_L_XS; 306 else if (HasVEX_L && OpPrefix == X86Local::XD) 307 insnContext = IC_VEX_L_XD; 308 else if (HasREX_W && OpPrefix == X86Local::XS) 309 insnContext = IC_VEX_W_XS; 310 else if (HasREX_W && OpPrefix == X86Local::XD) 311 insnContext = IC_VEX_W_XD; 312 else if (HasREX_W && OpPrefix == X86Local::PS) 313 insnContext = IC_VEX_W; 314 else if (HasVEX_L && OpPrefix == X86Local::PS) 315 insnContext = IC_VEX_L; 316 else if (OpPrefix == X86Local::XD) 317 insnContext = IC_VEX_XD; 318 else if (OpPrefix == X86Local::XS) 319 insnContext = IC_VEX_XS; 320 else if (OpPrefix == X86Local::PS) 321 insnContext = IC_VEX; 322 else { 323 errs() << "Instruction does not use a prefix: " << Name << "\n"; 324 llvm_unreachable("Invalid prefix"); 325 } 326 } else if (Is64Bit || HasREX_W || AdSize == X86Local::AdSize64) { 327 if (HasREX_W && (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)) 328 insnContext = IC_64BIT_REXW_OPSIZE; 329 else if (HasREX_W && AdSize == X86Local::AdSize32) 330 insnContext = IC_64BIT_REXW_ADSIZE; 331 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD) 332 insnContext = IC_64BIT_XD_OPSIZE; 333 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS) 334 insnContext = IC_64BIT_XS_OPSIZE; 335 else if (AdSize == X86Local::AdSize32 && OpPrefix == X86Local::PD) 336 insnContext = IC_64BIT_OPSIZE_ADSIZE; 337 else if (OpSize == X86Local::OpSize16 && AdSize == X86Local::AdSize32) 338 insnContext = IC_64BIT_OPSIZE_ADSIZE; 339 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD) 340 insnContext = IC_64BIT_OPSIZE; 341 else if (AdSize == X86Local::AdSize32) 342 insnContext = IC_64BIT_ADSIZE; 343 else if (HasREX_W && OpPrefix == X86Local::XS) 344 insnContext = IC_64BIT_REXW_XS; 345 else if (HasREX_W && OpPrefix == X86Local::XD) 346 insnContext = IC_64BIT_REXW_XD; 347 else if (OpPrefix == X86Local::XD) 348 insnContext = IC_64BIT_XD; 349 else if (OpPrefix == X86Local::XS) 350 insnContext = IC_64BIT_XS; 351 else if (ExplicitREX2Prefix) 352 insnContext = IC_64BIT_REX2; 353 else if (HasREX_W) 354 insnContext = IC_64BIT_REXW; 355 else 356 insnContext = IC_64BIT; 357 } else { 358 if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD) 359 insnContext = IC_XD_OPSIZE; 360 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS) 361 insnContext = IC_XS_OPSIZE; 362 else if (AdSize == X86Local::AdSize16 && OpPrefix == X86Local::XD) 363 insnContext = IC_XD_ADSIZE; 364 else if (AdSize == X86Local::AdSize16 && OpPrefix == X86Local::XS) 365 insnContext = IC_XS_ADSIZE; 366 else if (AdSize == X86Local::AdSize16 && OpPrefix == X86Local::PD) 367 insnContext = IC_OPSIZE_ADSIZE; 368 else if (OpSize == X86Local::OpSize16 && AdSize == X86Local::AdSize16) 369 insnContext = IC_OPSIZE_ADSIZE; 370 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD) 371 insnContext = IC_OPSIZE; 372 else if (AdSize == X86Local::AdSize16) 373 insnContext = IC_ADSIZE; 374 else if (OpPrefix == X86Local::XD) 375 insnContext = IC_XD; 376 else if (OpPrefix == X86Local::XS) 377 insnContext = IC_XS; 378 else 379 insnContext = IC; 380 } 381 382 return insnContext; 383 } 384 385 void RecognizableInstr::adjustOperandEncoding(OperandEncoding &encoding) { 386 // The scaling factor for AVX512 compressed displacement encoding is an 387 // instruction attribute. Adjust the ModRM encoding type to include the 388 // scale for compressed displacement. 389 if ((encoding != ENCODING_RM && encoding != ENCODING_VSIB && 390 encoding != ENCODING_SIB) || 391 CD8_Scale == 0) 392 return; 393 encoding = (OperandEncoding)(encoding + Log2_32(CD8_Scale)); 394 assert(((encoding >= ENCODING_RM && encoding <= ENCODING_RM_CD64) || 395 (encoding == ENCODING_SIB) || 396 (encoding >= ENCODING_VSIB && encoding <= ENCODING_VSIB_CD64)) && 397 "Invalid CDisp scaling"); 398 } 399 400 void RecognizableInstr::handleOperand( 401 bool optional, unsigned &operandIndex, unsigned &physicalOperandIndex, 402 unsigned numPhysicalOperands, const unsigned *operandMapping, 403 OperandEncoding (*encodingFromString)(const std::string &, 404 uint8_t OpSize)) { 405 if (optional) { 406 if (physicalOperandIndex >= numPhysicalOperands) 407 return; 408 } else { 409 assert(physicalOperandIndex < numPhysicalOperands); 410 } 411 412 while (operandMapping[operandIndex] != operandIndex) { 413 Spec->operands[operandIndex].encoding = ENCODING_DUP; 414 Spec->operands[operandIndex].type = 415 (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]); 416 ++operandIndex; 417 } 418 419 StringRef typeName = (*Operands)[operandIndex].Rec->getName(); 420 421 OperandEncoding encoding = encodingFromString(std::string(typeName), OpSize); 422 // Adjust the encoding type for an operand based on the instruction. 423 adjustOperandEncoding(encoding); 424 Spec->operands[operandIndex].encoding = encoding; 425 Spec->operands[operandIndex].type = 426 typeFromString(std::string(typeName), HasREX_W, OpSize); 427 428 ++operandIndex; 429 ++physicalOperandIndex; 430 } 431 432 void RecognizableInstr::emitInstructionSpecifier() { 433 Spec->name = Name; 434 435 Spec->insnContext = insnContext(); 436 437 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands; 438 439 unsigned numOperands = OperandList.size(); 440 unsigned numPhysicalOperands = 0; 441 442 // operandMapping maps from operands in OperandList to their originals. 443 // If operandMapping[i] != i, then the entry is a duplicate. 444 unsigned operandMapping[X86_MAX_OPERANDS]; 445 assert(numOperands <= X86_MAX_OPERANDS && 446 "X86_MAX_OPERANDS is not large enough"); 447 448 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) { 449 if (!OperandList[operandIndex].Constraints.empty()) { 450 const CGIOperandList::ConstraintInfo &Constraint = 451 OperandList[operandIndex].Constraints[0]; 452 if (Constraint.isTied()) { 453 operandMapping[operandIndex] = operandIndex; 454 operandMapping[Constraint.getTiedOperand()] = operandIndex; 455 } else { 456 ++numPhysicalOperands; 457 operandMapping[operandIndex] = operandIndex; 458 } 459 } else { 460 ++numPhysicalOperands; 461 operandMapping[operandIndex] = operandIndex; 462 } 463 } 464 465 #define HANDLE_OPERAND(class) \ 466 handleOperand(false, operandIndex, physicalOperandIndex, \ 467 numPhysicalOperands, operandMapping, \ 468 class##EncodingFromString); 469 470 #define HANDLE_OPTIONAL(class) \ 471 handleOperand(true, operandIndex, physicalOperandIndex, numPhysicalOperands, \ 472 operandMapping, class##EncodingFromString); 473 474 // operandIndex should always be < numOperands 475 unsigned operandIndex = 0; 476 // physicalOperandIndex should always be < numPhysicalOperands 477 unsigned physicalOperandIndex = 0; 478 479 #ifndef NDEBUG 480 // Given the set of prefix bits, how many additional operands does the 481 // instruction have? 482 unsigned additionalOperands = 0; 483 if (HasVEX_4V) 484 ++additionalOperands; 485 if (HasEVEX_K) 486 ++additionalOperands; 487 #endif 488 489 switch (Form) { 490 default: 491 llvm_unreachable("Unhandled form"); 492 case X86Local::PrefixByte: 493 return; 494 case X86Local::RawFrmSrc: 495 HANDLE_OPERAND(relocation); 496 return; 497 case X86Local::RawFrmDst: 498 HANDLE_OPERAND(relocation); 499 return; 500 case X86Local::RawFrmDstSrc: 501 HANDLE_OPERAND(relocation); 502 HANDLE_OPERAND(relocation); 503 return; 504 case X86Local::RawFrm: 505 // Operand 1 (optional) is an address or immediate. 506 assert(numPhysicalOperands <= 1 && 507 "Unexpected number of operands for RawFrm"); 508 HANDLE_OPTIONAL(relocation) 509 break; 510 case X86Local::RawFrmMemOffs: 511 // Operand 1 is an address. 512 HANDLE_OPERAND(relocation); 513 break; 514 case X86Local::AddRegFrm: 515 // Operand 1 is added to the opcode. 516 // Operand 2 (optional) is an address. 517 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 && 518 "Unexpected number of operands for AddRegFrm"); 519 HANDLE_OPERAND(opcodeModifier) 520 HANDLE_OPTIONAL(relocation) 521 break; 522 case X86Local::AddCCFrm: 523 // Operand 1 (optional) is an address or immediate. 524 assert(numPhysicalOperands == 2 && 525 "Unexpected number of operands for AddCCFrm"); 526 HANDLE_OPERAND(relocation) 527 HANDLE_OPERAND(opcodeModifier) 528 break; 529 case X86Local::MRMDestReg: 530 // Operand 1 is a register operand in the R/M field. 531 // - In AVX512 there may be a mask operand here - 532 // Operand 2 is a register operand in the Reg/Opcode field. 533 // - In AVX, there is a register operand in the VEX.vvvv field here - 534 // Operand 3 (optional) is an immediate. 535 assert(numPhysicalOperands >= 2 + additionalOperands && 536 numPhysicalOperands <= 3 + additionalOperands && 537 "Unexpected number of operands for MRMDestReg"); 538 539 HANDLE_OPERAND(rmRegister) 540 if (HasEVEX_K) 541 HANDLE_OPERAND(writemaskRegister) 542 543 if (HasVEX_4V) 544 // FIXME: In AVX, the register below becomes the one encoded 545 // in ModRMVEX and the one above the one in the VEX.VVVV field 546 HANDLE_OPERAND(vvvvRegister) 547 548 HANDLE_OPERAND(roRegister) 549 HANDLE_OPTIONAL(immediate) 550 break; 551 case X86Local::MRMDestMem4VOp3CC: 552 // Operand 1 is a register operand in the Reg/Opcode field. 553 // Operand 2 is a register operand in the R/M field. 554 // Operand 3 is VEX.vvvv 555 // Operand 4 is condition code. 556 assert(numPhysicalOperands == 4 && 557 "Unexpected number of operands for MRMDestMem4VOp3CC"); 558 HANDLE_OPERAND(roRegister) 559 HANDLE_OPERAND(memory) 560 HANDLE_OPERAND(vvvvRegister) 561 HANDLE_OPERAND(opcodeModifier) 562 break; 563 case X86Local::MRMDestMem: 564 case X86Local::MRMDestMemFSIB: 565 // Operand 1 is a memory operand (possibly SIB-extended) 566 // Operand 2 is a register operand in the Reg/Opcode field. 567 // - In AVX, there is a register operand in the VEX.vvvv field here - 568 // Operand 3 (optional) is an immediate. 569 assert(numPhysicalOperands >= 2 + additionalOperands && 570 numPhysicalOperands <= 3 + additionalOperands && 571 "Unexpected number of operands for MRMDestMemFrm with VEX_4V"); 572 573 HANDLE_OPERAND(memory) 574 575 if (HasEVEX_K) 576 HANDLE_OPERAND(writemaskRegister) 577 578 if (HasVEX_4V) 579 // FIXME: In AVX, the register below becomes the one encoded 580 // in ModRMVEX and the one above the one in the VEX.VVVV field 581 HANDLE_OPERAND(vvvvRegister) 582 583 HANDLE_OPERAND(roRegister) 584 HANDLE_OPTIONAL(immediate) 585 break; 586 case X86Local::MRMSrcReg: 587 // Operand 1 is a register operand in the Reg/Opcode field. 588 // Operand 2 is a register operand in the R/M field. 589 // - In AVX, there is a register operand in the VEX.vvvv field here - 590 // Operand 3 (optional) is an immediate. 591 // Operand 4 (optional) is an immediate. 592 593 assert(numPhysicalOperands >= 2 + additionalOperands && 594 numPhysicalOperands <= 4 + additionalOperands && 595 "Unexpected number of operands for MRMSrcRegFrm"); 596 597 HANDLE_OPERAND(roRegister) 598 599 if (HasEVEX_K) 600 HANDLE_OPERAND(writemaskRegister) 601 602 if (HasVEX_4V) 603 // FIXME: In AVX, the register below becomes the one encoded 604 // in ModRMVEX and the one above the one in the VEX.VVVV field 605 HANDLE_OPERAND(vvvvRegister) 606 607 HANDLE_OPERAND(rmRegister) 608 HANDLE_OPTIONAL(immediate) 609 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4 610 break; 611 case X86Local::MRMSrcReg4VOp3: 612 assert(numPhysicalOperands == 3 && 613 "Unexpected number of operands for MRMSrcReg4VOp3Frm"); 614 HANDLE_OPERAND(roRegister) 615 HANDLE_OPERAND(rmRegister) 616 HANDLE_OPERAND(vvvvRegister) 617 break; 618 case X86Local::MRMSrcRegOp4: 619 assert(numPhysicalOperands >= 4 && numPhysicalOperands <= 5 && 620 "Unexpected number of operands for MRMSrcRegOp4Frm"); 621 HANDLE_OPERAND(roRegister) 622 HANDLE_OPERAND(vvvvRegister) 623 HANDLE_OPERAND(immediate) // Register in imm[7:4] 624 HANDLE_OPERAND(rmRegister) 625 HANDLE_OPTIONAL(immediate) 626 break; 627 case X86Local::MRMSrcRegCC: 628 assert(numPhysicalOperands == 3 && 629 "Unexpected number of operands for MRMSrcRegCC"); 630 HANDLE_OPERAND(roRegister) 631 HANDLE_OPERAND(rmRegister) 632 HANDLE_OPERAND(opcodeModifier) 633 break; 634 case X86Local::MRMSrcMem: 635 case X86Local::MRMSrcMemFSIB: 636 // Operand 1 is a register operand in the Reg/Opcode field. 637 // Operand 2 is a memory operand (possibly SIB-extended) 638 // - In AVX, there is a register operand in the VEX.vvvv field here - 639 // Operand 3 (optional) is an immediate. 640 641 assert(numPhysicalOperands >= 2 + additionalOperands && 642 numPhysicalOperands <= 4 + additionalOperands && 643 "Unexpected number of operands for MRMSrcMemFrm"); 644 645 HANDLE_OPERAND(roRegister) 646 647 if (HasEVEX_K) 648 HANDLE_OPERAND(writemaskRegister) 649 650 if (HasVEX_4V) 651 // FIXME: In AVX, the register below becomes the one encoded 652 // in ModRMVEX and the one above the one in the VEX.VVVV field 653 HANDLE_OPERAND(vvvvRegister) 654 655 HANDLE_OPERAND(memory) 656 HANDLE_OPTIONAL(immediate) 657 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4 658 break; 659 case X86Local::MRMSrcMem4VOp3: 660 assert(numPhysicalOperands == 3 && 661 "Unexpected number of operands for MRMSrcMem4VOp3Frm"); 662 HANDLE_OPERAND(roRegister) 663 HANDLE_OPERAND(memory) 664 HANDLE_OPERAND(vvvvRegister) 665 break; 666 case X86Local::MRMSrcMemOp4: 667 assert(numPhysicalOperands >= 4 && numPhysicalOperands <= 5 && 668 "Unexpected number of operands for MRMSrcMemOp4Frm"); 669 HANDLE_OPERAND(roRegister) 670 HANDLE_OPERAND(vvvvRegister) 671 HANDLE_OPERAND(immediate) // Register in imm[7:4] 672 HANDLE_OPERAND(memory) 673 HANDLE_OPTIONAL(immediate) 674 break; 675 case X86Local::MRMSrcMemCC: 676 assert(numPhysicalOperands == 3 && 677 "Unexpected number of operands for MRMSrcMemCC"); 678 HANDLE_OPERAND(roRegister) 679 HANDLE_OPERAND(memory) 680 HANDLE_OPERAND(opcodeModifier) 681 break; 682 case X86Local::MRMXrCC: 683 assert(numPhysicalOperands == 2 && 684 "Unexpected number of operands for MRMXrCC"); 685 HANDLE_OPERAND(rmRegister) 686 HANDLE_OPERAND(opcodeModifier) 687 break; 688 case X86Local::MRMr0: 689 // Operand 1 is a register operand in the R/M field. 690 HANDLE_OPERAND(roRegister) 691 break; 692 case X86Local::MRMXr: 693 case X86Local::MRM0r: 694 case X86Local::MRM1r: 695 case X86Local::MRM2r: 696 case X86Local::MRM3r: 697 case X86Local::MRM4r: 698 case X86Local::MRM5r: 699 case X86Local::MRM6r: 700 case X86Local::MRM7r: 701 // Operand 1 is a register operand in the R/M field. 702 // Operand 2 (optional) is an immediate or relocation. 703 // Operand 3 (optional) is an immediate. 704 assert(numPhysicalOperands >= 0 + additionalOperands && 705 numPhysicalOperands <= 3 + additionalOperands && 706 "Unexpected number of operands for MRMnr"); 707 708 if (HasVEX_4V) 709 HANDLE_OPERAND(vvvvRegister) 710 711 if (HasEVEX_K) 712 HANDLE_OPERAND(writemaskRegister) 713 HANDLE_OPTIONAL(rmRegister) 714 HANDLE_OPTIONAL(relocation) 715 HANDLE_OPTIONAL(immediate) 716 break; 717 case X86Local::MRMXmCC: 718 assert(numPhysicalOperands == 2 && 719 "Unexpected number of operands for MRMXm"); 720 HANDLE_OPERAND(memory) 721 HANDLE_OPERAND(opcodeModifier) 722 break; 723 case X86Local::MRMXm: 724 case X86Local::MRM0m: 725 case X86Local::MRM1m: 726 case X86Local::MRM2m: 727 case X86Local::MRM3m: 728 case X86Local::MRM4m: 729 case X86Local::MRM5m: 730 case X86Local::MRM6m: 731 case X86Local::MRM7m: 732 // Operand 1 is a memory operand (possibly SIB-extended) 733 // Operand 2 (optional) is an immediate or relocation. 734 assert(numPhysicalOperands >= 1 + additionalOperands && 735 numPhysicalOperands <= 2 + additionalOperands && 736 "Unexpected number of operands for MRMnm"); 737 738 if (HasVEX_4V) 739 HANDLE_OPERAND(vvvvRegister) 740 if (HasEVEX_K) 741 HANDLE_OPERAND(writemaskRegister) 742 HANDLE_OPERAND(memory) 743 HANDLE_OPTIONAL(relocation) 744 break; 745 case X86Local::RawFrmImm8: 746 // operand 1 is a 16-bit immediate 747 // operand 2 is an 8-bit immediate 748 assert(numPhysicalOperands == 2 && 749 "Unexpected number of operands for X86Local::RawFrmImm8"); 750 HANDLE_OPERAND(immediate) 751 HANDLE_OPERAND(immediate) 752 break; 753 case X86Local::RawFrmImm16: 754 // operand 1 is a 16-bit immediate 755 // operand 2 is a 16-bit immediate 756 HANDLE_OPERAND(immediate) 757 HANDLE_OPERAND(immediate) 758 break; 759 case X86Local::MRM0X: 760 case X86Local::MRM1X: 761 case X86Local::MRM2X: 762 case X86Local::MRM3X: 763 case X86Local::MRM4X: 764 case X86Local::MRM5X: 765 case X86Local::MRM6X: 766 case X86Local::MRM7X: 767 #define MAP(from, to) case X86Local::MRM_##from: 768 X86_INSTR_MRM_MAPPING 769 #undef MAP 770 HANDLE_OPTIONAL(relocation) 771 break; 772 } 773 774 #undef HANDLE_OPERAND 775 #undef HANDLE_OPTIONAL 776 } 777 778 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const { 779 // Special cases where the LLVM tables are not complete 780 781 #define MAP(from, to) case X86Local::MRM_##from: 782 783 std::optional<OpcodeType> opcodeType; 784 switch (OpMap) { 785 default: 786 llvm_unreachable("Invalid map!"); 787 case X86Local::OB: 788 opcodeType = ONEBYTE; 789 break; 790 case X86Local::TB: 791 opcodeType = TWOBYTE; 792 break; 793 case X86Local::T8: 794 opcodeType = THREEBYTE_38; 795 break; 796 case X86Local::TA: 797 opcodeType = THREEBYTE_3A; 798 break; 799 case X86Local::XOP8: 800 opcodeType = XOP8_MAP; 801 break; 802 case X86Local::XOP9: 803 opcodeType = XOP9_MAP; 804 break; 805 case X86Local::XOPA: 806 opcodeType = XOPA_MAP; 807 break; 808 case X86Local::ThreeDNow: 809 opcodeType = THREEDNOW_MAP; 810 break; 811 case X86Local::T_MAP4: 812 opcodeType = MAP4; 813 break; 814 case X86Local::T_MAP5: 815 opcodeType = MAP5; 816 break; 817 case X86Local::T_MAP6: 818 opcodeType = MAP6; 819 break; 820 case X86Local::T_MAP7: 821 opcodeType = MAP7; 822 break; 823 } 824 825 std::unique_ptr<ModRMFilter> filter; 826 switch (Form) { 827 default: 828 llvm_unreachable("Invalid form!"); 829 case X86Local::Pseudo: 830 llvm_unreachable("Pseudo should not be emitted!"); 831 case X86Local::RawFrm: 832 case X86Local::AddRegFrm: 833 case X86Local::RawFrmMemOffs: 834 case X86Local::RawFrmSrc: 835 case X86Local::RawFrmDst: 836 case X86Local::RawFrmDstSrc: 837 case X86Local::RawFrmImm8: 838 case X86Local::RawFrmImm16: 839 case X86Local::AddCCFrm: 840 case X86Local::PrefixByte: 841 filter = std::make_unique<DumbFilter>(); 842 break; 843 case X86Local::MRMDestReg: 844 case X86Local::MRMSrcReg: 845 case X86Local::MRMSrcReg4VOp3: 846 case X86Local::MRMSrcRegOp4: 847 case X86Local::MRMSrcRegCC: 848 case X86Local::MRMXrCC: 849 case X86Local::MRMXr: 850 filter = std::make_unique<ModFilter>(true); 851 break; 852 case X86Local::MRMDestMem: 853 case X86Local::MRMDestMem4VOp3CC: 854 case X86Local::MRMDestMemFSIB: 855 case X86Local::MRMSrcMem: 856 case X86Local::MRMSrcMemFSIB: 857 case X86Local::MRMSrcMem4VOp3: 858 case X86Local::MRMSrcMemOp4: 859 case X86Local::MRMSrcMemCC: 860 case X86Local::MRMXmCC: 861 case X86Local::MRMXm: 862 filter = std::make_unique<ModFilter>(false); 863 break; 864 case X86Local::MRM0r: 865 case X86Local::MRM1r: 866 case X86Local::MRM2r: 867 case X86Local::MRM3r: 868 case X86Local::MRM4r: 869 case X86Local::MRM5r: 870 case X86Local::MRM6r: 871 case X86Local::MRM7r: 872 filter = std::make_unique<ExtendedFilter>(true, Form - X86Local::MRM0r); 873 break; 874 case X86Local::MRM0X: 875 case X86Local::MRM1X: 876 case X86Local::MRM2X: 877 case X86Local::MRM3X: 878 case X86Local::MRM4X: 879 case X86Local::MRM5X: 880 case X86Local::MRM6X: 881 case X86Local::MRM7X: 882 filter = std::make_unique<ExtendedFilter>(true, Form - X86Local::MRM0X); 883 break; 884 case X86Local::MRMr0: 885 filter = std::make_unique<ExtendedRMFilter>(true, Form - X86Local::MRMr0); 886 break; 887 case X86Local::MRM0m: 888 case X86Local::MRM1m: 889 case X86Local::MRM2m: 890 case X86Local::MRM3m: 891 case X86Local::MRM4m: 892 case X86Local::MRM5m: 893 case X86Local::MRM6m: 894 case X86Local::MRM7m: 895 filter = std::make_unique<ExtendedFilter>(false, Form - X86Local::MRM0m); 896 break; 897 X86_INSTR_MRM_MAPPING 898 filter = std::make_unique<ExactFilter>(0xC0 + Form - X86Local::MRM_C0); 899 break; 900 } // switch (Form) 901 902 uint8_t opcodeToSet = Opcode; 903 904 unsigned AddressSize = 0; 905 switch (AdSize) { 906 case X86Local::AdSize16: 907 AddressSize = 16; 908 break; 909 case X86Local::AdSize32: 910 AddressSize = 32; 911 break; 912 case X86Local::AdSize64: 913 AddressSize = 64; 914 break; 915 } 916 917 assert(opcodeType && "Opcode type not set"); 918 assert(filter && "Filter not set"); 919 920 if (Form == X86Local::AddRegFrm || Form == X86Local::MRMSrcRegCC || 921 Form == X86Local::MRMSrcMemCC || Form == X86Local::MRMXrCC || 922 Form == X86Local::MRMXmCC || Form == X86Local::AddCCFrm || 923 Form == X86Local::MRMDestMem4VOp3CC) { 924 uint8_t Count = Form == X86Local::AddRegFrm ? 8 : 16; 925 assert(((opcodeToSet % Count) == 0) && "ADDREG_FRM opcode not aligned"); 926 927 uint8_t currentOpcode; 928 929 for (currentOpcode = opcodeToSet; 930 currentOpcode < (uint8_t)(opcodeToSet + Count); ++currentOpcode) 931 tables.setTableFields(*opcodeType, insnContext(), currentOpcode, *filter, 932 UID, Is32Bit, OpPrefix == 0, 933 IgnoresVEX_L || EncodeRC, IgnoresW, AddressSize); 934 } else { 935 tables.setTableFields(*opcodeType, insnContext(), opcodeToSet, *filter, UID, 936 Is32Bit, OpPrefix == 0, IgnoresVEX_L || EncodeRC, 937 IgnoresW, AddressSize); 938 } 939 940 #undef MAP 941 } 942 943 #define TYPE(str, type) \ 944 if (s == str) \ 945 return type; 946 OperandType RecognizableInstr::typeFromString(const std::string &s, 947 bool hasREX_W, uint8_t OpSize) { 948 if (hasREX_W) { 949 // For instructions with a REX_W prefix, a declared 32-bit register encoding 950 // is special. 951 TYPE("GR32", TYPE_R32) 952 } 953 if (OpSize == X86Local::OpSize16) { 954 // For OpSize16 instructions, a declared 16-bit register or 955 // immediate encoding is special. 956 TYPE("GR16", TYPE_Rv) 957 } else if (OpSize == X86Local::OpSize32) { 958 // For OpSize32 instructions, a declared 32-bit register or 959 // immediate encoding is special. 960 TYPE("GR32", TYPE_Rv) 961 } 962 TYPE("i16mem", TYPE_M) 963 TYPE("i16imm", TYPE_IMM) 964 TYPE("i16i8imm", TYPE_IMM) 965 TYPE("GR16", TYPE_R16) 966 TYPE("GR16orGR32orGR64", TYPE_R16) 967 TYPE("i32mem", TYPE_M) 968 TYPE("i32imm", TYPE_IMM) 969 TYPE("i32i8imm", TYPE_IMM) 970 TYPE("GR32", TYPE_R32) 971 TYPE("GR32orGR64", TYPE_R32) 972 TYPE("i64mem", TYPE_M) 973 TYPE("i64i32imm", TYPE_IMM) 974 TYPE("i64i8imm", TYPE_IMM) 975 TYPE("GR64", TYPE_R64) 976 TYPE("i8mem", TYPE_M) 977 TYPE("i8imm", TYPE_IMM) 978 TYPE("u4imm", TYPE_UIMM8) 979 TYPE("u8imm", TYPE_UIMM8) 980 TYPE("i16u8imm", TYPE_UIMM8) 981 TYPE("i32u8imm", TYPE_UIMM8) 982 TYPE("i64u8imm", TYPE_UIMM8) 983 TYPE("GR8", TYPE_R8) 984 TYPE("VR128", TYPE_XMM) 985 TYPE("VR128X", TYPE_XMM) 986 TYPE("f128mem", TYPE_M) 987 TYPE("f256mem", TYPE_M) 988 TYPE("f512mem", TYPE_M) 989 TYPE("FR128", TYPE_XMM) 990 TYPE("FR64", TYPE_XMM) 991 TYPE("FR64X", TYPE_XMM) 992 TYPE("f64mem", TYPE_M) 993 TYPE("sdmem", TYPE_M) 994 TYPE("FR16X", TYPE_XMM) 995 TYPE("FR32", TYPE_XMM) 996 TYPE("FR32X", TYPE_XMM) 997 TYPE("f32mem", TYPE_M) 998 TYPE("f16mem", TYPE_M) 999 TYPE("ssmem", TYPE_M) 1000 TYPE("shmem", TYPE_M) 1001 TYPE("RST", TYPE_ST) 1002 TYPE("RSTi", TYPE_ST) 1003 TYPE("i128mem", TYPE_M) 1004 TYPE("i256mem", TYPE_M) 1005 TYPE("i512mem", TYPE_M) 1006 TYPE("i512mem_GR16", TYPE_M) 1007 TYPE("i512mem_GR32", TYPE_M) 1008 TYPE("i512mem_GR64", TYPE_M) 1009 TYPE("i64i32imm_brtarget", TYPE_REL) 1010 TYPE("i16imm_brtarget", TYPE_REL) 1011 TYPE("i32imm_brtarget", TYPE_REL) 1012 TYPE("ccode", TYPE_IMM) 1013 TYPE("AVX512RC", TYPE_IMM) 1014 TYPE("brtarget32", TYPE_REL) 1015 TYPE("brtarget16", TYPE_REL) 1016 TYPE("brtarget8", TYPE_REL) 1017 TYPE("f80mem", TYPE_M) 1018 TYPE("lea64_32mem", TYPE_M) 1019 TYPE("lea64mem", TYPE_M) 1020 TYPE("VR64", TYPE_MM64) 1021 TYPE("i64imm", TYPE_IMM) 1022 TYPE("anymem", TYPE_M) 1023 TYPE("opaquemem", TYPE_M) 1024 TYPE("sibmem", TYPE_MSIB) 1025 TYPE("SEGMENT_REG", TYPE_SEGMENTREG) 1026 TYPE("DEBUG_REG", TYPE_DEBUGREG) 1027 TYPE("CONTROL_REG", TYPE_CONTROLREG) 1028 TYPE("srcidx8", TYPE_SRCIDX) 1029 TYPE("srcidx16", TYPE_SRCIDX) 1030 TYPE("srcidx32", TYPE_SRCIDX) 1031 TYPE("srcidx64", TYPE_SRCIDX) 1032 TYPE("dstidx8", TYPE_DSTIDX) 1033 TYPE("dstidx16", TYPE_DSTIDX) 1034 TYPE("dstidx32", TYPE_DSTIDX) 1035 TYPE("dstidx64", TYPE_DSTIDX) 1036 TYPE("offset16_8", TYPE_MOFFS) 1037 TYPE("offset16_16", TYPE_MOFFS) 1038 TYPE("offset16_32", TYPE_MOFFS) 1039 TYPE("offset32_8", TYPE_MOFFS) 1040 TYPE("offset32_16", TYPE_MOFFS) 1041 TYPE("offset32_32", TYPE_MOFFS) 1042 TYPE("offset32_64", TYPE_MOFFS) 1043 TYPE("offset64_8", TYPE_MOFFS) 1044 TYPE("offset64_16", TYPE_MOFFS) 1045 TYPE("offset64_32", TYPE_MOFFS) 1046 TYPE("offset64_64", TYPE_MOFFS) 1047 TYPE("VR256", TYPE_YMM) 1048 TYPE("VR256X", TYPE_YMM) 1049 TYPE("VR512", TYPE_ZMM) 1050 TYPE("VK1", TYPE_VK) 1051 TYPE("VK1WM", TYPE_VK) 1052 TYPE("VK2", TYPE_VK) 1053 TYPE("VK2WM", TYPE_VK) 1054 TYPE("VK4", TYPE_VK) 1055 TYPE("VK4WM", TYPE_VK) 1056 TYPE("VK8", TYPE_VK) 1057 TYPE("VK8WM", TYPE_VK) 1058 TYPE("VK16", TYPE_VK) 1059 TYPE("VK16WM", TYPE_VK) 1060 TYPE("VK32", TYPE_VK) 1061 TYPE("VK32WM", TYPE_VK) 1062 TYPE("VK64", TYPE_VK) 1063 TYPE("VK64WM", TYPE_VK) 1064 TYPE("VK1Pair", TYPE_VK_PAIR) 1065 TYPE("VK2Pair", TYPE_VK_PAIR) 1066 TYPE("VK4Pair", TYPE_VK_PAIR) 1067 TYPE("VK8Pair", TYPE_VK_PAIR) 1068 TYPE("VK16Pair", TYPE_VK_PAIR) 1069 TYPE("vx64mem", TYPE_MVSIBX) 1070 TYPE("vx128mem", TYPE_MVSIBX) 1071 TYPE("vx256mem", TYPE_MVSIBX) 1072 TYPE("vy128mem", TYPE_MVSIBY) 1073 TYPE("vy256mem", TYPE_MVSIBY) 1074 TYPE("vx64xmem", TYPE_MVSIBX) 1075 TYPE("vx128xmem", TYPE_MVSIBX) 1076 TYPE("vx256xmem", TYPE_MVSIBX) 1077 TYPE("vy128xmem", TYPE_MVSIBY) 1078 TYPE("vy256xmem", TYPE_MVSIBY) 1079 TYPE("vy512xmem", TYPE_MVSIBY) 1080 TYPE("vz256mem", TYPE_MVSIBZ) 1081 TYPE("vz512mem", TYPE_MVSIBZ) 1082 TYPE("BNDR", TYPE_BNDR) 1083 TYPE("TILE", TYPE_TMM) 1084 errs() << "Unhandled type string " << s << "\n"; 1085 llvm_unreachable("Unhandled type string"); 1086 } 1087 #undef TYPE 1088 1089 #define ENCODING(str, encoding) \ 1090 if (s == str) \ 1091 return encoding; 1092 OperandEncoding 1093 RecognizableInstr::immediateEncodingFromString(const std::string &s, 1094 uint8_t OpSize) { 1095 if (OpSize != X86Local::OpSize16) { 1096 // For instructions without an OpSize prefix, a declared 16-bit register or 1097 // immediate encoding is special. 1098 ENCODING("i16imm", ENCODING_IW) 1099 } 1100 ENCODING("i32i8imm", ENCODING_IB) 1101 ENCODING("AVX512RC", ENCODING_IRC) 1102 ENCODING("i16imm", ENCODING_Iv) 1103 ENCODING("i16i8imm", ENCODING_IB) 1104 ENCODING("i32imm", ENCODING_Iv) 1105 ENCODING("i64i32imm", ENCODING_ID) 1106 ENCODING("i64i8imm", ENCODING_IB) 1107 ENCODING("i8imm", ENCODING_IB) 1108 ENCODING("u4imm", ENCODING_IB) 1109 ENCODING("u8imm", ENCODING_IB) 1110 ENCODING("i16u8imm", ENCODING_IB) 1111 ENCODING("i32u8imm", ENCODING_IB) 1112 ENCODING("i64u8imm", ENCODING_IB) 1113 // This is not a typo. Instructions like BLENDVPD put 1114 // register IDs in 8-bit immediates nowadays. 1115 ENCODING("FR32", ENCODING_IB) 1116 ENCODING("FR64", ENCODING_IB) 1117 ENCODING("FR128", ENCODING_IB) 1118 ENCODING("VR128", ENCODING_IB) 1119 ENCODING("VR256", ENCODING_IB) 1120 ENCODING("FR16X", ENCODING_IB) 1121 ENCODING("FR32X", ENCODING_IB) 1122 ENCODING("FR64X", ENCODING_IB) 1123 ENCODING("VR128X", ENCODING_IB) 1124 ENCODING("VR256X", ENCODING_IB) 1125 ENCODING("VR512", ENCODING_IB) 1126 ENCODING("TILE", ENCODING_IB) 1127 errs() << "Unhandled immediate encoding " << s << "\n"; 1128 llvm_unreachable("Unhandled immediate encoding"); 1129 } 1130 1131 OperandEncoding 1132 RecognizableInstr::rmRegisterEncodingFromString(const std::string &s, 1133 uint8_t OpSize) { 1134 ENCODING("RST", ENCODING_FP) 1135 ENCODING("RSTi", ENCODING_FP) 1136 ENCODING("GR16", ENCODING_RM) 1137 ENCODING("GR16orGR32orGR64", ENCODING_RM) 1138 ENCODING("GR32", ENCODING_RM) 1139 ENCODING("GR32orGR64", ENCODING_RM) 1140 ENCODING("GR64", ENCODING_RM) 1141 ENCODING("GR8", ENCODING_RM) 1142 ENCODING("VR128", ENCODING_RM) 1143 ENCODING("VR128X", ENCODING_RM) 1144 ENCODING("FR128", ENCODING_RM) 1145 ENCODING("FR64", ENCODING_RM) 1146 ENCODING("FR32", ENCODING_RM) 1147 ENCODING("FR64X", ENCODING_RM) 1148 ENCODING("FR32X", ENCODING_RM) 1149 ENCODING("FR16X", ENCODING_RM) 1150 ENCODING("VR64", ENCODING_RM) 1151 ENCODING("VR256", ENCODING_RM) 1152 ENCODING("VR256X", ENCODING_RM) 1153 ENCODING("VR512", ENCODING_RM) 1154 ENCODING("VK1", ENCODING_RM) 1155 ENCODING("VK2", ENCODING_RM) 1156 ENCODING("VK4", ENCODING_RM) 1157 ENCODING("VK8", ENCODING_RM) 1158 ENCODING("VK16", ENCODING_RM) 1159 ENCODING("VK32", ENCODING_RM) 1160 ENCODING("VK64", ENCODING_RM) 1161 ENCODING("BNDR", ENCODING_RM) 1162 ENCODING("TILE", ENCODING_RM) 1163 errs() << "Unhandled R/M register encoding " << s << "\n"; 1164 llvm_unreachable("Unhandled R/M register encoding"); 1165 } 1166 1167 OperandEncoding 1168 RecognizableInstr::roRegisterEncodingFromString(const std::string &s, 1169 uint8_t OpSize) { 1170 ENCODING("GR16", ENCODING_REG) 1171 ENCODING("GR16orGR32orGR64", ENCODING_REG) 1172 ENCODING("GR32", ENCODING_REG) 1173 ENCODING("GR32orGR64", ENCODING_REG) 1174 ENCODING("GR64", ENCODING_REG) 1175 ENCODING("GR8", ENCODING_REG) 1176 ENCODING("VR128", ENCODING_REG) 1177 ENCODING("FR128", ENCODING_REG) 1178 ENCODING("FR64", ENCODING_REG) 1179 ENCODING("FR32", ENCODING_REG) 1180 ENCODING("VR64", ENCODING_REG) 1181 ENCODING("SEGMENT_REG", ENCODING_REG) 1182 ENCODING("DEBUG_REG", ENCODING_REG) 1183 ENCODING("CONTROL_REG", ENCODING_REG) 1184 ENCODING("VR256", ENCODING_REG) 1185 ENCODING("VR256X", ENCODING_REG) 1186 ENCODING("VR128X", ENCODING_REG) 1187 ENCODING("FR64X", ENCODING_REG) 1188 ENCODING("FR32X", ENCODING_REG) 1189 ENCODING("FR16X", ENCODING_REG) 1190 ENCODING("VR512", ENCODING_REG) 1191 ENCODING("VK1", ENCODING_REG) 1192 ENCODING("VK2", ENCODING_REG) 1193 ENCODING("VK4", ENCODING_REG) 1194 ENCODING("VK8", ENCODING_REG) 1195 ENCODING("VK16", ENCODING_REG) 1196 ENCODING("VK32", ENCODING_REG) 1197 ENCODING("VK64", ENCODING_REG) 1198 ENCODING("VK1Pair", ENCODING_REG) 1199 ENCODING("VK2Pair", ENCODING_REG) 1200 ENCODING("VK4Pair", ENCODING_REG) 1201 ENCODING("VK8Pair", ENCODING_REG) 1202 ENCODING("VK16Pair", ENCODING_REG) 1203 ENCODING("VK1WM", ENCODING_REG) 1204 ENCODING("VK2WM", ENCODING_REG) 1205 ENCODING("VK4WM", ENCODING_REG) 1206 ENCODING("VK8WM", ENCODING_REG) 1207 ENCODING("VK16WM", ENCODING_REG) 1208 ENCODING("VK32WM", ENCODING_REG) 1209 ENCODING("VK64WM", ENCODING_REG) 1210 ENCODING("BNDR", ENCODING_REG) 1211 ENCODING("TILE", ENCODING_REG) 1212 errs() << "Unhandled reg/opcode register encoding " << s << "\n"; 1213 llvm_unreachable("Unhandled reg/opcode register encoding"); 1214 } 1215 1216 OperandEncoding 1217 RecognizableInstr::vvvvRegisterEncodingFromString(const std::string &s, 1218 uint8_t OpSize) { 1219 ENCODING("GR32", ENCODING_VVVV) 1220 ENCODING("GR64", ENCODING_VVVV) 1221 ENCODING("FR32", ENCODING_VVVV) 1222 ENCODING("FR128", ENCODING_VVVV) 1223 ENCODING("FR64", ENCODING_VVVV) 1224 ENCODING("VR128", ENCODING_VVVV) 1225 ENCODING("VR256", ENCODING_VVVV) 1226 ENCODING("FR16X", ENCODING_VVVV) 1227 ENCODING("FR32X", ENCODING_VVVV) 1228 ENCODING("FR64X", ENCODING_VVVV) 1229 ENCODING("VR128X", ENCODING_VVVV) 1230 ENCODING("VR256X", ENCODING_VVVV) 1231 ENCODING("VR512", ENCODING_VVVV) 1232 ENCODING("VK1", ENCODING_VVVV) 1233 ENCODING("VK2", ENCODING_VVVV) 1234 ENCODING("VK4", ENCODING_VVVV) 1235 ENCODING("VK8", ENCODING_VVVV) 1236 ENCODING("VK16", ENCODING_VVVV) 1237 ENCODING("VK32", ENCODING_VVVV) 1238 ENCODING("VK64", ENCODING_VVVV) 1239 ENCODING("TILE", ENCODING_VVVV) 1240 errs() << "Unhandled VEX.vvvv register encoding " << s << "\n"; 1241 llvm_unreachable("Unhandled VEX.vvvv register encoding"); 1242 } 1243 1244 OperandEncoding 1245 RecognizableInstr::writemaskRegisterEncodingFromString(const std::string &s, 1246 uint8_t OpSize) { 1247 ENCODING("VK1WM", ENCODING_WRITEMASK) 1248 ENCODING("VK2WM", ENCODING_WRITEMASK) 1249 ENCODING("VK4WM", ENCODING_WRITEMASK) 1250 ENCODING("VK8WM", ENCODING_WRITEMASK) 1251 ENCODING("VK16WM", ENCODING_WRITEMASK) 1252 ENCODING("VK32WM", ENCODING_WRITEMASK) 1253 ENCODING("VK64WM", ENCODING_WRITEMASK) 1254 errs() << "Unhandled mask register encoding " << s << "\n"; 1255 llvm_unreachable("Unhandled mask register encoding"); 1256 } 1257 1258 OperandEncoding 1259 RecognizableInstr::memoryEncodingFromString(const std::string &s, 1260 uint8_t OpSize) { 1261 ENCODING("i16mem", ENCODING_RM) 1262 ENCODING("i32mem", ENCODING_RM) 1263 ENCODING("i64mem", ENCODING_RM) 1264 ENCODING("i8mem", ENCODING_RM) 1265 ENCODING("shmem", ENCODING_RM) 1266 ENCODING("ssmem", ENCODING_RM) 1267 ENCODING("sdmem", ENCODING_RM) 1268 ENCODING("f128mem", ENCODING_RM) 1269 ENCODING("f256mem", ENCODING_RM) 1270 ENCODING("f512mem", ENCODING_RM) 1271 ENCODING("f64mem", ENCODING_RM) 1272 ENCODING("f32mem", ENCODING_RM) 1273 ENCODING("f16mem", ENCODING_RM) 1274 ENCODING("i128mem", ENCODING_RM) 1275 ENCODING("i256mem", ENCODING_RM) 1276 ENCODING("i512mem", ENCODING_RM) 1277 ENCODING("i512mem_GR16", ENCODING_RM) 1278 ENCODING("i512mem_GR32", ENCODING_RM) 1279 ENCODING("i512mem_GR64", ENCODING_RM) 1280 ENCODING("f80mem", ENCODING_RM) 1281 ENCODING("lea64_32mem", ENCODING_RM) 1282 ENCODING("lea64mem", ENCODING_RM) 1283 ENCODING("anymem", ENCODING_RM) 1284 ENCODING("opaquemem", ENCODING_RM) 1285 ENCODING("sibmem", ENCODING_SIB) 1286 ENCODING("vx64mem", ENCODING_VSIB) 1287 ENCODING("vx128mem", ENCODING_VSIB) 1288 ENCODING("vx256mem", ENCODING_VSIB) 1289 ENCODING("vy128mem", ENCODING_VSIB) 1290 ENCODING("vy256mem", ENCODING_VSIB) 1291 ENCODING("vx64xmem", ENCODING_VSIB) 1292 ENCODING("vx128xmem", ENCODING_VSIB) 1293 ENCODING("vx256xmem", ENCODING_VSIB) 1294 ENCODING("vy128xmem", ENCODING_VSIB) 1295 ENCODING("vy256xmem", ENCODING_VSIB) 1296 ENCODING("vy512xmem", ENCODING_VSIB) 1297 ENCODING("vz256mem", ENCODING_VSIB) 1298 ENCODING("vz512mem", ENCODING_VSIB) 1299 errs() << "Unhandled memory encoding " << s << "\n"; 1300 llvm_unreachable("Unhandled memory encoding"); 1301 } 1302 1303 OperandEncoding 1304 RecognizableInstr::relocationEncodingFromString(const std::string &s, 1305 uint8_t OpSize) { 1306 if (OpSize != X86Local::OpSize16) { 1307 // For instructions without an OpSize prefix, a declared 16-bit register or 1308 // immediate encoding is special. 1309 ENCODING("i16imm", ENCODING_IW) 1310 } 1311 ENCODING("i16imm", ENCODING_Iv) 1312 ENCODING("i16i8imm", ENCODING_IB) 1313 ENCODING("i32imm", ENCODING_Iv) 1314 ENCODING("i32i8imm", ENCODING_IB) 1315 ENCODING("i64i32imm", ENCODING_ID) 1316 ENCODING("i64i8imm", ENCODING_IB) 1317 ENCODING("i8imm", ENCODING_IB) 1318 ENCODING("u8imm", ENCODING_IB) 1319 ENCODING("i16u8imm", ENCODING_IB) 1320 ENCODING("i32u8imm", ENCODING_IB) 1321 ENCODING("i64u8imm", ENCODING_IB) 1322 ENCODING("i64i32imm_brtarget", ENCODING_ID) 1323 ENCODING("i16imm_brtarget", ENCODING_IW) 1324 ENCODING("i32imm_brtarget", ENCODING_ID) 1325 ENCODING("brtarget32", ENCODING_ID) 1326 ENCODING("brtarget16", ENCODING_IW) 1327 ENCODING("brtarget8", ENCODING_IB) 1328 ENCODING("i64imm", ENCODING_IO) 1329 ENCODING("offset16_8", ENCODING_Ia) 1330 ENCODING("offset16_16", ENCODING_Ia) 1331 ENCODING("offset16_32", ENCODING_Ia) 1332 ENCODING("offset32_8", ENCODING_Ia) 1333 ENCODING("offset32_16", ENCODING_Ia) 1334 ENCODING("offset32_32", ENCODING_Ia) 1335 ENCODING("offset32_64", ENCODING_Ia) 1336 ENCODING("offset64_8", ENCODING_Ia) 1337 ENCODING("offset64_16", ENCODING_Ia) 1338 ENCODING("offset64_32", ENCODING_Ia) 1339 ENCODING("offset64_64", ENCODING_Ia) 1340 ENCODING("srcidx8", ENCODING_SI) 1341 ENCODING("srcidx16", ENCODING_SI) 1342 ENCODING("srcidx32", ENCODING_SI) 1343 ENCODING("srcidx64", ENCODING_SI) 1344 ENCODING("dstidx8", ENCODING_DI) 1345 ENCODING("dstidx16", ENCODING_DI) 1346 ENCODING("dstidx32", ENCODING_DI) 1347 ENCODING("dstidx64", ENCODING_DI) 1348 errs() << "Unhandled relocation encoding " << s << "\n"; 1349 llvm_unreachable("Unhandled relocation encoding"); 1350 } 1351 1352 OperandEncoding 1353 RecognizableInstr::opcodeModifierEncodingFromString(const std::string &s, 1354 uint8_t OpSize) { 1355 ENCODING("GR32", ENCODING_Rv) 1356 ENCODING("GR64", ENCODING_RO) 1357 ENCODING("GR16", ENCODING_Rv) 1358 ENCODING("GR8", ENCODING_RB) 1359 ENCODING("ccode", ENCODING_CC) 1360 errs() << "Unhandled opcode modifier encoding " << s << "\n"; 1361 llvm_unreachable("Unhandled opcode modifier encoding"); 1362 } 1363 #undef ENCODING 1364