1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file is part of the X86 Disassembler Emitter. 10 // It contains the implementation of a single recognizable instruction. 11 // Documentation for the disassembler emitter in general can be found in 12 // X86DisassemblerEmitter.h. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #include "X86RecognizableInstr.h" 17 #include "X86DisassemblerShared.h" 18 #include "X86DisassemblerTables.h" 19 #include "X86ModRMFilters.h" 20 #include "llvm/Support/ErrorHandling.h" 21 #include "llvm/TableGen/Record.h" 22 #include <string> 23 24 using namespace llvm; 25 using namespace X86Disassembler; 26 27 std::string X86Disassembler::getMnemonic(const CodeGenInstruction *I, unsigned Variant) { 28 std::string AsmString = I->FlattenAsmStringVariants(I->AsmString, Variant); 29 StringRef Mnemonic(AsmString); 30 // Extract a mnemonic assuming it's separated by \t 31 Mnemonic = Mnemonic.take_until([](char C) { return C == '\t'; }); 32 33 // Special case: CMOVCC, JCC, SETCC have "${cond}" in mnemonic. 34 // Replace it with "CC" in-place. 35 size_t CondPos = Mnemonic.find("${cond}"); 36 if (CondPos != StringRef::npos) 37 Mnemonic = AsmString.replace(CondPos, StringRef::npos, "CC"); 38 return Mnemonic.upper(); 39 } 40 41 bool X86Disassembler::isRegisterOperand(const Record *Rec) { 42 return Rec->isSubClassOf("RegisterClass") || 43 Rec->isSubClassOf("RegisterOperand"); 44 } 45 46 bool X86Disassembler::isMemoryOperand(const Record *Rec) { 47 return Rec->isSubClassOf("Operand") && 48 Rec->getValueAsString("OperandType") == "OPERAND_MEMORY"; 49 } 50 51 bool X86Disassembler::isImmediateOperand(const Record *Rec) { 52 return Rec->isSubClassOf("Operand") && 53 Rec->getValueAsString("OperandType") == "OPERAND_IMMEDIATE"; 54 } 55 56 unsigned X86Disassembler::getRegOperandSize(const Record *RegRec) { 57 if (RegRec->isSubClassOf("RegisterClass")) 58 return RegRec->getValueAsInt("Alignment"); 59 if (RegRec->isSubClassOf("RegisterOperand")) 60 return RegRec->getValueAsDef("RegClass")->getValueAsInt("Alignment"); 61 62 llvm_unreachable("Register operand's size not known!"); 63 } 64 65 unsigned X86Disassembler::getMemOperandSize(const Record *MemRec) { 66 if (MemRec->isSubClassOf("X86MemOperand")) 67 return MemRec->getValueAsInt("Size"); 68 69 llvm_unreachable("Memory operand's size not known!"); 70 } 71 72 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit. 73 /// Useful for switch statements and the like. 74 /// 75 /// @param init - A reference to the BitsInit to be decoded. 76 /// @return - The field, with the first bit in the BitsInit as the lowest 77 /// order bit. 78 static uint8_t byteFromBitsInit(BitsInit &init) { 79 int width = init.getNumBits(); 80 81 assert(width <= 8 && "Field is too large for uint8_t!"); 82 83 int index; 84 uint8_t mask = 0x01; 85 86 uint8_t ret = 0; 87 88 for (index = 0; index < width; index++) { 89 if (cast<BitInit>(init.getBit(index))->getValue()) 90 ret |= mask; 91 92 mask <<= 1; 93 } 94 95 return ret; 96 } 97 98 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the 99 /// name of the field. 100 /// 101 /// @param rec - The record from which to extract the value. 102 /// @param name - The name of the field in the record. 103 /// @return - The field, as translated by byteFromBitsInit(). 104 static uint8_t byteFromRec(const Record* rec, StringRef name) { 105 BitsInit* bits = rec->getValueAsBitsInit(name); 106 return byteFromBitsInit(*bits); 107 } 108 109 RecognizableInstrBase::RecognizableInstrBase(const CodeGenInstruction &insn) { 110 const Record *Rec = insn.TheDef; 111 assert(Rec->isSubClassOf("X86Inst") && "Not a X86 Instruction"); 112 OpPrefix = byteFromRec(Rec, "OpPrefixBits"); 113 OpMap = byteFromRec(Rec, "OpMapBits"); 114 Opcode = byteFromRec(Rec, "Opcode"); 115 Form = byteFromRec(Rec, "FormBits"); 116 Encoding = byteFromRec(Rec, "OpEncBits"); 117 OpSize = byteFromRec(Rec, "OpSizeBits"); 118 AdSize = byteFromRec(Rec, "AdSizeBits"); 119 HasREX_W = Rec->getValueAsBit("hasREX_W"); 120 HasVEX_4V = Rec->getValueAsBit("hasVEX_4V"); 121 IgnoresW = Rec->getValueAsBit("IgnoresW"); 122 IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L"); 123 HasEVEX_L2 = Rec->getValueAsBit("hasEVEX_L2"); 124 HasEVEX_K = Rec->getValueAsBit("hasEVEX_K"); 125 HasEVEX_KZ = Rec->getValueAsBit("hasEVEX_Z"); 126 HasEVEX_B = Rec->getValueAsBit("hasEVEX_B"); 127 IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly"); 128 IsAsmParserOnly = Rec->getValueAsBit("isAsmParserOnly"); 129 ForceDisassemble = Rec->getValueAsBit("ForceDisassemble"); 130 CD8_Scale = byteFromRec(Rec, "CD8_Scale"); 131 HasVEX_L = Rec->getValueAsBit("hasVEX_L"); 132 133 EncodeRC = HasEVEX_B && 134 (Form == X86Local::MRMDestReg || Form == X86Local::MRMSrcReg); 135 } 136 137 bool RecognizableInstrBase::shouldBeEmitted() const { 138 return Form != X86Local::Pseudo && (!IsCodeGenOnly || ForceDisassemble) && 139 !IsAsmParserOnly; 140 } 141 142 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables, 143 const CodeGenInstruction &insn, 144 InstrUID uid) 145 : RecognizableInstrBase(insn), Rec(insn.TheDef), Name(Rec->getName().str()), 146 Is32Bit(false), Is64Bit(false), Operands(&insn.Operands.OperandList), 147 UID(uid), Spec(&tables.specForUID(uid)) { 148 // Check for 64-bit inst which does not require REX 149 // FIXME: Is there some better way to check for In64BitMode? 150 std::vector<Record *> Predicates = Rec->getValueAsListOfDefs("Predicates"); 151 for (unsigned i = 0, e = Predicates.size(); i != e; ++i) { 152 if (Predicates[i]->getName().contains("Not64Bit") || 153 Predicates[i]->getName().contains("In32Bit")) { 154 Is32Bit = true; 155 break; 156 } 157 if (Predicates[i]->getName().contains("In64Bit")) { 158 Is64Bit = true; 159 break; 160 } 161 } 162 } 163 164 void RecognizableInstr::processInstr(DisassemblerTables &tables, 165 const CodeGenInstruction &insn, 166 InstrUID uid) { 167 if (!insn.TheDef->isSubClassOf("X86Inst")) 168 return; 169 RecognizableInstr recogInstr(tables, insn, uid); 170 171 if (!recogInstr.shouldBeEmitted()) 172 return; 173 recogInstr.emitInstructionSpecifier(); 174 recogInstr.emitDecodePath(tables); 175 } 176 177 #define EVEX_KB(n) (HasEVEX_KZ && HasEVEX_B ? n##_KZ_B : \ 178 (HasEVEX_K && HasEVEX_B ? n##_K_B : \ 179 (HasEVEX_KZ ? n##_KZ : \ 180 (HasEVEX_K? n##_K : (HasEVEX_B ? n##_B : n))))) 181 182 InstructionContext RecognizableInstr::insnContext() const { 183 InstructionContext insnContext; 184 185 if (Encoding == X86Local::EVEX) { 186 if (HasVEX_L && HasEVEX_L2) { 187 errs() << "Don't support VEX.L if EVEX_L2 is enabled: " << Name << "\n"; 188 llvm_unreachable("Don't support VEX.L if EVEX_L2 is enabled"); 189 } 190 // VEX_L & VEX_W 191 if (!EncodeRC && HasVEX_L && HasREX_W) { 192 if (OpPrefix == X86Local::PD) 193 insnContext = EVEX_KB(IC_EVEX_L_W_OPSIZE); 194 else if (OpPrefix == X86Local::XS) 195 insnContext = EVEX_KB(IC_EVEX_L_W_XS); 196 else if (OpPrefix == X86Local::XD) 197 insnContext = EVEX_KB(IC_EVEX_L_W_XD); 198 else if (OpPrefix == X86Local::PS) 199 insnContext = EVEX_KB(IC_EVEX_L_W); 200 else { 201 errs() << "Instruction does not use a prefix: " << Name << "\n"; 202 llvm_unreachable("Invalid prefix"); 203 } 204 } else if (!EncodeRC && HasVEX_L) { 205 // VEX_L 206 if (OpPrefix == X86Local::PD) 207 insnContext = EVEX_KB(IC_EVEX_L_OPSIZE); 208 else if (OpPrefix == X86Local::XS) 209 insnContext = EVEX_KB(IC_EVEX_L_XS); 210 else if (OpPrefix == X86Local::XD) 211 insnContext = EVEX_KB(IC_EVEX_L_XD); 212 else if (OpPrefix == X86Local::PS) 213 insnContext = EVEX_KB(IC_EVEX_L); 214 else { 215 errs() << "Instruction does not use a prefix: " << Name << "\n"; 216 llvm_unreachable("Invalid prefix"); 217 } 218 } else if (!EncodeRC && HasEVEX_L2 && HasREX_W) { 219 // EVEX_L2 & VEX_W 220 if (OpPrefix == X86Local::PD) 221 insnContext = EVEX_KB(IC_EVEX_L2_W_OPSIZE); 222 else if (OpPrefix == X86Local::XS) 223 insnContext = EVEX_KB(IC_EVEX_L2_W_XS); 224 else if (OpPrefix == X86Local::XD) 225 insnContext = EVEX_KB(IC_EVEX_L2_W_XD); 226 else if (OpPrefix == X86Local::PS) 227 insnContext = EVEX_KB(IC_EVEX_L2_W); 228 else { 229 errs() << "Instruction does not use a prefix: " << Name << "\n"; 230 llvm_unreachable("Invalid prefix"); 231 } 232 } else if (!EncodeRC && HasEVEX_L2) { 233 // EVEX_L2 234 if (OpPrefix == X86Local::PD) 235 insnContext = EVEX_KB(IC_EVEX_L2_OPSIZE); 236 else if (OpPrefix == X86Local::XD) 237 insnContext = EVEX_KB(IC_EVEX_L2_XD); 238 else if (OpPrefix == X86Local::XS) 239 insnContext = EVEX_KB(IC_EVEX_L2_XS); 240 else if (OpPrefix == X86Local::PS) 241 insnContext = EVEX_KB(IC_EVEX_L2); 242 else { 243 errs() << "Instruction does not use a prefix: " << Name << "\n"; 244 llvm_unreachable("Invalid prefix"); 245 } 246 } 247 else if (HasREX_W) { 248 // VEX_W 249 if (OpPrefix == X86Local::PD) 250 insnContext = EVEX_KB(IC_EVEX_W_OPSIZE); 251 else if (OpPrefix == X86Local::XS) 252 insnContext = EVEX_KB(IC_EVEX_W_XS); 253 else if (OpPrefix == X86Local::XD) 254 insnContext = EVEX_KB(IC_EVEX_W_XD); 255 else if (OpPrefix == X86Local::PS) 256 insnContext = EVEX_KB(IC_EVEX_W); 257 else { 258 errs() << "Instruction does not use a prefix: " << Name << "\n"; 259 llvm_unreachable("Invalid prefix"); 260 } 261 } 262 // No L, no W 263 else if (OpPrefix == X86Local::PD) 264 insnContext = EVEX_KB(IC_EVEX_OPSIZE); 265 else if (OpPrefix == X86Local::XD) 266 insnContext = EVEX_KB(IC_EVEX_XD); 267 else if (OpPrefix == X86Local::XS) 268 insnContext = EVEX_KB(IC_EVEX_XS); 269 else if (OpPrefix == X86Local::PS) 270 insnContext = EVEX_KB(IC_EVEX); 271 else { 272 errs() << "Instruction does not use a prefix: " << Name << "\n"; 273 llvm_unreachable("Invalid prefix"); 274 } 275 /// eof EVEX 276 } else if (Encoding == X86Local::VEX || Encoding == X86Local::XOP) { 277 if (HasVEX_L && HasREX_W) { 278 if (OpPrefix == X86Local::PD) 279 insnContext = IC_VEX_L_W_OPSIZE; 280 else if (OpPrefix == X86Local::XS) 281 insnContext = IC_VEX_L_W_XS; 282 else if (OpPrefix == X86Local::XD) 283 insnContext = IC_VEX_L_W_XD; 284 else if (OpPrefix == X86Local::PS) 285 insnContext = IC_VEX_L_W; 286 else { 287 errs() << "Instruction does not use a prefix: " << Name << "\n"; 288 llvm_unreachable("Invalid prefix"); 289 } 290 } else if (OpPrefix == X86Local::PD && HasVEX_L) 291 insnContext = IC_VEX_L_OPSIZE; 292 else if (OpPrefix == X86Local::PD && HasREX_W) 293 insnContext = IC_VEX_W_OPSIZE; 294 else if (OpPrefix == X86Local::PD) 295 insnContext = IC_VEX_OPSIZE; 296 else if (HasVEX_L && OpPrefix == X86Local::XS) 297 insnContext = IC_VEX_L_XS; 298 else if (HasVEX_L && OpPrefix == X86Local::XD) 299 insnContext = IC_VEX_L_XD; 300 else if (HasREX_W && OpPrefix == X86Local::XS) 301 insnContext = IC_VEX_W_XS; 302 else if (HasREX_W && OpPrefix == X86Local::XD) 303 insnContext = IC_VEX_W_XD; 304 else if (HasREX_W && OpPrefix == X86Local::PS) 305 insnContext = IC_VEX_W; 306 else if (HasVEX_L && OpPrefix == X86Local::PS) 307 insnContext = IC_VEX_L; 308 else if (OpPrefix == X86Local::XD) 309 insnContext = IC_VEX_XD; 310 else if (OpPrefix == X86Local::XS) 311 insnContext = IC_VEX_XS; 312 else if (OpPrefix == X86Local::PS) 313 insnContext = IC_VEX; 314 else { 315 errs() << "Instruction does not use a prefix: " << Name << "\n"; 316 llvm_unreachable("Invalid prefix"); 317 } 318 } else if (Is64Bit || HasREX_W || AdSize == X86Local::AdSize64) { 319 if (HasREX_W && (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)) 320 insnContext = IC_64BIT_REXW_OPSIZE; 321 else if (HasREX_W && AdSize == X86Local::AdSize32) 322 insnContext = IC_64BIT_REXW_ADSIZE; 323 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD) 324 insnContext = IC_64BIT_XD_OPSIZE; 325 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS) 326 insnContext = IC_64BIT_XS_OPSIZE; 327 else if (AdSize == X86Local::AdSize32 && OpPrefix == X86Local::PD) 328 insnContext = IC_64BIT_OPSIZE_ADSIZE; 329 else if (OpSize == X86Local::OpSize16 && AdSize == X86Local::AdSize32) 330 insnContext = IC_64BIT_OPSIZE_ADSIZE; 331 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD) 332 insnContext = IC_64BIT_OPSIZE; 333 else if (AdSize == X86Local::AdSize32) 334 insnContext = IC_64BIT_ADSIZE; 335 else if (HasREX_W && OpPrefix == X86Local::XS) 336 insnContext = IC_64BIT_REXW_XS; 337 else if (HasREX_W && OpPrefix == X86Local::XD) 338 insnContext = IC_64BIT_REXW_XD; 339 else if (OpPrefix == X86Local::XD) 340 insnContext = IC_64BIT_XD; 341 else if (OpPrefix == X86Local::XS) 342 insnContext = IC_64BIT_XS; 343 else if (HasREX_W) 344 insnContext = IC_64BIT_REXW; 345 else 346 insnContext = IC_64BIT; 347 } else { 348 if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD) 349 insnContext = IC_XD_OPSIZE; 350 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS) 351 insnContext = IC_XS_OPSIZE; 352 else if (AdSize == X86Local::AdSize16 && OpPrefix == X86Local::XD) 353 insnContext = IC_XD_ADSIZE; 354 else if (AdSize == X86Local::AdSize16 && OpPrefix == X86Local::XS) 355 insnContext = IC_XS_ADSIZE; 356 else if (AdSize == X86Local::AdSize16 && OpPrefix == X86Local::PD) 357 insnContext = IC_OPSIZE_ADSIZE; 358 else if (OpSize == X86Local::OpSize16 && AdSize == X86Local::AdSize16) 359 insnContext = IC_OPSIZE_ADSIZE; 360 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD) 361 insnContext = IC_OPSIZE; 362 else if (AdSize == X86Local::AdSize16) 363 insnContext = IC_ADSIZE; 364 else if (OpPrefix == X86Local::XD) 365 insnContext = IC_XD; 366 else if (OpPrefix == X86Local::XS) 367 insnContext = IC_XS; 368 else 369 insnContext = IC; 370 } 371 372 return insnContext; 373 } 374 375 void RecognizableInstr::adjustOperandEncoding(OperandEncoding &encoding) { 376 // The scaling factor for AVX512 compressed displacement encoding is an 377 // instruction attribute. Adjust the ModRM encoding type to include the 378 // scale for compressed displacement. 379 if ((encoding != ENCODING_RM && 380 encoding != ENCODING_VSIB && 381 encoding != ENCODING_SIB) ||CD8_Scale == 0) 382 return; 383 encoding = (OperandEncoding)(encoding + Log2_32(CD8_Scale)); 384 assert(((encoding >= ENCODING_RM && encoding <= ENCODING_RM_CD64) || 385 (encoding == ENCODING_SIB) || 386 (encoding >= ENCODING_VSIB && encoding <= ENCODING_VSIB_CD64)) && 387 "Invalid CDisp scaling"); 388 } 389 390 void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex, 391 unsigned &physicalOperandIndex, 392 unsigned numPhysicalOperands, 393 const unsigned *operandMapping, 394 OperandEncoding (*encodingFromString) 395 (const std::string&, 396 uint8_t OpSize)) { 397 if (optional) { 398 if (physicalOperandIndex >= numPhysicalOperands) 399 return; 400 } else { 401 assert(physicalOperandIndex < numPhysicalOperands); 402 } 403 404 while (operandMapping[operandIndex] != operandIndex) { 405 Spec->operands[operandIndex].encoding = ENCODING_DUP; 406 Spec->operands[operandIndex].type = 407 (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]); 408 ++operandIndex; 409 } 410 411 StringRef typeName = (*Operands)[operandIndex].Rec->getName(); 412 413 OperandEncoding encoding = encodingFromString(std::string(typeName), OpSize); 414 // Adjust the encoding type for an operand based on the instruction. 415 adjustOperandEncoding(encoding); 416 Spec->operands[operandIndex].encoding = encoding; 417 Spec->operands[operandIndex].type = 418 typeFromString(std::string(typeName), HasREX_W, OpSize); 419 420 ++operandIndex; 421 ++physicalOperandIndex; 422 } 423 424 void RecognizableInstr::emitInstructionSpecifier() { 425 Spec->name = Name; 426 427 Spec->insnContext = insnContext(); 428 429 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands; 430 431 unsigned numOperands = OperandList.size(); 432 unsigned numPhysicalOperands = 0; 433 434 // operandMapping maps from operands in OperandList to their originals. 435 // If operandMapping[i] != i, then the entry is a duplicate. 436 unsigned operandMapping[X86_MAX_OPERANDS]; 437 assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough"); 438 439 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) { 440 if (!OperandList[operandIndex].Constraints.empty()) { 441 const CGIOperandList::ConstraintInfo &Constraint = 442 OperandList[operandIndex].Constraints[0]; 443 if (Constraint.isTied()) { 444 operandMapping[operandIndex] = operandIndex; 445 operandMapping[Constraint.getTiedOperand()] = operandIndex; 446 } else { 447 ++numPhysicalOperands; 448 operandMapping[operandIndex] = operandIndex; 449 } 450 } else { 451 ++numPhysicalOperands; 452 operandMapping[operandIndex] = operandIndex; 453 } 454 } 455 456 #define HANDLE_OPERAND(class) \ 457 handleOperand(false, \ 458 operandIndex, \ 459 physicalOperandIndex, \ 460 numPhysicalOperands, \ 461 operandMapping, \ 462 class##EncodingFromString); 463 464 #define HANDLE_OPTIONAL(class) \ 465 handleOperand(true, \ 466 operandIndex, \ 467 physicalOperandIndex, \ 468 numPhysicalOperands, \ 469 operandMapping, \ 470 class##EncodingFromString); 471 472 // operandIndex should always be < numOperands 473 unsigned operandIndex = 0; 474 // physicalOperandIndex should always be < numPhysicalOperands 475 unsigned physicalOperandIndex = 0; 476 477 #ifndef NDEBUG 478 // Given the set of prefix bits, how many additional operands does the 479 // instruction have? 480 unsigned additionalOperands = 0; 481 if (HasVEX_4V) 482 ++additionalOperands; 483 if (HasEVEX_K) 484 ++additionalOperands; 485 #endif 486 487 switch (Form) { 488 default: llvm_unreachable("Unhandled form"); 489 case X86Local::PrefixByte: 490 return; 491 case X86Local::RawFrmSrc: 492 HANDLE_OPERAND(relocation); 493 return; 494 case X86Local::RawFrmDst: 495 HANDLE_OPERAND(relocation); 496 return; 497 case X86Local::RawFrmDstSrc: 498 HANDLE_OPERAND(relocation); 499 HANDLE_OPERAND(relocation); 500 return; 501 case X86Local::RawFrm: 502 // Operand 1 (optional) is an address or immediate. 503 assert(numPhysicalOperands <= 1 && 504 "Unexpected number of operands for RawFrm"); 505 HANDLE_OPTIONAL(relocation) 506 break; 507 case X86Local::RawFrmMemOffs: 508 // Operand 1 is an address. 509 HANDLE_OPERAND(relocation); 510 break; 511 case X86Local::AddRegFrm: 512 // Operand 1 is added to the opcode. 513 // Operand 2 (optional) is an address. 514 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 && 515 "Unexpected number of operands for AddRegFrm"); 516 HANDLE_OPERAND(opcodeModifier) 517 HANDLE_OPTIONAL(relocation) 518 break; 519 case X86Local::AddCCFrm: 520 // Operand 1 (optional) is an address or immediate. 521 assert(numPhysicalOperands == 2 && 522 "Unexpected number of operands for AddCCFrm"); 523 HANDLE_OPERAND(relocation) 524 HANDLE_OPERAND(opcodeModifier) 525 break; 526 case X86Local::MRMDestReg: 527 // Operand 1 is a register operand in the R/M field. 528 // - In AVX512 there may be a mask operand here - 529 // Operand 2 is a register operand in the Reg/Opcode field. 530 // - In AVX, there is a register operand in the VEX.vvvv field here - 531 // Operand 3 (optional) is an immediate. 532 assert(numPhysicalOperands >= 2 + additionalOperands && 533 numPhysicalOperands <= 3 + additionalOperands && 534 "Unexpected number of operands for MRMDestReg"); 535 536 HANDLE_OPERAND(rmRegister) 537 if (HasEVEX_K) 538 HANDLE_OPERAND(writemaskRegister) 539 540 if (HasVEX_4V) 541 // FIXME: In AVX, the register below becomes the one encoded 542 // in ModRMVEX and the one above the one in the VEX.VVVV field 543 HANDLE_OPERAND(vvvvRegister) 544 545 HANDLE_OPERAND(roRegister) 546 HANDLE_OPTIONAL(immediate) 547 break; 548 case X86Local::MRMDestMem4VOp3CC: 549 // Operand 1 is a register operand in the Reg/Opcode field. 550 // Operand 2 is a register operand in the R/M field. 551 // Operand 3 is VEX.vvvv 552 // Operand 4 is condition code. 553 assert(numPhysicalOperands == 4 && 554 "Unexpected number of operands for MRMDestMem4VOp3CC"); 555 HANDLE_OPERAND(roRegister) 556 HANDLE_OPERAND(memory) 557 HANDLE_OPERAND(vvvvRegister) 558 HANDLE_OPERAND(opcodeModifier) 559 break; 560 case X86Local::MRMDestMem: 561 case X86Local::MRMDestMemFSIB: 562 // Operand 1 is a memory operand (possibly SIB-extended) 563 // Operand 2 is a register operand in the Reg/Opcode field. 564 // - In AVX, there is a register operand in the VEX.vvvv field here - 565 // Operand 3 (optional) is an immediate. 566 assert(numPhysicalOperands >= 2 + additionalOperands && 567 numPhysicalOperands <= 3 + additionalOperands && 568 "Unexpected number of operands for MRMDestMemFrm with VEX_4V"); 569 570 HANDLE_OPERAND(memory) 571 572 if (HasEVEX_K) 573 HANDLE_OPERAND(writemaskRegister) 574 575 if (HasVEX_4V) 576 // FIXME: In AVX, the register below becomes the one encoded 577 // in ModRMVEX and the one above the one in the VEX.VVVV field 578 HANDLE_OPERAND(vvvvRegister) 579 580 HANDLE_OPERAND(roRegister) 581 HANDLE_OPTIONAL(immediate) 582 break; 583 case X86Local::MRMSrcReg: 584 // Operand 1 is a register operand in the Reg/Opcode field. 585 // Operand 2 is a register operand in the R/M field. 586 // - In AVX, there is a register operand in the VEX.vvvv field here - 587 // Operand 3 (optional) is an immediate. 588 // Operand 4 (optional) is an immediate. 589 590 assert(numPhysicalOperands >= 2 + additionalOperands && 591 numPhysicalOperands <= 4 + additionalOperands && 592 "Unexpected number of operands for MRMSrcRegFrm"); 593 594 HANDLE_OPERAND(roRegister) 595 596 if (HasEVEX_K) 597 HANDLE_OPERAND(writemaskRegister) 598 599 if (HasVEX_4V) 600 // FIXME: In AVX, the register below becomes the one encoded 601 // in ModRMVEX and the one above the one in the VEX.VVVV field 602 HANDLE_OPERAND(vvvvRegister) 603 604 HANDLE_OPERAND(rmRegister) 605 HANDLE_OPTIONAL(immediate) 606 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4 607 break; 608 case X86Local::MRMSrcReg4VOp3: 609 assert(numPhysicalOperands == 3 && 610 "Unexpected number of operands for MRMSrcReg4VOp3Frm"); 611 HANDLE_OPERAND(roRegister) 612 HANDLE_OPERAND(rmRegister) 613 HANDLE_OPERAND(vvvvRegister) 614 break; 615 case X86Local::MRMSrcRegOp4: 616 assert(numPhysicalOperands >= 4 && numPhysicalOperands <= 5 && 617 "Unexpected number of operands for MRMSrcRegOp4Frm"); 618 HANDLE_OPERAND(roRegister) 619 HANDLE_OPERAND(vvvvRegister) 620 HANDLE_OPERAND(immediate) // Register in imm[7:4] 621 HANDLE_OPERAND(rmRegister) 622 HANDLE_OPTIONAL(immediate) 623 break; 624 case X86Local::MRMSrcRegCC: 625 assert(numPhysicalOperands == 3 && 626 "Unexpected number of operands for MRMSrcRegCC"); 627 HANDLE_OPERAND(roRegister) 628 HANDLE_OPERAND(rmRegister) 629 HANDLE_OPERAND(opcodeModifier) 630 break; 631 case X86Local::MRMSrcMem: 632 case X86Local::MRMSrcMemFSIB: 633 // Operand 1 is a register operand in the Reg/Opcode field. 634 // Operand 2 is a memory operand (possibly SIB-extended) 635 // - In AVX, there is a register operand in the VEX.vvvv field here - 636 // Operand 3 (optional) is an immediate. 637 638 assert(numPhysicalOperands >= 2 + additionalOperands && 639 numPhysicalOperands <= 4 + additionalOperands && 640 "Unexpected number of operands for MRMSrcMemFrm"); 641 642 HANDLE_OPERAND(roRegister) 643 644 if (HasEVEX_K) 645 HANDLE_OPERAND(writemaskRegister) 646 647 if (HasVEX_4V) 648 // FIXME: In AVX, the register below becomes the one encoded 649 // in ModRMVEX and the one above the one in the VEX.VVVV field 650 HANDLE_OPERAND(vvvvRegister) 651 652 HANDLE_OPERAND(memory) 653 HANDLE_OPTIONAL(immediate) 654 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4 655 break; 656 case X86Local::MRMSrcMem4VOp3: 657 assert(numPhysicalOperands == 3 && 658 "Unexpected number of operands for MRMSrcMem4VOp3Frm"); 659 HANDLE_OPERAND(roRegister) 660 HANDLE_OPERAND(memory) 661 HANDLE_OPERAND(vvvvRegister) 662 break; 663 case X86Local::MRMSrcMemOp4: 664 assert(numPhysicalOperands >= 4 && numPhysicalOperands <= 5 && 665 "Unexpected number of operands for MRMSrcMemOp4Frm"); 666 HANDLE_OPERAND(roRegister) 667 HANDLE_OPERAND(vvvvRegister) 668 HANDLE_OPERAND(immediate) // Register in imm[7:4] 669 HANDLE_OPERAND(memory) 670 HANDLE_OPTIONAL(immediate) 671 break; 672 case X86Local::MRMSrcMemCC: 673 assert(numPhysicalOperands == 3 && 674 "Unexpected number of operands for MRMSrcMemCC"); 675 HANDLE_OPERAND(roRegister) 676 HANDLE_OPERAND(memory) 677 HANDLE_OPERAND(opcodeModifier) 678 break; 679 case X86Local::MRMXrCC: 680 assert(numPhysicalOperands == 2 && 681 "Unexpected number of operands for MRMXrCC"); 682 HANDLE_OPERAND(rmRegister) 683 HANDLE_OPERAND(opcodeModifier) 684 break; 685 case X86Local::MRMr0: 686 // Operand 1 is a register operand in the R/M field. 687 HANDLE_OPERAND(roRegister) 688 break; 689 case X86Local::MRMXr: 690 case X86Local::MRM0r: 691 case X86Local::MRM1r: 692 case X86Local::MRM2r: 693 case X86Local::MRM3r: 694 case X86Local::MRM4r: 695 case X86Local::MRM5r: 696 case X86Local::MRM6r: 697 case X86Local::MRM7r: 698 // Operand 1 is a register operand in the R/M field. 699 // Operand 2 (optional) is an immediate or relocation. 700 // Operand 3 (optional) is an immediate. 701 assert(numPhysicalOperands >= 0 + additionalOperands && 702 numPhysicalOperands <= 3 + additionalOperands && 703 "Unexpected number of operands for MRMnr"); 704 705 if (HasVEX_4V) 706 HANDLE_OPERAND(vvvvRegister) 707 708 if (HasEVEX_K) 709 HANDLE_OPERAND(writemaskRegister) 710 HANDLE_OPTIONAL(rmRegister) 711 HANDLE_OPTIONAL(relocation) 712 HANDLE_OPTIONAL(immediate) 713 break; 714 case X86Local::MRMXmCC: 715 assert(numPhysicalOperands == 2 && 716 "Unexpected number of operands for MRMXm"); 717 HANDLE_OPERAND(memory) 718 HANDLE_OPERAND(opcodeModifier) 719 break; 720 case X86Local::MRMXm: 721 case X86Local::MRM0m: 722 case X86Local::MRM1m: 723 case X86Local::MRM2m: 724 case X86Local::MRM3m: 725 case X86Local::MRM4m: 726 case X86Local::MRM5m: 727 case X86Local::MRM6m: 728 case X86Local::MRM7m: 729 // Operand 1 is a memory operand (possibly SIB-extended) 730 // Operand 2 (optional) is an immediate or relocation. 731 assert(numPhysicalOperands >= 1 + additionalOperands && 732 numPhysicalOperands <= 2 + additionalOperands && 733 "Unexpected number of operands for MRMnm"); 734 735 if (HasVEX_4V) 736 HANDLE_OPERAND(vvvvRegister) 737 if (HasEVEX_K) 738 HANDLE_OPERAND(writemaskRegister) 739 HANDLE_OPERAND(memory) 740 HANDLE_OPTIONAL(relocation) 741 break; 742 case X86Local::RawFrmImm8: 743 // operand 1 is a 16-bit immediate 744 // operand 2 is an 8-bit immediate 745 assert(numPhysicalOperands == 2 && 746 "Unexpected number of operands for X86Local::RawFrmImm8"); 747 HANDLE_OPERAND(immediate) 748 HANDLE_OPERAND(immediate) 749 break; 750 case X86Local::RawFrmImm16: 751 // operand 1 is a 16-bit immediate 752 // operand 2 is a 16-bit immediate 753 HANDLE_OPERAND(immediate) 754 HANDLE_OPERAND(immediate) 755 break; 756 case X86Local::MRM0X: 757 case X86Local::MRM1X: 758 case X86Local::MRM2X: 759 case X86Local::MRM3X: 760 case X86Local::MRM4X: 761 case X86Local::MRM5X: 762 case X86Local::MRM6X: 763 case X86Local::MRM7X: 764 #define MAP(from, to) case X86Local::MRM_##from: 765 X86_INSTR_MRM_MAPPING 766 #undef MAP 767 HANDLE_OPTIONAL(relocation) 768 break; 769 } 770 771 #undef HANDLE_OPERAND 772 #undef HANDLE_OPTIONAL 773 } 774 775 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const { 776 // Special cases where the LLVM tables are not complete 777 778 #define MAP(from, to) \ 779 case X86Local::MRM_##from: 780 781 std::optional<OpcodeType> opcodeType; 782 switch (OpMap) { 783 default: llvm_unreachable("Invalid map!"); 784 case X86Local::OB: opcodeType = ONEBYTE; break; 785 case X86Local::TB: opcodeType = TWOBYTE; break; 786 case X86Local::T8: opcodeType = THREEBYTE_38; break; 787 case X86Local::TA: opcodeType = THREEBYTE_3A; break; 788 case X86Local::XOP8: opcodeType = XOP8_MAP; break; 789 case X86Local::XOP9: opcodeType = XOP9_MAP; break; 790 case X86Local::XOPA: opcodeType = XOPA_MAP; break; 791 case X86Local::ThreeDNow: opcodeType = THREEDNOW_MAP; break; 792 case X86Local::T_MAP5: opcodeType = MAP5; break; 793 case X86Local::T_MAP6: opcodeType = MAP6; break; 794 } 795 796 std::unique_ptr<ModRMFilter> filter; 797 switch (Form) { 798 default: llvm_unreachable("Invalid form!"); 799 case X86Local::Pseudo: llvm_unreachable("Pseudo should not be emitted!"); 800 case X86Local::RawFrm: 801 case X86Local::AddRegFrm: 802 case X86Local::RawFrmMemOffs: 803 case X86Local::RawFrmSrc: 804 case X86Local::RawFrmDst: 805 case X86Local::RawFrmDstSrc: 806 case X86Local::RawFrmImm8: 807 case X86Local::RawFrmImm16: 808 case X86Local::AddCCFrm: 809 case X86Local::PrefixByte: 810 filter = std::make_unique<DumbFilter>(); 811 break; 812 case X86Local::MRMDestReg: 813 case X86Local::MRMSrcReg: 814 case X86Local::MRMSrcReg4VOp3: 815 case X86Local::MRMSrcRegOp4: 816 case X86Local::MRMSrcRegCC: 817 case X86Local::MRMXrCC: 818 case X86Local::MRMXr: 819 filter = std::make_unique<ModFilter>(true); 820 break; 821 case X86Local::MRMDestMem: 822 case X86Local::MRMDestMem4VOp3CC: 823 case X86Local::MRMDestMemFSIB: 824 case X86Local::MRMSrcMem: 825 case X86Local::MRMSrcMemFSIB: 826 case X86Local::MRMSrcMem4VOp3: 827 case X86Local::MRMSrcMemOp4: 828 case X86Local::MRMSrcMemCC: 829 case X86Local::MRMXmCC: 830 case X86Local::MRMXm: 831 filter = std::make_unique<ModFilter>(false); 832 break; 833 case X86Local::MRM0r: case X86Local::MRM1r: 834 case X86Local::MRM2r: case X86Local::MRM3r: 835 case X86Local::MRM4r: case X86Local::MRM5r: 836 case X86Local::MRM6r: case X86Local::MRM7r: 837 filter = std::make_unique<ExtendedFilter>(true, Form - X86Local::MRM0r); 838 break; 839 case X86Local::MRM0X: case X86Local::MRM1X: 840 case X86Local::MRM2X: case X86Local::MRM3X: 841 case X86Local::MRM4X: case X86Local::MRM5X: 842 case X86Local::MRM6X: case X86Local::MRM7X: 843 filter = std::make_unique<ExtendedFilter>(true, Form - X86Local::MRM0X); 844 break; 845 case X86Local::MRMr0: 846 filter = std::make_unique<ExtendedRMFilter>(true, Form - X86Local::MRMr0); 847 break; 848 case X86Local::MRM0m: case X86Local::MRM1m: 849 case X86Local::MRM2m: case X86Local::MRM3m: 850 case X86Local::MRM4m: case X86Local::MRM5m: 851 case X86Local::MRM6m: case X86Local::MRM7m: 852 filter = std::make_unique<ExtendedFilter>(false, Form - X86Local::MRM0m); 853 break; 854 X86_INSTR_MRM_MAPPING 855 filter = std::make_unique<ExactFilter>(0xC0 + Form - X86Local::MRM_C0); 856 break; 857 } // switch (Form) 858 859 uint8_t opcodeToSet = Opcode; 860 861 unsigned AddressSize = 0; 862 switch (AdSize) { 863 case X86Local::AdSize16: AddressSize = 16; break; 864 case X86Local::AdSize32: AddressSize = 32; break; 865 case X86Local::AdSize64: AddressSize = 64; break; 866 } 867 868 assert(opcodeType && "Opcode type not set"); 869 assert(filter && "Filter not set"); 870 871 if (Form == X86Local::AddRegFrm || Form == X86Local::MRMSrcRegCC || 872 Form == X86Local::MRMSrcMemCC || Form == X86Local::MRMXrCC || 873 Form == X86Local::MRMXmCC || Form == X86Local::AddCCFrm || 874 Form == X86Local::MRMDestMem4VOp3CC) { 875 uint8_t Count = Form == X86Local::AddRegFrm ? 8 : 16; 876 assert(((opcodeToSet % Count) == 0) && "ADDREG_FRM opcode not aligned"); 877 878 uint8_t currentOpcode; 879 880 for (currentOpcode = opcodeToSet; 881 currentOpcode < (uint8_t)(opcodeToSet + Count); ++currentOpcode) 882 tables.setTableFields(*opcodeType, insnContext(), currentOpcode, *filter, 883 UID, Is32Bit, OpPrefix == 0, 884 IgnoresVEX_L || EncodeRC, 885 IgnoresW, AddressSize); 886 } else { 887 tables.setTableFields(*opcodeType, insnContext(), opcodeToSet, *filter, UID, 888 Is32Bit, OpPrefix == 0, IgnoresVEX_L || EncodeRC, 889 IgnoresW, AddressSize); 890 } 891 892 #undef MAP 893 } 894 895 #define TYPE(str, type) if (s == str) return type; 896 OperandType RecognizableInstr::typeFromString(const std::string &s, 897 bool hasREX_W, 898 uint8_t OpSize) { 899 if(hasREX_W) { 900 // For instructions with a REX_W prefix, a declared 32-bit register encoding 901 // is special. 902 TYPE("GR32", TYPE_R32) 903 } 904 if(OpSize == X86Local::OpSize16) { 905 // For OpSize16 instructions, a declared 16-bit register or 906 // immediate encoding is special. 907 TYPE("GR16", TYPE_Rv) 908 } else if(OpSize == X86Local::OpSize32) { 909 // For OpSize32 instructions, a declared 32-bit register or 910 // immediate encoding is special. 911 TYPE("GR32", TYPE_Rv) 912 } 913 TYPE("i16mem", TYPE_M) 914 TYPE("i16imm", TYPE_IMM) 915 TYPE("i16i8imm", TYPE_IMM) 916 TYPE("GR16", TYPE_R16) 917 TYPE("GR16orGR32orGR64", TYPE_R16) 918 TYPE("i32mem", TYPE_M) 919 TYPE("i32imm", TYPE_IMM) 920 TYPE("i32i8imm", TYPE_IMM) 921 TYPE("GR32", TYPE_R32) 922 TYPE("GR32orGR64", TYPE_R32) 923 TYPE("i64mem", TYPE_M) 924 TYPE("i64i32imm", TYPE_IMM) 925 TYPE("i64i8imm", TYPE_IMM) 926 TYPE("GR64", TYPE_R64) 927 TYPE("i8mem", TYPE_M) 928 TYPE("i8imm", TYPE_IMM) 929 TYPE("u4imm", TYPE_UIMM8) 930 TYPE("u8imm", TYPE_UIMM8) 931 TYPE("i16u8imm", TYPE_UIMM8) 932 TYPE("i32u8imm", TYPE_UIMM8) 933 TYPE("i64u8imm", TYPE_UIMM8) 934 TYPE("GR8", TYPE_R8) 935 TYPE("VR128", TYPE_XMM) 936 TYPE("VR128X", TYPE_XMM) 937 TYPE("f128mem", TYPE_M) 938 TYPE("f256mem", TYPE_M) 939 TYPE("f512mem", TYPE_M) 940 TYPE("FR128", TYPE_XMM) 941 TYPE("FR64", TYPE_XMM) 942 TYPE("FR64X", TYPE_XMM) 943 TYPE("f64mem", TYPE_M) 944 TYPE("sdmem", TYPE_M) 945 TYPE("FR16X", TYPE_XMM) 946 TYPE("FR32", TYPE_XMM) 947 TYPE("FR32X", TYPE_XMM) 948 TYPE("f32mem", TYPE_M) 949 TYPE("f16mem", TYPE_M) 950 TYPE("ssmem", TYPE_M) 951 TYPE("shmem", TYPE_M) 952 TYPE("RST", TYPE_ST) 953 TYPE("RSTi", TYPE_ST) 954 TYPE("i128mem", TYPE_M) 955 TYPE("i256mem", TYPE_M) 956 TYPE("i512mem", TYPE_M) 957 TYPE("i512mem_GR16", TYPE_M) 958 TYPE("i512mem_GR32", TYPE_M) 959 TYPE("i512mem_GR64", TYPE_M) 960 TYPE("i64i32imm_brtarget", TYPE_REL) 961 TYPE("i16imm_brtarget", TYPE_REL) 962 TYPE("i32imm_brtarget", TYPE_REL) 963 TYPE("ccode", TYPE_IMM) 964 TYPE("AVX512RC", TYPE_IMM) 965 TYPE("brtarget32", TYPE_REL) 966 TYPE("brtarget16", TYPE_REL) 967 TYPE("brtarget8", TYPE_REL) 968 TYPE("f80mem", TYPE_M) 969 TYPE("lea64_32mem", TYPE_M) 970 TYPE("lea64mem", TYPE_M) 971 TYPE("VR64", TYPE_MM64) 972 TYPE("i64imm", TYPE_IMM) 973 TYPE("anymem", TYPE_M) 974 TYPE("opaquemem", TYPE_M) 975 TYPE("sibmem", TYPE_MSIB) 976 TYPE("SEGMENT_REG", TYPE_SEGMENTREG) 977 TYPE("DEBUG_REG", TYPE_DEBUGREG) 978 TYPE("CONTROL_REG", TYPE_CONTROLREG) 979 TYPE("srcidx8", TYPE_SRCIDX) 980 TYPE("srcidx16", TYPE_SRCIDX) 981 TYPE("srcidx32", TYPE_SRCIDX) 982 TYPE("srcidx64", TYPE_SRCIDX) 983 TYPE("dstidx8", TYPE_DSTIDX) 984 TYPE("dstidx16", TYPE_DSTIDX) 985 TYPE("dstidx32", TYPE_DSTIDX) 986 TYPE("dstidx64", TYPE_DSTIDX) 987 TYPE("offset16_8", TYPE_MOFFS) 988 TYPE("offset16_16", TYPE_MOFFS) 989 TYPE("offset16_32", TYPE_MOFFS) 990 TYPE("offset32_8", TYPE_MOFFS) 991 TYPE("offset32_16", TYPE_MOFFS) 992 TYPE("offset32_32", TYPE_MOFFS) 993 TYPE("offset32_64", TYPE_MOFFS) 994 TYPE("offset64_8", TYPE_MOFFS) 995 TYPE("offset64_16", TYPE_MOFFS) 996 TYPE("offset64_32", TYPE_MOFFS) 997 TYPE("offset64_64", TYPE_MOFFS) 998 TYPE("VR256", TYPE_YMM) 999 TYPE("VR256X", TYPE_YMM) 1000 TYPE("VR512", TYPE_ZMM) 1001 TYPE("VK1", TYPE_VK) 1002 TYPE("VK1WM", TYPE_VK) 1003 TYPE("VK2", TYPE_VK) 1004 TYPE("VK2WM", TYPE_VK) 1005 TYPE("VK4", TYPE_VK) 1006 TYPE("VK4WM", TYPE_VK) 1007 TYPE("VK8", TYPE_VK) 1008 TYPE("VK8WM", TYPE_VK) 1009 TYPE("VK16", TYPE_VK) 1010 TYPE("VK16WM", TYPE_VK) 1011 TYPE("VK32", TYPE_VK) 1012 TYPE("VK32WM", TYPE_VK) 1013 TYPE("VK64", TYPE_VK) 1014 TYPE("VK64WM", TYPE_VK) 1015 TYPE("VK1Pair", TYPE_VK_PAIR) 1016 TYPE("VK2Pair", TYPE_VK_PAIR) 1017 TYPE("VK4Pair", TYPE_VK_PAIR) 1018 TYPE("VK8Pair", TYPE_VK_PAIR) 1019 TYPE("VK16Pair", TYPE_VK_PAIR) 1020 TYPE("vx64mem", TYPE_MVSIBX) 1021 TYPE("vx128mem", TYPE_MVSIBX) 1022 TYPE("vx256mem", TYPE_MVSIBX) 1023 TYPE("vy128mem", TYPE_MVSIBY) 1024 TYPE("vy256mem", TYPE_MVSIBY) 1025 TYPE("vx64xmem", TYPE_MVSIBX) 1026 TYPE("vx128xmem", TYPE_MVSIBX) 1027 TYPE("vx256xmem", TYPE_MVSIBX) 1028 TYPE("vy128xmem", TYPE_MVSIBY) 1029 TYPE("vy256xmem", TYPE_MVSIBY) 1030 TYPE("vy512xmem", TYPE_MVSIBY) 1031 TYPE("vz256mem", TYPE_MVSIBZ) 1032 TYPE("vz512mem", TYPE_MVSIBZ) 1033 TYPE("BNDR", TYPE_BNDR) 1034 TYPE("TILE", TYPE_TMM) 1035 errs() << "Unhandled type string " << s << "\n"; 1036 llvm_unreachable("Unhandled type string"); 1037 } 1038 #undef TYPE 1039 1040 #define ENCODING(str, encoding) if (s == str) return encoding; 1041 OperandEncoding 1042 RecognizableInstr::immediateEncodingFromString(const std::string &s, 1043 uint8_t OpSize) { 1044 if(OpSize != X86Local::OpSize16) { 1045 // For instructions without an OpSize prefix, a declared 16-bit register or 1046 // immediate encoding is special. 1047 ENCODING("i16imm", ENCODING_IW) 1048 } 1049 ENCODING("i32i8imm", ENCODING_IB) 1050 ENCODING("AVX512RC", ENCODING_IRC) 1051 ENCODING("i16imm", ENCODING_Iv) 1052 ENCODING("i16i8imm", ENCODING_IB) 1053 ENCODING("i32imm", ENCODING_Iv) 1054 ENCODING("i64i32imm", ENCODING_ID) 1055 ENCODING("i64i8imm", ENCODING_IB) 1056 ENCODING("i8imm", ENCODING_IB) 1057 ENCODING("u4imm", ENCODING_IB) 1058 ENCODING("u8imm", ENCODING_IB) 1059 ENCODING("i16u8imm", ENCODING_IB) 1060 ENCODING("i32u8imm", ENCODING_IB) 1061 ENCODING("i64u8imm", ENCODING_IB) 1062 // This is not a typo. Instructions like BLENDVPD put 1063 // register IDs in 8-bit immediates nowadays. 1064 ENCODING("FR32", ENCODING_IB) 1065 ENCODING("FR64", ENCODING_IB) 1066 ENCODING("FR128", ENCODING_IB) 1067 ENCODING("VR128", ENCODING_IB) 1068 ENCODING("VR256", ENCODING_IB) 1069 ENCODING("FR16X", ENCODING_IB) 1070 ENCODING("FR32X", ENCODING_IB) 1071 ENCODING("FR64X", ENCODING_IB) 1072 ENCODING("VR128X", ENCODING_IB) 1073 ENCODING("VR256X", ENCODING_IB) 1074 ENCODING("VR512", ENCODING_IB) 1075 ENCODING("TILE", ENCODING_IB) 1076 errs() << "Unhandled immediate encoding " << s << "\n"; 1077 llvm_unreachable("Unhandled immediate encoding"); 1078 } 1079 1080 OperandEncoding 1081 RecognizableInstr::rmRegisterEncodingFromString(const std::string &s, 1082 uint8_t OpSize) { 1083 ENCODING("RST", ENCODING_FP) 1084 ENCODING("RSTi", ENCODING_FP) 1085 ENCODING("GR16", ENCODING_RM) 1086 ENCODING("GR16orGR32orGR64",ENCODING_RM) 1087 ENCODING("GR32", ENCODING_RM) 1088 ENCODING("GR32orGR64", ENCODING_RM) 1089 ENCODING("GR64", ENCODING_RM) 1090 ENCODING("GR8", ENCODING_RM) 1091 ENCODING("VR128", ENCODING_RM) 1092 ENCODING("VR128X", ENCODING_RM) 1093 ENCODING("FR128", ENCODING_RM) 1094 ENCODING("FR64", ENCODING_RM) 1095 ENCODING("FR32", ENCODING_RM) 1096 ENCODING("FR64X", ENCODING_RM) 1097 ENCODING("FR32X", ENCODING_RM) 1098 ENCODING("FR16X", ENCODING_RM) 1099 ENCODING("VR64", ENCODING_RM) 1100 ENCODING("VR256", ENCODING_RM) 1101 ENCODING("VR256X", ENCODING_RM) 1102 ENCODING("VR512", ENCODING_RM) 1103 ENCODING("VK1", ENCODING_RM) 1104 ENCODING("VK2", ENCODING_RM) 1105 ENCODING("VK4", ENCODING_RM) 1106 ENCODING("VK8", ENCODING_RM) 1107 ENCODING("VK16", ENCODING_RM) 1108 ENCODING("VK32", ENCODING_RM) 1109 ENCODING("VK64", ENCODING_RM) 1110 ENCODING("BNDR", ENCODING_RM) 1111 ENCODING("TILE", ENCODING_RM) 1112 errs() << "Unhandled R/M register encoding " << s << "\n"; 1113 llvm_unreachable("Unhandled R/M register encoding"); 1114 } 1115 1116 OperandEncoding 1117 RecognizableInstr::roRegisterEncodingFromString(const std::string &s, 1118 uint8_t OpSize) { 1119 ENCODING("GR16", ENCODING_REG) 1120 ENCODING("GR16orGR32orGR64",ENCODING_REG) 1121 ENCODING("GR32", ENCODING_REG) 1122 ENCODING("GR32orGR64", ENCODING_REG) 1123 ENCODING("GR64", ENCODING_REG) 1124 ENCODING("GR8", ENCODING_REG) 1125 ENCODING("VR128", ENCODING_REG) 1126 ENCODING("FR128", ENCODING_REG) 1127 ENCODING("FR64", ENCODING_REG) 1128 ENCODING("FR32", ENCODING_REG) 1129 ENCODING("VR64", ENCODING_REG) 1130 ENCODING("SEGMENT_REG", ENCODING_REG) 1131 ENCODING("DEBUG_REG", ENCODING_REG) 1132 ENCODING("CONTROL_REG", ENCODING_REG) 1133 ENCODING("VR256", ENCODING_REG) 1134 ENCODING("VR256X", ENCODING_REG) 1135 ENCODING("VR128X", ENCODING_REG) 1136 ENCODING("FR64X", ENCODING_REG) 1137 ENCODING("FR32X", ENCODING_REG) 1138 ENCODING("FR16X", ENCODING_REG) 1139 ENCODING("VR512", ENCODING_REG) 1140 ENCODING("VK1", ENCODING_REG) 1141 ENCODING("VK2", ENCODING_REG) 1142 ENCODING("VK4", ENCODING_REG) 1143 ENCODING("VK8", ENCODING_REG) 1144 ENCODING("VK16", ENCODING_REG) 1145 ENCODING("VK32", ENCODING_REG) 1146 ENCODING("VK64", ENCODING_REG) 1147 ENCODING("VK1Pair", ENCODING_REG) 1148 ENCODING("VK2Pair", ENCODING_REG) 1149 ENCODING("VK4Pair", ENCODING_REG) 1150 ENCODING("VK8Pair", ENCODING_REG) 1151 ENCODING("VK16Pair", ENCODING_REG) 1152 ENCODING("VK1WM", ENCODING_REG) 1153 ENCODING("VK2WM", ENCODING_REG) 1154 ENCODING("VK4WM", ENCODING_REG) 1155 ENCODING("VK8WM", ENCODING_REG) 1156 ENCODING("VK16WM", ENCODING_REG) 1157 ENCODING("VK32WM", ENCODING_REG) 1158 ENCODING("VK64WM", ENCODING_REG) 1159 ENCODING("BNDR", ENCODING_REG) 1160 ENCODING("TILE", ENCODING_REG) 1161 errs() << "Unhandled reg/opcode register encoding " << s << "\n"; 1162 llvm_unreachable("Unhandled reg/opcode register encoding"); 1163 } 1164 1165 OperandEncoding 1166 RecognizableInstr::vvvvRegisterEncodingFromString(const std::string &s, 1167 uint8_t OpSize) { 1168 ENCODING("GR32", ENCODING_VVVV) 1169 ENCODING("GR64", ENCODING_VVVV) 1170 ENCODING("FR32", ENCODING_VVVV) 1171 ENCODING("FR128", ENCODING_VVVV) 1172 ENCODING("FR64", ENCODING_VVVV) 1173 ENCODING("VR128", ENCODING_VVVV) 1174 ENCODING("VR256", ENCODING_VVVV) 1175 ENCODING("FR16X", ENCODING_VVVV) 1176 ENCODING("FR32X", ENCODING_VVVV) 1177 ENCODING("FR64X", ENCODING_VVVV) 1178 ENCODING("VR128X", ENCODING_VVVV) 1179 ENCODING("VR256X", ENCODING_VVVV) 1180 ENCODING("VR512", ENCODING_VVVV) 1181 ENCODING("VK1", ENCODING_VVVV) 1182 ENCODING("VK2", ENCODING_VVVV) 1183 ENCODING("VK4", ENCODING_VVVV) 1184 ENCODING("VK8", ENCODING_VVVV) 1185 ENCODING("VK16", ENCODING_VVVV) 1186 ENCODING("VK32", ENCODING_VVVV) 1187 ENCODING("VK64", ENCODING_VVVV) 1188 ENCODING("TILE", ENCODING_VVVV) 1189 errs() << "Unhandled VEX.vvvv register encoding " << s << "\n"; 1190 llvm_unreachable("Unhandled VEX.vvvv register encoding"); 1191 } 1192 1193 OperandEncoding 1194 RecognizableInstr::writemaskRegisterEncodingFromString(const std::string &s, 1195 uint8_t OpSize) { 1196 ENCODING("VK1WM", ENCODING_WRITEMASK) 1197 ENCODING("VK2WM", ENCODING_WRITEMASK) 1198 ENCODING("VK4WM", ENCODING_WRITEMASK) 1199 ENCODING("VK8WM", ENCODING_WRITEMASK) 1200 ENCODING("VK16WM", ENCODING_WRITEMASK) 1201 ENCODING("VK32WM", ENCODING_WRITEMASK) 1202 ENCODING("VK64WM", ENCODING_WRITEMASK) 1203 errs() << "Unhandled mask register encoding " << s << "\n"; 1204 llvm_unreachable("Unhandled mask register encoding"); 1205 } 1206 1207 OperandEncoding 1208 RecognizableInstr::memoryEncodingFromString(const std::string &s, 1209 uint8_t OpSize) { 1210 ENCODING("i16mem", ENCODING_RM) 1211 ENCODING("i32mem", ENCODING_RM) 1212 ENCODING("i64mem", ENCODING_RM) 1213 ENCODING("i8mem", ENCODING_RM) 1214 ENCODING("shmem", ENCODING_RM) 1215 ENCODING("ssmem", ENCODING_RM) 1216 ENCODING("sdmem", ENCODING_RM) 1217 ENCODING("f128mem", ENCODING_RM) 1218 ENCODING("f256mem", ENCODING_RM) 1219 ENCODING("f512mem", ENCODING_RM) 1220 ENCODING("f64mem", ENCODING_RM) 1221 ENCODING("f32mem", ENCODING_RM) 1222 ENCODING("f16mem", ENCODING_RM) 1223 ENCODING("i128mem", ENCODING_RM) 1224 ENCODING("i256mem", ENCODING_RM) 1225 ENCODING("i512mem", ENCODING_RM) 1226 ENCODING("i512mem_GR16", ENCODING_RM) 1227 ENCODING("i512mem_GR32", ENCODING_RM) 1228 ENCODING("i512mem_GR64", ENCODING_RM) 1229 ENCODING("f80mem", ENCODING_RM) 1230 ENCODING("lea64_32mem", ENCODING_RM) 1231 ENCODING("lea64mem", ENCODING_RM) 1232 ENCODING("anymem", ENCODING_RM) 1233 ENCODING("opaquemem", ENCODING_RM) 1234 ENCODING("sibmem", ENCODING_SIB) 1235 ENCODING("vx64mem", ENCODING_VSIB) 1236 ENCODING("vx128mem", ENCODING_VSIB) 1237 ENCODING("vx256mem", ENCODING_VSIB) 1238 ENCODING("vy128mem", ENCODING_VSIB) 1239 ENCODING("vy256mem", ENCODING_VSIB) 1240 ENCODING("vx64xmem", ENCODING_VSIB) 1241 ENCODING("vx128xmem", ENCODING_VSIB) 1242 ENCODING("vx256xmem", ENCODING_VSIB) 1243 ENCODING("vy128xmem", ENCODING_VSIB) 1244 ENCODING("vy256xmem", ENCODING_VSIB) 1245 ENCODING("vy512xmem", ENCODING_VSIB) 1246 ENCODING("vz256mem", ENCODING_VSIB) 1247 ENCODING("vz512mem", ENCODING_VSIB) 1248 errs() << "Unhandled memory encoding " << s << "\n"; 1249 llvm_unreachable("Unhandled memory encoding"); 1250 } 1251 1252 OperandEncoding 1253 RecognizableInstr::relocationEncodingFromString(const std::string &s, 1254 uint8_t OpSize) { 1255 if(OpSize != X86Local::OpSize16) { 1256 // For instructions without an OpSize prefix, a declared 16-bit register or 1257 // immediate encoding is special. 1258 ENCODING("i16imm", ENCODING_IW) 1259 } 1260 ENCODING("i16imm", ENCODING_Iv) 1261 ENCODING("i16i8imm", ENCODING_IB) 1262 ENCODING("i32imm", ENCODING_Iv) 1263 ENCODING("i32i8imm", ENCODING_IB) 1264 ENCODING("i64i32imm", ENCODING_ID) 1265 ENCODING("i64i8imm", ENCODING_IB) 1266 ENCODING("i8imm", ENCODING_IB) 1267 ENCODING("u8imm", ENCODING_IB) 1268 ENCODING("i16u8imm", ENCODING_IB) 1269 ENCODING("i32u8imm", ENCODING_IB) 1270 ENCODING("i64u8imm", ENCODING_IB) 1271 ENCODING("i64i32imm_brtarget", ENCODING_ID) 1272 ENCODING("i16imm_brtarget", ENCODING_IW) 1273 ENCODING("i32imm_brtarget", ENCODING_ID) 1274 ENCODING("brtarget32", ENCODING_ID) 1275 ENCODING("brtarget16", ENCODING_IW) 1276 ENCODING("brtarget8", ENCODING_IB) 1277 ENCODING("i64imm", ENCODING_IO) 1278 ENCODING("offset16_8", ENCODING_Ia) 1279 ENCODING("offset16_16", ENCODING_Ia) 1280 ENCODING("offset16_32", ENCODING_Ia) 1281 ENCODING("offset32_8", ENCODING_Ia) 1282 ENCODING("offset32_16", ENCODING_Ia) 1283 ENCODING("offset32_32", ENCODING_Ia) 1284 ENCODING("offset32_64", ENCODING_Ia) 1285 ENCODING("offset64_8", ENCODING_Ia) 1286 ENCODING("offset64_16", ENCODING_Ia) 1287 ENCODING("offset64_32", ENCODING_Ia) 1288 ENCODING("offset64_64", ENCODING_Ia) 1289 ENCODING("srcidx8", ENCODING_SI) 1290 ENCODING("srcidx16", ENCODING_SI) 1291 ENCODING("srcidx32", ENCODING_SI) 1292 ENCODING("srcidx64", ENCODING_SI) 1293 ENCODING("dstidx8", ENCODING_DI) 1294 ENCODING("dstidx16", ENCODING_DI) 1295 ENCODING("dstidx32", ENCODING_DI) 1296 ENCODING("dstidx64", ENCODING_DI) 1297 errs() << "Unhandled relocation encoding " << s << "\n"; 1298 llvm_unreachable("Unhandled relocation encoding"); 1299 } 1300 1301 OperandEncoding 1302 RecognizableInstr::opcodeModifierEncodingFromString(const std::string &s, 1303 uint8_t OpSize) { 1304 ENCODING("GR32", ENCODING_Rv) 1305 ENCODING("GR64", ENCODING_RO) 1306 ENCODING("GR16", ENCODING_Rv) 1307 ENCODING("GR8", ENCODING_RB) 1308 ENCODING("ccode", ENCODING_CC) 1309 errs() << "Unhandled opcode modifier encoding " << s << "\n"; 1310 llvm_unreachable("Unhandled opcode modifier encoding"); 1311 } 1312 #undef ENCODING 1313