1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file is part of the X86 Disassembler Emitter. 10 // It contains the implementation of a single recognizable instruction. 11 // Documentation for the disassembler emitter in general can be found in 12 // X86DisassemblerEmitter.h. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #include "X86RecognizableInstr.h" 17 #include "X86DisassemblerShared.h" 18 #include "X86DisassemblerTables.h" 19 #include "X86ModRMFilters.h" 20 #include "llvm/Support/ErrorHandling.h" 21 #include "llvm/TableGen/Record.h" 22 #include <string> 23 24 using namespace llvm; 25 using namespace X86Disassembler; 26 27 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit. 28 /// Useful for switch statements and the like. 29 /// 30 /// @param init - A reference to the BitsInit to be decoded. 31 /// @return - The field, with the first bit in the BitsInit as the lowest 32 /// order bit. 33 static uint8_t byteFromBitsInit(BitsInit &init) { 34 int width = init.getNumBits(); 35 36 assert(width <= 8 && "Field is too large for uint8_t!"); 37 38 int index; 39 uint8_t mask = 0x01; 40 41 uint8_t ret = 0; 42 43 for (index = 0; index < width; index++) { 44 if (cast<BitInit>(init.getBit(index))->getValue()) 45 ret |= mask; 46 47 mask <<= 1; 48 } 49 50 return ret; 51 } 52 53 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the 54 /// name of the field. 55 /// 56 /// @param rec - The record from which to extract the value. 57 /// @param name - The name of the field in the record. 58 /// @return - The field, as translated by byteFromBitsInit(). 59 static uint8_t byteFromRec(const Record* rec, StringRef name) { 60 BitsInit* bits = rec->getValueAsBitsInit(name); 61 return byteFromBitsInit(*bits); 62 } 63 64 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables, 65 const CodeGenInstruction &insn, 66 InstrUID uid) { 67 UID = uid; 68 69 Rec = insn.TheDef; 70 Name = std::string(Rec->getName()); 71 Spec = &tables.specForUID(UID); 72 73 if (!Rec->isSubClassOf("X86Inst")) { 74 ShouldBeEmitted = false; 75 return; 76 } 77 78 OpPrefix = byteFromRec(Rec, "OpPrefixBits"); 79 OpMap = byteFromRec(Rec, "OpMapBits"); 80 Opcode = byteFromRec(Rec, "Opcode"); 81 Form = byteFromRec(Rec, "FormBits"); 82 Encoding = byteFromRec(Rec, "OpEncBits"); 83 84 OpSize = byteFromRec(Rec, "OpSizeBits"); 85 AdSize = byteFromRec(Rec, "AdSizeBits"); 86 HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix"); 87 HasVEX_4V = Rec->getValueAsBit("hasVEX_4V"); 88 HasVEX_W = Rec->getValueAsBit("HasVEX_W"); 89 IgnoresVEX_W = Rec->getValueAsBit("IgnoresVEX_W"); 90 IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L"); 91 HasEVEX_L2Prefix = Rec->getValueAsBit("hasEVEX_L2"); 92 HasEVEX_K = Rec->getValueAsBit("hasEVEX_K"); 93 HasEVEX_KZ = Rec->getValueAsBit("hasEVEX_Z"); 94 HasEVEX_B = Rec->getValueAsBit("hasEVEX_B"); 95 IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly"); 96 ForceDisassemble = Rec->getValueAsBit("ForceDisassemble"); 97 CD8_Scale = byteFromRec(Rec, "CD8_Scale"); 98 99 Name = std::string(Rec->getName()); 100 101 Operands = &insn.Operands.OperandList; 102 103 HasVEX_LPrefix = Rec->getValueAsBit("hasVEX_L"); 104 105 EncodeRC = HasEVEX_B && 106 (Form == X86Local::MRMDestReg || Form == X86Local::MRMSrcReg); 107 108 // Check for 64-bit inst which does not require REX 109 Is32Bit = false; 110 Is64Bit = false; 111 // FIXME: Is there some better way to check for In64BitMode? 112 std::vector<Record*> Predicates = Rec->getValueAsListOfDefs("Predicates"); 113 for (unsigned i = 0, e = Predicates.size(); i != e; ++i) { 114 if (Predicates[i]->getName().contains("Not64Bit") || 115 Predicates[i]->getName().contains("In32Bit")) { 116 Is32Bit = true; 117 break; 118 } 119 if (Predicates[i]->getName().contains("In64Bit")) { 120 Is64Bit = true; 121 break; 122 } 123 } 124 125 if (Form == X86Local::Pseudo || (IsCodeGenOnly && !ForceDisassemble)) { 126 ShouldBeEmitted = false; 127 return; 128 } 129 130 ShouldBeEmitted = true; 131 } 132 133 void RecognizableInstr::processInstr(DisassemblerTables &tables, 134 const CodeGenInstruction &insn, 135 InstrUID uid) 136 { 137 // Ignore "asm parser only" instructions. 138 if (insn.TheDef->getValueAsBit("isAsmParserOnly")) 139 return; 140 141 RecognizableInstr recogInstr(tables, insn, uid); 142 143 if (recogInstr.shouldBeEmitted()) { 144 recogInstr.emitInstructionSpecifier(); 145 recogInstr.emitDecodePath(tables); 146 } 147 } 148 149 #define EVEX_KB(n) (HasEVEX_KZ && HasEVEX_B ? n##_KZ_B : \ 150 (HasEVEX_K && HasEVEX_B ? n##_K_B : \ 151 (HasEVEX_KZ ? n##_KZ : \ 152 (HasEVEX_K? n##_K : (HasEVEX_B ? n##_B : n))))) 153 154 InstructionContext RecognizableInstr::insnContext() const { 155 InstructionContext insnContext; 156 157 if (Encoding == X86Local::EVEX) { 158 if (HasVEX_LPrefix && HasEVEX_L2Prefix) { 159 errs() << "Don't support VEX.L if EVEX_L2 is enabled: " << Name << "\n"; 160 llvm_unreachable("Don't support VEX.L if EVEX_L2 is enabled"); 161 } 162 // VEX_L & VEX_W 163 if (!EncodeRC && HasVEX_LPrefix && HasVEX_W) { 164 if (OpPrefix == X86Local::PD) 165 insnContext = EVEX_KB(IC_EVEX_L_W_OPSIZE); 166 else if (OpPrefix == X86Local::XS) 167 insnContext = EVEX_KB(IC_EVEX_L_W_XS); 168 else if (OpPrefix == X86Local::XD) 169 insnContext = EVEX_KB(IC_EVEX_L_W_XD); 170 else if (OpPrefix == X86Local::PS) 171 insnContext = EVEX_KB(IC_EVEX_L_W); 172 else { 173 errs() << "Instruction does not use a prefix: " << Name << "\n"; 174 llvm_unreachable("Invalid prefix"); 175 } 176 } else if (!EncodeRC && HasVEX_LPrefix) { 177 // VEX_L 178 if (OpPrefix == X86Local::PD) 179 insnContext = EVEX_KB(IC_EVEX_L_OPSIZE); 180 else if (OpPrefix == X86Local::XS) 181 insnContext = EVEX_KB(IC_EVEX_L_XS); 182 else if (OpPrefix == X86Local::XD) 183 insnContext = EVEX_KB(IC_EVEX_L_XD); 184 else if (OpPrefix == X86Local::PS) 185 insnContext = EVEX_KB(IC_EVEX_L); 186 else { 187 errs() << "Instruction does not use a prefix: " << Name << "\n"; 188 llvm_unreachable("Invalid prefix"); 189 } 190 } else if (!EncodeRC && HasEVEX_L2Prefix && HasVEX_W) { 191 // EVEX_L2 & VEX_W 192 if (OpPrefix == X86Local::PD) 193 insnContext = EVEX_KB(IC_EVEX_L2_W_OPSIZE); 194 else if (OpPrefix == X86Local::XS) 195 insnContext = EVEX_KB(IC_EVEX_L2_W_XS); 196 else if (OpPrefix == X86Local::XD) 197 insnContext = EVEX_KB(IC_EVEX_L2_W_XD); 198 else if (OpPrefix == X86Local::PS) 199 insnContext = EVEX_KB(IC_EVEX_L2_W); 200 else { 201 errs() << "Instruction does not use a prefix: " << Name << "\n"; 202 llvm_unreachable("Invalid prefix"); 203 } 204 } else if (!EncodeRC && HasEVEX_L2Prefix) { 205 // EVEX_L2 206 if (OpPrefix == X86Local::PD) 207 insnContext = EVEX_KB(IC_EVEX_L2_OPSIZE); 208 else if (OpPrefix == X86Local::XD) 209 insnContext = EVEX_KB(IC_EVEX_L2_XD); 210 else if (OpPrefix == X86Local::XS) 211 insnContext = EVEX_KB(IC_EVEX_L2_XS); 212 else if (OpPrefix == X86Local::PS) 213 insnContext = EVEX_KB(IC_EVEX_L2); 214 else { 215 errs() << "Instruction does not use a prefix: " << Name << "\n"; 216 llvm_unreachable("Invalid prefix"); 217 } 218 } 219 else if (HasVEX_W) { 220 // VEX_W 221 if (OpPrefix == X86Local::PD) 222 insnContext = EVEX_KB(IC_EVEX_W_OPSIZE); 223 else if (OpPrefix == X86Local::XS) 224 insnContext = EVEX_KB(IC_EVEX_W_XS); 225 else if (OpPrefix == X86Local::XD) 226 insnContext = EVEX_KB(IC_EVEX_W_XD); 227 else if (OpPrefix == X86Local::PS) 228 insnContext = EVEX_KB(IC_EVEX_W); 229 else { 230 errs() << "Instruction does not use a prefix: " << Name << "\n"; 231 llvm_unreachable("Invalid prefix"); 232 } 233 } 234 // No L, no W 235 else if (OpPrefix == X86Local::PD) 236 insnContext = EVEX_KB(IC_EVEX_OPSIZE); 237 else if (OpPrefix == X86Local::XD) 238 insnContext = EVEX_KB(IC_EVEX_XD); 239 else if (OpPrefix == X86Local::XS) 240 insnContext = EVEX_KB(IC_EVEX_XS); 241 else if (OpPrefix == X86Local::PS) 242 insnContext = EVEX_KB(IC_EVEX); 243 else { 244 errs() << "Instruction does not use a prefix: " << Name << "\n"; 245 llvm_unreachable("Invalid prefix"); 246 } 247 /// eof EVEX 248 } else if (Encoding == X86Local::VEX || Encoding == X86Local::XOP) { 249 if (HasVEX_LPrefix && HasVEX_W) { 250 if (OpPrefix == X86Local::PD) 251 insnContext = IC_VEX_L_W_OPSIZE; 252 else if (OpPrefix == X86Local::XS) 253 insnContext = IC_VEX_L_W_XS; 254 else if (OpPrefix == X86Local::XD) 255 insnContext = IC_VEX_L_W_XD; 256 else if (OpPrefix == X86Local::PS) 257 insnContext = IC_VEX_L_W; 258 else { 259 errs() << "Instruction does not use a prefix: " << Name << "\n"; 260 llvm_unreachable("Invalid prefix"); 261 } 262 } else if (OpPrefix == X86Local::PD && HasVEX_LPrefix) 263 insnContext = IC_VEX_L_OPSIZE; 264 else if (OpPrefix == X86Local::PD && HasVEX_W) 265 insnContext = IC_VEX_W_OPSIZE; 266 else if (OpPrefix == X86Local::PD && Is64Bit && 267 AdSize == X86Local::AdSize32) 268 insnContext = IC_64BIT_VEX_OPSIZE_ADSIZE; 269 else if (OpPrefix == X86Local::PD && Is64Bit) 270 insnContext = IC_64BIT_VEX_OPSIZE; 271 else if (OpPrefix == X86Local::PD) 272 insnContext = IC_VEX_OPSIZE; 273 else if (HasVEX_LPrefix && OpPrefix == X86Local::XS) 274 insnContext = IC_VEX_L_XS; 275 else if (HasVEX_LPrefix && OpPrefix == X86Local::XD) 276 insnContext = IC_VEX_L_XD; 277 else if (HasVEX_W && OpPrefix == X86Local::XS) 278 insnContext = IC_VEX_W_XS; 279 else if (HasVEX_W && OpPrefix == X86Local::XD) 280 insnContext = IC_VEX_W_XD; 281 else if (HasVEX_W && OpPrefix == X86Local::PS) 282 insnContext = IC_VEX_W; 283 else if (HasVEX_LPrefix && OpPrefix == X86Local::PS) 284 insnContext = IC_VEX_L; 285 else if (OpPrefix == X86Local::XD) 286 insnContext = IC_VEX_XD; 287 else if (OpPrefix == X86Local::XS) 288 insnContext = IC_VEX_XS; 289 else if (OpPrefix == X86Local::PS) 290 insnContext = IC_VEX; 291 else { 292 errs() << "Instruction does not use a prefix: " << Name << "\n"; 293 llvm_unreachable("Invalid prefix"); 294 } 295 } else if (Is64Bit || HasREX_WPrefix || AdSize == X86Local::AdSize64) { 296 if (HasREX_WPrefix && (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)) 297 insnContext = IC_64BIT_REXW_OPSIZE; 298 else if (HasREX_WPrefix && AdSize == X86Local::AdSize32) 299 insnContext = IC_64BIT_REXW_ADSIZE; 300 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD) 301 insnContext = IC_64BIT_XD_OPSIZE; 302 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS) 303 insnContext = IC_64BIT_XS_OPSIZE; 304 else if (AdSize == X86Local::AdSize32 && OpPrefix == X86Local::PD) 305 insnContext = IC_64BIT_OPSIZE_ADSIZE; 306 else if (OpSize == X86Local::OpSize16 && AdSize == X86Local::AdSize32) 307 insnContext = IC_64BIT_OPSIZE_ADSIZE; 308 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD) 309 insnContext = IC_64BIT_OPSIZE; 310 else if (AdSize == X86Local::AdSize32) 311 insnContext = IC_64BIT_ADSIZE; 312 else if (HasREX_WPrefix && OpPrefix == X86Local::XS) 313 insnContext = IC_64BIT_REXW_XS; 314 else if (HasREX_WPrefix && OpPrefix == X86Local::XD) 315 insnContext = IC_64BIT_REXW_XD; 316 else if (OpPrefix == X86Local::XD) 317 insnContext = IC_64BIT_XD; 318 else if (OpPrefix == X86Local::XS) 319 insnContext = IC_64BIT_XS; 320 else if (HasREX_WPrefix) 321 insnContext = IC_64BIT_REXW; 322 else 323 insnContext = IC_64BIT; 324 } else { 325 if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD) 326 insnContext = IC_XD_OPSIZE; 327 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS) 328 insnContext = IC_XS_OPSIZE; 329 else if (AdSize == X86Local::AdSize16 && OpPrefix == X86Local::XD) 330 insnContext = IC_XD_ADSIZE; 331 else if (AdSize == X86Local::AdSize16 && OpPrefix == X86Local::XS) 332 insnContext = IC_XS_ADSIZE; 333 else if (AdSize == X86Local::AdSize16 && OpPrefix == X86Local::PD) 334 insnContext = IC_OPSIZE_ADSIZE; 335 else if (OpSize == X86Local::OpSize16 && AdSize == X86Local::AdSize16) 336 insnContext = IC_OPSIZE_ADSIZE; 337 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD) 338 insnContext = IC_OPSIZE; 339 else if (AdSize == X86Local::AdSize16) 340 insnContext = IC_ADSIZE; 341 else if (OpPrefix == X86Local::XD) 342 insnContext = IC_XD; 343 else if (OpPrefix == X86Local::XS) 344 insnContext = IC_XS; 345 else 346 insnContext = IC; 347 } 348 349 return insnContext; 350 } 351 352 void RecognizableInstr::adjustOperandEncoding(OperandEncoding &encoding) { 353 // The scaling factor for AVX512 compressed displacement encoding is an 354 // instruction attribute. Adjust the ModRM encoding type to include the 355 // scale for compressed displacement. 356 if ((encoding != ENCODING_RM && 357 encoding != ENCODING_VSIB && 358 encoding != ENCODING_SIB) ||CD8_Scale == 0) 359 return; 360 encoding = (OperandEncoding)(encoding + Log2_32(CD8_Scale)); 361 assert(((encoding >= ENCODING_RM && encoding <= ENCODING_RM_CD64) || 362 (encoding == ENCODING_SIB) || 363 (encoding >= ENCODING_VSIB && encoding <= ENCODING_VSIB_CD64)) && 364 "Invalid CDisp scaling"); 365 } 366 367 void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex, 368 unsigned &physicalOperandIndex, 369 unsigned numPhysicalOperands, 370 const unsigned *operandMapping, 371 OperandEncoding (*encodingFromString) 372 (const std::string&, 373 uint8_t OpSize)) { 374 if (optional) { 375 if (physicalOperandIndex >= numPhysicalOperands) 376 return; 377 } else { 378 assert(physicalOperandIndex < numPhysicalOperands); 379 } 380 381 while (operandMapping[operandIndex] != operandIndex) { 382 Spec->operands[operandIndex].encoding = ENCODING_DUP; 383 Spec->operands[operandIndex].type = 384 (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]); 385 ++operandIndex; 386 } 387 388 StringRef typeName = (*Operands)[operandIndex].Rec->getName(); 389 390 OperandEncoding encoding = encodingFromString(std::string(typeName), OpSize); 391 // Adjust the encoding type for an operand based on the instruction. 392 adjustOperandEncoding(encoding); 393 Spec->operands[operandIndex].encoding = encoding; 394 Spec->operands[operandIndex].type = 395 typeFromString(std::string(typeName), HasREX_WPrefix, OpSize); 396 397 ++operandIndex; 398 ++physicalOperandIndex; 399 } 400 401 void RecognizableInstr::emitInstructionSpecifier() { 402 Spec->name = Name; 403 404 Spec->insnContext = insnContext(); 405 406 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands; 407 408 unsigned numOperands = OperandList.size(); 409 unsigned numPhysicalOperands = 0; 410 411 // operandMapping maps from operands in OperandList to their originals. 412 // If operandMapping[i] != i, then the entry is a duplicate. 413 unsigned operandMapping[X86_MAX_OPERANDS]; 414 assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough"); 415 416 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) { 417 if (!OperandList[operandIndex].Constraints.empty()) { 418 const CGIOperandList::ConstraintInfo &Constraint = 419 OperandList[operandIndex].Constraints[0]; 420 if (Constraint.isTied()) { 421 operandMapping[operandIndex] = operandIndex; 422 operandMapping[Constraint.getTiedOperand()] = operandIndex; 423 } else { 424 ++numPhysicalOperands; 425 operandMapping[operandIndex] = operandIndex; 426 } 427 } else { 428 ++numPhysicalOperands; 429 operandMapping[operandIndex] = operandIndex; 430 } 431 } 432 433 #define HANDLE_OPERAND(class) \ 434 handleOperand(false, \ 435 operandIndex, \ 436 physicalOperandIndex, \ 437 numPhysicalOperands, \ 438 operandMapping, \ 439 class##EncodingFromString); 440 441 #define HANDLE_OPTIONAL(class) \ 442 handleOperand(true, \ 443 operandIndex, \ 444 physicalOperandIndex, \ 445 numPhysicalOperands, \ 446 operandMapping, \ 447 class##EncodingFromString); 448 449 // operandIndex should always be < numOperands 450 unsigned operandIndex = 0; 451 // physicalOperandIndex should always be < numPhysicalOperands 452 unsigned physicalOperandIndex = 0; 453 454 #ifndef NDEBUG 455 // Given the set of prefix bits, how many additional operands does the 456 // instruction have? 457 unsigned additionalOperands = 0; 458 if (HasVEX_4V) 459 ++additionalOperands; 460 if (HasEVEX_K) 461 ++additionalOperands; 462 #endif 463 464 switch (Form) { 465 default: llvm_unreachable("Unhandled form"); 466 case X86Local::PrefixByte: 467 return; 468 case X86Local::RawFrmSrc: 469 HANDLE_OPERAND(relocation); 470 return; 471 case X86Local::RawFrmDst: 472 HANDLE_OPERAND(relocation); 473 return; 474 case X86Local::RawFrmDstSrc: 475 HANDLE_OPERAND(relocation); 476 HANDLE_OPERAND(relocation); 477 return; 478 case X86Local::RawFrm: 479 // Operand 1 (optional) is an address or immediate. 480 assert(numPhysicalOperands <= 1 && 481 "Unexpected number of operands for RawFrm"); 482 HANDLE_OPTIONAL(relocation) 483 break; 484 case X86Local::RawFrmMemOffs: 485 // Operand 1 is an address. 486 HANDLE_OPERAND(relocation); 487 break; 488 case X86Local::AddRegFrm: 489 // Operand 1 is added to the opcode. 490 // Operand 2 (optional) is an address. 491 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 && 492 "Unexpected number of operands for AddRegFrm"); 493 HANDLE_OPERAND(opcodeModifier) 494 HANDLE_OPTIONAL(relocation) 495 break; 496 case X86Local::AddCCFrm: 497 // Operand 1 (optional) is an address or immediate. 498 assert(numPhysicalOperands == 2 && 499 "Unexpected number of operands for AddCCFrm"); 500 HANDLE_OPERAND(relocation) 501 HANDLE_OPERAND(opcodeModifier) 502 break; 503 case X86Local::MRMDestReg: 504 // Operand 1 is a register operand in the R/M field. 505 // - In AVX512 there may be a mask operand here - 506 // Operand 2 is a register operand in the Reg/Opcode field. 507 // - In AVX, there is a register operand in the VEX.vvvv field here - 508 // Operand 3 (optional) is an immediate. 509 assert(numPhysicalOperands >= 2 + additionalOperands && 510 numPhysicalOperands <= 3 + additionalOperands && 511 "Unexpected number of operands for MRMDestRegFrm"); 512 513 HANDLE_OPERAND(rmRegister) 514 if (HasEVEX_K) 515 HANDLE_OPERAND(writemaskRegister) 516 517 if (HasVEX_4V) 518 // FIXME: In AVX, the register below becomes the one encoded 519 // in ModRMVEX and the one above the one in the VEX.VVVV field 520 HANDLE_OPERAND(vvvvRegister) 521 522 HANDLE_OPERAND(roRegister) 523 HANDLE_OPTIONAL(immediate) 524 break; 525 case X86Local::MRMDestMem: 526 case X86Local::MRMDestMemFSIB: 527 // Operand 1 is a memory operand (possibly SIB-extended) 528 // Operand 2 is a register operand in the Reg/Opcode field. 529 // - In AVX, there is a register operand in the VEX.vvvv field here - 530 // Operand 3 (optional) is an immediate. 531 assert(numPhysicalOperands >= 2 + additionalOperands && 532 numPhysicalOperands <= 3 + additionalOperands && 533 "Unexpected number of operands for MRMDestMemFrm with VEX_4V"); 534 535 HANDLE_OPERAND(memory) 536 537 if (HasEVEX_K) 538 HANDLE_OPERAND(writemaskRegister) 539 540 if (HasVEX_4V) 541 // FIXME: In AVX, the register below becomes the one encoded 542 // in ModRMVEX and the one above the one in the VEX.VVVV field 543 HANDLE_OPERAND(vvvvRegister) 544 545 HANDLE_OPERAND(roRegister) 546 HANDLE_OPTIONAL(immediate) 547 break; 548 case X86Local::MRMSrcReg: 549 // Operand 1 is a register operand in the Reg/Opcode field. 550 // Operand 2 is a register operand in the R/M field. 551 // - In AVX, there is a register operand in the VEX.vvvv field here - 552 // Operand 3 (optional) is an immediate. 553 // Operand 4 (optional) is an immediate. 554 555 assert(numPhysicalOperands >= 2 + additionalOperands && 556 numPhysicalOperands <= 4 + additionalOperands && 557 "Unexpected number of operands for MRMSrcRegFrm"); 558 559 HANDLE_OPERAND(roRegister) 560 561 if (HasEVEX_K) 562 HANDLE_OPERAND(writemaskRegister) 563 564 if (HasVEX_4V) 565 // FIXME: In AVX, the register below becomes the one encoded 566 // in ModRMVEX and the one above the one in the VEX.VVVV field 567 HANDLE_OPERAND(vvvvRegister) 568 569 HANDLE_OPERAND(rmRegister) 570 HANDLE_OPTIONAL(immediate) 571 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4 572 break; 573 case X86Local::MRMSrcReg4VOp3: 574 assert(numPhysicalOperands == 3 && 575 "Unexpected number of operands for MRMSrcReg4VOp3Frm"); 576 HANDLE_OPERAND(roRegister) 577 HANDLE_OPERAND(rmRegister) 578 HANDLE_OPERAND(vvvvRegister) 579 break; 580 case X86Local::MRMSrcRegOp4: 581 assert(numPhysicalOperands >= 4 && numPhysicalOperands <= 5 && 582 "Unexpected number of operands for MRMSrcRegOp4Frm"); 583 HANDLE_OPERAND(roRegister) 584 HANDLE_OPERAND(vvvvRegister) 585 HANDLE_OPERAND(immediate) // Register in imm[7:4] 586 HANDLE_OPERAND(rmRegister) 587 HANDLE_OPTIONAL(immediate) 588 break; 589 case X86Local::MRMSrcRegCC: 590 assert(numPhysicalOperands == 3 && 591 "Unexpected number of operands for MRMSrcRegCC"); 592 HANDLE_OPERAND(roRegister) 593 HANDLE_OPERAND(rmRegister) 594 HANDLE_OPERAND(opcodeModifier) 595 break; 596 case X86Local::MRMSrcMem: 597 case X86Local::MRMSrcMemFSIB: 598 // Operand 1 is a register operand in the Reg/Opcode field. 599 // Operand 2 is a memory operand (possibly SIB-extended) 600 // - In AVX, there is a register operand in the VEX.vvvv field here - 601 // Operand 3 (optional) is an immediate. 602 603 assert(numPhysicalOperands >= 2 + additionalOperands && 604 numPhysicalOperands <= 4 + additionalOperands && 605 "Unexpected number of operands for MRMSrcMemFrm"); 606 607 HANDLE_OPERAND(roRegister) 608 609 if (HasEVEX_K) 610 HANDLE_OPERAND(writemaskRegister) 611 612 if (HasVEX_4V) 613 // FIXME: In AVX, the register below becomes the one encoded 614 // in ModRMVEX and the one above the one in the VEX.VVVV field 615 HANDLE_OPERAND(vvvvRegister) 616 617 HANDLE_OPERAND(memory) 618 HANDLE_OPTIONAL(immediate) 619 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4 620 break; 621 case X86Local::MRMSrcMem4VOp3: 622 assert(numPhysicalOperands == 3 && 623 "Unexpected number of operands for MRMSrcMem4VOp3Frm"); 624 HANDLE_OPERAND(roRegister) 625 HANDLE_OPERAND(memory) 626 HANDLE_OPERAND(vvvvRegister) 627 break; 628 case X86Local::MRMSrcMemOp4: 629 assert(numPhysicalOperands >= 4 && numPhysicalOperands <= 5 && 630 "Unexpected number of operands for MRMSrcMemOp4Frm"); 631 HANDLE_OPERAND(roRegister) 632 HANDLE_OPERAND(vvvvRegister) 633 HANDLE_OPERAND(immediate) // Register in imm[7:4] 634 HANDLE_OPERAND(memory) 635 HANDLE_OPTIONAL(immediate) 636 break; 637 case X86Local::MRMSrcMemCC: 638 assert(numPhysicalOperands == 3 && 639 "Unexpected number of operands for MRMSrcMemCC"); 640 HANDLE_OPERAND(roRegister) 641 HANDLE_OPERAND(memory) 642 HANDLE_OPERAND(opcodeModifier) 643 break; 644 case X86Local::MRMXrCC: 645 assert(numPhysicalOperands == 2 && 646 "Unexpected number of operands for MRMXrCC"); 647 HANDLE_OPERAND(rmRegister) 648 HANDLE_OPERAND(opcodeModifier) 649 break; 650 case X86Local::MRMr0: 651 // Operand 1 is a register operand in the R/M field. 652 HANDLE_OPERAND(roRegister) 653 break; 654 case X86Local::MRMXr: 655 case X86Local::MRM0r: 656 case X86Local::MRM1r: 657 case X86Local::MRM2r: 658 case X86Local::MRM3r: 659 case X86Local::MRM4r: 660 case X86Local::MRM5r: 661 case X86Local::MRM6r: 662 case X86Local::MRM7r: 663 // Operand 1 is a register operand in the R/M field. 664 // Operand 2 (optional) is an immediate or relocation. 665 // Operand 3 (optional) is an immediate. 666 assert(numPhysicalOperands >= 0 + additionalOperands && 667 numPhysicalOperands <= 3 + additionalOperands && 668 "Unexpected number of operands for MRMnr"); 669 670 if (HasVEX_4V) 671 HANDLE_OPERAND(vvvvRegister) 672 673 if (HasEVEX_K) 674 HANDLE_OPERAND(writemaskRegister) 675 HANDLE_OPTIONAL(rmRegister) 676 HANDLE_OPTIONAL(relocation) 677 HANDLE_OPTIONAL(immediate) 678 break; 679 case X86Local::MRMXmCC: 680 assert(numPhysicalOperands == 2 && 681 "Unexpected number of operands for MRMXm"); 682 HANDLE_OPERAND(memory) 683 HANDLE_OPERAND(opcodeModifier) 684 break; 685 case X86Local::MRMXm: 686 case X86Local::MRM0m: 687 case X86Local::MRM1m: 688 case X86Local::MRM2m: 689 case X86Local::MRM3m: 690 case X86Local::MRM4m: 691 case X86Local::MRM5m: 692 case X86Local::MRM6m: 693 case X86Local::MRM7m: 694 // Operand 1 is a memory operand (possibly SIB-extended) 695 // Operand 2 (optional) is an immediate or relocation. 696 assert(numPhysicalOperands >= 1 + additionalOperands && 697 numPhysicalOperands <= 2 + additionalOperands && 698 "Unexpected number of operands for MRMnm"); 699 700 if (HasVEX_4V) 701 HANDLE_OPERAND(vvvvRegister) 702 if (HasEVEX_K) 703 HANDLE_OPERAND(writemaskRegister) 704 HANDLE_OPERAND(memory) 705 HANDLE_OPTIONAL(relocation) 706 break; 707 case X86Local::RawFrmImm8: 708 // operand 1 is a 16-bit immediate 709 // operand 2 is an 8-bit immediate 710 assert(numPhysicalOperands == 2 && 711 "Unexpected number of operands for X86Local::RawFrmImm8"); 712 HANDLE_OPERAND(immediate) 713 HANDLE_OPERAND(immediate) 714 break; 715 case X86Local::RawFrmImm16: 716 // operand 1 is a 16-bit immediate 717 // operand 2 is a 16-bit immediate 718 HANDLE_OPERAND(immediate) 719 HANDLE_OPERAND(immediate) 720 break; 721 case X86Local::MRM0X: 722 case X86Local::MRM1X: 723 case X86Local::MRM2X: 724 case X86Local::MRM3X: 725 case X86Local::MRM4X: 726 case X86Local::MRM5X: 727 case X86Local::MRM6X: 728 case X86Local::MRM7X: 729 #define MAP(from, to) case X86Local::MRM_##from: 730 X86_INSTR_MRM_MAPPING 731 #undef MAP 732 HANDLE_OPTIONAL(relocation) 733 break; 734 } 735 736 #undef HANDLE_OPERAND 737 #undef HANDLE_OPTIONAL 738 } 739 740 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const { 741 // Special cases where the LLVM tables are not complete 742 743 #define MAP(from, to) \ 744 case X86Local::MRM_##from: 745 746 llvm::Optional<OpcodeType> opcodeType; 747 switch (OpMap) { 748 default: llvm_unreachable("Invalid map!"); 749 case X86Local::OB: opcodeType = ONEBYTE; break; 750 case X86Local::TB: opcodeType = TWOBYTE; break; 751 case X86Local::T8: opcodeType = THREEBYTE_38; break; 752 case X86Local::TA: opcodeType = THREEBYTE_3A; break; 753 case X86Local::XOP8: opcodeType = XOP8_MAP; break; 754 case X86Local::XOP9: opcodeType = XOP9_MAP; break; 755 case X86Local::XOPA: opcodeType = XOPA_MAP; break; 756 case X86Local::ThreeDNow: opcodeType = THREEDNOW_MAP; break; 757 case X86Local::T_MAP5: opcodeType = MAP5; break; 758 case X86Local::T_MAP6: opcodeType = MAP6; break; 759 } 760 761 std::unique_ptr<ModRMFilter> filter; 762 switch (Form) { 763 default: llvm_unreachable("Invalid form!"); 764 case X86Local::Pseudo: llvm_unreachable("Pseudo should not be emitted!"); 765 case X86Local::RawFrm: 766 case X86Local::AddRegFrm: 767 case X86Local::RawFrmMemOffs: 768 case X86Local::RawFrmSrc: 769 case X86Local::RawFrmDst: 770 case X86Local::RawFrmDstSrc: 771 case X86Local::RawFrmImm8: 772 case X86Local::RawFrmImm16: 773 case X86Local::AddCCFrm: 774 case X86Local::PrefixByte: 775 filter = std::make_unique<DumbFilter>(); 776 break; 777 case X86Local::MRMDestReg: 778 case X86Local::MRMSrcReg: 779 case X86Local::MRMSrcReg4VOp3: 780 case X86Local::MRMSrcRegOp4: 781 case X86Local::MRMSrcRegCC: 782 case X86Local::MRMXrCC: 783 case X86Local::MRMXr: 784 filter = std::make_unique<ModFilter>(true); 785 break; 786 case X86Local::MRMDestMem: 787 case X86Local::MRMDestMemFSIB: 788 case X86Local::MRMSrcMem: 789 case X86Local::MRMSrcMemFSIB: 790 case X86Local::MRMSrcMem4VOp3: 791 case X86Local::MRMSrcMemOp4: 792 case X86Local::MRMSrcMemCC: 793 case X86Local::MRMXmCC: 794 case X86Local::MRMXm: 795 filter = std::make_unique<ModFilter>(false); 796 break; 797 case X86Local::MRM0r: case X86Local::MRM1r: 798 case X86Local::MRM2r: case X86Local::MRM3r: 799 case X86Local::MRM4r: case X86Local::MRM5r: 800 case X86Local::MRM6r: case X86Local::MRM7r: 801 filter = std::make_unique<ExtendedFilter>(true, Form - X86Local::MRM0r); 802 break; 803 case X86Local::MRM0X: case X86Local::MRM1X: 804 case X86Local::MRM2X: case X86Local::MRM3X: 805 case X86Local::MRM4X: case X86Local::MRM5X: 806 case X86Local::MRM6X: case X86Local::MRM7X: 807 filter = std::make_unique<ExtendedFilter>(true, Form - X86Local::MRM0X); 808 break; 809 case X86Local::MRMr0: 810 filter = std::make_unique<ExtendedRMFilter>(true, Form - X86Local::MRMr0); 811 break; 812 case X86Local::MRM0m: case X86Local::MRM1m: 813 case X86Local::MRM2m: case X86Local::MRM3m: 814 case X86Local::MRM4m: case X86Local::MRM5m: 815 case X86Local::MRM6m: case X86Local::MRM7m: 816 filter = std::make_unique<ExtendedFilter>(false, Form - X86Local::MRM0m); 817 break; 818 X86_INSTR_MRM_MAPPING 819 filter = std::make_unique<ExactFilter>(0xC0 + Form - X86Local::MRM_C0); 820 break; 821 } // switch (Form) 822 823 uint8_t opcodeToSet = Opcode; 824 825 unsigned AddressSize = 0; 826 switch (AdSize) { 827 case X86Local::AdSize16: AddressSize = 16; break; 828 case X86Local::AdSize32: AddressSize = 32; break; 829 case X86Local::AdSize64: AddressSize = 64; break; 830 } 831 832 assert(opcodeType && "Opcode type not set"); 833 assert(filter && "Filter not set"); 834 835 if (Form == X86Local::AddRegFrm || Form == X86Local::MRMSrcRegCC || 836 Form == X86Local::MRMSrcMemCC || Form == X86Local::MRMXrCC || 837 Form == X86Local::MRMXmCC || Form == X86Local::AddCCFrm) { 838 unsigned Count = Form == X86Local::AddRegFrm ? 8 : 16; 839 assert(((opcodeToSet % Count) == 0) && "ADDREG_FRM opcode not aligned"); 840 841 uint8_t currentOpcode; 842 843 for (currentOpcode = opcodeToSet; currentOpcode < opcodeToSet + Count; 844 ++currentOpcode) 845 tables.setTableFields(*opcodeType, insnContext(), currentOpcode, *filter, 846 UID, Is32Bit, OpPrefix == 0, 847 IgnoresVEX_L || EncodeRC, 848 IgnoresVEX_W, AddressSize); 849 } else { 850 tables.setTableFields(*opcodeType, insnContext(), opcodeToSet, *filter, UID, 851 Is32Bit, OpPrefix == 0, IgnoresVEX_L || EncodeRC, 852 IgnoresVEX_W, AddressSize); 853 } 854 855 #undef MAP 856 } 857 858 #define TYPE(str, type) if (s == str) return type; 859 OperandType RecognizableInstr::typeFromString(const std::string &s, 860 bool hasREX_WPrefix, 861 uint8_t OpSize) { 862 if(hasREX_WPrefix) { 863 // For instructions with a REX_W prefix, a declared 32-bit register encoding 864 // is special. 865 TYPE("GR32", TYPE_R32) 866 } 867 if(OpSize == X86Local::OpSize16) { 868 // For OpSize16 instructions, a declared 16-bit register or 869 // immediate encoding is special. 870 TYPE("GR16", TYPE_Rv) 871 } else if(OpSize == X86Local::OpSize32) { 872 // For OpSize32 instructions, a declared 32-bit register or 873 // immediate encoding is special. 874 TYPE("GR32", TYPE_Rv) 875 } 876 TYPE("i16mem", TYPE_M) 877 TYPE("i16imm", TYPE_IMM) 878 TYPE("i16i8imm", TYPE_IMM) 879 TYPE("GR16", TYPE_R16) 880 TYPE("GR16orGR32orGR64", TYPE_R16) 881 TYPE("i32mem", TYPE_M) 882 TYPE("i32imm", TYPE_IMM) 883 TYPE("i32i8imm", TYPE_IMM) 884 TYPE("GR32", TYPE_R32) 885 TYPE("GR32orGR64", TYPE_R32) 886 TYPE("i64mem", TYPE_M) 887 TYPE("i64i32imm", TYPE_IMM) 888 TYPE("i64i8imm", TYPE_IMM) 889 TYPE("GR64", TYPE_R64) 890 TYPE("i8mem", TYPE_M) 891 TYPE("i8imm", TYPE_IMM) 892 TYPE("u4imm", TYPE_UIMM8) 893 TYPE("u8imm", TYPE_UIMM8) 894 TYPE("i16u8imm", TYPE_UIMM8) 895 TYPE("i32u8imm", TYPE_UIMM8) 896 TYPE("i64u8imm", TYPE_UIMM8) 897 TYPE("GR8", TYPE_R8) 898 TYPE("VR128", TYPE_XMM) 899 TYPE("VR128X", TYPE_XMM) 900 TYPE("f128mem", TYPE_M) 901 TYPE("f256mem", TYPE_M) 902 TYPE("f512mem", TYPE_M) 903 TYPE("FR128", TYPE_XMM) 904 TYPE("FR64", TYPE_XMM) 905 TYPE("FR64X", TYPE_XMM) 906 TYPE("f64mem", TYPE_M) 907 TYPE("sdmem", TYPE_M) 908 TYPE("FR16X", TYPE_XMM) 909 TYPE("FR32", TYPE_XMM) 910 TYPE("FR32X", TYPE_XMM) 911 TYPE("f32mem", TYPE_M) 912 TYPE("f16mem", TYPE_M) 913 TYPE("ssmem", TYPE_M) 914 TYPE("shmem", TYPE_M) 915 TYPE("RST", TYPE_ST) 916 TYPE("RSTi", TYPE_ST) 917 TYPE("i128mem", TYPE_M) 918 TYPE("i256mem", TYPE_M) 919 TYPE("i512mem", TYPE_M) 920 TYPE("i64i32imm_brtarget", TYPE_REL) 921 TYPE("i16imm_brtarget", TYPE_REL) 922 TYPE("i32imm_brtarget", TYPE_REL) 923 TYPE("ccode", TYPE_IMM) 924 TYPE("AVX512RC", TYPE_IMM) 925 TYPE("brtarget32", TYPE_REL) 926 TYPE("brtarget16", TYPE_REL) 927 TYPE("brtarget8", TYPE_REL) 928 TYPE("f80mem", TYPE_M) 929 TYPE("lea64_32mem", TYPE_M) 930 TYPE("lea64mem", TYPE_M) 931 TYPE("VR64", TYPE_MM64) 932 TYPE("i64imm", TYPE_IMM) 933 TYPE("anymem", TYPE_M) 934 TYPE("opaquemem", TYPE_M) 935 TYPE("sibmem", TYPE_MSIB) 936 TYPE("SEGMENT_REG", TYPE_SEGMENTREG) 937 TYPE("DEBUG_REG", TYPE_DEBUGREG) 938 TYPE("CONTROL_REG", TYPE_CONTROLREG) 939 TYPE("srcidx8", TYPE_SRCIDX) 940 TYPE("srcidx16", TYPE_SRCIDX) 941 TYPE("srcidx32", TYPE_SRCIDX) 942 TYPE("srcidx64", TYPE_SRCIDX) 943 TYPE("dstidx8", TYPE_DSTIDX) 944 TYPE("dstidx16", TYPE_DSTIDX) 945 TYPE("dstidx32", TYPE_DSTIDX) 946 TYPE("dstidx64", TYPE_DSTIDX) 947 TYPE("offset16_8", TYPE_MOFFS) 948 TYPE("offset16_16", TYPE_MOFFS) 949 TYPE("offset16_32", TYPE_MOFFS) 950 TYPE("offset32_8", TYPE_MOFFS) 951 TYPE("offset32_16", TYPE_MOFFS) 952 TYPE("offset32_32", TYPE_MOFFS) 953 TYPE("offset32_64", TYPE_MOFFS) 954 TYPE("offset64_8", TYPE_MOFFS) 955 TYPE("offset64_16", TYPE_MOFFS) 956 TYPE("offset64_32", TYPE_MOFFS) 957 TYPE("offset64_64", TYPE_MOFFS) 958 TYPE("VR256", TYPE_YMM) 959 TYPE("VR256X", TYPE_YMM) 960 TYPE("VR512", TYPE_ZMM) 961 TYPE("VK1", TYPE_VK) 962 TYPE("VK1WM", TYPE_VK) 963 TYPE("VK2", TYPE_VK) 964 TYPE("VK2WM", TYPE_VK) 965 TYPE("VK4", TYPE_VK) 966 TYPE("VK4WM", TYPE_VK) 967 TYPE("VK8", TYPE_VK) 968 TYPE("VK8WM", TYPE_VK) 969 TYPE("VK16", TYPE_VK) 970 TYPE("VK16WM", TYPE_VK) 971 TYPE("VK32", TYPE_VK) 972 TYPE("VK32WM", TYPE_VK) 973 TYPE("VK64", TYPE_VK) 974 TYPE("VK64WM", TYPE_VK) 975 TYPE("VK1Pair", TYPE_VK_PAIR) 976 TYPE("VK2Pair", TYPE_VK_PAIR) 977 TYPE("VK4Pair", TYPE_VK_PAIR) 978 TYPE("VK8Pair", TYPE_VK_PAIR) 979 TYPE("VK16Pair", TYPE_VK_PAIR) 980 TYPE("vx64mem", TYPE_MVSIBX) 981 TYPE("vx128mem", TYPE_MVSIBX) 982 TYPE("vx256mem", TYPE_MVSIBX) 983 TYPE("vy128mem", TYPE_MVSIBY) 984 TYPE("vy256mem", TYPE_MVSIBY) 985 TYPE("vx64xmem", TYPE_MVSIBX) 986 TYPE("vx128xmem", TYPE_MVSIBX) 987 TYPE("vx256xmem", TYPE_MVSIBX) 988 TYPE("vy128xmem", TYPE_MVSIBY) 989 TYPE("vy256xmem", TYPE_MVSIBY) 990 TYPE("vy512xmem", TYPE_MVSIBY) 991 TYPE("vz256mem", TYPE_MVSIBZ) 992 TYPE("vz512mem", TYPE_MVSIBZ) 993 TYPE("BNDR", TYPE_BNDR) 994 TYPE("TILE", TYPE_TMM) 995 errs() << "Unhandled type string " << s << "\n"; 996 llvm_unreachable("Unhandled type string"); 997 } 998 #undef TYPE 999 1000 #define ENCODING(str, encoding) if (s == str) return encoding; 1001 OperandEncoding 1002 RecognizableInstr::immediateEncodingFromString(const std::string &s, 1003 uint8_t OpSize) { 1004 if(OpSize != X86Local::OpSize16) { 1005 // For instructions without an OpSize prefix, a declared 16-bit register or 1006 // immediate encoding is special. 1007 ENCODING("i16imm", ENCODING_IW) 1008 } 1009 ENCODING("i32i8imm", ENCODING_IB) 1010 ENCODING("AVX512RC", ENCODING_IRC) 1011 ENCODING("i16imm", ENCODING_Iv) 1012 ENCODING("i16i8imm", ENCODING_IB) 1013 ENCODING("i32imm", ENCODING_Iv) 1014 ENCODING("i64i32imm", ENCODING_ID) 1015 ENCODING("i64i8imm", ENCODING_IB) 1016 ENCODING("i8imm", ENCODING_IB) 1017 ENCODING("u4imm", ENCODING_IB) 1018 ENCODING("u8imm", ENCODING_IB) 1019 ENCODING("i16u8imm", ENCODING_IB) 1020 ENCODING("i32u8imm", ENCODING_IB) 1021 ENCODING("i64u8imm", ENCODING_IB) 1022 // This is not a typo. Instructions like BLENDVPD put 1023 // register IDs in 8-bit immediates nowadays. 1024 ENCODING("FR32", ENCODING_IB) 1025 ENCODING("FR64", ENCODING_IB) 1026 ENCODING("FR128", ENCODING_IB) 1027 ENCODING("VR128", ENCODING_IB) 1028 ENCODING("VR256", ENCODING_IB) 1029 ENCODING("FR16X", ENCODING_IB) 1030 ENCODING("FR32X", ENCODING_IB) 1031 ENCODING("FR64X", ENCODING_IB) 1032 ENCODING("VR128X", ENCODING_IB) 1033 ENCODING("VR256X", ENCODING_IB) 1034 ENCODING("VR512", ENCODING_IB) 1035 ENCODING("TILE", ENCODING_IB) 1036 errs() << "Unhandled immediate encoding " << s << "\n"; 1037 llvm_unreachable("Unhandled immediate encoding"); 1038 } 1039 1040 OperandEncoding 1041 RecognizableInstr::rmRegisterEncodingFromString(const std::string &s, 1042 uint8_t OpSize) { 1043 ENCODING("RST", ENCODING_FP) 1044 ENCODING("RSTi", ENCODING_FP) 1045 ENCODING("GR16", ENCODING_RM) 1046 ENCODING("GR16orGR32orGR64",ENCODING_RM) 1047 ENCODING("GR32", ENCODING_RM) 1048 ENCODING("GR32orGR64", ENCODING_RM) 1049 ENCODING("GR64", ENCODING_RM) 1050 ENCODING("GR8", ENCODING_RM) 1051 ENCODING("VR128", ENCODING_RM) 1052 ENCODING("VR128X", ENCODING_RM) 1053 ENCODING("FR128", ENCODING_RM) 1054 ENCODING("FR64", ENCODING_RM) 1055 ENCODING("FR32", ENCODING_RM) 1056 ENCODING("FR64X", ENCODING_RM) 1057 ENCODING("FR32X", ENCODING_RM) 1058 ENCODING("FR16X", ENCODING_RM) 1059 ENCODING("VR64", ENCODING_RM) 1060 ENCODING("VR256", ENCODING_RM) 1061 ENCODING("VR256X", ENCODING_RM) 1062 ENCODING("VR512", ENCODING_RM) 1063 ENCODING("VK1", ENCODING_RM) 1064 ENCODING("VK2", ENCODING_RM) 1065 ENCODING("VK4", ENCODING_RM) 1066 ENCODING("VK8", ENCODING_RM) 1067 ENCODING("VK16", ENCODING_RM) 1068 ENCODING("VK32", ENCODING_RM) 1069 ENCODING("VK64", ENCODING_RM) 1070 ENCODING("BNDR", ENCODING_RM) 1071 ENCODING("TILE", ENCODING_RM) 1072 errs() << "Unhandled R/M register encoding " << s << "\n"; 1073 llvm_unreachable("Unhandled R/M register encoding"); 1074 } 1075 1076 OperandEncoding 1077 RecognizableInstr::roRegisterEncodingFromString(const std::string &s, 1078 uint8_t OpSize) { 1079 ENCODING("GR16", ENCODING_REG) 1080 ENCODING("GR16orGR32orGR64",ENCODING_REG) 1081 ENCODING("GR32", ENCODING_REG) 1082 ENCODING("GR32orGR64", ENCODING_REG) 1083 ENCODING("GR64", ENCODING_REG) 1084 ENCODING("GR8", ENCODING_REG) 1085 ENCODING("VR128", ENCODING_REG) 1086 ENCODING("FR128", ENCODING_REG) 1087 ENCODING("FR64", ENCODING_REG) 1088 ENCODING("FR32", ENCODING_REG) 1089 ENCODING("VR64", ENCODING_REG) 1090 ENCODING("SEGMENT_REG", ENCODING_REG) 1091 ENCODING("DEBUG_REG", ENCODING_REG) 1092 ENCODING("CONTROL_REG", ENCODING_REG) 1093 ENCODING("VR256", ENCODING_REG) 1094 ENCODING("VR256X", ENCODING_REG) 1095 ENCODING("VR128X", ENCODING_REG) 1096 ENCODING("FR64X", ENCODING_REG) 1097 ENCODING("FR32X", ENCODING_REG) 1098 ENCODING("FR16X", ENCODING_REG) 1099 ENCODING("VR512", ENCODING_REG) 1100 ENCODING("VK1", ENCODING_REG) 1101 ENCODING("VK2", ENCODING_REG) 1102 ENCODING("VK4", ENCODING_REG) 1103 ENCODING("VK8", ENCODING_REG) 1104 ENCODING("VK16", ENCODING_REG) 1105 ENCODING("VK32", ENCODING_REG) 1106 ENCODING("VK64", ENCODING_REG) 1107 ENCODING("VK1Pair", ENCODING_REG) 1108 ENCODING("VK2Pair", ENCODING_REG) 1109 ENCODING("VK4Pair", ENCODING_REG) 1110 ENCODING("VK8Pair", ENCODING_REG) 1111 ENCODING("VK16Pair", ENCODING_REG) 1112 ENCODING("VK1WM", ENCODING_REG) 1113 ENCODING("VK2WM", ENCODING_REG) 1114 ENCODING("VK4WM", ENCODING_REG) 1115 ENCODING("VK8WM", ENCODING_REG) 1116 ENCODING("VK16WM", ENCODING_REG) 1117 ENCODING("VK32WM", ENCODING_REG) 1118 ENCODING("VK64WM", ENCODING_REG) 1119 ENCODING("BNDR", ENCODING_REG) 1120 ENCODING("TILE", ENCODING_REG) 1121 errs() << "Unhandled reg/opcode register encoding " << s << "\n"; 1122 llvm_unreachable("Unhandled reg/opcode register encoding"); 1123 } 1124 1125 OperandEncoding 1126 RecognizableInstr::vvvvRegisterEncodingFromString(const std::string &s, 1127 uint8_t OpSize) { 1128 ENCODING("GR32", ENCODING_VVVV) 1129 ENCODING("GR64", ENCODING_VVVV) 1130 ENCODING("FR32", ENCODING_VVVV) 1131 ENCODING("FR128", ENCODING_VVVV) 1132 ENCODING("FR64", ENCODING_VVVV) 1133 ENCODING("VR128", ENCODING_VVVV) 1134 ENCODING("VR256", ENCODING_VVVV) 1135 ENCODING("FR16X", ENCODING_VVVV) 1136 ENCODING("FR32X", ENCODING_VVVV) 1137 ENCODING("FR64X", ENCODING_VVVV) 1138 ENCODING("VR128X", ENCODING_VVVV) 1139 ENCODING("VR256X", ENCODING_VVVV) 1140 ENCODING("VR512", ENCODING_VVVV) 1141 ENCODING("VK1", ENCODING_VVVV) 1142 ENCODING("VK2", ENCODING_VVVV) 1143 ENCODING("VK4", ENCODING_VVVV) 1144 ENCODING("VK8", ENCODING_VVVV) 1145 ENCODING("VK16", ENCODING_VVVV) 1146 ENCODING("VK32", ENCODING_VVVV) 1147 ENCODING("VK64", ENCODING_VVVV) 1148 ENCODING("TILE", ENCODING_VVVV) 1149 errs() << "Unhandled VEX.vvvv register encoding " << s << "\n"; 1150 llvm_unreachable("Unhandled VEX.vvvv register encoding"); 1151 } 1152 1153 OperandEncoding 1154 RecognizableInstr::writemaskRegisterEncodingFromString(const std::string &s, 1155 uint8_t OpSize) { 1156 ENCODING("VK1WM", ENCODING_WRITEMASK) 1157 ENCODING("VK2WM", ENCODING_WRITEMASK) 1158 ENCODING("VK4WM", ENCODING_WRITEMASK) 1159 ENCODING("VK8WM", ENCODING_WRITEMASK) 1160 ENCODING("VK16WM", ENCODING_WRITEMASK) 1161 ENCODING("VK32WM", ENCODING_WRITEMASK) 1162 ENCODING("VK64WM", ENCODING_WRITEMASK) 1163 errs() << "Unhandled mask register encoding " << s << "\n"; 1164 llvm_unreachable("Unhandled mask register encoding"); 1165 } 1166 1167 OperandEncoding 1168 RecognizableInstr::memoryEncodingFromString(const std::string &s, 1169 uint8_t OpSize) { 1170 ENCODING("i16mem", ENCODING_RM) 1171 ENCODING("i32mem", ENCODING_RM) 1172 ENCODING("i64mem", ENCODING_RM) 1173 ENCODING("i8mem", ENCODING_RM) 1174 ENCODING("shmem", ENCODING_RM) 1175 ENCODING("ssmem", ENCODING_RM) 1176 ENCODING("sdmem", ENCODING_RM) 1177 ENCODING("f128mem", ENCODING_RM) 1178 ENCODING("f256mem", ENCODING_RM) 1179 ENCODING("f512mem", ENCODING_RM) 1180 ENCODING("f64mem", ENCODING_RM) 1181 ENCODING("f32mem", ENCODING_RM) 1182 ENCODING("f16mem", ENCODING_RM) 1183 ENCODING("i128mem", ENCODING_RM) 1184 ENCODING("i256mem", ENCODING_RM) 1185 ENCODING("i512mem", ENCODING_RM) 1186 ENCODING("f80mem", ENCODING_RM) 1187 ENCODING("lea64_32mem", ENCODING_RM) 1188 ENCODING("lea64mem", ENCODING_RM) 1189 ENCODING("anymem", ENCODING_RM) 1190 ENCODING("opaquemem", ENCODING_RM) 1191 ENCODING("sibmem", ENCODING_SIB) 1192 ENCODING("vx64mem", ENCODING_VSIB) 1193 ENCODING("vx128mem", ENCODING_VSIB) 1194 ENCODING("vx256mem", ENCODING_VSIB) 1195 ENCODING("vy128mem", ENCODING_VSIB) 1196 ENCODING("vy256mem", ENCODING_VSIB) 1197 ENCODING("vx64xmem", ENCODING_VSIB) 1198 ENCODING("vx128xmem", ENCODING_VSIB) 1199 ENCODING("vx256xmem", ENCODING_VSIB) 1200 ENCODING("vy128xmem", ENCODING_VSIB) 1201 ENCODING("vy256xmem", ENCODING_VSIB) 1202 ENCODING("vy512xmem", ENCODING_VSIB) 1203 ENCODING("vz256mem", ENCODING_VSIB) 1204 ENCODING("vz512mem", ENCODING_VSIB) 1205 errs() << "Unhandled memory encoding " << s << "\n"; 1206 llvm_unreachable("Unhandled memory encoding"); 1207 } 1208 1209 OperandEncoding 1210 RecognizableInstr::relocationEncodingFromString(const std::string &s, 1211 uint8_t OpSize) { 1212 if(OpSize != X86Local::OpSize16) { 1213 // For instructions without an OpSize prefix, a declared 16-bit register or 1214 // immediate encoding is special. 1215 ENCODING("i16imm", ENCODING_IW) 1216 } 1217 ENCODING("i16imm", ENCODING_Iv) 1218 ENCODING("i16i8imm", ENCODING_IB) 1219 ENCODING("i32imm", ENCODING_Iv) 1220 ENCODING("i32i8imm", ENCODING_IB) 1221 ENCODING("i64i32imm", ENCODING_ID) 1222 ENCODING("i64i8imm", ENCODING_IB) 1223 ENCODING("i8imm", ENCODING_IB) 1224 ENCODING("u8imm", ENCODING_IB) 1225 ENCODING("i16u8imm", ENCODING_IB) 1226 ENCODING("i32u8imm", ENCODING_IB) 1227 ENCODING("i64u8imm", ENCODING_IB) 1228 ENCODING("i64i32imm_brtarget", ENCODING_ID) 1229 ENCODING("i16imm_brtarget", ENCODING_IW) 1230 ENCODING("i32imm_brtarget", ENCODING_ID) 1231 ENCODING("brtarget32", ENCODING_ID) 1232 ENCODING("brtarget16", ENCODING_IW) 1233 ENCODING("brtarget8", ENCODING_IB) 1234 ENCODING("i64imm", ENCODING_IO) 1235 ENCODING("offset16_8", ENCODING_Ia) 1236 ENCODING("offset16_16", ENCODING_Ia) 1237 ENCODING("offset16_32", ENCODING_Ia) 1238 ENCODING("offset32_8", ENCODING_Ia) 1239 ENCODING("offset32_16", ENCODING_Ia) 1240 ENCODING("offset32_32", ENCODING_Ia) 1241 ENCODING("offset32_64", ENCODING_Ia) 1242 ENCODING("offset64_8", ENCODING_Ia) 1243 ENCODING("offset64_16", ENCODING_Ia) 1244 ENCODING("offset64_32", ENCODING_Ia) 1245 ENCODING("offset64_64", ENCODING_Ia) 1246 ENCODING("srcidx8", ENCODING_SI) 1247 ENCODING("srcidx16", ENCODING_SI) 1248 ENCODING("srcidx32", ENCODING_SI) 1249 ENCODING("srcidx64", ENCODING_SI) 1250 ENCODING("dstidx8", ENCODING_DI) 1251 ENCODING("dstidx16", ENCODING_DI) 1252 ENCODING("dstidx32", ENCODING_DI) 1253 ENCODING("dstidx64", ENCODING_DI) 1254 errs() << "Unhandled relocation encoding " << s << "\n"; 1255 llvm_unreachable("Unhandled relocation encoding"); 1256 } 1257 1258 OperandEncoding 1259 RecognizableInstr::opcodeModifierEncodingFromString(const std::string &s, 1260 uint8_t OpSize) { 1261 ENCODING("GR32", ENCODING_Rv) 1262 ENCODING("GR64", ENCODING_RO) 1263 ENCODING("GR16", ENCODING_Rv) 1264 ENCODING("GR8", ENCODING_RB) 1265 ENCODING("ccode", ENCODING_CC) 1266 errs() << "Unhandled opcode modifier encoding " << s << "\n"; 1267 llvm_unreachable("Unhandled opcode modifier encoding"); 1268 } 1269 #undef ENCODING 1270