1 //===- X86RecognizableInstr.cpp - Disassembler instruction spec --*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file is part of the X86 Disassembler Emitter. 10 // It contains the implementation of a single recognizable instruction. 11 // Documentation for the disassembler emitter in general can be found in 12 // X86DisassemblerEmitter.h. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #include "X86RecognizableInstr.h" 17 #include "X86DisassemblerShared.h" 18 #include "X86DisassemblerTables.h" 19 #include "X86ModRMFilters.h" 20 #include "llvm/Support/ErrorHandling.h" 21 #include "llvm/TableGen/Record.h" 22 #include <string> 23 24 using namespace llvm; 25 using namespace X86Disassembler; 26 27 std::string X86Disassembler::getMnemonic(const CodeGenInstruction *I, 28 unsigned Variant) { 29 std::string AsmString = I->FlattenAsmStringVariants(I->AsmString, Variant); 30 StringRef Mnemonic(AsmString); 31 // Extract a mnemonic assuming it's separated by \t 32 Mnemonic = Mnemonic.take_until([](char C) { return C == '\t'; }); 33 34 // Special case: CMOVCC, JCC, SETCC have "${cond}" in mnemonic. 35 // Replace it with "CC" in-place. 36 size_t CondPos = Mnemonic.find("${cond}"); 37 if (CondPos != StringRef::npos) 38 Mnemonic = AsmString.replace(CondPos, StringRef::npos, "CC"); 39 return Mnemonic.upper(); 40 } 41 42 bool X86Disassembler::isRegisterOperand(const Record *Rec) { 43 return Rec->isSubClassOf("RegisterClass") || 44 Rec->isSubClassOf("RegisterOperand"); 45 } 46 47 bool X86Disassembler::isMemoryOperand(const Record *Rec) { 48 return Rec->isSubClassOf("Operand") && 49 Rec->getValueAsString("OperandType") == "OPERAND_MEMORY"; 50 } 51 52 bool X86Disassembler::isImmediateOperand(const Record *Rec) { 53 return Rec->isSubClassOf("Operand") && 54 Rec->getValueAsString("OperandType") == "OPERAND_IMMEDIATE"; 55 } 56 57 unsigned X86Disassembler::getRegOperandSize(const Record *RegRec) { 58 if (RegRec->isSubClassOf("RegisterClass")) 59 return RegRec->getValueAsInt("Alignment"); 60 if (RegRec->isSubClassOf("RegisterOperand")) 61 return RegRec->getValueAsDef("RegClass")->getValueAsInt("Alignment"); 62 63 llvm_unreachable("Register operand's size not known!"); 64 } 65 66 unsigned X86Disassembler::getMemOperandSize(const Record *MemRec) { 67 if (MemRec->isSubClassOf("X86MemOperand")) 68 return MemRec->getValueAsInt("Size"); 69 70 llvm_unreachable("Memory operand's size not known!"); 71 } 72 73 /// byteFromBitsInit - Extracts a value at most 8 bits in width from a BitsInit. 74 /// Useful for switch statements and the like. 75 /// 76 /// @param init - A reference to the BitsInit to be decoded. 77 /// @return - The field, with the first bit in the BitsInit as the lowest 78 /// order bit. 79 static uint8_t byteFromBitsInit(BitsInit &init) { 80 int width = init.getNumBits(); 81 82 assert(width <= 8 && "Field is too large for uint8_t!"); 83 84 int index; 85 uint8_t mask = 0x01; 86 87 uint8_t ret = 0; 88 89 for (index = 0; index < width; index++) { 90 if (cast<BitInit>(init.getBit(index))->getValue()) 91 ret |= mask; 92 93 mask <<= 1; 94 } 95 96 return ret; 97 } 98 99 /// byteFromRec - Extract a value at most 8 bits in with from a Record given the 100 /// name of the field. 101 /// 102 /// @param rec - The record from which to extract the value. 103 /// @param name - The name of the field in the record. 104 /// @return - The field, as translated by byteFromBitsInit(). 105 static uint8_t byteFromRec(const Record *rec, StringRef name) { 106 BitsInit *bits = rec->getValueAsBitsInit(name); 107 return byteFromBitsInit(*bits); 108 } 109 110 RecognizableInstrBase::RecognizableInstrBase(const CodeGenInstruction &insn) { 111 const Record *Rec = insn.TheDef; 112 assert(Rec->isSubClassOf("X86Inst") && "Not a X86 Instruction"); 113 OpPrefix = byteFromRec(Rec, "OpPrefixBits"); 114 OpMap = byteFromRec(Rec, "OpMapBits"); 115 Opcode = byteFromRec(Rec, "Opcode"); 116 Form = byteFromRec(Rec, "FormBits"); 117 Encoding = byteFromRec(Rec, "OpEncBits"); 118 OpSize = byteFromRec(Rec, "OpSizeBits"); 119 AdSize = byteFromRec(Rec, "AdSizeBits"); 120 HasREX_W = Rec->getValueAsBit("hasREX_W"); 121 HasVEX_4V = Rec->getValueAsBit("hasVEX_4V"); 122 IgnoresW = Rec->getValueAsBit("IgnoresW"); 123 IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L"); 124 HasEVEX_L2 = Rec->getValueAsBit("hasEVEX_L2"); 125 HasEVEX_K = Rec->getValueAsBit("hasEVEX_K"); 126 HasEVEX_KZ = Rec->getValueAsBit("hasEVEX_Z"); 127 HasEVEX_B = Rec->getValueAsBit("hasEVEX_B"); 128 HasEVEX_NF = Rec->getValueAsBit("hasEVEX_NF"); 129 IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly"); 130 IsAsmParserOnly = Rec->getValueAsBit("isAsmParserOnly"); 131 ForceDisassemble = Rec->getValueAsBit("ForceDisassemble"); 132 CD8_Scale = byteFromRec(Rec, "CD8_Scale"); 133 HasVEX_L = Rec->getValueAsBit("hasVEX_L"); 134 ExplicitREX2Prefix = 135 byteFromRec(Rec, "explicitOpPrefixBits") == X86Local::ExplicitREX2; 136 137 EncodeRC = HasEVEX_B && 138 (Form == X86Local::MRMDestReg || Form == X86Local::MRMSrcReg); 139 } 140 141 bool RecognizableInstrBase::shouldBeEmitted() const { 142 return Form != X86Local::Pseudo && (!IsCodeGenOnly || ForceDisassemble) && 143 !IsAsmParserOnly; 144 } 145 146 RecognizableInstr::RecognizableInstr(DisassemblerTables &tables, 147 const CodeGenInstruction &insn, 148 InstrUID uid) 149 : RecognizableInstrBase(insn), Rec(insn.TheDef), Name(Rec->getName().str()), 150 Is32Bit(false), Is64Bit(false), Operands(&insn.Operands.OperandList), 151 UID(uid), Spec(&tables.specForUID(uid)) { 152 // Check for 64-bit inst which does not require REX 153 // FIXME: Is there some better way to check for In64BitMode? 154 std::vector<Record *> Predicates = Rec->getValueAsListOfDefs("Predicates"); 155 for (unsigned i = 0, e = Predicates.size(); i != e; ++i) { 156 if (Predicates[i]->getName().contains("Not64Bit") || 157 Predicates[i]->getName().contains("In32Bit")) { 158 Is32Bit = true; 159 break; 160 } 161 if (Predicates[i]->getName().contains("In64Bit")) { 162 Is64Bit = true; 163 break; 164 } 165 } 166 } 167 168 void RecognizableInstr::processInstr(DisassemblerTables &tables, 169 const CodeGenInstruction &insn, 170 InstrUID uid) { 171 if (!insn.TheDef->isSubClassOf("X86Inst")) 172 return; 173 RecognizableInstr recogInstr(tables, insn, uid); 174 175 if (!recogInstr.shouldBeEmitted()) 176 return; 177 recogInstr.emitInstructionSpecifier(); 178 recogInstr.emitDecodePath(tables); 179 } 180 181 #define EVEX_KB(n) \ 182 (HasEVEX_KZ && HasEVEX_B \ 183 ? n##_KZ_B \ 184 : (HasEVEX_K && HasEVEX_B \ 185 ? n##_K_B \ 186 : (HasEVEX_KZ ? n##_KZ \ 187 : (HasEVEX_K ? n##_K : (HasEVEX_B ? n##_B : n))))) 188 189 #define EVEX_NF(n) (HasEVEX_NF ? n##_NF : n) 190 #define EVEX_B_NF(n) (HasEVEX_B ? EVEX_NF(n##_B) : EVEX_NF(n)) 191 192 InstructionContext RecognizableInstr::insnContext() const { 193 InstructionContext insnContext; 194 195 if (Encoding == X86Local::EVEX) { 196 if (HasVEX_L && HasEVEX_L2) { 197 errs() << "Don't support VEX.L if EVEX_L2 is enabled: " << Name << "\n"; 198 llvm_unreachable("Don't support VEX.L if EVEX_L2 is enabled"); 199 } 200 if (HasEVEX_NF) { 201 if (OpPrefix == X86Local::PD) 202 insnContext = EVEX_B_NF(IC_EVEX_OPSIZE); 203 else if (HasREX_W) 204 insnContext = EVEX_B_NF(IC_EVEX_W); 205 else 206 insnContext = EVEX_B_NF(IC_EVEX); 207 } else if (!EncodeRC && HasVEX_L && HasREX_W) { 208 // VEX_L & VEX_W 209 if (OpPrefix == X86Local::PD) 210 insnContext = EVEX_KB(IC_EVEX_L_W_OPSIZE); 211 else if (OpPrefix == X86Local::XS) 212 insnContext = EVEX_KB(IC_EVEX_L_W_XS); 213 else if (OpPrefix == X86Local::XD) 214 insnContext = EVEX_KB(IC_EVEX_L_W_XD); 215 else if (OpPrefix == X86Local::PS) 216 insnContext = EVEX_KB(IC_EVEX_L_W); 217 else { 218 errs() << "Instruction does not use a prefix: " << Name << "\n"; 219 llvm_unreachable("Invalid prefix"); 220 } 221 } else if (!EncodeRC && HasVEX_L) { 222 // VEX_L 223 if (OpPrefix == X86Local::PD) 224 insnContext = EVEX_KB(IC_EVEX_L_OPSIZE); 225 else if (OpPrefix == X86Local::XS) 226 insnContext = EVEX_KB(IC_EVEX_L_XS); 227 else if (OpPrefix == X86Local::XD) 228 insnContext = EVEX_KB(IC_EVEX_L_XD); 229 else if (OpPrefix == X86Local::PS) 230 insnContext = EVEX_KB(IC_EVEX_L); 231 else { 232 errs() << "Instruction does not use a prefix: " << Name << "\n"; 233 llvm_unreachable("Invalid prefix"); 234 } 235 } else if (!EncodeRC && HasEVEX_L2 && HasREX_W) { 236 // EVEX_L2 & VEX_W 237 if (OpPrefix == X86Local::PD) 238 insnContext = EVEX_KB(IC_EVEX_L2_W_OPSIZE); 239 else if (OpPrefix == X86Local::XS) 240 insnContext = EVEX_KB(IC_EVEX_L2_W_XS); 241 else if (OpPrefix == X86Local::XD) 242 insnContext = EVEX_KB(IC_EVEX_L2_W_XD); 243 else if (OpPrefix == X86Local::PS) 244 insnContext = EVEX_KB(IC_EVEX_L2_W); 245 else { 246 errs() << "Instruction does not use a prefix: " << Name << "\n"; 247 llvm_unreachable("Invalid prefix"); 248 } 249 } else if (!EncodeRC && HasEVEX_L2) { 250 // EVEX_L2 251 if (OpPrefix == X86Local::PD) 252 insnContext = EVEX_KB(IC_EVEX_L2_OPSIZE); 253 else if (OpPrefix == X86Local::XD) 254 insnContext = EVEX_KB(IC_EVEX_L2_XD); 255 else if (OpPrefix == X86Local::XS) 256 insnContext = EVEX_KB(IC_EVEX_L2_XS); 257 else if (OpPrefix == X86Local::PS) 258 insnContext = EVEX_KB(IC_EVEX_L2); 259 else { 260 errs() << "Instruction does not use a prefix: " << Name << "\n"; 261 llvm_unreachable("Invalid prefix"); 262 } 263 } else if (HasREX_W) { 264 // VEX_W 265 if (OpPrefix == X86Local::PD) 266 insnContext = EVEX_KB(IC_EVEX_W_OPSIZE); 267 else if (OpPrefix == X86Local::XS) 268 insnContext = EVEX_KB(IC_EVEX_W_XS); 269 else if (OpPrefix == X86Local::XD) 270 insnContext = EVEX_KB(IC_EVEX_W_XD); 271 else if (OpPrefix == X86Local::PS) 272 insnContext = EVEX_KB(IC_EVEX_W); 273 else { 274 errs() << "Instruction does not use a prefix: " << Name << "\n"; 275 llvm_unreachable("Invalid prefix"); 276 } 277 } 278 // No L, no W 279 else if (OpPrefix == X86Local::PD) { 280 if (AdSize == X86Local::AdSize32) 281 insnContext = IC_EVEX_OPSIZE_ADSIZE; 282 else 283 insnContext = EVEX_KB(IC_EVEX_OPSIZE); 284 } else if (OpPrefix == X86Local::XD) 285 insnContext = EVEX_KB(IC_EVEX_XD); 286 else if (OpPrefix == X86Local::XS) 287 insnContext = EVEX_KB(IC_EVEX_XS); 288 else if (OpPrefix == X86Local::PS) 289 insnContext = EVEX_KB(IC_EVEX); 290 else { 291 errs() << "Instruction does not use a prefix: " << Name << "\n"; 292 llvm_unreachable("Invalid prefix"); 293 } 294 /// eof EVEX 295 } else if (Encoding == X86Local::VEX || Encoding == X86Local::XOP) { 296 if (HasVEX_L && HasREX_W) { 297 if (OpPrefix == X86Local::PD) 298 insnContext = IC_VEX_L_W_OPSIZE; 299 else if (OpPrefix == X86Local::XS) 300 insnContext = IC_VEX_L_W_XS; 301 else if (OpPrefix == X86Local::XD) 302 insnContext = IC_VEX_L_W_XD; 303 else if (OpPrefix == X86Local::PS) 304 insnContext = IC_VEX_L_W; 305 else { 306 errs() << "Instruction does not use a prefix: " << Name << "\n"; 307 llvm_unreachable("Invalid prefix"); 308 } 309 } else if (OpPrefix == X86Local::PD && HasVEX_L) 310 insnContext = IC_VEX_L_OPSIZE; 311 else if (OpPrefix == X86Local::PD && HasREX_W) 312 insnContext = IC_VEX_W_OPSIZE; 313 else if (OpPrefix == X86Local::PD) 314 insnContext = IC_VEX_OPSIZE; 315 else if (HasVEX_L && OpPrefix == X86Local::XS) 316 insnContext = IC_VEX_L_XS; 317 else if (HasVEX_L && OpPrefix == X86Local::XD) 318 insnContext = IC_VEX_L_XD; 319 else if (HasREX_W && OpPrefix == X86Local::XS) 320 insnContext = IC_VEX_W_XS; 321 else if (HasREX_W && OpPrefix == X86Local::XD) 322 insnContext = IC_VEX_W_XD; 323 else if (HasREX_W && OpPrefix == X86Local::PS) 324 insnContext = IC_VEX_W; 325 else if (HasVEX_L && OpPrefix == X86Local::PS) 326 insnContext = IC_VEX_L; 327 else if (OpPrefix == X86Local::XD) 328 insnContext = IC_VEX_XD; 329 else if (OpPrefix == X86Local::XS) 330 insnContext = IC_VEX_XS; 331 else if (OpPrefix == X86Local::PS) 332 insnContext = IC_VEX; 333 else { 334 errs() << "Instruction does not use a prefix: " << Name << "\n"; 335 llvm_unreachable("Invalid prefix"); 336 } 337 } else if (Is64Bit || HasREX_W || AdSize == X86Local::AdSize64) { 338 if (HasREX_W && (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD)) 339 insnContext = IC_64BIT_REXW_OPSIZE; 340 else if (HasREX_W && AdSize == X86Local::AdSize32) 341 insnContext = IC_64BIT_REXW_ADSIZE; 342 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD) 343 insnContext = IC_64BIT_XD_OPSIZE; 344 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS) 345 insnContext = IC_64BIT_XS_OPSIZE; 346 else if (AdSize == X86Local::AdSize32 && OpPrefix == X86Local::PD) 347 insnContext = IC_64BIT_OPSIZE_ADSIZE; 348 else if (OpSize == X86Local::OpSize16 && AdSize == X86Local::AdSize32) 349 insnContext = IC_64BIT_OPSIZE_ADSIZE; 350 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD) 351 insnContext = IC_64BIT_OPSIZE; 352 else if (AdSize == X86Local::AdSize32) 353 insnContext = IC_64BIT_ADSIZE; 354 else if (HasREX_W && OpPrefix == X86Local::XS) 355 insnContext = IC_64BIT_REXW_XS; 356 else if (HasREX_W && OpPrefix == X86Local::XD) 357 insnContext = IC_64BIT_REXW_XD; 358 else if (OpPrefix == X86Local::XD) 359 insnContext = IC_64BIT_XD; 360 else if (OpPrefix == X86Local::XS) 361 insnContext = IC_64BIT_XS; 362 else if (ExplicitREX2Prefix) 363 insnContext = IC_64BIT_REX2; 364 else if (HasREX_W) 365 insnContext = IC_64BIT_REXW; 366 else 367 insnContext = IC_64BIT; 368 } else { 369 if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XD) 370 insnContext = IC_XD_OPSIZE; 371 else if (OpSize == X86Local::OpSize16 && OpPrefix == X86Local::XS) 372 insnContext = IC_XS_OPSIZE; 373 else if (AdSize == X86Local::AdSize16 && OpPrefix == X86Local::XD) 374 insnContext = IC_XD_ADSIZE; 375 else if (AdSize == X86Local::AdSize16 && OpPrefix == X86Local::XS) 376 insnContext = IC_XS_ADSIZE; 377 else if (AdSize == X86Local::AdSize16 && OpPrefix == X86Local::PD) 378 insnContext = IC_OPSIZE_ADSIZE; 379 else if (OpSize == X86Local::OpSize16 && AdSize == X86Local::AdSize16) 380 insnContext = IC_OPSIZE_ADSIZE; 381 else if (OpSize == X86Local::OpSize16 || OpPrefix == X86Local::PD) 382 insnContext = IC_OPSIZE; 383 else if (AdSize == X86Local::AdSize16) 384 insnContext = IC_ADSIZE; 385 else if (OpPrefix == X86Local::XD) 386 insnContext = IC_XD; 387 else if (OpPrefix == X86Local::XS) 388 insnContext = IC_XS; 389 else 390 insnContext = IC; 391 } 392 393 return insnContext; 394 } 395 396 void RecognizableInstr::adjustOperandEncoding(OperandEncoding &encoding) { 397 // The scaling factor for AVX512 compressed displacement encoding is an 398 // instruction attribute. Adjust the ModRM encoding type to include the 399 // scale for compressed displacement. 400 if ((encoding != ENCODING_RM && encoding != ENCODING_VSIB && 401 encoding != ENCODING_SIB) || 402 CD8_Scale == 0) 403 return; 404 encoding = (OperandEncoding)(encoding + Log2_32(CD8_Scale)); 405 assert(((encoding >= ENCODING_RM && encoding <= ENCODING_RM_CD64) || 406 (encoding == ENCODING_SIB) || 407 (encoding >= ENCODING_VSIB && encoding <= ENCODING_VSIB_CD64)) && 408 "Invalid CDisp scaling"); 409 } 410 411 void RecognizableInstr::handleOperand( 412 bool optional, unsigned &operandIndex, unsigned &physicalOperandIndex, 413 unsigned numPhysicalOperands, const unsigned *operandMapping, 414 OperandEncoding (*encodingFromString)(const std::string &, 415 uint8_t OpSize)) { 416 if (optional) { 417 if (physicalOperandIndex >= numPhysicalOperands) 418 return; 419 } else { 420 assert(physicalOperandIndex < numPhysicalOperands); 421 } 422 423 while (operandMapping[operandIndex] != operandIndex) { 424 Spec->operands[operandIndex].encoding = ENCODING_DUP; 425 Spec->operands[operandIndex].type = 426 (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]); 427 ++operandIndex; 428 } 429 430 StringRef typeName = (*Operands)[operandIndex].Rec->getName(); 431 432 OperandEncoding encoding = encodingFromString(std::string(typeName), OpSize); 433 // Adjust the encoding type for an operand based on the instruction. 434 adjustOperandEncoding(encoding); 435 Spec->operands[operandIndex].encoding = encoding; 436 Spec->operands[operandIndex].type = 437 typeFromString(std::string(typeName), HasREX_W, OpSize); 438 439 ++operandIndex; 440 ++physicalOperandIndex; 441 } 442 443 void RecognizableInstr::emitInstructionSpecifier() { 444 Spec->name = Name; 445 446 Spec->insnContext = insnContext(); 447 448 const std::vector<CGIOperandList::OperandInfo> &OperandList = *Operands; 449 450 unsigned numOperands = OperandList.size(); 451 unsigned numPhysicalOperands = 0; 452 453 // operandMapping maps from operands in OperandList to their originals. 454 // If operandMapping[i] != i, then the entry is a duplicate. 455 unsigned operandMapping[X86_MAX_OPERANDS]; 456 assert(numOperands <= X86_MAX_OPERANDS && 457 "X86_MAX_OPERANDS is not large enough"); 458 459 for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) { 460 if (!OperandList[operandIndex].Constraints.empty()) { 461 const CGIOperandList::ConstraintInfo &Constraint = 462 OperandList[operandIndex].Constraints[0]; 463 if (Constraint.isTied()) { 464 operandMapping[operandIndex] = operandIndex; 465 operandMapping[Constraint.getTiedOperand()] = operandIndex; 466 } else { 467 ++numPhysicalOperands; 468 operandMapping[operandIndex] = operandIndex; 469 } 470 } else { 471 ++numPhysicalOperands; 472 operandMapping[operandIndex] = operandIndex; 473 } 474 } 475 476 #define HANDLE_OPERAND(class) \ 477 handleOperand(false, operandIndex, physicalOperandIndex, \ 478 numPhysicalOperands, operandMapping, \ 479 class##EncodingFromString); 480 481 #define HANDLE_OPTIONAL(class) \ 482 handleOperand(true, operandIndex, physicalOperandIndex, numPhysicalOperands, \ 483 operandMapping, class##EncodingFromString); 484 485 // operandIndex should always be < numOperands 486 unsigned operandIndex = 0; 487 // physicalOperandIndex should always be < numPhysicalOperands 488 unsigned physicalOperandIndex = 0; 489 490 #ifndef NDEBUG 491 // Given the set of prefix bits, how many additional operands does the 492 // instruction have? 493 unsigned additionalOperands = 0; 494 if (HasVEX_4V) 495 ++additionalOperands; 496 if (HasEVEX_K) 497 ++additionalOperands; 498 #endif 499 500 bool IsND = OpMap == X86Local::T_MAP4 && HasEVEX_B && HasVEX_4V; 501 switch (Form) { 502 default: 503 llvm_unreachable("Unhandled form"); 504 case X86Local::PrefixByte: 505 return; 506 case X86Local::RawFrmSrc: 507 HANDLE_OPERAND(relocation); 508 return; 509 case X86Local::RawFrmDst: 510 HANDLE_OPERAND(relocation); 511 return; 512 case X86Local::RawFrmDstSrc: 513 HANDLE_OPERAND(relocation); 514 HANDLE_OPERAND(relocation); 515 return; 516 case X86Local::RawFrm: 517 // Operand 1 (optional) is an address or immediate. 518 assert(numPhysicalOperands <= 1 && 519 "Unexpected number of operands for RawFrm"); 520 HANDLE_OPTIONAL(relocation) 521 break; 522 case X86Local::RawFrmMemOffs: 523 // Operand 1 is an address. 524 HANDLE_OPERAND(relocation); 525 break; 526 case X86Local::AddRegFrm: 527 // Operand 1 is added to the opcode. 528 // Operand 2 (optional) is an address. 529 assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 && 530 "Unexpected number of operands for AddRegFrm"); 531 HANDLE_OPERAND(opcodeModifier) 532 HANDLE_OPTIONAL(relocation) 533 break; 534 case X86Local::AddCCFrm: 535 // Operand 1 (optional) is an address or immediate. 536 assert(numPhysicalOperands == 2 && 537 "Unexpected number of operands for AddCCFrm"); 538 HANDLE_OPERAND(relocation) 539 HANDLE_OPERAND(opcodeModifier) 540 break; 541 case X86Local::MRMDestReg: 542 // Operand 1 is a register operand in the R/M field. 543 // - In AVX512 there may be a mask operand here - 544 // Operand 2 is a register operand in the Reg/Opcode field. 545 // - In AVX, there is a register operand in the VEX.vvvv field here - 546 // Operand 3 (optional) is an immediate. 547 assert(numPhysicalOperands >= 2 + additionalOperands && 548 numPhysicalOperands <= 3 + additionalOperands && 549 "Unexpected number of operands for MRMDestReg"); 550 551 if (IsND) 552 HANDLE_OPERAND(vvvvRegister) 553 554 HANDLE_OPERAND(rmRegister) 555 if (HasEVEX_K) 556 HANDLE_OPERAND(writemaskRegister) 557 558 if (!IsND && HasVEX_4V) 559 // FIXME: In AVX, the register below becomes the one encoded 560 // in ModRMVEX and the one above the one in the VEX.VVVV field 561 HANDLE_OPERAND(vvvvRegister) 562 563 HANDLE_OPERAND(roRegister) 564 HANDLE_OPTIONAL(immediate) 565 break; 566 case X86Local::MRMDestMem4VOp3CC: 567 // Operand 1 is a register operand in the Reg/Opcode field. 568 // Operand 2 is a register operand in the R/M field. 569 // Operand 3 is VEX.vvvv 570 // Operand 4 is condition code. 571 assert(numPhysicalOperands == 4 && 572 "Unexpected number of operands for MRMDestMem4VOp3CC"); 573 HANDLE_OPERAND(roRegister) 574 HANDLE_OPERAND(memory) 575 HANDLE_OPERAND(vvvvRegister) 576 HANDLE_OPERAND(opcodeModifier) 577 break; 578 case X86Local::MRMDestMem: 579 case X86Local::MRMDestMemFSIB: 580 // Operand 1 is a memory operand (possibly SIB-extended) 581 // Operand 2 is a register operand in the Reg/Opcode field. 582 // - In AVX, there is a register operand in the VEX.vvvv field here - 583 // Operand 3 (optional) is an immediate. 584 assert(numPhysicalOperands >= 2 + additionalOperands && 585 numPhysicalOperands <= 3 + additionalOperands && 586 "Unexpected number of operands for MRMDestMemFrm with VEX_4V"); 587 588 if (IsND) 589 HANDLE_OPERAND(vvvvRegister) 590 591 HANDLE_OPERAND(memory) 592 593 if (HasEVEX_K) 594 HANDLE_OPERAND(writemaskRegister) 595 596 if (!IsND && HasVEX_4V) 597 // FIXME: In AVX, the register below becomes the one encoded 598 // in ModRMVEX and the one above the one in the VEX.VVVV field 599 HANDLE_OPERAND(vvvvRegister) 600 601 HANDLE_OPERAND(roRegister) 602 HANDLE_OPTIONAL(immediate) 603 break; 604 case X86Local::MRMSrcReg: 605 // Operand 1 is a register operand in the Reg/Opcode field. 606 // Operand 2 is a register operand in the R/M field. 607 // - In AVX, there is a register operand in the VEX.vvvv field here - 608 // Operand 3 (optional) is an immediate. 609 // Operand 4 (optional) is an immediate. 610 611 assert(numPhysicalOperands >= 2 + additionalOperands && 612 numPhysicalOperands <= 4 + additionalOperands && 613 "Unexpected number of operands for MRMSrcRegFrm"); 614 615 if (IsND) 616 HANDLE_OPERAND(vvvvRegister) 617 618 HANDLE_OPERAND(roRegister) 619 620 if (HasEVEX_K) 621 HANDLE_OPERAND(writemaskRegister) 622 623 if (!IsND && HasVEX_4V) 624 // FIXME: In AVX, the register below becomes the one encoded 625 // in ModRMVEX and the one above the one in the VEX.VVVV field 626 HANDLE_OPERAND(vvvvRegister) 627 628 HANDLE_OPERAND(rmRegister) 629 HANDLE_OPTIONAL(immediate) 630 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4 631 break; 632 case X86Local::MRMSrcReg4VOp3: 633 assert(numPhysicalOperands == 3 && 634 "Unexpected number of operands for MRMSrcReg4VOp3Frm"); 635 HANDLE_OPERAND(roRegister) 636 HANDLE_OPERAND(rmRegister) 637 HANDLE_OPERAND(vvvvRegister) 638 break; 639 case X86Local::MRMSrcRegOp4: 640 assert(numPhysicalOperands >= 4 && numPhysicalOperands <= 5 && 641 "Unexpected number of operands for MRMSrcRegOp4Frm"); 642 HANDLE_OPERAND(roRegister) 643 HANDLE_OPERAND(vvvvRegister) 644 HANDLE_OPERAND(immediate) // Register in imm[7:4] 645 HANDLE_OPERAND(rmRegister) 646 HANDLE_OPTIONAL(immediate) 647 break; 648 case X86Local::MRMSrcRegCC: 649 assert(numPhysicalOperands == 3 && 650 "Unexpected number of operands for MRMSrcRegCC"); 651 HANDLE_OPERAND(roRegister) 652 HANDLE_OPERAND(rmRegister) 653 HANDLE_OPERAND(opcodeModifier) 654 break; 655 case X86Local::MRMSrcMem: 656 case X86Local::MRMSrcMemFSIB: 657 // Operand 1 is a register operand in the Reg/Opcode field. 658 // Operand 2 is a memory operand (possibly SIB-extended) 659 // - In AVX, there is a register operand in the VEX.vvvv field here - 660 // Operand 3 (optional) is an immediate. 661 662 assert(numPhysicalOperands >= 2 + additionalOperands && 663 numPhysicalOperands <= 4 + additionalOperands && 664 "Unexpected number of operands for MRMSrcMemFrm"); 665 if (IsND) 666 HANDLE_OPERAND(vvvvRegister) 667 668 HANDLE_OPERAND(roRegister) 669 670 if (HasEVEX_K) 671 HANDLE_OPERAND(writemaskRegister) 672 673 if (!IsND && HasVEX_4V) 674 // FIXME: In AVX, the register below becomes the one encoded 675 // in ModRMVEX and the one above the one in the VEX.VVVV field 676 HANDLE_OPERAND(vvvvRegister) 677 678 HANDLE_OPERAND(memory) 679 HANDLE_OPTIONAL(immediate) 680 HANDLE_OPTIONAL(immediate) // above might be a register in 7:4 681 break; 682 case X86Local::MRMSrcMem4VOp3: 683 assert(numPhysicalOperands == 3 && 684 "Unexpected number of operands for MRMSrcMem4VOp3Frm"); 685 HANDLE_OPERAND(roRegister) 686 HANDLE_OPERAND(memory) 687 HANDLE_OPERAND(vvvvRegister) 688 break; 689 case X86Local::MRMSrcMemOp4: 690 assert(numPhysicalOperands >= 4 && numPhysicalOperands <= 5 && 691 "Unexpected number of operands for MRMSrcMemOp4Frm"); 692 HANDLE_OPERAND(roRegister) 693 HANDLE_OPERAND(vvvvRegister) 694 HANDLE_OPERAND(immediate) // Register in imm[7:4] 695 HANDLE_OPERAND(memory) 696 HANDLE_OPTIONAL(immediate) 697 break; 698 case X86Local::MRMSrcMemCC: 699 assert(numPhysicalOperands == 3 && 700 "Unexpected number of operands for MRMSrcMemCC"); 701 HANDLE_OPERAND(roRegister) 702 HANDLE_OPERAND(memory) 703 HANDLE_OPERAND(opcodeModifier) 704 break; 705 case X86Local::MRMXrCC: 706 assert(numPhysicalOperands == 2 && 707 "Unexpected number of operands for MRMXrCC"); 708 HANDLE_OPERAND(rmRegister) 709 HANDLE_OPERAND(opcodeModifier) 710 break; 711 case X86Local::MRMr0: 712 // Operand 1 is a register operand in the R/M field. 713 HANDLE_OPERAND(roRegister) 714 break; 715 case X86Local::MRMXr: 716 case X86Local::MRM0r: 717 case X86Local::MRM1r: 718 case X86Local::MRM2r: 719 case X86Local::MRM3r: 720 case X86Local::MRM4r: 721 case X86Local::MRM5r: 722 case X86Local::MRM6r: 723 case X86Local::MRM7r: 724 // Operand 1 is a register operand in the R/M field. 725 // Operand 2 (optional) is an immediate or relocation. 726 // Operand 3 (optional) is an immediate. 727 assert(numPhysicalOperands >= 0 + additionalOperands && 728 numPhysicalOperands <= 3 + additionalOperands && 729 "Unexpected number of operands for MRMnr"); 730 731 if (HasVEX_4V) 732 HANDLE_OPERAND(vvvvRegister) 733 734 if (HasEVEX_K) 735 HANDLE_OPERAND(writemaskRegister) 736 HANDLE_OPTIONAL(rmRegister) 737 HANDLE_OPTIONAL(relocation) 738 HANDLE_OPTIONAL(immediate) 739 break; 740 case X86Local::MRMXmCC: 741 assert(numPhysicalOperands == 2 && 742 "Unexpected number of operands for MRMXm"); 743 HANDLE_OPERAND(memory) 744 HANDLE_OPERAND(opcodeModifier) 745 break; 746 case X86Local::MRMXm: 747 case X86Local::MRM0m: 748 case X86Local::MRM1m: 749 case X86Local::MRM2m: 750 case X86Local::MRM3m: 751 case X86Local::MRM4m: 752 case X86Local::MRM5m: 753 case X86Local::MRM6m: 754 case X86Local::MRM7m: 755 // Operand 1 is a memory operand (possibly SIB-extended) 756 // Operand 2 (optional) is an immediate or relocation. 757 assert(numPhysicalOperands >= 1 + additionalOperands && 758 numPhysicalOperands <= 2 + additionalOperands && 759 "Unexpected number of operands for MRMnm"); 760 761 if (HasVEX_4V) 762 HANDLE_OPERAND(vvvvRegister) 763 if (HasEVEX_K) 764 HANDLE_OPERAND(writemaskRegister) 765 HANDLE_OPERAND(memory) 766 HANDLE_OPTIONAL(relocation) 767 break; 768 case X86Local::RawFrmImm8: 769 // operand 1 is a 16-bit immediate 770 // operand 2 is an 8-bit immediate 771 assert(numPhysicalOperands == 2 && 772 "Unexpected number of operands for X86Local::RawFrmImm8"); 773 HANDLE_OPERAND(immediate) 774 HANDLE_OPERAND(immediate) 775 break; 776 case X86Local::RawFrmImm16: 777 // operand 1 is a 16-bit immediate 778 // operand 2 is a 16-bit immediate 779 HANDLE_OPERAND(immediate) 780 HANDLE_OPERAND(immediate) 781 break; 782 case X86Local::MRM0X: 783 case X86Local::MRM1X: 784 case X86Local::MRM2X: 785 case X86Local::MRM3X: 786 case X86Local::MRM4X: 787 case X86Local::MRM5X: 788 case X86Local::MRM6X: 789 case X86Local::MRM7X: 790 #define MAP(from, to) case X86Local::MRM_##from: 791 X86_INSTR_MRM_MAPPING 792 #undef MAP 793 HANDLE_OPTIONAL(relocation) 794 break; 795 } 796 797 #undef HANDLE_OPERAND 798 #undef HANDLE_OPTIONAL 799 } 800 801 void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const { 802 // Special cases where the LLVM tables are not complete 803 804 #define MAP(from, to) case X86Local::MRM_##from: 805 806 std::optional<OpcodeType> opcodeType; 807 switch (OpMap) { 808 default: 809 llvm_unreachable("Invalid map!"); 810 case X86Local::OB: 811 opcodeType = ONEBYTE; 812 break; 813 case X86Local::TB: 814 opcodeType = TWOBYTE; 815 break; 816 case X86Local::T8: 817 opcodeType = THREEBYTE_38; 818 break; 819 case X86Local::TA: 820 opcodeType = THREEBYTE_3A; 821 break; 822 case X86Local::XOP8: 823 opcodeType = XOP8_MAP; 824 break; 825 case X86Local::XOP9: 826 opcodeType = XOP9_MAP; 827 break; 828 case X86Local::XOPA: 829 opcodeType = XOPA_MAP; 830 break; 831 case X86Local::ThreeDNow: 832 opcodeType = THREEDNOW_MAP; 833 break; 834 case X86Local::T_MAP4: 835 opcodeType = MAP4; 836 break; 837 case X86Local::T_MAP5: 838 opcodeType = MAP5; 839 break; 840 case X86Local::T_MAP6: 841 opcodeType = MAP6; 842 break; 843 case X86Local::T_MAP7: 844 opcodeType = MAP7; 845 break; 846 } 847 848 std::unique_ptr<ModRMFilter> filter; 849 switch (Form) { 850 default: 851 llvm_unreachable("Invalid form!"); 852 case X86Local::Pseudo: 853 llvm_unreachable("Pseudo should not be emitted!"); 854 case X86Local::RawFrm: 855 case X86Local::AddRegFrm: 856 case X86Local::RawFrmMemOffs: 857 case X86Local::RawFrmSrc: 858 case X86Local::RawFrmDst: 859 case X86Local::RawFrmDstSrc: 860 case X86Local::RawFrmImm8: 861 case X86Local::RawFrmImm16: 862 case X86Local::AddCCFrm: 863 case X86Local::PrefixByte: 864 filter = std::make_unique<DumbFilter>(); 865 break; 866 case X86Local::MRMDestReg: 867 case X86Local::MRMSrcReg: 868 case X86Local::MRMSrcReg4VOp3: 869 case X86Local::MRMSrcRegOp4: 870 case X86Local::MRMSrcRegCC: 871 case X86Local::MRMXrCC: 872 case X86Local::MRMXr: 873 filter = std::make_unique<ModFilter>(true); 874 break; 875 case X86Local::MRMDestMem: 876 case X86Local::MRMDestMem4VOp3CC: 877 case X86Local::MRMDestMemFSIB: 878 case X86Local::MRMSrcMem: 879 case X86Local::MRMSrcMemFSIB: 880 case X86Local::MRMSrcMem4VOp3: 881 case X86Local::MRMSrcMemOp4: 882 case X86Local::MRMSrcMemCC: 883 case X86Local::MRMXmCC: 884 case X86Local::MRMXm: 885 filter = std::make_unique<ModFilter>(false); 886 break; 887 case X86Local::MRM0r: 888 case X86Local::MRM1r: 889 case X86Local::MRM2r: 890 case X86Local::MRM3r: 891 case X86Local::MRM4r: 892 case X86Local::MRM5r: 893 case X86Local::MRM6r: 894 case X86Local::MRM7r: 895 filter = std::make_unique<ExtendedFilter>(true, Form - X86Local::MRM0r); 896 break; 897 case X86Local::MRM0X: 898 case X86Local::MRM1X: 899 case X86Local::MRM2X: 900 case X86Local::MRM3X: 901 case X86Local::MRM4X: 902 case X86Local::MRM5X: 903 case X86Local::MRM6X: 904 case X86Local::MRM7X: 905 filter = std::make_unique<ExtendedFilter>(true, Form - X86Local::MRM0X); 906 break; 907 case X86Local::MRMr0: 908 filter = std::make_unique<ExtendedRMFilter>(true, Form - X86Local::MRMr0); 909 break; 910 case X86Local::MRM0m: 911 case X86Local::MRM1m: 912 case X86Local::MRM2m: 913 case X86Local::MRM3m: 914 case X86Local::MRM4m: 915 case X86Local::MRM5m: 916 case X86Local::MRM6m: 917 case X86Local::MRM7m: 918 filter = std::make_unique<ExtendedFilter>(false, Form - X86Local::MRM0m); 919 break; 920 X86_INSTR_MRM_MAPPING 921 filter = std::make_unique<ExactFilter>(0xC0 + Form - X86Local::MRM_C0); 922 break; 923 } // switch (Form) 924 925 uint8_t opcodeToSet = Opcode; 926 927 unsigned AddressSize = 0; 928 switch (AdSize) { 929 case X86Local::AdSize16: 930 AddressSize = 16; 931 break; 932 case X86Local::AdSize32: 933 AddressSize = 32; 934 break; 935 case X86Local::AdSize64: 936 AddressSize = 64; 937 break; 938 } 939 940 assert(opcodeType && "Opcode type not set"); 941 assert(filter && "Filter not set"); 942 943 if (Form == X86Local::AddRegFrm || Form == X86Local::MRMSrcRegCC || 944 Form == X86Local::MRMSrcMemCC || Form == X86Local::MRMXrCC || 945 Form == X86Local::MRMXmCC || Form == X86Local::AddCCFrm || 946 Form == X86Local::MRMDestMem4VOp3CC) { 947 uint8_t Count = Form == X86Local::AddRegFrm ? 8 : 16; 948 assert(((opcodeToSet % Count) == 0) && "ADDREG_FRM opcode not aligned"); 949 950 uint8_t currentOpcode; 951 952 for (currentOpcode = opcodeToSet; 953 currentOpcode < (uint8_t)(opcodeToSet + Count); ++currentOpcode) 954 tables.setTableFields(*opcodeType, insnContext(), currentOpcode, *filter, 955 UID, Is32Bit, OpPrefix == 0, 956 IgnoresVEX_L || EncodeRC, IgnoresW, AddressSize); 957 } else { 958 tables.setTableFields(*opcodeType, insnContext(), opcodeToSet, *filter, UID, 959 Is32Bit, OpPrefix == 0, IgnoresVEX_L || EncodeRC, 960 IgnoresW, AddressSize); 961 } 962 963 #undef MAP 964 } 965 966 #define TYPE(str, type) \ 967 if (s == str) \ 968 return type; 969 OperandType RecognizableInstr::typeFromString(const std::string &s, 970 bool hasREX_W, uint8_t OpSize) { 971 if (hasREX_W) { 972 // For instructions with a REX_W prefix, a declared 32-bit register encoding 973 // is special. 974 TYPE("GR32", TYPE_R32) 975 } 976 if (OpSize == X86Local::OpSize16) { 977 // For OpSize16 instructions, a declared 16-bit register or 978 // immediate encoding is special. 979 TYPE("GR16", TYPE_Rv) 980 } else if (OpSize == X86Local::OpSize32) { 981 // For OpSize32 instructions, a declared 32-bit register or 982 // immediate encoding is special. 983 TYPE("GR32", TYPE_Rv) 984 } 985 TYPE("i16mem", TYPE_M) 986 TYPE("i16imm", TYPE_IMM) 987 TYPE("i16i8imm", TYPE_IMM) 988 TYPE("GR16", TYPE_R16) 989 TYPE("GR16orGR32orGR64", TYPE_R16) 990 TYPE("i32mem", TYPE_M) 991 TYPE("i32imm", TYPE_IMM) 992 TYPE("i32i8imm", TYPE_IMM) 993 TYPE("GR32", TYPE_R32) 994 TYPE("GR32orGR64", TYPE_R32) 995 TYPE("i64mem", TYPE_M) 996 TYPE("i64i32imm", TYPE_IMM) 997 TYPE("i64i8imm", TYPE_IMM) 998 TYPE("GR64", TYPE_R64) 999 TYPE("i8mem", TYPE_M) 1000 TYPE("i8imm", TYPE_IMM) 1001 TYPE("u4imm", TYPE_UIMM8) 1002 TYPE("u8imm", TYPE_UIMM8) 1003 TYPE("i16u8imm", TYPE_UIMM8) 1004 TYPE("i32u8imm", TYPE_UIMM8) 1005 TYPE("i64u8imm", TYPE_UIMM8) 1006 TYPE("GR8", TYPE_R8) 1007 TYPE("VR128", TYPE_XMM) 1008 TYPE("VR128X", TYPE_XMM) 1009 TYPE("f128mem", TYPE_M) 1010 TYPE("f256mem", TYPE_M) 1011 TYPE("f512mem", TYPE_M) 1012 TYPE("FR128", TYPE_XMM) 1013 TYPE("FR64", TYPE_XMM) 1014 TYPE("FR64X", TYPE_XMM) 1015 TYPE("f64mem", TYPE_M) 1016 TYPE("sdmem", TYPE_M) 1017 TYPE("FR16X", TYPE_XMM) 1018 TYPE("FR32", TYPE_XMM) 1019 TYPE("FR32X", TYPE_XMM) 1020 TYPE("f32mem", TYPE_M) 1021 TYPE("f16mem", TYPE_M) 1022 TYPE("ssmem", TYPE_M) 1023 TYPE("shmem", TYPE_M) 1024 TYPE("RST", TYPE_ST) 1025 TYPE("RSTi", TYPE_ST) 1026 TYPE("i128mem", TYPE_M) 1027 TYPE("i256mem", TYPE_M) 1028 TYPE("i512mem", TYPE_M) 1029 TYPE("i512mem_GR16", TYPE_M) 1030 TYPE("i512mem_GR32", TYPE_M) 1031 TYPE("i512mem_GR64", TYPE_M) 1032 TYPE("i64i32imm_brtarget", TYPE_REL) 1033 TYPE("i16imm_brtarget", TYPE_REL) 1034 TYPE("i32imm_brtarget", TYPE_REL) 1035 TYPE("ccode", TYPE_IMM) 1036 TYPE("AVX512RC", TYPE_IMM) 1037 TYPE("brtarget32", TYPE_REL) 1038 TYPE("brtarget16", TYPE_REL) 1039 TYPE("brtarget8", TYPE_REL) 1040 TYPE("f80mem", TYPE_M) 1041 TYPE("lea64_32mem", TYPE_M) 1042 TYPE("lea64mem", TYPE_M) 1043 TYPE("VR64", TYPE_MM64) 1044 TYPE("i64imm", TYPE_IMM) 1045 TYPE("anymem", TYPE_M) 1046 TYPE("opaquemem", TYPE_M) 1047 TYPE("sibmem", TYPE_MSIB) 1048 TYPE("SEGMENT_REG", TYPE_SEGMENTREG) 1049 TYPE("DEBUG_REG", TYPE_DEBUGREG) 1050 TYPE("CONTROL_REG", TYPE_CONTROLREG) 1051 TYPE("srcidx8", TYPE_SRCIDX) 1052 TYPE("srcidx16", TYPE_SRCIDX) 1053 TYPE("srcidx32", TYPE_SRCIDX) 1054 TYPE("srcidx64", TYPE_SRCIDX) 1055 TYPE("dstidx8", TYPE_DSTIDX) 1056 TYPE("dstidx16", TYPE_DSTIDX) 1057 TYPE("dstidx32", TYPE_DSTIDX) 1058 TYPE("dstidx64", TYPE_DSTIDX) 1059 TYPE("offset16_8", TYPE_MOFFS) 1060 TYPE("offset16_16", TYPE_MOFFS) 1061 TYPE("offset16_32", TYPE_MOFFS) 1062 TYPE("offset32_8", TYPE_MOFFS) 1063 TYPE("offset32_16", TYPE_MOFFS) 1064 TYPE("offset32_32", TYPE_MOFFS) 1065 TYPE("offset32_64", TYPE_MOFFS) 1066 TYPE("offset64_8", TYPE_MOFFS) 1067 TYPE("offset64_16", TYPE_MOFFS) 1068 TYPE("offset64_32", TYPE_MOFFS) 1069 TYPE("offset64_64", TYPE_MOFFS) 1070 TYPE("VR256", TYPE_YMM) 1071 TYPE("VR256X", TYPE_YMM) 1072 TYPE("VR512", TYPE_ZMM) 1073 TYPE("VK1", TYPE_VK) 1074 TYPE("VK1WM", TYPE_VK) 1075 TYPE("VK2", TYPE_VK) 1076 TYPE("VK2WM", TYPE_VK) 1077 TYPE("VK4", TYPE_VK) 1078 TYPE("VK4WM", TYPE_VK) 1079 TYPE("VK8", TYPE_VK) 1080 TYPE("VK8WM", TYPE_VK) 1081 TYPE("VK16", TYPE_VK) 1082 TYPE("VK16WM", TYPE_VK) 1083 TYPE("VK32", TYPE_VK) 1084 TYPE("VK32WM", TYPE_VK) 1085 TYPE("VK64", TYPE_VK) 1086 TYPE("VK64WM", TYPE_VK) 1087 TYPE("VK1Pair", TYPE_VK_PAIR) 1088 TYPE("VK2Pair", TYPE_VK_PAIR) 1089 TYPE("VK4Pair", TYPE_VK_PAIR) 1090 TYPE("VK8Pair", TYPE_VK_PAIR) 1091 TYPE("VK16Pair", TYPE_VK_PAIR) 1092 TYPE("vx64mem", TYPE_MVSIBX) 1093 TYPE("vx128mem", TYPE_MVSIBX) 1094 TYPE("vx256mem", TYPE_MVSIBX) 1095 TYPE("vy128mem", TYPE_MVSIBY) 1096 TYPE("vy256mem", TYPE_MVSIBY) 1097 TYPE("vx64xmem", TYPE_MVSIBX) 1098 TYPE("vx128xmem", TYPE_MVSIBX) 1099 TYPE("vx256xmem", TYPE_MVSIBX) 1100 TYPE("vy128xmem", TYPE_MVSIBY) 1101 TYPE("vy256xmem", TYPE_MVSIBY) 1102 TYPE("vy512xmem", TYPE_MVSIBY) 1103 TYPE("vz256mem", TYPE_MVSIBZ) 1104 TYPE("vz512mem", TYPE_MVSIBZ) 1105 TYPE("BNDR", TYPE_BNDR) 1106 TYPE("TILE", TYPE_TMM) 1107 errs() << "Unhandled type string " << s << "\n"; 1108 llvm_unreachable("Unhandled type string"); 1109 } 1110 #undef TYPE 1111 1112 #define ENCODING(str, encoding) \ 1113 if (s == str) \ 1114 return encoding; 1115 OperandEncoding 1116 RecognizableInstr::immediateEncodingFromString(const std::string &s, 1117 uint8_t OpSize) { 1118 if (OpSize != X86Local::OpSize16) { 1119 // For instructions without an OpSize prefix, a declared 16-bit register or 1120 // immediate encoding is special. 1121 ENCODING("i16imm", ENCODING_IW) 1122 } 1123 ENCODING("i32i8imm", ENCODING_IB) 1124 ENCODING("AVX512RC", ENCODING_IRC) 1125 ENCODING("i16imm", ENCODING_Iv) 1126 ENCODING("i16i8imm", ENCODING_IB) 1127 ENCODING("i32imm", ENCODING_Iv) 1128 ENCODING("i64i32imm", ENCODING_ID) 1129 ENCODING("i64i8imm", ENCODING_IB) 1130 ENCODING("i8imm", ENCODING_IB) 1131 ENCODING("u4imm", ENCODING_IB) 1132 ENCODING("u8imm", ENCODING_IB) 1133 ENCODING("i16u8imm", ENCODING_IB) 1134 ENCODING("i32u8imm", ENCODING_IB) 1135 ENCODING("i64u8imm", ENCODING_IB) 1136 // This is not a typo. Instructions like BLENDVPD put 1137 // register IDs in 8-bit immediates nowadays. 1138 ENCODING("FR32", ENCODING_IB) 1139 ENCODING("FR64", ENCODING_IB) 1140 ENCODING("FR128", ENCODING_IB) 1141 ENCODING("VR128", ENCODING_IB) 1142 ENCODING("VR256", ENCODING_IB) 1143 ENCODING("FR16X", ENCODING_IB) 1144 ENCODING("FR32X", ENCODING_IB) 1145 ENCODING("FR64X", ENCODING_IB) 1146 ENCODING("VR128X", ENCODING_IB) 1147 ENCODING("VR256X", ENCODING_IB) 1148 ENCODING("VR512", ENCODING_IB) 1149 ENCODING("TILE", ENCODING_IB) 1150 errs() << "Unhandled immediate encoding " << s << "\n"; 1151 llvm_unreachable("Unhandled immediate encoding"); 1152 } 1153 1154 OperandEncoding 1155 RecognizableInstr::rmRegisterEncodingFromString(const std::string &s, 1156 uint8_t OpSize) { 1157 ENCODING("RST", ENCODING_FP) 1158 ENCODING("RSTi", ENCODING_FP) 1159 ENCODING("GR16", ENCODING_RM) 1160 ENCODING("GR16orGR32orGR64", ENCODING_RM) 1161 ENCODING("GR32", ENCODING_RM) 1162 ENCODING("GR32orGR64", ENCODING_RM) 1163 ENCODING("GR64", ENCODING_RM) 1164 ENCODING("GR8", ENCODING_RM) 1165 ENCODING("VR128", ENCODING_RM) 1166 ENCODING("VR128X", ENCODING_RM) 1167 ENCODING("FR128", ENCODING_RM) 1168 ENCODING("FR64", ENCODING_RM) 1169 ENCODING("FR32", ENCODING_RM) 1170 ENCODING("FR64X", ENCODING_RM) 1171 ENCODING("FR32X", ENCODING_RM) 1172 ENCODING("FR16X", ENCODING_RM) 1173 ENCODING("VR64", ENCODING_RM) 1174 ENCODING("VR256", ENCODING_RM) 1175 ENCODING("VR256X", ENCODING_RM) 1176 ENCODING("VR512", ENCODING_RM) 1177 ENCODING("VK1", ENCODING_RM) 1178 ENCODING("VK2", ENCODING_RM) 1179 ENCODING("VK4", ENCODING_RM) 1180 ENCODING("VK8", ENCODING_RM) 1181 ENCODING("VK16", ENCODING_RM) 1182 ENCODING("VK32", ENCODING_RM) 1183 ENCODING("VK64", ENCODING_RM) 1184 ENCODING("BNDR", ENCODING_RM) 1185 ENCODING("TILE", ENCODING_RM) 1186 errs() << "Unhandled R/M register encoding " << s << "\n"; 1187 llvm_unreachable("Unhandled R/M register encoding"); 1188 } 1189 1190 OperandEncoding 1191 RecognizableInstr::roRegisterEncodingFromString(const std::string &s, 1192 uint8_t OpSize) { 1193 ENCODING("GR16", ENCODING_REG) 1194 ENCODING("GR16orGR32orGR64", ENCODING_REG) 1195 ENCODING("GR32", ENCODING_REG) 1196 ENCODING("GR32orGR64", ENCODING_REG) 1197 ENCODING("GR64", ENCODING_REG) 1198 ENCODING("GR8", ENCODING_REG) 1199 ENCODING("VR128", ENCODING_REG) 1200 ENCODING("FR128", ENCODING_REG) 1201 ENCODING("FR64", ENCODING_REG) 1202 ENCODING("FR32", ENCODING_REG) 1203 ENCODING("VR64", ENCODING_REG) 1204 ENCODING("SEGMENT_REG", ENCODING_REG) 1205 ENCODING("DEBUG_REG", ENCODING_REG) 1206 ENCODING("CONTROL_REG", ENCODING_REG) 1207 ENCODING("VR256", ENCODING_REG) 1208 ENCODING("VR256X", ENCODING_REG) 1209 ENCODING("VR128X", ENCODING_REG) 1210 ENCODING("FR64X", ENCODING_REG) 1211 ENCODING("FR32X", ENCODING_REG) 1212 ENCODING("FR16X", ENCODING_REG) 1213 ENCODING("VR512", ENCODING_REG) 1214 ENCODING("VK1", ENCODING_REG) 1215 ENCODING("VK2", ENCODING_REG) 1216 ENCODING("VK4", ENCODING_REG) 1217 ENCODING("VK8", ENCODING_REG) 1218 ENCODING("VK16", ENCODING_REG) 1219 ENCODING("VK32", ENCODING_REG) 1220 ENCODING("VK64", ENCODING_REG) 1221 ENCODING("VK1Pair", ENCODING_REG) 1222 ENCODING("VK2Pair", ENCODING_REG) 1223 ENCODING("VK4Pair", ENCODING_REG) 1224 ENCODING("VK8Pair", ENCODING_REG) 1225 ENCODING("VK16Pair", ENCODING_REG) 1226 ENCODING("VK1WM", ENCODING_REG) 1227 ENCODING("VK2WM", ENCODING_REG) 1228 ENCODING("VK4WM", ENCODING_REG) 1229 ENCODING("VK8WM", ENCODING_REG) 1230 ENCODING("VK16WM", ENCODING_REG) 1231 ENCODING("VK32WM", ENCODING_REG) 1232 ENCODING("VK64WM", ENCODING_REG) 1233 ENCODING("BNDR", ENCODING_REG) 1234 ENCODING("TILE", ENCODING_REG) 1235 errs() << "Unhandled reg/opcode register encoding " << s << "\n"; 1236 llvm_unreachable("Unhandled reg/opcode register encoding"); 1237 } 1238 1239 OperandEncoding 1240 RecognizableInstr::vvvvRegisterEncodingFromString(const std::string &s, 1241 uint8_t OpSize) { 1242 ENCODING("GR8", ENCODING_VVVV) 1243 ENCODING("GR16", ENCODING_VVVV) 1244 ENCODING("GR32", ENCODING_VVVV) 1245 ENCODING("GR64", ENCODING_VVVV) 1246 ENCODING("FR32", ENCODING_VVVV) 1247 ENCODING("FR128", ENCODING_VVVV) 1248 ENCODING("FR64", ENCODING_VVVV) 1249 ENCODING("VR128", ENCODING_VVVV) 1250 ENCODING("VR256", ENCODING_VVVV) 1251 ENCODING("FR16X", ENCODING_VVVV) 1252 ENCODING("FR32X", ENCODING_VVVV) 1253 ENCODING("FR64X", ENCODING_VVVV) 1254 ENCODING("VR128X", ENCODING_VVVV) 1255 ENCODING("VR256X", ENCODING_VVVV) 1256 ENCODING("VR512", ENCODING_VVVV) 1257 ENCODING("VK1", ENCODING_VVVV) 1258 ENCODING("VK2", ENCODING_VVVV) 1259 ENCODING("VK4", ENCODING_VVVV) 1260 ENCODING("VK8", ENCODING_VVVV) 1261 ENCODING("VK16", ENCODING_VVVV) 1262 ENCODING("VK32", ENCODING_VVVV) 1263 ENCODING("VK64", ENCODING_VVVV) 1264 ENCODING("TILE", ENCODING_VVVV) 1265 errs() << "Unhandled VEX.vvvv register encoding " << s << "\n"; 1266 llvm_unreachable("Unhandled VEX.vvvv register encoding"); 1267 } 1268 1269 OperandEncoding 1270 RecognizableInstr::writemaskRegisterEncodingFromString(const std::string &s, 1271 uint8_t OpSize) { 1272 ENCODING("VK1WM", ENCODING_WRITEMASK) 1273 ENCODING("VK2WM", ENCODING_WRITEMASK) 1274 ENCODING("VK4WM", ENCODING_WRITEMASK) 1275 ENCODING("VK8WM", ENCODING_WRITEMASK) 1276 ENCODING("VK16WM", ENCODING_WRITEMASK) 1277 ENCODING("VK32WM", ENCODING_WRITEMASK) 1278 ENCODING("VK64WM", ENCODING_WRITEMASK) 1279 errs() << "Unhandled mask register encoding " << s << "\n"; 1280 llvm_unreachable("Unhandled mask register encoding"); 1281 } 1282 1283 OperandEncoding 1284 RecognizableInstr::memoryEncodingFromString(const std::string &s, 1285 uint8_t OpSize) { 1286 ENCODING("i16mem", ENCODING_RM) 1287 ENCODING("i32mem", ENCODING_RM) 1288 ENCODING("i64mem", ENCODING_RM) 1289 ENCODING("i8mem", ENCODING_RM) 1290 ENCODING("shmem", ENCODING_RM) 1291 ENCODING("ssmem", ENCODING_RM) 1292 ENCODING("sdmem", ENCODING_RM) 1293 ENCODING("f128mem", ENCODING_RM) 1294 ENCODING("f256mem", ENCODING_RM) 1295 ENCODING("f512mem", ENCODING_RM) 1296 ENCODING("f64mem", ENCODING_RM) 1297 ENCODING("f32mem", ENCODING_RM) 1298 ENCODING("f16mem", ENCODING_RM) 1299 ENCODING("i128mem", ENCODING_RM) 1300 ENCODING("i256mem", ENCODING_RM) 1301 ENCODING("i512mem", ENCODING_RM) 1302 ENCODING("i512mem_GR16", ENCODING_RM) 1303 ENCODING("i512mem_GR32", ENCODING_RM) 1304 ENCODING("i512mem_GR64", ENCODING_RM) 1305 ENCODING("f80mem", ENCODING_RM) 1306 ENCODING("lea64_32mem", ENCODING_RM) 1307 ENCODING("lea64mem", ENCODING_RM) 1308 ENCODING("anymem", ENCODING_RM) 1309 ENCODING("opaquemem", ENCODING_RM) 1310 ENCODING("sibmem", ENCODING_SIB) 1311 ENCODING("vx64mem", ENCODING_VSIB) 1312 ENCODING("vx128mem", ENCODING_VSIB) 1313 ENCODING("vx256mem", ENCODING_VSIB) 1314 ENCODING("vy128mem", ENCODING_VSIB) 1315 ENCODING("vy256mem", ENCODING_VSIB) 1316 ENCODING("vx64xmem", ENCODING_VSIB) 1317 ENCODING("vx128xmem", ENCODING_VSIB) 1318 ENCODING("vx256xmem", ENCODING_VSIB) 1319 ENCODING("vy128xmem", ENCODING_VSIB) 1320 ENCODING("vy256xmem", ENCODING_VSIB) 1321 ENCODING("vy512xmem", ENCODING_VSIB) 1322 ENCODING("vz256mem", ENCODING_VSIB) 1323 ENCODING("vz512mem", ENCODING_VSIB) 1324 errs() << "Unhandled memory encoding " << s << "\n"; 1325 llvm_unreachable("Unhandled memory encoding"); 1326 } 1327 1328 OperandEncoding 1329 RecognizableInstr::relocationEncodingFromString(const std::string &s, 1330 uint8_t OpSize) { 1331 if (OpSize != X86Local::OpSize16) { 1332 // For instructions without an OpSize prefix, a declared 16-bit register or 1333 // immediate encoding is special. 1334 ENCODING("i16imm", ENCODING_IW) 1335 } 1336 ENCODING("i16imm", ENCODING_Iv) 1337 ENCODING("i16i8imm", ENCODING_IB) 1338 ENCODING("i32imm", ENCODING_Iv) 1339 ENCODING("i32i8imm", ENCODING_IB) 1340 ENCODING("i64i32imm", ENCODING_ID) 1341 ENCODING("i64i8imm", ENCODING_IB) 1342 ENCODING("i8imm", ENCODING_IB) 1343 ENCODING("u8imm", ENCODING_IB) 1344 ENCODING("i16u8imm", ENCODING_IB) 1345 ENCODING("i32u8imm", ENCODING_IB) 1346 ENCODING("i64u8imm", ENCODING_IB) 1347 ENCODING("i64i32imm_brtarget", ENCODING_ID) 1348 ENCODING("i16imm_brtarget", ENCODING_IW) 1349 ENCODING("i32imm_brtarget", ENCODING_ID) 1350 ENCODING("brtarget32", ENCODING_ID) 1351 ENCODING("brtarget16", ENCODING_IW) 1352 ENCODING("brtarget8", ENCODING_IB) 1353 ENCODING("i64imm", ENCODING_IO) 1354 ENCODING("offset16_8", ENCODING_Ia) 1355 ENCODING("offset16_16", ENCODING_Ia) 1356 ENCODING("offset16_32", ENCODING_Ia) 1357 ENCODING("offset32_8", ENCODING_Ia) 1358 ENCODING("offset32_16", ENCODING_Ia) 1359 ENCODING("offset32_32", ENCODING_Ia) 1360 ENCODING("offset32_64", ENCODING_Ia) 1361 ENCODING("offset64_8", ENCODING_Ia) 1362 ENCODING("offset64_16", ENCODING_Ia) 1363 ENCODING("offset64_32", ENCODING_Ia) 1364 ENCODING("offset64_64", ENCODING_Ia) 1365 ENCODING("srcidx8", ENCODING_SI) 1366 ENCODING("srcidx16", ENCODING_SI) 1367 ENCODING("srcidx32", ENCODING_SI) 1368 ENCODING("srcidx64", ENCODING_SI) 1369 ENCODING("dstidx8", ENCODING_DI) 1370 ENCODING("dstidx16", ENCODING_DI) 1371 ENCODING("dstidx32", ENCODING_DI) 1372 ENCODING("dstidx64", ENCODING_DI) 1373 errs() << "Unhandled relocation encoding " << s << "\n"; 1374 llvm_unreachable("Unhandled relocation encoding"); 1375 } 1376 1377 OperandEncoding 1378 RecognizableInstr::opcodeModifierEncodingFromString(const std::string &s, 1379 uint8_t OpSize) { 1380 ENCODING("GR32", ENCODING_Rv) 1381 ENCODING("GR64", ENCODING_RO) 1382 ENCODING("GR16", ENCODING_Rv) 1383 ENCODING("GR8", ENCODING_RB) 1384 ENCODING("ccode", ENCODING_CC) 1385 errs() << "Unhandled opcode modifier encoding " << s << "\n"; 1386 llvm_unreachable("Unhandled opcode modifier encoding"); 1387 } 1388 #undef ENCODING 1389