1*0b57cec5SDimitry Andric //===- X86DisassemblerShared.h - Emitter shared header ----------*- C++ -*-===// 2*0b57cec5SDimitry Andric // 3*0b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4*0b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 5*0b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6*0b57cec5SDimitry Andric // 7*0b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 8*0b57cec5SDimitry Andric 9*0b57cec5SDimitry Andric #ifndef LLVM_UTILS_TABLEGEN_X86DISASSEMBLERSHARED_H 10*0b57cec5SDimitry Andric #define LLVM_UTILS_TABLEGEN_X86DISASSEMBLERSHARED_H 11*0b57cec5SDimitry Andric 12*0b57cec5SDimitry Andric #include <cstring> 13*0b57cec5SDimitry Andric #include <string> 14*0b57cec5SDimitry Andric 15*0b57cec5SDimitry Andric #include "llvm/Support/X86DisassemblerDecoderCommon.h" 16*0b57cec5SDimitry Andric 17*0b57cec5SDimitry Andric struct InstructionSpecifier { 18*0b57cec5SDimitry Andric llvm::X86Disassembler::OperandSpecifier 19*0b57cec5SDimitry Andric operands[llvm::X86Disassembler::X86_MAX_OPERANDS]; 20*0b57cec5SDimitry Andric llvm::X86Disassembler::InstructionContext insnContext; 21*0b57cec5SDimitry Andric std::string name; 22*0b57cec5SDimitry Andric 23*0b57cec5SDimitry Andric InstructionSpecifier() { 24*0b57cec5SDimitry Andric insnContext = llvm::X86Disassembler::IC; 25*0b57cec5SDimitry Andric name = ""; 26*0b57cec5SDimitry Andric memset(operands, 0, sizeof(operands)); 27*0b57cec5SDimitry Andric } 28*0b57cec5SDimitry Andric }; 29*0b57cec5SDimitry Andric 30*0b57cec5SDimitry Andric /// Specifies whether a ModR/M byte is needed and (if so) which 31*0b57cec5SDimitry Andric /// instruction each possible value of the ModR/M byte corresponds to. Once 32*0b57cec5SDimitry Andric /// this information is known, we have narrowed down to a single instruction. 33*0b57cec5SDimitry Andric struct ModRMDecision { 34*0b57cec5SDimitry Andric uint8_t modrm_type; 35*0b57cec5SDimitry Andric llvm::X86Disassembler::InstrUID instructionIDs[256]; 36*0b57cec5SDimitry Andric }; 37*0b57cec5SDimitry Andric 38*0b57cec5SDimitry Andric /// Specifies which set of ModR/M->instruction tables to look at 39*0b57cec5SDimitry Andric /// given a particular opcode. 40*0b57cec5SDimitry Andric struct OpcodeDecision { 41*0b57cec5SDimitry Andric ModRMDecision modRMDecisions[256]; 42*0b57cec5SDimitry Andric }; 43*0b57cec5SDimitry Andric 44*0b57cec5SDimitry Andric /// Specifies which opcode->instruction tables to look at given 45*0b57cec5SDimitry Andric /// a particular context (set of attributes). Since there are many possible 46*0b57cec5SDimitry Andric /// contexts, the decoder first uses CONTEXTS_SYM to determine which context 47*0b57cec5SDimitry Andric /// applies given a specific set of attributes. Hence there are only IC_max 48*0b57cec5SDimitry Andric /// entries in this table, rather than 2^(ATTR_max). 49*0b57cec5SDimitry Andric struct ContextDecision { 50*0b57cec5SDimitry Andric OpcodeDecision opcodeDecisions[llvm::X86Disassembler::IC_max]; 51*0b57cec5SDimitry Andric 52*0b57cec5SDimitry Andric ContextDecision() { 53*0b57cec5SDimitry Andric memset(opcodeDecisions, 0, sizeof(opcodeDecisions)); 54*0b57cec5SDimitry Andric } 55*0b57cec5SDimitry Andric }; 56*0b57cec5SDimitry Andric 57*0b57cec5SDimitry Andric #endif 58