1 //===- TableGen.cpp - Top-Level TableGen implementation for LLVM ----------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains the main function for LLVM's TableGen. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "TableGenBackends.h" // Declares all backends. 14 #include "llvm/Support/CommandLine.h" 15 #include "llvm/Support/InitLLVM.h" 16 #include "llvm/TableGen/Main.h" 17 #include "llvm/TableGen/Record.h" 18 #include "llvm/TableGen/SetTheory.h" 19 20 using namespace llvm; 21 22 enum ActionType { 23 PrintRecords, 24 PrintDetailedRecords, 25 NullBackend, 26 DumpJSON, 27 GenEmitter, 28 GenRegisterInfo, 29 GenInstrInfo, 30 GenInstrDocs, 31 GenAsmWriter, 32 GenAsmMatcher, 33 GenDisassembler, 34 GenPseudoLowering, 35 GenCompressInst, 36 GenCallingConv, 37 GenDAGISel, 38 GenDFAPacketizer, 39 GenFastISel, 40 GenSubtarget, 41 GenIntrinsicEnums, 42 GenIntrinsicImpl, 43 PrintEnums, 44 PrintSets, 45 GenOptParserDefs, 46 GenOptRST, 47 GenCTags, 48 GenAttributes, 49 GenSearchableTables, 50 GenGlobalISel, 51 GenGICombiner, 52 GenX86EVEX2VEXTables, 53 GenX86FoldTables, 54 GenX86MnemonicTables, 55 GenRegisterBank, 56 GenExegesis, 57 GenAutomata, 58 GenDirectivesEnumDecl, 59 GenDirectivesEnumImpl, 60 GenDXILOperation, 61 GenRISCVTargetDef, 62 }; 63 64 namespace llvm { 65 cl::opt<bool> EmitLongStrLiterals( 66 "long-string-literals", 67 cl::desc("when emitting large string tables, prefer string literals over " 68 "comma-separated char literals. This can be a readability and " 69 "compile-time performance win, but upsets some compilers"), 70 cl::Hidden, cl::init(true)); 71 } // end namespace llvm 72 73 namespace { 74 cl::opt<ActionType> Action( 75 cl::desc("Action to perform:"), 76 cl::values( 77 clEnumValN(PrintRecords, "print-records", 78 "Print all records to stdout (default)"), 79 clEnumValN(PrintDetailedRecords, "print-detailed-records", 80 "Print full details of all records to stdout"), 81 clEnumValN(NullBackend, "null-backend", 82 "Do nothing after parsing (useful for timing)"), 83 clEnumValN(DumpJSON, "dump-json", 84 "Dump all records as machine-readable JSON"), 85 clEnumValN(GenEmitter, "gen-emitter", "Generate machine code emitter"), 86 clEnumValN(GenRegisterInfo, "gen-register-info", 87 "Generate registers and register classes info"), 88 clEnumValN(GenInstrInfo, "gen-instr-info", 89 "Generate instruction descriptions"), 90 clEnumValN(GenInstrDocs, "gen-instr-docs", 91 "Generate instruction documentation"), 92 clEnumValN(GenCallingConv, "gen-callingconv", 93 "Generate calling convention descriptions"), 94 clEnumValN(GenAsmWriter, "gen-asm-writer", "Generate assembly writer"), 95 clEnumValN(GenDisassembler, "gen-disassembler", 96 "Generate disassembler"), 97 clEnumValN(GenPseudoLowering, "gen-pseudo-lowering", 98 "Generate pseudo instruction lowering"), 99 clEnumValN(GenCompressInst, "gen-compress-inst-emitter", 100 "Generate RISCV compressed instructions."), 101 clEnumValN(GenAsmMatcher, "gen-asm-matcher", 102 "Generate assembly instruction matcher"), 103 clEnumValN(GenDAGISel, "gen-dag-isel", 104 "Generate a DAG instruction selector"), 105 clEnumValN(GenDFAPacketizer, "gen-dfa-packetizer", 106 "Generate DFA Packetizer for VLIW targets"), 107 clEnumValN(GenFastISel, "gen-fast-isel", 108 "Generate a \"fast\" instruction selector"), 109 clEnumValN(GenSubtarget, "gen-subtarget", 110 "Generate subtarget enumerations"), 111 clEnumValN(GenIntrinsicEnums, "gen-intrinsic-enums", 112 "Generate intrinsic enums"), 113 clEnumValN(GenIntrinsicImpl, "gen-intrinsic-impl", 114 "Generate intrinsic information"), 115 clEnumValN(PrintEnums, "print-enums", "Print enum values for a class"), 116 clEnumValN(PrintSets, "print-sets", 117 "Print expanded sets for testing DAG exprs"), 118 clEnumValN(GenOptParserDefs, "gen-opt-parser-defs", 119 "Generate option definitions"), 120 clEnumValN(GenOptRST, "gen-opt-rst", "Generate option RST"), 121 clEnumValN(GenCTags, "gen-ctags", "Generate ctags-compatible index"), 122 clEnumValN(GenAttributes, "gen-attrs", "Generate attributes"), 123 clEnumValN(GenSearchableTables, "gen-searchable-tables", 124 "Generate generic binary-searchable table"), 125 clEnumValN(GenGlobalISel, "gen-global-isel", 126 "Generate GlobalISel selector"), 127 clEnumValN(GenGICombiner, "gen-global-isel-combiner", 128 "Generate GlobalISel combiner"), 129 clEnumValN(GenX86EVEX2VEXTables, "gen-x86-EVEX2VEX-tables", 130 "Generate X86 EVEX to VEX compress tables"), 131 clEnumValN(GenX86FoldTables, "gen-x86-fold-tables", 132 "Generate X86 fold tables"), 133 clEnumValN(GenX86MnemonicTables, "gen-x86-mnemonic-tables", 134 "Generate X86 mnemonic tables"), 135 clEnumValN(GenRegisterBank, "gen-register-bank", 136 "Generate registers bank descriptions"), 137 clEnumValN(GenExegesis, "gen-exegesis", 138 "Generate llvm-exegesis tables"), 139 clEnumValN(GenAutomata, "gen-automata", "Generate generic automata"), 140 clEnumValN(GenDirectivesEnumDecl, "gen-directive-decl", 141 "Generate directive related declaration code (header file)"), 142 clEnumValN(GenDirectivesEnumImpl, "gen-directive-impl", 143 "Generate directive related implementation code"), 144 clEnumValN(GenDXILOperation, "gen-dxil-operation", 145 "Generate DXIL operation information"), 146 clEnumValN(GenRISCVTargetDef, "gen-riscv-target-def", 147 "Generate the list of CPU for RISCV"))); 148 cl::OptionCategory PrintEnumsCat("Options for -print-enums"); 149 cl::opt<std::string> Class("class", cl::desc("Print Enum list for this class"), 150 cl::value_desc("class name"), 151 cl::cat(PrintEnumsCat)); 152 153 bool LLVMTableGenMain(raw_ostream &OS, RecordKeeper &Records) { 154 switch (Action) { 155 case PrintRecords: 156 OS << Records; // No argument, dump all contents 157 break; 158 case PrintDetailedRecords: 159 EmitDetailedRecords(Records, OS); 160 break; 161 case NullBackend: // No backend at all. 162 break; 163 case DumpJSON: 164 EmitJSON(Records, OS); 165 break; 166 case GenEmitter: 167 EmitCodeEmitter(Records, OS); 168 break; 169 case GenRegisterInfo: 170 EmitRegisterInfo(Records, OS); 171 break; 172 case GenInstrInfo: 173 EmitInstrInfo(Records, OS); 174 break; 175 case GenInstrDocs: 176 EmitInstrDocs(Records, OS); 177 break; 178 case GenCallingConv: 179 EmitCallingConv(Records, OS); 180 break; 181 case GenAsmWriter: 182 EmitAsmWriter(Records, OS); 183 break; 184 case GenAsmMatcher: 185 EmitAsmMatcher(Records, OS); 186 break; 187 case GenDisassembler: 188 EmitDisassembler(Records, OS); 189 break; 190 case GenPseudoLowering: 191 EmitPseudoLowering(Records, OS); 192 break; 193 case GenCompressInst: 194 EmitCompressInst(Records, OS); 195 break; 196 case GenDAGISel: 197 EmitDAGISel(Records, OS); 198 break; 199 case GenDFAPacketizer: 200 EmitDFAPacketizer(Records, OS); 201 break; 202 case GenFastISel: 203 EmitFastISel(Records, OS); 204 break; 205 case GenSubtarget: 206 EmitSubtarget(Records, OS); 207 break; 208 case GenIntrinsicEnums: 209 EmitIntrinsicEnums(Records, OS); 210 break; 211 case GenIntrinsicImpl: 212 EmitIntrinsicImpl(Records, OS); 213 break; 214 case GenOptParserDefs: 215 EmitOptParser(Records, OS); 216 break; 217 case GenOptRST: 218 EmitOptRST(Records, OS); 219 break; 220 case PrintEnums: 221 { 222 for (Record *Rec : Records.getAllDerivedDefinitions(Class)) 223 OS << Rec->getName() << ", "; 224 OS << "\n"; 225 break; 226 } 227 case PrintSets: 228 { 229 SetTheory Sets; 230 Sets.addFieldExpander("Set", "Elements"); 231 for (Record *Rec : Records.getAllDerivedDefinitions("Set")) { 232 OS << Rec->getName() << " = ["; 233 const std::vector<Record*> *Elts = Sets.expand(Rec); 234 assert(Elts && "Couldn't expand Set instance"); 235 for (Record *Elt : *Elts) 236 OS << ' ' << Elt->getName(); 237 OS << " ]\n"; 238 } 239 break; 240 } 241 case GenCTags: 242 EmitCTags(Records, OS); 243 break; 244 case GenAttributes: 245 EmitAttributes(Records, OS); 246 break; 247 case GenSearchableTables: 248 EmitSearchableTables(Records, OS); 249 break; 250 case GenGlobalISel: 251 EmitGlobalISel(Records, OS); 252 break; 253 case GenGICombiner: 254 EmitGICombiner(Records, OS); 255 break; 256 case GenRegisterBank: 257 EmitRegisterBank(Records, OS); 258 break; 259 case GenX86EVEX2VEXTables: 260 EmitX86EVEX2VEXTables(Records, OS); 261 break; 262 case GenX86MnemonicTables: 263 EmitX86MnemonicTables(Records, OS); 264 break; 265 case GenX86FoldTables: 266 EmitX86FoldTables(Records, OS); 267 break; 268 case GenExegesis: 269 EmitExegesis(Records, OS); 270 break; 271 case GenAutomata: 272 EmitAutomata(Records, OS); 273 break; 274 case GenDirectivesEnumDecl: 275 EmitDirectivesDecl(Records, OS); 276 break; 277 case GenDirectivesEnumImpl: 278 EmitDirectivesImpl(Records, OS); 279 break; 280 case GenDXILOperation: 281 EmitDXILOperation(Records, OS); 282 break; 283 case GenRISCVTargetDef: 284 EmitRISCVTargetDef(Records, OS); 285 break; 286 } 287 288 return false; 289 } 290 } 291 292 int main(int argc, char **argv) { 293 InitLLVM X(argc, argv); 294 cl::ParseCommandLineOptions(argc, argv); 295 296 return TableGenMain(argv[0], &LLVMTableGenMain); 297 } 298 299 #ifndef __has_feature 300 #define __has_feature(x) 0 301 #endif 302 303 #if __has_feature(address_sanitizer) || \ 304 (defined(__SANITIZE_ADDRESS__) && defined(__GNUC__)) || \ 305 __has_feature(leak_sanitizer) 306 307 #include <sanitizer/lsan_interface.h> 308 // Disable LeakSanitizer for this binary as it has too many leaks that are not 309 // very interesting to fix. See compiler-rt/include/sanitizer/lsan_interface.h . 310 LLVM_ATTRIBUTE_USED int __lsan_is_turned_off() { return 1; } 311 312 #endif 313