1 //===- RegisterInfoEmitter.cpp - Generate a Register File Desc. -*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This tablegen backend is responsible for emitting a description of a target 10 // register file for a code generator. It uses instances of the Register, 11 // RegisterAliases, and RegisterClass classes to gather this information. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #include "Basic/SequenceToOffsetTable.h" 16 #include "Common/CodeGenHwModes.h" 17 #include "Common/CodeGenRegisters.h" 18 #include "Common/CodeGenTarget.h" 19 #include "Common/InfoByHwMode.h" 20 #include "Common/Types.h" 21 #include "llvm/ADT/ArrayRef.h" 22 #include "llvm/ADT/BitVector.h" 23 #include "llvm/ADT/STLExtras.h" 24 #include "llvm/ADT/SetVector.h" 25 #include "llvm/ADT/SmallVector.h" 26 #include "llvm/ADT/SparseBitVector.h" 27 #include "llvm/ADT/Twine.h" 28 #include "llvm/CodeGenTypes/MachineValueType.h" 29 #include "llvm/Support/Casting.h" 30 #include "llvm/Support/CommandLine.h" 31 #include "llvm/Support/Format.h" 32 #include "llvm/Support/raw_ostream.h" 33 #include "llvm/TableGen/Error.h" 34 #include "llvm/TableGen/Record.h" 35 #include "llvm/TableGen/SetTheory.h" 36 #include "llvm/TableGen/TGTimer.h" 37 #include "llvm/TableGen/TableGenBackend.h" 38 #include <algorithm> 39 #include <cassert> 40 #include <cstddef> 41 #include <cstdint> 42 #include <deque> 43 #include <iterator> 44 #include <set> 45 #include <string> 46 #include <vector> 47 48 using namespace llvm; 49 50 static cl::OptionCategory RegisterInfoCat("Options for -gen-register-info"); 51 52 static cl::opt<bool> 53 RegisterInfoDebug("register-info-debug", cl::init(false), 54 cl::desc("Dump register information to help debugging"), 55 cl::cat(RegisterInfoCat)); 56 57 namespace { 58 59 class RegisterInfoEmitter { 60 const RecordKeeper &Records; 61 const CodeGenTarget Target; 62 CodeGenRegBank &RegBank; 63 64 public: 65 RegisterInfoEmitter(const RecordKeeper &R) 66 : Records(R), Target(R), RegBank(Target.getRegBank()) { 67 RegBank.computeDerivedInfo(); 68 } 69 70 // runEnums - Print out enum values for all of the registers. 71 void runEnums(raw_ostream &OS); 72 73 // runMCDesc - Print out MC register descriptions. 74 void runMCDesc(raw_ostream &OS); 75 76 // runTargetHeader - Emit a header fragment for the register info emitter. 77 void runTargetHeader(raw_ostream &OS); 78 79 // runTargetDesc - Output the target register and register file descriptions. 80 void runTargetDesc(raw_ostream &OS); 81 82 // run - Output the register file description. 83 void run(raw_ostream &OS); 84 85 void debugDump(raw_ostream &OS); 86 87 private: 88 void EmitRegMapping(raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, 89 bool isCtor); 90 void EmitRegMappingTables(raw_ostream &OS, 91 const std::deque<CodeGenRegister> &Regs, 92 bool isCtor); 93 void EmitRegUnitPressure(raw_ostream &OS, StringRef ClassName); 94 void emitComposeSubRegIndices(raw_ostream &OS, StringRef ClassName); 95 void emitComposeSubRegIndexLaneMask(raw_ostream &OS, StringRef ClassName); 96 }; 97 98 } // end anonymous namespace 99 100 // runEnums - Print out enum values for all of the registers. 101 void RegisterInfoEmitter::runEnums(raw_ostream &OS) { 102 const auto &Registers = RegBank.getRegisters(); 103 104 // Register enums are stored as uint16_t in the tables. Make sure we'll fit. 105 assert(Registers.size() <= 0xffff && "Too many regs to fit in tables"); 106 107 StringRef Namespace = Registers.front().TheDef->getValueAsString("Namespace"); 108 109 emitSourceFileHeader("Target Register Enum Values", OS); 110 111 OS << "\n#ifdef GET_REGINFO_ENUM\n"; 112 OS << "#undef GET_REGINFO_ENUM\n\n"; 113 114 OS << "namespace llvm {\n\n"; 115 116 OS << "class MCRegisterClass;\n" 117 << "extern const MCRegisterClass " << Target.getName() 118 << "MCRegisterClasses[];\n\n"; 119 120 if (!Namespace.empty()) 121 OS << "namespace " << Namespace << " {\n"; 122 OS << "enum : unsigned {\n NoRegister,\n"; 123 124 for (const auto &Reg : Registers) 125 OS << " " << Reg.getName() << " = " << Reg.EnumValue << ",\n"; 126 assert(Registers.size() == Registers.back().EnumValue && 127 "Register enum value mismatch!"); 128 OS << " NUM_TARGET_REGS // " << Registers.size() + 1 << "\n"; 129 OS << "};\n"; 130 if (!Namespace.empty()) 131 OS << "} // end namespace " << Namespace << "\n"; 132 133 const auto &RegisterClasses = RegBank.getRegClasses(); 134 if (!RegisterClasses.empty()) { 135 136 // RegisterClass enums are stored as uint16_t in the tables. 137 assert(RegisterClasses.size() <= 0xffff && 138 "Too many register classes to fit in tables"); 139 140 OS << "\n// Register classes\n\n"; 141 if (!Namespace.empty()) 142 OS << "namespace " << Namespace << " {\n"; 143 OS << "enum {\n"; 144 for (const auto &RC : RegisterClasses) 145 OS << " " << RC.getIdName() << " = " << RC.EnumValue << ",\n"; 146 OS << "\n};\n"; 147 if (!Namespace.empty()) 148 OS << "} // end namespace " << Namespace << "\n\n"; 149 } 150 151 ArrayRef<const Record *> RegAltNameIndices = Target.getRegAltNameIndices(); 152 // If the only definition is the default NoRegAltName, we don't need to 153 // emit anything. 154 if (RegAltNameIndices.size() > 1) { 155 OS << "\n// Register alternate name indices\n\n"; 156 if (!Namespace.empty()) 157 OS << "namespace " << Namespace << " {\n"; 158 OS << "enum {\n"; 159 for (unsigned i = 0, e = RegAltNameIndices.size(); i != e; ++i) 160 OS << " " << RegAltNameIndices[i]->getName() << ",\t// " << i << "\n"; 161 OS << " NUM_TARGET_REG_ALT_NAMES = " << RegAltNameIndices.size() << "\n"; 162 OS << "};\n"; 163 if (!Namespace.empty()) 164 OS << "} // end namespace " << Namespace << "\n\n"; 165 } 166 167 auto &SubRegIndices = RegBank.getSubRegIndices(); 168 if (!SubRegIndices.empty()) { 169 OS << "\n// Subregister indices\n\n"; 170 std::string Namespace = SubRegIndices.front().getNamespace(); 171 if (!Namespace.empty()) 172 OS << "namespace " << Namespace << " {\n"; 173 OS << "enum : uint16_t {\n NoSubRegister,\n"; 174 unsigned i = 0; 175 for (const auto &Idx : SubRegIndices) 176 OS << " " << Idx.getName() << ",\t// " << ++i << "\n"; 177 OS << " NUM_TARGET_SUBREGS\n};\n"; 178 if (!Namespace.empty()) 179 OS << "} // end namespace " << Namespace << "\n\n"; 180 } 181 182 OS << "// Register pressure sets enum.\n"; 183 if (!Namespace.empty()) 184 OS << "namespace " << Namespace << " {\n"; 185 OS << "enum RegisterPressureSets {\n"; 186 unsigned NumSets = RegBank.getNumRegPressureSets(); 187 for (unsigned i = 0; i < NumSets; ++i) { 188 const RegUnitSet &RegUnits = RegBank.getRegSetAt(i); 189 OS << " " << RegUnits.Name << " = " << i << ",\n"; 190 } 191 OS << "};\n"; 192 if (!Namespace.empty()) 193 OS << "} // end namespace " << Namespace << '\n'; 194 OS << '\n'; 195 196 OS << "} // end namespace llvm\n\n"; 197 OS << "#endif // GET_REGINFO_ENUM\n\n"; 198 } 199 200 static void printInt(raw_ostream &OS, int Val) { OS << Val; } 201 202 void RegisterInfoEmitter::EmitRegUnitPressure(raw_ostream &OS, 203 StringRef ClassName) { 204 unsigned NumRCs = RegBank.getRegClasses().size(); 205 unsigned NumSets = RegBank.getNumRegPressureSets(); 206 207 OS << "/// Get the weight in units of pressure for this register class.\n" 208 << "const RegClassWeight &" << ClassName << "::\n" 209 << "getRegClassWeight(const TargetRegisterClass *RC) const {\n" 210 << " static const RegClassWeight RCWeightTable[] = {\n"; 211 for (const auto &RC : RegBank.getRegClasses()) { 212 const CodeGenRegister::Vec &Regs = RC.getMembers(); 213 OS << " {" << RC.getWeight(RegBank) << ", "; 214 if (Regs.empty() || RC.Artificial) 215 OS << '0'; 216 else { 217 std::vector<unsigned> RegUnits; 218 RC.buildRegUnitSet(RegBank, RegUnits); 219 OS << RegBank.getRegUnitSetWeight(RegUnits); 220 } 221 OS << "}, \t// " << RC.getName() << "\n"; 222 } 223 OS << " };\n" 224 << " return RCWeightTable[RC->getID()];\n" 225 << "}\n\n"; 226 227 // Reasonable targets (not ARMv7) have unit weight for all units, so don't 228 // bother generating a table. 229 bool RegUnitsHaveUnitWeight = true; 230 for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits(); 231 UnitIdx < UnitEnd; ++UnitIdx) { 232 if (RegBank.getRegUnit(UnitIdx).Weight > 1) 233 RegUnitsHaveUnitWeight = false; 234 } 235 OS << "/// Get the weight in units of pressure for this register unit.\n" 236 << "unsigned " << ClassName << "::\n" 237 << "getRegUnitWeight(unsigned RegUnit) const {\n" 238 << " assert(RegUnit < " << RegBank.getNumNativeRegUnits() 239 << " && \"invalid register unit\");\n"; 240 if (!RegUnitsHaveUnitWeight) { 241 OS << " static const uint8_t RUWeightTable[] = {\n "; 242 for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits(); 243 UnitIdx < UnitEnd; ++UnitIdx) { 244 const RegUnit &RU = RegBank.getRegUnit(UnitIdx); 245 assert(RU.Weight < 256 && "RegUnit too heavy"); 246 OS << RU.Weight << ", "; 247 } 248 OS << "};\n" 249 << " return RUWeightTable[RegUnit];\n"; 250 } else { 251 OS << " // All register units have unit weight.\n" 252 << " return 1;\n"; 253 } 254 OS << "}\n\n"; 255 256 OS << "\n" 257 << "// Get the number of dimensions of register pressure.\n" 258 << "unsigned " << ClassName << "::getNumRegPressureSets() const {\n" 259 << " return " << NumSets << ";\n}\n\n"; 260 261 OS << "// Get the name of this register unit pressure set.\n" 262 << "const char *" << ClassName << "::\n" 263 << "getRegPressureSetName(unsigned Idx) const {\n" 264 << " static const char *PressureNameTable[] = {\n"; 265 unsigned MaxRegUnitWeight = 0; 266 for (unsigned i = 0; i < NumSets; ++i) { 267 const RegUnitSet &RegUnits = RegBank.getRegSetAt(i); 268 MaxRegUnitWeight = std::max(MaxRegUnitWeight, RegUnits.Weight); 269 OS << " \"" << RegUnits.Name << "\",\n"; 270 } 271 OS << " };\n" 272 << " return PressureNameTable[Idx];\n" 273 << "}\n\n"; 274 275 OS << "// Get the register unit pressure limit for this dimension.\n" 276 << "// This limit must be adjusted dynamically for reserved registers.\n" 277 << "unsigned " << ClassName << "::\n" 278 << "getRegPressureSetLimit(const MachineFunction &MF, unsigned Idx) const " 279 "{\n" 280 << " static const " << getMinimalTypeForRange(MaxRegUnitWeight, 32) 281 << " PressureLimitTable[] = {\n"; 282 for (unsigned i = 0; i < NumSets; ++i) { 283 const RegUnitSet &RegUnits = RegBank.getRegSetAt(i); 284 OS << " " << RegUnits.Weight << ", \t// " << i << ": " << RegUnits.Name 285 << "\n"; 286 } 287 OS << " };\n" 288 << " return PressureLimitTable[Idx];\n" 289 << "}\n\n"; 290 291 SequenceToOffsetTable<std::vector<int>> PSetsSeqs(/*Terminator=*/-1); 292 293 // This table may be larger than NumRCs if some register units needed a list 294 // of unit sets that did not correspond to a register class. 295 unsigned NumRCUnitSets = RegBank.getNumRegClassPressureSetLists(); 296 std::vector<std::vector<int>> PSets(NumRCUnitSets); 297 298 for (unsigned i = 0, e = NumRCUnitSets; i != e; ++i) { 299 ArrayRef<unsigned> PSetIDs = RegBank.getRCPressureSetIDs(i); 300 PSets[i].reserve(PSetIDs.size()); 301 for (unsigned PSetID : PSetIDs) { 302 PSets[i].push_back(RegBank.getRegPressureSet(PSetID).Order); 303 } 304 llvm::sort(PSets[i]); 305 PSetsSeqs.add(PSets[i]); 306 } 307 308 PSetsSeqs.layout(); 309 310 OS << "/// Table of pressure sets per register class or unit.\n" 311 << "static const int RCSetsTable[] = {\n"; 312 PSetsSeqs.emit(OS, printInt); 313 OS << "};\n\n"; 314 315 OS << "/// Get the dimensions of register pressure impacted by this " 316 << "register class.\n" 317 << "/// Returns a -1 terminated array of pressure set IDs\n" 318 << "const int *" << ClassName << "::\n" 319 << "getRegClassPressureSets(const TargetRegisterClass *RC) const {\n"; 320 OS << " static const " << getMinimalTypeForRange(PSetsSeqs.size() - 1, 32) 321 << " RCSetStartTable[] = {\n "; 322 for (unsigned i = 0, e = NumRCs; i != e; ++i) { 323 OS << PSetsSeqs.get(PSets[i]) << ","; 324 } 325 OS << "};\n" 326 << " return &RCSetsTable[RCSetStartTable[RC->getID()]];\n" 327 << "}\n\n"; 328 329 OS << "/// Get the dimensions of register pressure impacted by this " 330 << "register unit.\n" 331 << "/// Returns a -1 terminated array of pressure set IDs\n" 332 << "const int *" << ClassName << "::\n" 333 << "getRegUnitPressureSets(unsigned RegUnit) const {\n" 334 << " assert(RegUnit < " << RegBank.getNumNativeRegUnits() 335 << " && \"invalid register unit\");\n"; 336 OS << " static const " << getMinimalTypeForRange(PSetsSeqs.size() - 1, 32) 337 << " RUSetStartTable[] = {\n "; 338 for (unsigned UnitIdx = 0, UnitEnd = RegBank.getNumNativeRegUnits(); 339 UnitIdx < UnitEnd; ++UnitIdx) { 340 OS << PSetsSeqs.get(PSets[RegBank.getRegUnit(UnitIdx).RegClassUnitSetsIdx]) 341 << ","; 342 } 343 OS << "};\n" 344 << " return &RCSetsTable[RUSetStartTable[RegUnit]];\n" 345 << "}\n\n"; 346 } 347 348 using DwarfRegNumsMapPair = std::pair<const Record *, std::vector<int64_t>>; 349 using DwarfRegNumsVecTy = std::vector<DwarfRegNumsMapPair>; 350 351 static void finalizeDwarfRegNumsKeys(DwarfRegNumsVecTy &DwarfRegNums) { 352 // Sort and unique to get a map-like vector. We want the last assignment to 353 // match previous behaviour. 354 llvm::stable_sort(DwarfRegNums, on_first<LessRecordRegister>()); 355 // Warn about duplicate assignments. 356 const Record *LastSeenReg = nullptr; 357 for (const auto &X : DwarfRegNums) { 358 const auto &Reg = X.first; 359 // The only way LessRecordRegister can return equal is if they're the same 360 // string. Use simple equality instead. 361 if (LastSeenReg && Reg->getName() == LastSeenReg->getName()) 362 PrintWarning(Reg->getLoc(), Twine("DWARF numbers for register ") + 363 getQualifiedName(Reg) + 364 "specified multiple times"); 365 LastSeenReg = Reg; 366 } 367 auto Last = llvm::unique(DwarfRegNums, [](const DwarfRegNumsMapPair &A, 368 const DwarfRegNumsMapPair &B) { 369 return A.first->getName() == B.first->getName(); 370 }); 371 DwarfRegNums.erase(Last, DwarfRegNums.end()); 372 } 373 374 void RegisterInfoEmitter::EmitRegMappingTables( 375 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) { 376 // Collect all information about dwarf register numbers 377 DwarfRegNumsVecTy DwarfRegNums; 378 379 // First, just pull all provided information to the map 380 unsigned maxLength = 0; 381 for (auto &RE : Regs) { 382 const Record *Reg = RE.TheDef; 383 std::vector<int64_t> RegNums = Reg->getValueAsListOfInts("DwarfNumbers"); 384 maxLength = std::max((size_t)maxLength, RegNums.size()); 385 DwarfRegNums.emplace_back(Reg, std::move(RegNums)); 386 } 387 finalizeDwarfRegNumsKeys(DwarfRegNums); 388 389 if (!maxLength) 390 return; 391 392 // Now we know maximal length of number list. Append -1's, where needed 393 for (auto &DwarfRegNum : DwarfRegNums) 394 for (unsigned I = DwarfRegNum.second.size(), E = maxLength; I != E; ++I) 395 DwarfRegNum.second.push_back(-1); 396 397 StringRef Namespace = Regs.front().TheDef->getValueAsString("Namespace"); 398 399 OS << "// " << Namespace << " Dwarf<->LLVM register mappings.\n"; 400 401 // Emit reverse information about the dwarf register numbers. 402 for (unsigned j = 0; j < 2; ++j) { 403 for (unsigned I = 0, E = maxLength; I != E; ++I) { 404 OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace; 405 OS << (j == 0 ? "DwarfFlavour" : "EHFlavour"); 406 OS << I << "Dwarf2L[]"; 407 408 if (!isCtor) { 409 OS << " = {\n"; 410 411 // Store the mapping sorted by the LLVM reg num so lookup can be done 412 // with a binary search. 413 std::map<uint64_t, const Record *> Dwarf2LMap; 414 for (auto &DwarfRegNum : DwarfRegNums) { 415 int DwarfRegNo = DwarfRegNum.second[I]; 416 if (DwarfRegNo < 0) 417 continue; 418 Dwarf2LMap[DwarfRegNo] = DwarfRegNum.first; 419 } 420 421 for (auto &I : Dwarf2LMap) 422 OS << " { " << I.first << "U, " << getQualifiedName(I.second) 423 << " },\n"; 424 425 OS << "};\n"; 426 } else { 427 OS << ";\n"; 428 } 429 430 // We have to store the size in a const global, it's used in multiple 431 // places. 432 OS << "extern const unsigned " << Namespace 433 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << I << "Dwarf2LSize"; 434 if (!isCtor) 435 OS << " = std::size(" << Namespace 436 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << I << "Dwarf2L);\n\n"; 437 else 438 OS << ";\n\n"; 439 } 440 } 441 442 for (auto &RE : Regs) { 443 const Record *Reg = RE.TheDef; 444 const RecordVal *V = Reg->getValue("DwarfAlias"); 445 if (!V || !V->getValue()) 446 continue; 447 448 const DefInit *DI = cast<DefInit>(V->getValue()); 449 const Record *Alias = DI->getDef(); 450 const auto &AliasIter = llvm::lower_bound( 451 DwarfRegNums, Alias, [](const DwarfRegNumsMapPair &A, const Record *B) { 452 return LessRecordRegister()(A.first, B); 453 }); 454 assert(AliasIter != DwarfRegNums.end() && AliasIter->first == Alias && 455 "Expected Alias to be present in map"); 456 const auto &RegIter = llvm::lower_bound( 457 DwarfRegNums, Reg, [](const DwarfRegNumsMapPair &A, const Record *B) { 458 return LessRecordRegister()(A.first, B); 459 }); 460 assert(RegIter != DwarfRegNums.end() && RegIter->first == Reg && 461 "Expected Reg to be present in map"); 462 RegIter->second = AliasIter->second; 463 } 464 465 // Emit information about the dwarf register numbers. 466 for (unsigned j = 0; j < 2; ++j) { 467 for (unsigned i = 0, e = maxLength; i != e; ++i) { 468 OS << "extern const MCRegisterInfo::DwarfLLVMRegPair " << Namespace; 469 OS << (j == 0 ? "DwarfFlavour" : "EHFlavour"); 470 OS << i << "L2Dwarf[]"; 471 if (!isCtor) { 472 OS << " = {\n"; 473 // Store the mapping sorted by the Dwarf reg num so lookup can be done 474 // with a binary search. 475 for (auto &DwarfRegNum : DwarfRegNums) { 476 int RegNo = DwarfRegNum.second[i]; 477 if (RegNo == -1) // -1 is the default value, don't emit a mapping. 478 continue; 479 480 OS << " { " << getQualifiedName(DwarfRegNum.first) << ", " << RegNo 481 << "U },\n"; 482 } 483 OS << "};\n"; 484 } else { 485 OS << ";\n"; 486 } 487 488 // We have to store the size in a const global, it's used in multiple 489 // places. 490 OS << "extern const unsigned " << Namespace 491 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "L2DwarfSize"; 492 if (!isCtor) 493 OS << " = std::size(" << Namespace 494 << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i << "L2Dwarf);\n\n"; 495 else 496 OS << ";\n\n"; 497 } 498 } 499 } 500 501 void RegisterInfoEmitter::EmitRegMapping( 502 raw_ostream &OS, const std::deque<CodeGenRegister> &Regs, bool isCtor) { 503 // Emit the initializer so the tables from EmitRegMappingTables get wired up 504 // to the MCRegisterInfo object. 505 unsigned maxLength = 0; 506 for (auto &RE : Regs) { 507 const Record *Reg = RE.TheDef; 508 maxLength = std::max((size_t)maxLength, 509 Reg->getValueAsListOfInts("DwarfNumbers").size()); 510 } 511 512 if (!maxLength) 513 return; 514 515 StringRef Namespace = Regs.front().TheDef->getValueAsString("Namespace"); 516 517 // Emit reverse information about the dwarf register numbers. 518 for (unsigned j = 0; j < 2; ++j) { 519 OS << " switch ("; 520 if (j == 0) 521 OS << "DwarfFlavour"; 522 else 523 OS << "EHFlavour"; 524 OS << ") {\n" 525 << " default:\n" 526 << " llvm_unreachable(\"Unknown DWARF flavour\");\n"; 527 528 for (unsigned i = 0, e = maxLength; i != e; ++i) { 529 OS << " case " << i << ":\n"; 530 OS << " "; 531 if (!isCtor) 532 OS << "RI->"; 533 std::string Tmp; 534 raw_string_ostream(Tmp) 535 << Namespace << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i 536 << "Dwarf2L"; 537 OS << "mapDwarfRegsToLLVMRegs(" << Tmp << ", " << Tmp << "Size, "; 538 if (j == 0) 539 OS << "false"; 540 else 541 OS << "true"; 542 OS << ");\n"; 543 OS << " break;\n"; 544 } 545 OS << " }\n"; 546 } 547 548 // Emit information about the dwarf register numbers. 549 for (unsigned j = 0; j < 2; ++j) { 550 OS << " switch ("; 551 if (j == 0) 552 OS << "DwarfFlavour"; 553 else 554 OS << "EHFlavour"; 555 OS << ") {\n" 556 << " default:\n" 557 << " llvm_unreachable(\"Unknown DWARF flavour\");\n"; 558 559 for (unsigned i = 0, e = maxLength; i != e; ++i) { 560 OS << " case " << i << ":\n"; 561 OS << " "; 562 if (!isCtor) 563 OS << "RI->"; 564 std::string Tmp; 565 raw_string_ostream(Tmp) 566 << Namespace << (j == 0 ? "DwarfFlavour" : "EHFlavour") << i 567 << "L2Dwarf"; 568 OS << "mapLLVMRegsToDwarfRegs(" << Tmp << ", " << Tmp << "Size, "; 569 if (j == 0) 570 OS << "false"; 571 else 572 OS << "true"; 573 OS << ");\n"; 574 OS << " break;\n"; 575 } 576 OS << " }\n"; 577 } 578 } 579 580 // Print a BitVector as a sequence of hex numbers using a little-endian mapping. 581 // Width is the number of bits per hex number. 582 static void printBitVectorAsHex(raw_ostream &OS, const BitVector &Bits, 583 unsigned Width) { 584 assert(Width <= 32 && "Width too large"); 585 unsigned Digits = (Width + 3) / 4; 586 for (unsigned i = 0, e = Bits.size(); i < e; i += Width) { 587 unsigned Value = 0; 588 for (unsigned j = 0; j != Width && i + j != e; ++j) 589 Value |= Bits.test(i + j) << j; 590 OS << format("0x%0*x, ", Digits, Value); 591 } 592 } 593 594 // Helper to emit a set of bits into a constant byte array. 595 class BitVectorEmitter { 596 BitVector Values; 597 598 public: 599 void add(unsigned v) { 600 if (v >= Values.size()) 601 Values.resize(((v / 8) + 1) * 8); // Round up to the next byte. 602 Values[v] = true; 603 } 604 605 void print(raw_ostream &OS) { printBitVectorAsHex(OS, Values, 8); } 606 }; 607 608 static void printSimpleValueType(raw_ostream &OS, MVT::SimpleValueType VT) { 609 OS << getEnumName(VT); 610 } 611 612 static void printSubRegIndex(raw_ostream &OS, const CodeGenSubRegIndex *Idx) { 613 OS << (Idx ? Idx->EnumValue : 0); 614 } 615 616 // Differentially encoded register and regunit lists allow for better 617 // compression on regular register banks. The sequence is computed from the 618 // differential list as: 619 // 620 // out[0] = InitVal; 621 // out[n+1] = out[n] + diff[n]; // n = 0, 1, ... 622 // 623 // The initial value depends on the specific list. The list is terminated by a 624 // 0 differential which means we can't encode repeated elements. 625 626 typedef SmallVector<int16_t, 4> DiffVec; 627 typedef SmallVector<LaneBitmask, 4> MaskVec; 628 629 // Fills V with differentials between every two consecutive elements of List. 630 static DiffVec &diffEncode(DiffVec &V, SparseBitVector<> List) { 631 assert(V.empty() && "Clear DiffVec before diffEncode."); 632 SparseBitVector<>::iterator I = List.begin(), E = List.end(); 633 unsigned Val = *I; 634 while (++I != E) { 635 unsigned Cur = *I; 636 V.push_back(Cur - Val); 637 Val = Cur; 638 } 639 return V; 640 } 641 642 template <typename Iter> 643 static DiffVec &diffEncode(DiffVec &V, unsigned InitVal, Iter Begin, Iter End) { 644 assert(V.empty() && "Clear DiffVec before diffEncode."); 645 unsigned Val = InitVal; 646 for (Iter I = Begin; I != End; ++I) { 647 unsigned Cur = (*I)->EnumValue; 648 V.push_back(Cur - Val); 649 Val = Cur; 650 } 651 return V; 652 } 653 654 static void printDiff16(raw_ostream &OS, int16_t Val) { OS << Val; } 655 656 static void printMask(raw_ostream &OS, LaneBitmask Val) { 657 OS << "LaneBitmask(0x" << PrintLaneMask(Val) << ')'; 658 } 659 660 // Try to combine Idx's compose map into Vec if it is compatible. 661 // Return false if it's not possible. 662 static bool combine(const CodeGenSubRegIndex *Idx, 663 SmallVectorImpl<const CodeGenSubRegIndex *> &Vec) { 664 const CodeGenSubRegIndex::CompMap &Map = Idx->getComposites(); 665 for (const auto &I : Map) { 666 const CodeGenSubRegIndex *&Entry = Vec[I.first->EnumValue - 1]; 667 if (Entry && Entry != I.second) 668 return false; 669 } 670 671 // All entries are compatible. Make it so. 672 for (const auto &I : Map) { 673 const CodeGenSubRegIndex *&Entry = Vec[I.first->EnumValue - 1]; 674 assert((!Entry || Entry == I.second) && "Expected EnumValue to be unique"); 675 Entry = I.second; 676 } 677 return true; 678 } 679 680 void RegisterInfoEmitter::emitComposeSubRegIndices(raw_ostream &OS, 681 StringRef ClassName) { 682 const auto &SubRegIndices = RegBank.getSubRegIndices(); 683 684 // Many sub-register indexes are composition-compatible, meaning that 685 // 686 // compose(IdxA, IdxB) == compose(IdxA', IdxB) 687 // 688 // for many IdxA, IdxA' pairs. Not all sub-register indexes can be composed. 689 // The illegal entries can be use as wildcards to compress the table further. 690 691 // Map each Sub-register index to a compatible table row. 692 SmallVector<unsigned, 4> RowMap; 693 SmallVector<SmallVector<const CodeGenSubRegIndex *, 4>, 4> Rows; 694 695 auto SubRegIndicesSize = 696 std::distance(SubRegIndices.begin(), SubRegIndices.end()); 697 for (const auto &Idx : SubRegIndices) { 698 unsigned Found = ~0u; 699 for (unsigned r = 0, re = Rows.size(); r != re; ++r) { 700 if (combine(&Idx, Rows[r])) { 701 Found = r; 702 break; 703 } 704 } 705 if (Found == ~0u) { 706 Found = Rows.size(); 707 Rows.resize(Found + 1); 708 Rows.back().resize(SubRegIndicesSize); 709 combine(&Idx, Rows.back()); 710 } 711 RowMap.push_back(Found); 712 } 713 714 OS << "unsigned " << ClassName 715 << "::composeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const {\n"; 716 717 // Output the row map if there are multiple rows. 718 if (Rows.size() > 1) { 719 OS << " static const " << getMinimalTypeForRange(Rows.size(), 32) 720 << " RowMap[" << SubRegIndicesSize << "] = {\n "; 721 for (unsigned i = 0, e = SubRegIndicesSize; i != e; ++i) 722 OS << RowMap[i] << ", "; 723 OS << "\n };\n"; 724 } 725 726 // Output the rows. 727 OS << " static const " << getMinimalTypeForRange(SubRegIndicesSize + 1, 32) 728 << " Rows[" << Rows.size() << "][" << SubRegIndicesSize << "] = {\n"; 729 for (const auto &Row : Rows) { 730 OS << " { "; 731 for (const llvm::CodeGenSubRegIndex *Elem : 732 ArrayRef(&Row[0], SubRegIndicesSize)) 733 if (Elem) 734 OS << Elem->getQualifiedName() << ", "; 735 else 736 OS << "0, "; 737 OS << "},\n"; 738 } 739 OS << " };\n\n"; 740 741 OS << " --IdxA; assert(IdxA < " << SubRegIndicesSize << "); (void) IdxA;\n" 742 << " --IdxB; assert(IdxB < " << SubRegIndicesSize << ");\n"; 743 if (Rows.size() > 1) 744 OS << " return Rows[RowMap[IdxA]][IdxB];\n"; 745 else 746 OS << " return Rows[0][IdxB];\n"; 747 OS << "}\n\n"; 748 749 // Generate the reverse case. 750 // 751 // FIXME: This is the brute force approach. Compress the table similar to the 752 // forward case. 753 OS << "unsigned " << ClassName 754 << "::reverseComposeSubRegIndicesImpl(unsigned IdxA, unsigned IdxB) const " 755 "{\n"; 756 OS << " static const " << getMinimalTypeForRange(SubRegIndicesSize + 1, 32) 757 << " Table[" << SubRegIndicesSize << "][" << SubRegIndicesSize 758 << "] = {\n"; 759 760 // Find values where composeSubReg(A, X) == B; 761 for (const auto &IdxA : SubRegIndices) { 762 OS << " { "; 763 764 SmallVectorImpl<const CodeGenSubRegIndex *> &Row = 765 Rows[RowMap[IdxA.EnumValue - 1]]; 766 for (const auto &IdxB : SubRegIndices) { 767 const CodeGenSubRegIndex *FoundReverse = nullptr; 768 769 for (unsigned i = 0, e = SubRegIndicesSize; i != e; ++i) { 770 const CodeGenSubRegIndex *This = &SubRegIndices[i]; 771 const CodeGenSubRegIndex *Composed = Row[i]; 772 if (Composed == &IdxB) { 773 if (FoundReverse && FoundReverse != This) // Not unique 774 break; 775 FoundReverse = This; 776 } 777 } 778 779 if (FoundReverse) { 780 OS << FoundReverse->getQualifiedName() << ", "; 781 } else { 782 OS << "0, "; 783 } 784 } 785 OS << "},\n"; 786 } 787 788 OS << " };\n\n"; 789 OS << " --IdxA; assert(IdxA < " << SubRegIndicesSize << ");\n" 790 << " --IdxB; assert(IdxB < " << SubRegIndicesSize << ");\n"; 791 OS << " return Table[IdxA][IdxB];\n"; 792 OS << " }\n\n"; 793 } 794 795 void RegisterInfoEmitter::emitComposeSubRegIndexLaneMask(raw_ostream &OS, 796 StringRef ClassName) { 797 // See the comments in computeSubRegLaneMasks() for our goal here. 798 const auto &SubRegIndices = RegBank.getSubRegIndices(); 799 800 // Create a list of Mask+Rotate operations, with equivalent entries merged. 801 SmallVector<unsigned, 4> SubReg2SequenceIndexMap; 802 SmallVector<SmallVector<MaskRolPair, 1>, 4> Sequences; 803 for (const auto &Idx : SubRegIndices) { 804 const SmallVector<MaskRolPair, 1> &IdxSequence = 805 Idx.CompositionLaneMaskTransform; 806 807 unsigned Found = ~0u; 808 unsigned SIdx = 0; 809 unsigned NextSIdx; 810 for (size_t s = 0, se = Sequences.size(); s != se; ++s, SIdx = NextSIdx) { 811 SmallVectorImpl<MaskRolPair> &Sequence = Sequences[s]; 812 NextSIdx = SIdx + Sequence.size() + 1; 813 if (Sequence == IdxSequence) { 814 Found = SIdx; 815 break; 816 } 817 } 818 if (Found == ~0u) { 819 Sequences.push_back(IdxSequence); 820 Found = SIdx; 821 } 822 SubReg2SequenceIndexMap.push_back(Found); 823 } 824 825 OS << " struct MaskRolOp {\n" 826 " LaneBitmask Mask;\n" 827 " uint8_t RotateLeft;\n" 828 " };\n" 829 " static const MaskRolOp LaneMaskComposeSequences[] = {\n"; 830 unsigned Idx = 0; 831 for (size_t s = 0, se = Sequences.size(); s != se; ++s) { 832 OS << " "; 833 const SmallVectorImpl<MaskRolPair> &Sequence = Sequences[s]; 834 for (const MaskRolPair &P : Sequence) { 835 printMask(OS << "{ ", P.Mask); 836 OS << format(", %2u }, ", P.RotateLeft); 837 } 838 OS << "{ LaneBitmask::getNone(), 0 }"; 839 if (s + 1 != se) 840 OS << ", "; 841 OS << " // Sequence " << Idx << "\n"; 842 Idx += Sequence.size() + 1; 843 } 844 auto *IntType = 845 getMinimalTypeForRange(*llvm::max_element(SubReg2SequenceIndexMap)); 846 OS << " };\n" 847 " static const " 848 << IntType << " CompositeSequences[] = {\n"; 849 for (size_t i = 0, e = SubRegIndices.size(); i != e; ++i) { 850 OS << " "; 851 OS << SubReg2SequenceIndexMap[i]; 852 if (i + 1 != e) 853 OS << ","; 854 OS << " // to " << SubRegIndices[i].getName() << "\n"; 855 } 856 OS << " };\n\n"; 857 858 OS << "LaneBitmask " << ClassName 859 << "::composeSubRegIndexLaneMaskImpl(unsigned IdxA, LaneBitmask LaneMask)" 860 " const {\n" 861 " --IdxA; assert(IdxA < " 862 << SubRegIndices.size() 863 << " && \"Subregister index out of bounds\");\n" 864 " LaneBitmask Result;\n" 865 " for (const MaskRolOp *Ops =\n" 866 " &LaneMaskComposeSequences[CompositeSequences[IdxA]];\n" 867 " Ops->Mask.any(); ++Ops) {\n" 868 " LaneBitmask::Type M = LaneMask.getAsInteger() & " 869 "Ops->Mask.getAsInteger();\n" 870 " if (unsigned S = Ops->RotateLeft)\n" 871 " Result |= LaneBitmask((M << S) | (M >> (LaneBitmask::BitWidth - " 872 "S)));\n" 873 " else\n" 874 " Result |= LaneBitmask(M);\n" 875 " }\n" 876 " return Result;\n" 877 "}\n\n"; 878 879 OS << "LaneBitmask " << ClassName 880 << "::reverseComposeSubRegIndexLaneMaskImpl(unsigned IdxA, " 881 " LaneBitmask LaneMask) const {\n" 882 " LaneMask &= getSubRegIndexLaneMask(IdxA);\n" 883 " --IdxA; assert(IdxA < " 884 << SubRegIndices.size() 885 << " && \"Subregister index out of bounds\");\n" 886 " LaneBitmask Result;\n" 887 " for (const MaskRolOp *Ops =\n" 888 " &LaneMaskComposeSequences[CompositeSequences[IdxA]];\n" 889 " Ops->Mask.any(); ++Ops) {\n" 890 " LaneBitmask::Type M = LaneMask.getAsInteger();\n" 891 " if (unsigned S = Ops->RotateLeft)\n" 892 " Result |= LaneBitmask((M >> S) | (M << (LaneBitmask::BitWidth - " 893 "S)));\n" 894 " else\n" 895 " Result |= LaneBitmask(M);\n" 896 " }\n" 897 " return Result;\n" 898 "}\n\n"; 899 } 900 901 // 902 // runMCDesc - Print out MC register descriptions. 903 // 904 void RegisterInfoEmitter::runMCDesc(raw_ostream &OS) { 905 emitSourceFileHeader("MC Register Information", OS); 906 907 OS << "\n#ifdef GET_REGINFO_MC_DESC\n"; 908 OS << "#undef GET_REGINFO_MC_DESC\n\n"; 909 910 const auto &Regs = RegBank.getRegisters(); 911 912 auto &SubRegIndices = RegBank.getSubRegIndices(); 913 // The lists of sub-registers and super-registers go in the same array. That 914 // allows us to share suffixes. 915 typedef std::vector<const CodeGenRegister *> RegVec; 916 917 // Differentially encoded lists. 918 SequenceToOffsetTable<DiffVec> DiffSeqs; 919 SmallVector<DiffVec, 4> SubRegLists(Regs.size()); 920 SmallVector<DiffVec, 4> SuperRegLists(Regs.size()); 921 SmallVector<DiffVec, 4> RegUnitLists(Regs.size()); 922 923 // List of lane masks accompanying register unit sequences. 924 SequenceToOffsetTable<MaskVec> LaneMaskSeqs(/*Terminator=*/std::nullopt); 925 SmallVector<MaskVec, 4> RegUnitLaneMasks(Regs.size()); 926 927 // Keep track of sub-register names as well. These are not differentially 928 // encoded. 929 typedef SmallVector<const CodeGenSubRegIndex *, 4> SubRegIdxVec; 930 SequenceToOffsetTable<SubRegIdxVec, deref<std::less<>>> SubRegIdxSeqs( 931 /*Terminator=*/std::nullopt); 932 SmallVector<SubRegIdxVec, 4> SubRegIdxLists(Regs.size()); 933 934 SequenceToOffsetTable<std::string> RegStrings; 935 936 // Precompute register lists for the SequenceToOffsetTable. 937 unsigned i = 0; 938 for (auto I = Regs.begin(), E = Regs.end(); I != E; ++I, ++i) { 939 const auto &Reg = *I; 940 RegStrings.add(Reg.getName().str()); 941 942 // Compute the ordered sub-register list. 943 SetVector<const CodeGenRegister *> SR; 944 Reg.addSubRegsPreOrder(SR, RegBank); 945 diffEncode(SubRegLists[i], Reg.EnumValue, SR.begin(), SR.end()); 946 DiffSeqs.add(SubRegLists[i]); 947 948 // Compute the corresponding sub-register indexes. 949 SubRegIdxVec &SRIs = SubRegIdxLists[i]; 950 for (const CodeGenRegister *S : SR) 951 SRIs.push_back(Reg.getSubRegIndex(S)); 952 SubRegIdxSeqs.add(SRIs); 953 954 // Super-registers are already computed. 955 const RegVec &SuperRegList = Reg.getSuperRegs(); 956 diffEncode(SuperRegLists[i], Reg.EnumValue, SuperRegList.begin(), 957 SuperRegList.end()); 958 DiffSeqs.add(SuperRegLists[i]); 959 960 const SparseBitVector<> &RUs = Reg.getNativeRegUnits(); 961 DiffSeqs.add(diffEncode(RegUnitLists[i], RUs)); 962 963 const auto &RUMasks = Reg.getRegUnitLaneMasks(); 964 MaskVec &LaneMaskVec = RegUnitLaneMasks[i]; 965 assert(LaneMaskVec.empty()); 966 llvm::append_range(LaneMaskVec, RUMasks); 967 LaneMaskSeqs.add(LaneMaskVec); 968 } 969 970 // Compute the final layout of the sequence table. 971 DiffSeqs.layout(); 972 LaneMaskSeqs.layout(); 973 SubRegIdxSeqs.layout(); 974 975 OS << "namespace llvm {\n\n"; 976 977 const std::string &TargetName = Target.getName().str(); 978 979 // Emit the shared table of differential lists. 980 OS << "extern const int16_t " << TargetName << "RegDiffLists[] = {\n"; 981 DiffSeqs.emit(OS, printDiff16); 982 OS << "};\n\n"; 983 984 // Emit the shared table of regunit lane mask sequences. 985 OS << "extern const LaneBitmask " << TargetName << "LaneMaskLists[] = {\n"; 986 LaneMaskSeqs.emit(OS, printMask); 987 OS << "};\n\n"; 988 989 // Emit the table of sub-register indexes. 990 OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[] = {\n"; 991 SubRegIdxSeqs.emit(OS, printSubRegIndex); 992 OS << "};\n\n"; 993 994 // Emit the string table. 995 RegStrings.layout(); 996 RegStrings.emitStringLiteralDef(OS, Twine("extern const char ") + TargetName + 997 "RegStrings[]"); 998 999 OS << "extern const MCRegisterDesc " << TargetName 1000 << "RegDesc[] = { // Descriptors\n"; 1001 OS << " { " << RegStrings.get("") << ", 0, 0, 0, 0, 0, 0, 0 },\n"; 1002 1003 // Emit the register descriptors now. 1004 i = 0; 1005 for (const auto &Reg : Regs) { 1006 unsigned FirstRU = Reg.getNativeRegUnits().find_first(); 1007 unsigned Offset = DiffSeqs.get(RegUnitLists[i]); 1008 // The value must be kept in sync with MCRegisterInfo.h. 1009 constexpr unsigned RegUnitBits = 12; 1010 assert(isUInt<RegUnitBits>(FirstRU) && "Too many regunits"); 1011 assert(isUInt<32 - RegUnitBits>(Offset) && "Offset is too big"); 1012 OS << " { " << RegStrings.get(Reg.getName().str()) << ", " 1013 << DiffSeqs.get(SubRegLists[i]) << ", " << DiffSeqs.get(SuperRegLists[i]) 1014 << ", " << SubRegIdxSeqs.get(SubRegIdxLists[i]) << ", " 1015 << (Offset << RegUnitBits | FirstRU) << ", " 1016 << LaneMaskSeqs.get(RegUnitLaneMasks[i]) << ", " << Reg.Constant << ", " 1017 << Reg.Artificial << " },\n"; 1018 ++i; 1019 } 1020 OS << "};\n\n"; // End of register descriptors... 1021 1022 // Emit the table of register unit roots. Each regunit has one or two root 1023 // registers. 1024 OS << "extern const MCPhysReg " << TargetName << "RegUnitRoots[][2] = {\n"; 1025 for (unsigned i = 0, e = RegBank.getNumNativeRegUnits(); i != e; ++i) { 1026 ArrayRef<const CodeGenRegister *> Roots = RegBank.getRegUnit(i).getRoots(); 1027 assert(!Roots.empty() && "All regunits must have a root register."); 1028 assert(Roots.size() <= 2 && "More than two roots not supported yet."); 1029 OS << " { "; 1030 ListSeparator LS; 1031 for (const CodeGenRegister *R : Roots) 1032 OS << LS << getQualifiedName(R->TheDef); 1033 OS << " },\n"; 1034 } 1035 OS << "};\n\n"; 1036 1037 const auto &RegisterClasses = RegBank.getRegClasses(); 1038 1039 // Loop over all of the register classes... emitting each one. 1040 OS << "namespace { // Register classes...\n"; 1041 1042 SequenceToOffsetTable<std::string> RegClassStrings; 1043 1044 // Emit the register enum value arrays for each RegisterClass 1045 for (const auto &RC : RegisterClasses) { 1046 ArrayRef<const Record *> Order = RC.getOrder(); 1047 1048 // Give the register class a legal C name if it's anonymous. 1049 const std::string &Name = RC.getName(); 1050 1051 RegClassStrings.add(Name); 1052 1053 // Emit the register list now (unless it would be a zero-length array). 1054 if (!Order.empty()) { 1055 OS << " // " << Name << " Register Class...\n" 1056 << " const MCPhysReg " << Name << "[] = {\n "; 1057 for (const Record *Reg : Order) { 1058 OS << getQualifiedName(Reg) << ", "; 1059 } 1060 OS << "\n };\n\n"; 1061 1062 OS << " // " << Name << " Bit set.\n" 1063 << " const uint8_t " << Name << "Bits[] = {\n "; 1064 BitVectorEmitter BVE; 1065 for (const Record *Reg : Order) { 1066 BVE.add(RegBank.getReg(Reg)->EnumValue); 1067 } 1068 BVE.print(OS); 1069 OS << "\n };\n\n"; 1070 } 1071 } 1072 OS << "} // end anonymous namespace\n\n"; 1073 1074 RegClassStrings.layout(); 1075 RegClassStrings.emitStringLiteralDef( 1076 OS, Twine("extern const char ") + TargetName + "RegClassStrings[]"); 1077 1078 OS << "extern const MCRegisterClass " << TargetName 1079 << "MCRegisterClasses[] = {\n"; 1080 1081 for (const auto &RC : RegisterClasses) { 1082 ArrayRef<const Record *> Order = RC.getOrder(); 1083 std::string RCName = Order.empty() ? "nullptr" : RC.getName(); 1084 std::string RCBitsName = Order.empty() ? "nullptr" : RC.getName() + "Bits"; 1085 std::string RCBitsSize = Order.empty() ? "0" : "sizeof(" + RCBitsName + ")"; 1086 assert(isInt<8>(RC.CopyCost) && "Copy cost too large."); 1087 uint32_t RegSize = 0; 1088 if (RC.RSI.isSimple()) 1089 RegSize = RC.RSI.getSimple().RegSize; 1090 OS << " { " << RCName << ", " << RCBitsName << ", " 1091 << RegClassStrings.get(RC.getName()) << ", " << RC.getOrder().size() 1092 << ", " << RCBitsSize << ", " << RC.getQualifiedIdName() << ", " 1093 << RegSize << ", " << RC.CopyCost << ", " 1094 << (RC.Allocatable ? "true" : "false") << ", " 1095 << (RC.getBaseClassOrder() ? "true" : "false") << " },\n"; 1096 } 1097 1098 OS << "};\n\n"; 1099 1100 EmitRegMappingTables(OS, Regs, false); 1101 1102 // Emit Reg encoding table 1103 OS << "extern const uint16_t " << TargetName; 1104 OS << "RegEncodingTable[] = {\n"; 1105 // Add entry for NoRegister 1106 OS << " 0,\n"; 1107 for (const auto &RE : Regs) { 1108 const Record *Reg = RE.TheDef; 1109 const BitsInit *BI = Reg->getValueAsBitsInit("HWEncoding"); 1110 uint64_t Value = 0; 1111 for (unsigned b = 0, be = BI->getNumBits(); b != be; ++b) { 1112 if (const BitInit *B = dyn_cast<BitInit>(BI->getBit(b))) 1113 Value |= (uint64_t)B->getValue() << b; 1114 } 1115 OS << " " << Value << ",\n"; 1116 } 1117 OS << "};\n"; // End of HW encoding table 1118 1119 // MCRegisterInfo initialization routine. 1120 OS << "static inline void Init" << TargetName 1121 << "MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, " 1122 << "unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) " 1123 "{\n" 1124 << " RI->InitMCRegisterInfo(" << TargetName << "RegDesc, " 1125 << Regs.size() + 1 << ", RA, PC, " << TargetName << "MCRegisterClasses, " 1126 << RegisterClasses.size() << ", " << TargetName << "RegUnitRoots, " 1127 << RegBank.getNumNativeRegUnits() << ", " << TargetName << "RegDiffLists, " 1128 << TargetName << "LaneMaskLists, " << TargetName << "RegStrings, " 1129 << TargetName << "RegClassStrings, " << TargetName << "SubRegIdxLists, " 1130 << (std::distance(SubRegIndices.begin(), SubRegIndices.end()) + 1) << ",\n" 1131 << TargetName << "RegEncodingTable);\n\n"; 1132 1133 EmitRegMapping(OS, Regs, false); 1134 1135 OS << "}\n\n"; 1136 1137 OS << "} // end namespace llvm\n\n"; 1138 OS << "#endif // GET_REGINFO_MC_DESC\n\n"; 1139 } 1140 1141 void RegisterInfoEmitter::runTargetHeader(raw_ostream &OS) { 1142 emitSourceFileHeader("Register Information Header Fragment", OS); 1143 1144 OS << "\n#ifdef GET_REGINFO_HEADER\n"; 1145 OS << "#undef GET_REGINFO_HEADER\n\n"; 1146 1147 const std::string &TargetName = Target.getName().str(); 1148 std::string ClassName = TargetName + "GenRegisterInfo"; 1149 1150 OS << "#include \"llvm/CodeGen/TargetRegisterInfo.h\"\n\n"; 1151 1152 OS << "namespace llvm {\n\n"; 1153 1154 OS << "class " << TargetName << "FrameLowering;\n\n"; 1155 1156 OS << "struct " << ClassName << " : public TargetRegisterInfo {\n" 1157 << " explicit " << ClassName 1158 << "(unsigned RA, unsigned D = 0, unsigned E = 0,\n" 1159 << " unsigned PC = 0, unsigned HwMode = 0);\n"; 1160 if (!RegBank.getSubRegIndices().empty()) { 1161 OS << " unsigned composeSubRegIndicesImpl" 1162 << "(unsigned, unsigned) const override;\n" 1163 << " unsigned reverseComposeSubRegIndicesImpl" 1164 << "(unsigned, unsigned) const override;\n" 1165 << " LaneBitmask composeSubRegIndexLaneMaskImpl" 1166 << "(unsigned, LaneBitmask) const override;\n" 1167 << " LaneBitmask reverseComposeSubRegIndexLaneMaskImpl" 1168 << "(unsigned, LaneBitmask) const override;\n" 1169 << " const TargetRegisterClass *getSubClassWithSubReg" 1170 << "(const TargetRegisterClass *, unsigned) const override;\n" 1171 << " const TargetRegisterClass *getSubRegisterClass" 1172 << "(const TargetRegisterClass *, unsigned) const override;\n"; 1173 } 1174 OS << " const RegClassWeight &getRegClassWeight(" 1175 << "const TargetRegisterClass *RC) const override;\n" 1176 << " unsigned getRegUnitWeight(unsigned RegUnit) const override;\n" 1177 << " unsigned getNumRegPressureSets() const override;\n" 1178 << " const char *getRegPressureSetName(unsigned Idx) const override;\n" 1179 << " unsigned getRegPressureSetLimit(const MachineFunction &MF, unsigned " 1180 "Idx) const override;\n" 1181 << " const int *getRegClassPressureSets(" 1182 << "const TargetRegisterClass *RC) const override;\n" 1183 << " const int *getRegUnitPressureSets(" 1184 << "unsigned RegUnit) const override;\n" 1185 << " ArrayRef<const char *> getRegMaskNames() const override;\n" 1186 << " ArrayRef<const uint32_t *> getRegMasks() const override;\n" 1187 << " bool isGeneralPurposeRegister(const MachineFunction &, " 1188 << "MCRegister) const override;\n" 1189 << " bool isGeneralPurposeRegisterClass(const TargetRegisterClass *RC)" 1190 << " const override;\n" 1191 << " bool isFixedRegister(const MachineFunction &, " 1192 << "MCRegister) const override;\n" 1193 << " bool isArgumentRegister(const MachineFunction &, " 1194 << "MCRegister) const override;\n" 1195 << " bool isConstantPhysReg(MCRegister PhysReg) const override final;\n" 1196 << " /// Devirtualized TargetFrameLowering.\n" 1197 << " static const " << TargetName << "FrameLowering *getFrameLowering(\n" 1198 << " const MachineFunction &MF);\n"; 1199 1200 const auto &RegisterClasses = RegBank.getRegClasses(); 1201 if (llvm::any_of(RegisterClasses, 1202 [](const auto &RC) { return RC.getBaseClassOrder(); })) { 1203 OS << " const TargetRegisterClass *getPhysRegBaseClass(MCRegister Reg) " 1204 "const override;\n"; 1205 } 1206 1207 OS << "};\n\n"; 1208 1209 if (!RegisterClasses.empty()) { 1210 OS << "namespace " << RegisterClasses.front().Namespace 1211 << " { // Register classes\n"; 1212 1213 for (const auto &RC : RegisterClasses) { 1214 const std::string &Name = RC.getName(); 1215 1216 // Output the extern for the instance. 1217 OS << " extern const TargetRegisterClass " << Name << "RegClass;\n"; 1218 } 1219 OS << "} // end namespace " << RegisterClasses.front().Namespace << "\n\n"; 1220 } 1221 OS << "} // end namespace llvm\n\n"; 1222 OS << "#endif // GET_REGINFO_HEADER\n\n"; 1223 } 1224 1225 // 1226 // runTargetDesc - Output the target register and register file descriptions. 1227 // 1228 void RegisterInfoEmitter::runTargetDesc(raw_ostream &OS) { 1229 emitSourceFileHeader("Target Register and Register Classes Information", OS); 1230 1231 OS << "\n#ifdef GET_REGINFO_TARGET_DESC\n"; 1232 OS << "#undef GET_REGINFO_TARGET_DESC\n\n"; 1233 1234 OS << "namespace llvm {\n\n"; 1235 1236 // Get access to MCRegisterClass data. 1237 OS << "extern const MCRegisterClass " << Target.getName() 1238 << "MCRegisterClasses[];\n"; 1239 1240 // Start out by emitting each of the register classes. 1241 const auto &RegisterClasses = RegBank.getRegClasses(); 1242 const auto &SubRegIndices = RegBank.getSubRegIndices(); 1243 1244 // Collect all registers belonging to any allocatable class. 1245 std::set<const Record *> AllocatableRegs; 1246 1247 // Collect allocatable registers. 1248 for (const auto &RC : RegisterClasses) { 1249 ArrayRef<const Record *> Order = RC.getOrder(); 1250 1251 if (RC.Allocatable) 1252 AllocatableRegs.insert(Order.begin(), Order.end()); 1253 } 1254 1255 const CodeGenHwModes &CGH = Target.getHwModes(); 1256 unsigned NumModes = CGH.getNumModeIds(); 1257 1258 // Build a shared array of value types. 1259 SequenceToOffsetTable<std::vector<MVT::SimpleValueType>> VTSeqs( 1260 /*Terminator=*/MVT::Other); 1261 for (unsigned M = 0; M < NumModes; ++M) { 1262 for (const auto &RC : RegisterClasses) { 1263 std::vector<MVT::SimpleValueType> S; 1264 for (const ValueTypeByHwMode &VVT : RC.VTs) 1265 if (VVT.hasDefault() || VVT.hasMode(M)) 1266 S.push_back(VVT.get(M).SimpleTy); 1267 VTSeqs.add(S); 1268 } 1269 } 1270 VTSeqs.layout(); 1271 OS << "\nstatic const MVT::SimpleValueType VTLists[] = {\n"; 1272 VTSeqs.emit(OS, printSimpleValueType); 1273 OS << "};\n"; 1274 1275 // Emit SubRegIndex names, skipping 0. 1276 OS << "\nstatic const char *SubRegIndexNameTable[] = { \""; 1277 1278 for (const auto &Idx : SubRegIndices) { 1279 OS << Idx.getName(); 1280 OS << "\", \""; 1281 } 1282 OS << "\" };\n\n"; 1283 1284 // Emit the table of sub-register index sizes. 1285 OS << "static const TargetRegisterInfo::SubRegCoveredBits " 1286 "SubRegIdxRangeTable[] = {\n"; 1287 for (unsigned M = 0; M < NumModes; ++M) { 1288 OS << " { " << (uint16_t)-1 << ", " << (uint16_t)-1 << " },\n"; 1289 for (const auto &Idx : SubRegIndices) { 1290 const SubRegRange &Range = Idx.Range.get(M); 1291 OS << " { " << Range.Offset << ", " << Range.Size << " },\t// " 1292 << Idx.getName() << "\n"; 1293 } 1294 } 1295 OS << "};\n\n"; 1296 1297 // Emit SubRegIndex lane masks, including 0. 1298 OS << "\nstatic const LaneBitmask SubRegIndexLaneMaskTable[] = {\n " 1299 "LaneBitmask::getAll(),\n"; 1300 for (const auto &Idx : SubRegIndices) { 1301 printMask(OS << " ", Idx.LaneMask); 1302 OS << ", // " << Idx.getName() << '\n'; 1303 } 1304 OS << " };\n\n"; 1305 1306 OS << "\n"; 1307 1308 // Now that all of the structs have been emitted, emit the instances. 1309 if (!RegisterClasses.empty()) { 1310 OS << "\nstatic const TargetRegisterInfo::RegClassInfo RegClassInfos[]" 1311 << " = {\n"; 1312 for (unsigned M = 0; M < NumModes; ++M) { 1313 unsigned EV = 0; 1314 OS << " // Mode = " << M << " ("; 1315 if (M == 0) 1316 OS << "Default"; 1317 else 1318 OS << CGH.getMode(M).Name; 1319 OS << ")\n"; 1320 for (const auto &RC : RegisterClasses) { 1321 assert(RC.EnumValue == EV && "Unexpected order of register classes"); 1322 ++EV; 1323 (void)EV; 1324 const RegSizeInfo &RI = RC.RSI.get(M); 1325 OS << " { " << RI.RegSize << ", " << RI.SpillSize << ", " 1326 << RI.SpillAlignment; 1327 std::vector<MVT::SimpleValueType> VTs; 1328 for (const ValueTypeByHwMode &VVT : RC.VTs) 1329 if (VVT.hasDefault() || VVT.hasMode(M)) 1330 VTs.push_back(VVT.get(M).SimpleTy); 1331 OS << ", /*VTLists+*/" << VTSeqs.get(VTs) << " }, // " 1332 << RC.getName() << '\n'; 1333 } 1334 } 1335 OS << "};\n"; 1336 1337 // Emit register class bit mask tables. The first bit mask emitted for a 1338 // register class, RC, is the set of sub-classes, including RC itself. 1339 // 1340 // If RC has super-registers, also create a list of subreg indices and bit 1341 // masks, (Idx, Mask). The bit mask has a bit for every superreg regclass, 1342 // SuperRC, that satisfies: 1343 // 1344 // For all SuperReg in SuperRC: SuperReg:Idx in RC 1345 // 1346 // The 0-terminated list of subreg indices starts at: 1347 // 1348 // RC->getSuperRegIndices() = SuperRegIdxSeqs + ... 1349 // 1350 // The corresponding bitmasks follow the sub-class mask in memory. Each 1351 // mask has RCMaskWords uint32_t entries. 1352 // 1353 // Every bit mask present in the list has at least one bit set. 1354 1355 // Compress the sub-reg index lists. 1356 typedef std::vector<const CodeGenSubRegIndex *> IdxList; 1357 SmallVector<IdxList, 8> SuperRegIdxLists(RegisterClasses.size()); 1358 SequenceToOffsetTable<IdxList, deref<std::less<>>> SuperRegIdxSeqs; 1359 BitVector MaskBV(RegisterClasses.size()); 1360 1361 for (const auto &RC : RegisterClasses) { 1362 OS << "static const uint32_t " << RC.getName() 1363 << "SubClassMask[] = {\n "; 1364 printBitVectorAsHex(OS, RC.getSubClasses(), 32); 1365 1366 // Emit super-reg class masks for any relevant SubRegIndices that can 1367 // project into RC. 1368 IdxList &SRIList = SuperRegIdxLists[RC.EnumValue]; 1369 for (auto &Idx : SubRegIndices) { 1370 MaskBV.reset(); 1371 RC.getSuperRegClasses(&Idx, MaskBV); 1372 if (MaskBV.none()) 1373 continue; 1374 SRIList.push_back(&Idx); 1375 OS << "\n "; 1376 printBitVectorAsHex(OS, MaskBV, 32); 1377 OS << "// " << Idx.getName(); 1378 } 1379 SuperRegIdxSeqs.add(SRIList); 1380 OS << "\n};\n\n"; 1381 } 1382 1383 OS << "static const uint16_t SuperRegIdxSeqs[] = {\n"; 1384 SuperRegIdxSeqs.layout(); 1385 SuperRegIdxSeqs.emit(OS, printSubRegIndex); 1386 OS << "};\n\n"; 1387 1388 // Emit super-class lists. 1389 for (const auto &RC : RegisterClasses) { 1390 ArrayRef<CodeGenRegisterClass *> Supers = RC.getSuperClasses(); 1391 1392 // Skip classes without supers. 1393 if (Supers.empty()) 1394 continue; 1395 1396 OS << "static unsigned const " << RC.getName() << "Superclasses[] = {\n"; 1397 for (const auto *Super : Supers) 1398 OS << " " << Super->getQualifiedIdName() << ",\n"; 1399 OS << "};\n\n"; 1400 } 1401 1402 // Emit methods. 1403 for (const auto &RC : RegisterClasses) { 1404 if (!RC.AltOrderSelect.empty()) { 1405 OS << "\nstatic inline unsigned " << RC.getName() 1406 << "AltOrderSelect(const MachineFunction &MF, bool Rev) {" 1407 << RC.AltOrderSelect << "}\n\n" 1408 << "static ArrayRef<MCPhysReg> " << RC.getName() 1409 << "GetRawAllocationOrder(const MachineFunction &MF, bool Rev) {\n"; 1410 for (unsigned oi = 1, oe = RC.getNumOrders(); oi != oe; ++oi) { 1411 ArrayRef<const Record *> Elems = RC.getOrder(oi); 1412 if (!Elems.empty()) { 1413 OS << " static const MCPhysReg AltOrder" << oi << "[] = {"; 1414 for (unsigned elem = 0; elem != Elems.size(); ++elem) 1415 OS << (elem ? ", " : " ") << getQualifiedName(Elems[elem]); 1416 OS << " };\n"; 1417 } 1418 } 1419 OS << " const MCRegisterClass &MCR = " << Target.getName() 1420 << "MCRegisterClasses[" << RC.getQualifiedName() + "RegClassID];\n" 1421 << " const ArrayRef<MCPhysReg> Order[] = {\n" 1422 << " ArrayRef(MCR.begin(), MCR.getNumRegs()"; 1423 for (unsigned oi = 1, oe = RC.getNumOrders(); oi != oe; ++oi) 1424 if (RC.getOrder(oi).empty()) 1425 OS << "),\n ArrayRef<MCPhysReg>("; 1426 else 1427 OS << "),\n ArrayRef(AltOrder" << oi; 1428 OS << ")\n };\n const unsigned Select = " << RC.getName() 1429 << "AltOrderSelect(MF, Rev);\n assert(Select < " 1430 << RC.getNumOrders() << ");\n return Order[Select];\n}\n"; 1431 } 1432 } 1433 1434 // Now emit the actual value-initialized register class instances. 1435 OS << "\nnamespace " << RegisterClasses.front().Namespace 1436 << " { // Register class instances\n"; 1437 1438 for (const auto &RC : RegisterClasses) { 1439 OS << " extern const TargetRegisterClass " << RC.getName() 1440 << "RegClass = {\n " << '&' << Target.getName() 1441 << "MCRegisterClasses[" << RC.getName() << "RegClassID],\n " 1442 << RC.getName() << "SubClassMask,\n SuperRegIdxSeqs + " 1443 << SuperRegIdxSeqs.get(SuperRegIdxLists[RC.EnumValue]) << ",\n "; 1444 printMask(OS, RC.LaneMask); 1445 OS << ",\n " << (unsigned)RC.AllocationPriority << ",\n " 1446 << (RC.GlobalPriority ? "true" : "false") << ",\n " 1447 << format("0x%02x", RC.TSFlags) << ", /* TSFlags */\n " 1448 << (RC.HasDisjunctSubRegs ? "true" : "false") 1449 << ", /* HasDisjunctSubRegs */\n " 1450 << (RC.CoveredBySubRegs ? "true" : "false") 1451 << ", /* CoveredBySubRegs */\n "; 1452 if (RC.getSuperClasses().empty()) 1453 OS << "nullptr, "; 1454 else 1455 OS << RC.getName() << "Superclasses, "; 1456 OS << RC.getSuperClasses().size() << ",\n "; 1457 if (RC.AltOrderSelect.empty()) 1458 OS << "nullptr\n"; 1459 else 1460 OS << RC.getName() << "GetRawAllocationOrder\n"; 1461 OS << " };\n\n"; 1462 } 1463 1464 OS << "} // end namespace " << RegisterClasses.front().Namespace << "\n"; 1465 } 1466 1467 OS << "\nnamespace {\n"; 1468 OS << " const TargetRegisterClass *const RegisterClasses[] = {\n"; 1469 for (const auto &RC : RegisterClasses) 1470 OS << " &" << RC.getQualifiedName() << "RegClass,\n"; 1471 OS << " };\n"; 1472 OS << "} // end anonymous namespace\n"; 1473 1474 // Emit extra information about registers. 1475 const std::string &TargetName = Target.getName().str(); 1476 const auto &Regs = RegBank.getRegisters(); 1477 unsigned NumRegCosts = 1; 1478 for (const auto &Reg : Regs) 1479 NumRegCosts = std::max((size_t)NumRegCosts, Reg.CostPerUse.size()); 1480 1481 std::vector<unsigned> AllRegCostPerUse; 1482 llvm::BitVector InAllocClass(Regs.size() + 1, false); 1483 AllRegCostPerUse.insert(AllRegCostPerUse.end(), NumRegCosts, 0); 1484 1485 // Populate the vector RegCosts with the CostPerUse list of the registers 1486 // in the order they are read. Have at most NumRegCosts entries for 1487 // each register. Fill with zero for values which are not explicitly given. 1488 for (const auto &Reg : Regs) { 1489 auto Costs = Reg.CostPerUse; 1490 llvm::append_range(AllRegCostPerUse, Costs); 1491 if (NumRegCosts > Costs.size()) 1492 AllRegCostPerUse.insert(AllRegCostPerUse.end(), 1493 NumRegCosts - Costs.size(), 0); 1494 1495 if (AllocatableRegs.count(Reg.TheDef)) 1496 InAllocClass.set(Reg.EnumValue); 1497 } 1498 1499 // Emit the cost values as a 1D-array after grouping them by their indices, 1500 // i.e. the costs for all registers corresponds to index 0, 1, 2, etc. 1501 // Size of the emitted array should be NumRegCosts * (Regs.size() + 1). 1502 OS << "\nstatic const uint8_t " 1503 << "CostPerUseTable[] = { \n"; 1504 for (unsigned int I = 0; I < NumRegCosts; ++I) { 1505 for (unsigned J = I, E = AllRegCostPerUse.size(); J < E; J += NumRegCosts) 1506 OS << AllRegCostPerUse[J] << ", "; 1507 } 1508 OS << "};\n\n"; 1509 1510 OS << "\nstatic const bool " 1511 << "InAllocatableClassTable[] = { \n"; 1512 for (unsigned I = 0, E = InAllocClass.size(); I < E; ++I) { 1513 OS << (InAllocClass[I] ? "true" : "false") << ", "; 1514 } 1515 OS << "};\n\n"; 1516 1517 OS << "\nstatic const TargetRegisterInfoDesc " << TargetName 1518 << "RegInfoDesc = { // Extra Descriptors\n"; 1519 OS << "CostPerUseTable, " << NumRegCosts << ", " 1520 << "InAllocatableClassTable"; 1521 OS << "};\n\n"; // End of register descriptors... 1522 1523 std::string ClassName = Target.getName().str() + "GenRegisterInfo"; 1524 1525 auto SubRegIndicesSize = 1526 std::distance(SubRegIndices.begin(), SubRegIndices.end()); 1527 1528 if (!SubRegIndices.empty()) { 1529 emitComposeSubRegIndices(OS, ClassName); 1530 emitComposeSubRegIndexLaneMask(OS, ClassName); 1531 } 1532 1533 if (!SubRegIndices.empty()) { 1534 // Emit getSubClassWithSubReg. 1535 OS << "const TargetRegisterClass *" << ClassName 1536 << "::getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx)" 1537 << " const {\n"; 1538 // Use the smallest type that can hold a regclass ID with room for a 1539 // sentinel. 1540 if (RegisterClasses.size() <= UINT8_MAX) 1541 OS << " static const uint8_t Table["; 1542 else if (RegisterClasses.size() <= UINT16_MAX) 1543 OS << " static const uint16_t Table["; 1544 else 1545 PrintFatalError("Too many register classes."); 1546 OS << RegisterClasses.size() << "][" << SubRegIndicesSize << "] = {\n"; 1547 for (const auto &RC : RegisterClasses) { 1548 OS << " {\t// " << RC.getName() << "\n"; 1549 for (auto &Idx : SubRegIndices) { 1550 if (CodeGenRegisterClass *SRC = RC.getSubClassWithSubReg(&Idx)) 1551 OS << " " << SRC->EnumValue + 1 << ",\t// " << Idx.getName() 1552 << " -> " << SRC->getName() << "\n"; 1553 else 1554 OS << " 0,\t// " << Idx.getName() << "\n"; 1555 } 1556 OS << " },\n"; 1557 } 1558 OS << " };\n assert(RC && \"Missing regclass\");\n" 1559 << " if (!Idx) return RC;\n --Idx;\n" 1560 << " assert(Idx < " << SubRegIndicesSize << " && \"Bad subreg\");\n" 1561 << " unsigned TV = Table[RC->getID()][Idx];\n" 1562 << " return TV ? getRegClass(TV - 1) : nullptr;\n}\n\n"; 1563 1564 // Emit getSubRegisterClass 1565 OS << "const TargetRegisterClass *" << ClassName 1566 << "::getSubRegisterClass(const TargetRegisterClass *RC, unsigned Idx)" 1567 << " const {\n"; 1568 1569 // Use the smallest type that can hold a regclass ID with room for a 1570 // sentinel. 1571 if (RegisterClasses.size() <= UINT8_MAX) 1572 OS << " static const uint8_t Table["; 1573 else if (RegisterClasses.size() <= UINT16_MAX) 1574 OS << " static const uint16_t Table["; 1575 else 1576 PrintFatalError("Too many register classes."); 1577 1578 OS << RegisterClasses.size() << "][" << SubRegIndicesSize << "] = {\n"; 1579 1580 for (const auto &RC : RegisterClasses) { 1581 OS << " {\t// " << RC.getName() << '\n'; 1582 for (auto &Idx : SubRegIndices) { 1583 std::optional<std::pair<CodeGenRegisterClass *, CodeGenRegisterClass *>> 1584 MatchingSubClass = RC.getMatchingSubClassWithSubRegs(RegBank, &Idx); 1585 1586 unsigned EnumValue = 0; 1587 if (MatchingSubClass) { 1588 CodeGenRegisterClass *SubRegClass = MatchingSubClass->second; 1589 EnumValue = SubRegClass->EnumValue + 1; 1590 } 1591 1592 OS << " " << EnumValue << ",\t// " << RC.getName() << ':' 1593 << Idx.getName(); 1594 1595 if (MatchingSubClass) { 1596 CodeGenRegisterClass *SubRegClass = MatchingSubClass->second; 1597 OS << " -> " << SubRegClass->getName(); 1598 } 1599 1600 OS << '\n'; 1601 } 1602 1603 OS << " },\n"; 1604 } 1605 OS << " };\n assert(RC && \"Missing regclass\");\n" 1606 << " if (!Idx) return RC;\n --Idx;\n" 1607 << " assert(Idx < " << SubRegIndicesSize << " && \"Bad subreg\");\n" 1608 << " unsigned TV = Table[RC->getID()][Idx];\n" 1609 << " return TV ? getRegClass(TV - 1) : nullptr;\n}\n\n"; 1610 } 1611 1612 EmitRegUnitPressure(OS, ClassName); 1613 1614 // Emit register base class mapper 1615 if (!RegisterClasses.empty()) { 1616 // Collect base classes 1617 SmallVector<const CodeGenRegisterClass *> BaseClasses; 1618 for (const auto &RC : RegisterClasses) { 1619 if (RC.getBaseClassOrder()) 1620 BaseClasses.push_back(&RC); 1621 } 1622 if (!BaseClasses.empty()) { 1623 assert(BaseClasses.size() < UINT16_MAX && 1624 "Too many base register classes"); 1625 1626 // Apply order 1627 struct BaseClassOrdering { 1628 bool operator()(const CodeGenRegisterClass *LHS, 1629 const CodeGenRegisterClass *RHS) const { 1630 return std::pair(*LHS->getBaseClassOrder(), LHS->EnumValue) < 1631 std::pair(*RHS->getBaseClassOrder(), RHS->EnumValue); 1632 } 1633 }; 1634 llvm::stable_sort(BaseClasses, BaseClassOrdering()); 1635 1636 OS << "\n// Register to base register class mapping\n\n"; 1637 OS << "\n"; 1638 OS << "const TargetRegisterClass *" << ClassName 1639 << "::getPhysRegBaseClass(MCRegister Reg)" 1640 << " const {\n"; 1641 OS << " static const uint16_t InvalidRegClassID = UINT16_MAX;\n\n"; 1642 OS << " static const uint16_t Mapping[" << Regs.size() + 1 << "] = {\n"; 1643 OS << " InvalidRegClassID, // NoRegister\n"; 1644 for (const CodeGenRegister &Reg : Regs) { 1645 const CodeGenRegisterClass *BaseRC = nullptr; 1646 for (const CodeGenRegisterClass *RC : BaseClasses) { 1647 if (is_contained(RC->getMembers(), &Reg)) { 1648 BaseRC = RC; 1649 break; 1650 } 1651 } 1652 1653 OS << " " 1654 << (BaseRC ? BaseRC->getQualifiedIdName() : "InvalidRegClassID") 1655 << ", // " << Reg.getName() << "\n"; 1656 } 1657 OS << " };\n\n" 1658 " assert(Reg < ArrayRef(Mapping).size());\n" 1659 " unsigned RCID = Mapping[Reg.id()];\n" 1660 " if (RCID == InvalidRegClassID)\n" 1661 " return nullptr;\n" 1662 " return RegisterClasses[RCID];\n" 1663 "}\n"; 1664 } 1665 } 1666 1667 // Emit the constructor of the class... 1668 OS << "extern const MCRegisterDesc " << TargetName << "RegDesc[];\n"; 1669 OS << "extern const int16_t " << TargetName << "RegDiffLists[];\n"; 1670 OS << "extern const LaneBitmask " << TargetName << "LaneMaskLists[];\n"; 1671 OS << "extern const char " << TargetName << "RegStrings[];\n"; 1672 OS << "extern const char " << TargetName << "RegClassStrings[];\n"; 1673 OS << "extern const MCPhysReg " << TargetName << "RegUnitRoots[][2];\n"; 1674 OS << "extern const uint16_t " << TargetName << "SubRegIdxLists[];\n"; 1675 OS << "extern const uint16_t " << TargetName << "RegEncodingTable[];\n"; 1676 1677 EmitRegMappingTables(OS, Regs, true); 1678 1679 OS << ClassName << "::\n" 1680 << ClassName 1681 << "(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour,\n" 1682 " unsigned PC, unsigned HwMode)\n" 1683 << " : TargetRegisterInfo(&" << TargetName << "RegInfoDesc" 1684 << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() << ",\n" 1685 << " SubRegIndexNameTable, SubRegIdxRangeTable, " 1686 "SubRegIndexLaneMaskTable,\n" 1687 << " "; 1688 printMask(OS, RegBank.CoveringLanes); 1689 OS << ", RegClassInfos, VTLists, HwMode) {\n" 1690 << " InitMCRegisterInfo(" << TargetName << "RegDesc, " << Regs.size() + 1 1691 << ", RA, PC,\n " << TargetName 1692 << "MCRegisterClasses, " << RegisterClasses.size() << ",\n" 1693 << " " << TargetName << "RegUnitRoots,\n" 1694 << " " << RegBank.getNumNativeRegUnits() << ",\n" 1695 << " " << TargetName << "RegDiffLists,\n" 1696 << " " << TargetName << "LaneMaskLists,\n" 1697 << " " << TargetName << "RegStrings,\n" 1698 << " " << TargetName << "RegClassStrings,\n" 1699 << " " << TargetName << "SubRegIdxLists,\n" 1700 << " " << SubRegIndicesSize + 1 << ",\n" 1701 << " " << TargetName << "RegEncodingTable);\n\n"; 1702 1703 EmitRegMapping(OS, Regs, true); 1704 1705 OS << "}\n\n"; 1706 1707 // Emit CalleeSavedRegs information. 1708 ArrayRef<const Record *> CSRSets = 1709 Records.getAllDerivedDefinitions("CalleeSavedRegs"); 1710 for (const Record *CSRSet : CSRSets) { 1711 const SetTheory::RecVec *Regs = RegBank.getSets().expand(CSRSet); 1712 assert(Regs && "Cannot expand CalleeSavedRegs instance"); 1713 1714 // Emit the *_SaveList list of callee-saved registers. 1715 OS << "static const MCPhysReg " << CSRSet->getName() << "_SaveList[] = { "; 1716 for (const Record *Reg : *Regs) 1717 OS << getQualifiedName(Reg) << ", "; 1718 OS << "0 };\n"; 1719 1720 // Emit the *_RegMask bit mask of call-preserved registers. 1721 BitVector Covered = RegBank.computeCoveredRegisters(*Regs); 1722 1723 // Check for an optional OtherPreserved set. 1724 // Add those registers to RegMask, but not to SaveList. 1725 if (const DagInit *OPDag = 1726 dyn_cast<DagInit>(CSRSet->getValueInit("OtherPreserved"))) { 1727 SetTheory::RecSet OPSet; 1728 RegBank.getSets().evaluate(OPDag, OPSet, CSRSet->getLoc()); 1729 Covered |= RegBank.computeCoveredRegisters(OPSet.getArrayRef()); 1730 } 1731 1732 // Add all constant physical registers to the preserved mask: 1733 SetTheory::RecSet ConstantSet; 1734 for (const auto &Reg : RegBank.getRegisters()) { 1735 if (Reg.Constant) 1736 ConstantSet.insert(Reg.TheDef); 1737 } 1738 Covered |= RegBank.computeCoveredRegisters(ConstantSet.getArrayRef()); 1739 1740 OS << "static const uint32_t " << CSRSet->getName() << "_RegMask[] = { "; 1741 printBitVectorAsHex(OS, Covered, 32); 1742 OS << "};\n"; 1743 } 1744 OS << "\n\n"; 1745 1746 OS << "ArrayRef<const uint32_t *> " << ClassName 1747 << "::getRegMasks() const {\n"; 1748 if (!CSRSets.empty()) { 1749 OS << " static const uint32_t *const Masks[] = {\n"; 1750 for (const Record *CSRSet : CSRSets) 1751 OS << " " << CSRSet->getName() << "_RegMask,\n"; 1752 OS << " };\n"; 1753 OS << " return ArrayRef(Masks);\n"; 1754 } else { 1755 OS << " return {};\n"; 1756 } 1757 OS << "}\n\n"; 1758 1759 const std::list<CodeGenRegisterCategory> &RegCategories = 1760 RegBank.getRegCategories(); 1761 OS << "bool " << ClassName << "::\n" 1762 << "isGeneralPurposeRegister(const MachineFunction &MF, " 1763 << "MCRegister PhysReg) const {\n" 1764 << " return\n"; 1765 for (const CodeGenRegisterCategory &Category : RegCategories) 1766 if (Category.getName() == "GeneralPurposeRegisters") { 1767 for (const CodeGenRegisterClass *RC : Category.getClasses()) 1768 OS << " " << RC->getQualifiedName() 1769 << "RegClass.contains(PhysReg) ||\n"; 1770 break; 1771 } 1772 OS << " false;\n"; 1773 OS << "}\n\n"; 1774 1775 OS << "bool " << ClassName << "::\n" 1776 << "isGeneralPurposeRegisterClass(const TargetRegisterClass *RC)" 1777 << " const {\n" 1778 << " return\n"; 1779 for (const CodeGenRegisterCategory &Category : RegCategories) 1780 if (Category.getName() == "GeneralPurposeRegisters") { 1781 for (const CodeGenRegisterClass *RC : Category.getClasses()) 1782 OS << " " << RC->getQualifiedName() 1783 << "RegClass.hasSubClassEq(RC) ||\n"; 1784 break; 1785 } 1786 OS << " false;\n"; 1787 OS << "}\n\n"; 1788 1789 OS << "bool " << ClassName << "::\n" 1790 << "isFixedRegister(const MachineFunction &MF, " 1791 << "MCRegister PhysReg) const {\n" 1792 << " return\n"; 1793 for (const CodeGenRegisterCategory &Category : RegCategories) 1794 if (Category.getName() == "FixedRegisters") { 1795 for (const CodeGenRegisterClass *RC : Category.getClasses()) 1796 OS << " " << RC->getQualifiedName() 1797 << "RegClass.contains(PhysReg) ||\n"; 1798 break; 1799 } 1800 OS << " false;\n"; 1801 OS << "}\n\n"; 1802 1803 OS << "bool " << ClassName << "::\n" 1804 << "isArgumentRegister(const MachineFunction &MF, " 1805 << "MCRegister PhysReg) const {\n" 1806 << " return\n"; 1807 for (const CodeGenRegisterCategory &Category : RegCategories) 1808 if (Category.getName() == "ArgumentRegisters") { 1809 for (const CodeGenRegisterClass *RC : Category.getClasses()) 1810 OS << " " << RC->getQualifiedName() 1811 << "RegClass.contains(PhysReg) ||\n"; 1812 break; 1813 } 1814 OS << " false;\n"; 1815 OS << "}\n\n"; 1816 1817 OS << "bool " << ClassName << "::\n" 1818 << "isConstantPhysReg(MCRegister PhysReg) const {\n" 1819 << " return\n"; 1820 for (const auto &Reg : Regs) 1821 if (Reg.Constant) 1822 OS << " PhysReg == " << getQualifiedName(Reg.TheDef) << " ||\n"; 1823 OS << " false;\n"; 1824 OS << "}\n\n"; 1825 1826 OS << "ArrayRef<const char *> " << ClassName 1827 << "::getRegMaskNames() const {\n"; 1828 if (!CSRSets.empty()) { 1829 OS << " static const char *Names[] = {\n"; 1830 for (const Record *CSRSet : CSRSets) 1831 OS << " " << '"' << CSRSet->getName() << '"' << ",\n"; 1832 OS << " };\n"; 1833 OS << " return ArrayRef(Names);\n"; 1834 } else { 1835 OS << " return {};\n"; 1836 } 1837 OS << "}\n\n"; 1838 1839 OS << "const " << TargetName << "FrameLowering *\n" 1840 << TargetName 1841 << "GenRegisterInfo::getFrameLowering(const MachineFunction &MF) {\n" 1842 << " return static_cast<const " << TargetName << "FrameLowering *>(\n" 1843 << " MF.getSubtarget().getFrameLowering());\n" 1844 << "}\n\n"; 1845 1846 OS << "} // end namespace llvm\n\n"; 1847 OS << "#endif // GET_REGINFO_TARGET_DESC\n\n"; 1848 } 1849 1850 void RegisterInfoEmitter::run(raw_ostream &OS) { 1851 TGTimer &Timer = Records.getTimer(); 1852 Timer.startTimer("Print enums"); 1853 runEnums(OS); 1854 1855 Timer.startTimer("Print MC registers"); 1856 runMCDesc(OS); 1857 1858 Timer.startTimer("Print header fragment"); 1859 runTargetHeader(OS); 1860 1861 Timer.startTimer("Print target registers"); 1862 runTargetDesc(OS); 1863 1864 if (RegisterInfoDebug) 1865 debugDump(errs()); 1866 } 1867 1868 void RegisterInfoEmitter::debugDump(raw_ostream &OS) { 1869 const CodeGenHwModes &CGH = Target.getHwModes(); 1870 unsigned NumModes = CGH.getNumModeIds(); 1871 auto getModeName = [CGH](unsigned M) -> StringRef { 1872 if (M == 0) 1873 return "Default"; 1874 return CGH.getMode(M).Name; 1875 }; 1876 1877 for (const CodeGenRegisterClass &RC : RegBank.getRegClasses()) { 1878 OS << "RegisterClass " << RC.getName() << ":\n"; 1879 OS << "\tSpillSize: {"; 1880 for (unsigned M = 0; M != NumModes; ++M) 1881 OS << ' ' << getModeName(M) << ':' << RC.RSI.get(M).SpillSize; 1882 OS << " }\n\tSpillAlignment: {"; 1883 for (unsigned M = 0; M != NumModes; ++M) 1884 OS << ' ' << getModeName(M) << ':' << RC.RSI.get(M).SpillAlignment; 1885 OS << " }\n\tNumRegs: " << RC.getMembers().size() << '\n'; 1886 OS << "\tLaneMask: " << PrintLaneMask(RC.LaneMask) << '\n'; 1887 OS << "\tHasDisjunctSubRegs: " << RC.HasDisjunctSubRegs << '\n'; 1888 OS << "\tCoveredBySubRegs: " << RC.CoveredBySubRegs << '\n'; 1889 OS << "\tAllocatable: " << RC.Allocatable << '\n'; 1890 OS << "\tAllocationPriority: " << unsigned(RC.AllocationPriority) << '\n'; 1891 OS << "\tBaseClassOrder: " << RC.getBaseClassOrder() << '\n'; 1892 OS << "\tRegs:"; 1893 for (const CodeGenRegister *R : RC.getMembers()) { 1894 OS << " " << R->getName(); 1895 } 1896 OS << '\n'; 1897 OS << "\tSubClasses:"; 1898 const BitVector &SubClasses = RC.getSubClasses(); 1899 for (const CodeGenRegisterClass &SRC : RegBank.getRegClasses()) { 1900 if (!SubClasses.test(SRC.EnumValue)) 1901 continue; 1902 OS << " " << SRC.getName(); 1903 } 1904 OS << '\n'; 1905 OS << "\tSuperClasses:"; 1906 for (const CodeGenRegisterClass *SRC : RC.getSuperClasses()) { 1907 OS << " " << SRC->getName(); 1908 } 1909 OS << '\n'; 1910 } 1911 1912 for (const CodeGenSubRegIndex &SRI : RegBank.getSubRegIndices()) { 1913 OS << "SubRegIndex " << SRI.getName() << ":\n"; 1914 OS << "\tLaneMask: " << PrintLaneMask(SRI.LaneMask) << '\n'; 1915 OS << "\tAllSuperRegsCovered: " << SRI.AllSuperRegsCovered << '\n'; 1916 OS << "\tOffset: {"; 1917 for (unsigned M = 0; M != NumModes; ++M) 1918 OS << ' ' << getModeName(M) << ':' << SRI.Range.get(M).Offset; 1919 OS << " }\n\tSize: {"; 1920 for (unsigned M = 0; M != NumModes; ++M) 1921 OS << ' ' << getModeName(M) << ':' << SRI.Range.get(M).Size; 1922 OS << " }\n"; 1923 } 1924 1925 for (const CodeGenRegister &R : RegBank.getRegisters()) { 1926 OS << "Register " << R.getName() << ":\n"; 1927 OS << "\tCostPerUse: "; 1928 for (const auto &Cost : R.CostPerUse) 1929 OS << Cost << " "; 1930 OS << '\n'; 1931 OS << "\tCoveredBySubregs: " << R.CoveredBySubRegs << '\n'; 1932 OS << "\tHasDisjunctSubRegs: " << R.HasDisjunctSubRegs << '\n'; 1933 for (auto &[SubIdx, SubReg] : R.getSubRegs()) { 1934 OS << "\tSubReg " << SubIdx->getName() << " = " << SubReg->getName() 1935 << '\n'; 1936 } 1937 for (unsigned U : R.getNativeRegUnits()) 1938 OS << "\tRegUnit " << U << '\n'; 1939 } 1940 } 1941 1942 static TableGen::Emitter::OptClass<RegisterInfoEmitter> 1943 X("gen-register-info", "Generate registers and register classes info"); 1944