1 //===- DisassemblerEmitter.cpp - Generate a disassembler ------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "CodeGenTarget.h" 10 #include "WebAssemblyDisassemblerEmitter.h" 11 #include "X86DisassemblerTables.h" 12 #include "X86RecognizableInstr.h" 13 #include "llvm/TableGen/Error.h" 14 #include "llvm/TableGen/Record.h" 15 #include "llvm/TableGen/TableGenBackend.h" 16 17 using namespace llvm; 18 using namespace llvm::X86Disassembler; 19 20 /// DisassemblerEmitter - Contains disassembler table emitters for various 21 /// architectures. 22 23 /// X86 Disassembler Emitter 24 /// 25 /// *** IF YOU'RE HERE TO RESOLVE A "Primary decode conflict", LOOK DOWN NEAR 26 /// THE END OF THIS COMMENT! 27 /// 28 /// The X86 disassembler emitter is part of the X86 Disassembler, which is 29 /// documented in lib/Target/X86/X86Disassembler.h. 30 /// 31 /// The emitter produces the tables that the disassembler uses to translate 32 /// instructions. The emitter generates the following tables: 33 /// 34 /// - One table (CONTEXTS_SYM) that contains a mapping of attribute masks to 35 /// instruction contexts. Although for each attribute there are cases where 36 /// that attribute determines decoding, in the majority of cases decoding is 37 /// the same whether or not an attribute is present. For example, a 64-bit 38 /// instruction with an OPSIZE prefix and an XS prefix decodes the same way in 39 /// all cases as a 64-bit instruction with only OPSIZE set. (The XS prefix 40 /// may have effects on its execution, but does not change the instruction 41 /// returned.) This allows considerable space savings in other tables. 42 /// - Six tables (ONEBYTE_SYM, TWOBYTE_SYM, THREEBYTE38_SYM, THREEBYTE3A_SYM, 43 /// THREEBYTEA6_SYM, and THREEBYTEA7_SYM contain the hierarchy that the 44 /// decoder traverses while decoding an instruction. At the lowest level of 45 /// this hierarchy are instruction UIDs, 16-bit integers that can be used to 46 /// uniquely identify the instruction and correspond exactly to its position 47 /// in the list of CodeGenInstructions for the target. 48 /// - One table (INSTRUCTIONS_SYM) contains information about the operands of 49 /// each instruction and how to decode them. 50 /// 51 /// During table generation, there may be conflicts between instructions that 52 /// occupy the same space in the decode tables. These conflicts are resolved as 53 /// follows in setTableFields() (X86DisassemblerTables.cpp) 54 /// 55 /// - If the current context is the native context for one of the instructions 56 /// (that is, the attributes specified for it in the LLVM tables specify 57 /// precisely the current context), then it has priority. 58 /// - If the current context isn't native for either of the instructions, then 59 /// the higher-priority context wins (that is, the one that is more specific). 60 /// That hierarchy is determined by outranks() (X86DisassemblerTables.cpp) 61 /// - If the current context is native for both instructions, then the table 62 /// emitter reports a conflict and dies. 63 /// 64 /// *** RESOLUTION FOR "Primary decode conflict"S 65 /// 66 /// If two instructions collide, typically the solution is (in order of 67 /// likelihood): 68 /// 69 /// (1) to filter out one of the instructions by editing filter() 70 /// (X86RecognizableInstr.cpp). This is the most common resolution, but 71 /// check the Intel manuals first to make sure that (2) and (3) are not the 72 /// problem. 73 /// (2) to fix the tables (X86.td and its subsidiaries) so the opcodes are 74 /// accurate. Sometimes they are not. 75 /// (3) to fix the tables to reflect the actual context (for example, required 76 /// prefixes), and possibly to add a new context by editing 77 /// include/llvm/Support/X86DisassemblerDecoderCommon.h. This is unlikely 78 /// to be the cause. 79 /// 80 /// DisassemblerEmitter.cpp contains the implementation for the emitter, 81 /// which simply pulls out instructions from the CodeGenTarget and pushes them 82 /// into X86DisassemblerTables. 83 /// X86DisassemblerTables.h contains the interface for the instruction tables, 84 /// which manage and emit the structures discussed above. 85 /// X86DisassemblerTables.cpp contains the implementation for the instruction 86 /// tables. 87 /// X86ModRMFilters.h contains filters that can be used to determine which 88 /// ModR/M values are valid for a particular instruction. These are used to 89 /// populate ModRMDecisions. 90 /// X86RecognizableInstr.h contains the interface for a single instruction, 91 /// which knows how to translate itself from a CodeGenInstruction and provide 92 /// the information necessary for integration into the tables. 93 /// X86RecognizableInstr.cpp contains the implementation for a single 94 /// instruction. 95 96 namespace llvm { 97 98 extern void EmitFixedLenDecoder(RecordKeeper &RK, raw_ostream &OS, 99 const std::string &PredicateNamespace, 100 const std::string &GPrefix, 101 const std::string &GPostfix, 102 const std::string &ROK, 103 const std::string &RFail, const std::string &L); 104 105 void EmitDisassembler(RecordKeeper &Records, raw_ostream &OS) { 106 CodeGenTarget Target(Records); 107 emitSourceFileHeader(" * " + Target.getName().str() + " Disassembler", OS); 108 109 // X86 uses a custom disassembler. 110 if (Target.getName() == "X86") { 111 DisassemblerTables Tables; 112 113 ArrayRef<const CodeGenInstruction*> numberedInstructions = 114 Target.getInstructionsByEnumValue(); 115 116 for (unsigned i = 0, e = numberedInstructions.size(); i != e; ++i) 117 RecognizableInstr::processInstr(Tables, *numberedInstructions[i], i); 118 119 if (Tables.hasConflicts()) { 120 PrintError(Target.getTargetRecord()->getLoc(), "Primary decode conflict"); 121 return; 122 } 123 124 Tables.emit(OS); 125 return; 126 } 127 128 // WebAssembly has variable length opcodes, so can't use EmitFixedLenDecoder 129 // below (which depends on a Size table-gen Record), and also uses a custom 130 // disassembler. 131 if (Target.getName() == "WebAssembly") { 132 emitWebAssemblyDisassemblerTables(OS, Target.getInstructionsByEnumValue()); 133 return; 134 } 135 136 // ARM and Thumb have a CHECK() macro to deal with DecodeStatuses. 137 if (Target.getName() == "ARM" || Target.getName() == "Thumb" || 138 Target.getName() == "AArch64" || Target.getName() == "ARM64") { 139 std::string PredicateNamespace = Target.getName(); 140 if (PredicateNamespace == "Thumb") 141 PredicateNamespace = "ARM"; 142 143 EmitFixedLenDecoder(Records, OS, PredicateNamespace, 144 "if (!Check(S, ", "))", 145 "S", "MCDisassembler::Fail", 146 " MCDisassembler::DecodeStatus S = " 147 "MCDisassembler::Success;\n(void)S;"); 148 return; 149 } 150 151 EmitFixedLenDecoder(Records, OS, Target.getName(), 152 "if (", " == MCDisassembler::Fail)", 153 "MCDisassembler::Success", "MCDisassembler::Fail", ""); 154 } 155 156 } // end namespace llvm 157