1 //===- CodeGenTarget.h - Target Class Wrapper -------------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file defines wrappers for the Target class and related global 10 // functionality. This makes it easier to access the data and provides a single 11 // place that needs to check it for validity. All of these classes abort 12 // on error conditions. 13 // 14 //===----------------------------------------------------------------------===// 15 16 #ifndef LLVM_UTILS_TABLEGEN_CODEGENTARGET_H 17 #define LLVM_UTILS_TABLEGEN_CODEGENTARGET_H 18 19 #include "Basic/SDNodeProperties.h" 20 #include "CodeGenHwModes.h" 21 #include "CodeGenInstruction.h" 22 #include "InfoByHwMode.h" 23 #include "llvm/ADT/ArrayRef.h" 24 #include "llvm/ADT/DenseMap.h" 25 #include "llvm/ADT/SmallVector.h" 26 #include "llvm/ADT/StringRef.h" 27 #include "llvm/CodeGenTypes/MachineValueType.h" 28 #include <cassert> 29 #include <memory> 30 #include <optional> 31 #include <string> 32 #include <vector> 33 34 namespace llvm { 35 36 class RecordKeeper; 37 class Record; 38 class CodeGenRegBank; 39 class CodeGenRegister; 40 class CodeGenRegisterClass; 41 class CodeGenSchedModels; 42 class CodeGenSubRegIndex; 43 44 /// getValueType - Return the MVT::SimpleValueType that the specified TableGen 45 /// record corresponds to. 46 MVT::SimpleValueType getValueType(const Record *Rec); 47 48 StringRef getName(MVT::SimpleValueType T); 49 StringRef getEnumName(MVT::SimpleValueType T); 50 51 /// getQualifiedName - Return the name of the specified record, with a 52 /// namespace qualifier if the record contains one. 53 std::string getQualifiedName(const Record *R); 54 55 /// CodeGenTarget - This class corresponds to the Target class in the .td files. 56 /// 57 class CodeGenTarget { 58 RecordKeeper &Records; 59 Record *TargetRec; 60 61 mutable DenseMap<const Record *, std::unique_ptr<CodeGenInstruction>> 62 Instructions; 63 mutable std::unique_ptr<CodeGenRegBank> RegBank; 64 mutable std::vector<Record *> RegAltNameIndices; 65 mutable SmallVector<ValueTypeByHwMode, 8> LegalValueTypes; 66 CodeGenHwModes CGH; 67 std::vector<Record *> MacroFusions; 68 mutable bool HasVariableLengthEncodings = false; 69 70 void ReadRegAltNameIndices() const; 71 void ReadInstructions() const; 72 void ReadLegalValueTypes() const; 73 74 mutable std::unique_ptr<CodeGenSchedModels> SchedModels; 75 76 mutable StringRef InstNamespace; 77 mutable std::vector<const CodeGenInstruction *> InstrsByEnum; 78 mutable unsigned NumPseudoInstructions = 0; 79 80 public: 81 CodeGenTarget(RecordKeeper &Records); 82 ~CodeGenTarget(); 83 84 Record *getTargetRecord() const { return TargetRec; } 85 StringRef getName() const; 86 87 /// getInstNamespace - Return the target-specific instruction namespace. 88 /// 89 StringRef getInstNamespace() const; 90 91 /// getRegNamespace - Return the target-specific register namespace. 92 StringRef getRegNamespace() const; 93 94 /// getInstructionSet - Return the InstructionSet object. 95 /// 96 Record *getInstructionSet() const; 97 98 /// getAllowRegisterRenaming - Return the AllowRegisterRenaming flag value for 99 /// this target. 100 /// 101 bool getAllowRegisterRenaming() const; 102 103 /// getAsmParser - Return the AssemblyParser definition for this target. 104 /// 105 Record *getAsmParser() const; 106 107 /// getAsmParserVariant - Return the AssemblyParserVariant definition for 108 /// this target. 109 /// 110 Record *getAsmParserVariant(unsigned i) const; 111 112 /// getAsmParserVariantCount - Return the AssemblyParserVariant definition 113 /// available for this target. 114 /// 115 unsigned getAsmParserVariantCount() const; 116 117 /// getAsmWriter - Return the AssemblyWriter definition for this target. 118 /// 119 Record *getAsmWriter() const; 120 121 /// getRegBank - Return the register bank description. 122 CodeGenRegBank &getRegBank() const; 123 124 /// Return the largest register class on \p RegBank which supports \p Ty and 125 /// covers \p SubIdx if it exists. 126 std::optional<CodeGenRegisterClass *> 127 getSuperRegForSubReg(const ValueTypeByHwMode &Ty, CodeGenRegBank &RegBank, 128 const CodeGenSubRegIndex *SubIdx, 129 bool MustBeAllocatable = false) const; 130 131 /// getRegisterByName - If there is a register with the specific AsmName, 132 /// return it. 133 const CodeGenRegister *getRegisterByName(StringRef Name) const; 134 135 const std::vector<Record *> &getRegAltNameIndices() const { 136 if (RegAltNameIndices.empty()) 137 ReadRegAltNameIndices(); 138 return RegAltNameIndices; 139 } 140 141 const CodeGenRegisterClass &getRegisterClass(Record *R) const; 142 143 /// getRegisterVTs - Find the union of all possible SimpleValueTypes for the 144 /// specified physical register. 145 std::vector<ValueTypeByHwMode> getRegisterVTs(Record *R) const; 146 147 ArrayRef<ValueTypeByHwMode> getLegalValueTypes() const { 148 if (LegalValueTypes.empty()) 149 ReadLegalValueTypes(); 150 return LegalValueTypes; 151 } 152 153 CodeGenSchedModels &getSchedModels() const; 154 155 const CodeGenHwModes &getHwModes() const { return CGH; } 156 157 bool hasMacroFusion() const { return !MacroFusions.empty(); } 158 159 const std::vector<Record *> getMacroFusions() const { return MacroFusions; } 160 161 private: 162 DenseMap<const Record *, std::unique_ptr<CodeGenInstruction>> & 163 getInstructions() const { 164 if (Instructions.empty()) 165 ReadInstructions(); 166 return Instructions; 167 } 168 169 public: 170 CodeGenInstruction &getInstruction(const Record *InstRec) const { 171 if (Instructions.empty()) 172 ReadInstructions(); 173 auto I = Instructions.find(InstRec); 174 assert(I != Instructions.end() && "Not an instruction"); 175 return *I->second; 176 } 177 178 /// Returns the number of predefined instructions. 179 static unsigned getNumFixedInstructions(); 180 181 /// Returns the number of pseudo instructions. 182 unsigned getNumPseudoInstructions() const { 183 if (InstrsByEnum.empty()) 184 ComputeInstrsByEnum(); 185 return NumPseudoInstructions; 186 } 187 188 /// Return all of the instructions defined by the target, ordered by their 189 /// enum value. 190 /// The following order of instructions is also guaranteed: 191 /// - fixed / generic instructions as declared in TargetOpcodes.def, in order; 192 /// - pseudo instructions in lexicographical order sorted by name; 193 /// - other instructions in lexicographical order sorted by name. 194 ArrayRef<const CodeGenInstruction *> getInstructionsByEnumValue() const { 195 if (InstrsByEnum.empty()) 196 ComputeInstrsByEnum(); 197 return InstrsByEnum; 198 } 199 200 /// Return the integer enum value corresponding to this instruction record. 201 unsigned getInstrIntValue(const Record *R) const { 202 if (InstrsByEnum.empty()) 203 ComputeInstrsByEnum(); 204 return getInstruction(R).EnumVal; 205 } 206 207 typedef ArrayRef<const CodeGenInstruction *>::const_iterator inst_iterator; 208 inst_iterator inst_begin() const { 209 return getInstructionsByEnumValue().begin(); 210 } 211 inst_iterator inst_end() const { return getInstructionsByEnumValue().end(); } 212 213 /// Return whether instructions have variable length encodings on this target. 214 bool hasVariableLengthEncodings() const { return HasVariableLengthEncodings; } 215 216 /// isLittleEndianEncoding - are instruction bit patterns defined as [0..n]? 217 /// 218 bool isLittleEndianEncoding() const; 219 220 /// reverseBitsForLittleEndianEncoding - For little-endian instruction bit 221 /// encodings, reverse the bit order of all instructions. 222 void reverseBitsForLittleEndianEncoding(); 223 224 /// guessInstructionProperties - should we just guess unset instruction 225 /// properties? 226 bool guessInstructionProperties() const; 227 228 private: 229 void ComputeInstrsByEnum() const; 230 }; 231 232 /// ComplexPattern - ComplexPattern info, corresponding to the ComplexPattern 233 /// tablegen class in TargetSelectionDAG.td 234 class ComplexPattern { 235 Record *Ty; 236 unsigned NumOperands; 237 std::string SelectFunc; 238 std::vector<Record *> RootNodes; 239 unsigned Properties; // Node properties 240 unsigned Complexity; 241 242 public: 243 ComplexPattern(Record *R); 244 245 Record *getValueType() const { return Ty; } 246 unsigned getNumOperands() const { return NumOperands; } 247 const std::string &getSelectFunc() const { return SelectFunc; } 248 const std::vector<Record *> &getRootNodes() const { return RootNodes; } 249 bool hasProperty(enum SDNP Prop) const { return Properties & (1 << Prop); } 250 unsigned getComplexity() const { return Complexity; } 251 }; 252 253 } // namespace llvm 254 255 #endif 256