1 //===- AsmWriterEmitter.cpp - Generate an assembly writer -----------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This tablegen backend emits an assembly printer for the current target. 10 // Note that this is currently fairly skeletal, but will grow over time. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "AsmWriterInst.h" 15 #include "CodeGenInstruction.h" 16 #include "CodeGenRegisters.h" 17 #include "CodeGenTarget.h" 18 #include "SequenceToOffsetTable.h" 19 #include "Types.h" 20 #include "llvm/ADT/ArrayRef.h" 21 #include "llvm/ADT/DenseMap.h" 22 #include "llvm/ADT/SmallString.h" 23 #include "llvm/ADT/SmallVector.h" 24 #include "llvm/ADT/STLExtras.h" 25 #include "llvm/ADT/StringExtras.h" 26 #include "llvm/ADT/StringRef.h" 27 #include "llvm/ADT/Twine.h" 28 #include "llvm/Support/Casting.h" 29 #include "llvm/Support/Debug.h" 30 #include "llvm/Support/ErrorHandling.h" 31 #include "llvm/Support/Format.h" 32 #include "llvm/Support/FormatVariadic.h" 33 #include "llvm/Support/MathExtras.h" 34 #include "llvm/Support/raw_ostream.h" 35 #include "llvm/TableGen/Error.h" 36 #include "llvm/TableGen/Record.h" 37 #include "llvm/TableGen/TableGenBackend.h" 38 #include <algorithm> 39 #include <cassert> 40 #include <cstddef> 41 #include <cstdint> 42 #include <deque> 43 #include <iterator> 44 #include <map> 45 #include <set> 46 #include <string> 47 #include <tuple> 48 #include <utility> 49 #include <vector> 50 51 using namespace llvm; 52 53 #define DEBUG_TYPE "asm-writer-emitter" 54 55 namespace { 56 57 class AsmWriterEmitter { 58 RecordKeeper &Records; 59 CodeGenTarget Target; 60 ArrayRef<const CodeGenInstruction *> NumberedInstructions; 61 std::vector<AsmWriterInst> Instructions; 62 63 public: 64 AsmWriterEmitter(RecordKeeper &R); 65 66 void run(raw_ostream &o); 67 private: 68 void EmitGetMnemonic( 69 raw_ostream &o, 70 std::vector<std::vector<std::string>> &TableDrivenOperandPrinters, 71 unsigned &BitsLeft, unsigned &AsmStrBits); 72 void EmitPrintInstruction( 73 raw_ostream &o, 74 std::vector<std::vector<std::string>> &TableDrivenOperandPrinters, 75 unsigned &BitsLeft, unsigned &AsmStrBits); 76 void EmitGetRegisterName(raw_ostream &o); 77 void EmitPrintAliasInstruction(raw_ostream &O); 78 79 void FindUniqueOperandCommands(std::vector<std::string> &UOC, 80 std::vector<std::vector<unsigned>> &InstIdxs, 81 std::vector<unsigned> &InstOpsUsed, 82 bool PassSubtarget) const; 83 }; 84 85 } // end anonymous namespace 86 87 static void PrintCases(std::vector<std::pair<std::string, 88 AsmWriterOperand>> &OpsToPrint, raw_ostream &O, 89 bool PassSubtarget) { 90 O << " case " << OpsToPrint.back().first << ":"; 91 AsmWriterOperand TheOp = OpsToPrint.back().second; 92 OpsToPrint.pop_back(); 93 94 // Check to see if any other operands are identical in this list, and if so, 95 // emit a case label for them. 96 for (unsigned i = OpsToPrint.size(); i != 0; --i) 97 if (OpsToPrint[i-1].second == TheOp) { 98 O << "\n case " << OpsToPrint[i-1].first << ":"; 99 OpsToPrint.erase(OpsToPrint.begin()+i-1); 100 } 101 102 // Finally, emit the code. 103 O << "\n " << TheOp.getCode(PassSubtarget); 104 O << "\n break;\n"; 105 } 106 107 /// EmitInstructions - Emit the last instruction in the vector and any other 108 /// instructions that are suitably similar to it. 109 static void EmitInstructions(std::vector<AsmWriterInst> &Insts, 110 raw_ostream &O, bool PassSubtarget) { 111 AsmWriterInst FirstInst = Insts.back(); 112 Insts.pop_back(); 113 114 std::vector<AsmWriterInst> SimilarInsts; 115 unsigned DifferingOperand = ~0; 116 for (unsigned i = Insts.size(); i != 0; --i) { 117 unsigned DiffOp = Insts[i-1].MatchesAllButOneOp(FirstInst); 118 if (DiffOp != ~1U) { 119 if (DifferingOperand == ~0U) // First match! 120 DifferingOperand = DiffOp; 121 122 // If this differs in the same operand as the rest of the instructions in 123 // this class, move it to the SimilarInsts list. 124 if (DifferingOperand == DiffOp || DiffOp == ~0U) { 125 SimilarInsts.push_back(Insts[i-1]); 126 Insts.erase(Insts.begin()+i-1); 127 } 128 } 129 } 130 131 O << " case " << FirstInst.CGI->Namespace << "::" 132 << FirstInst.CGI->TheDef->getName() << ":\n"; 133 for (const AsmWriterInst &AWI : SimilarInsts) 134 O << " case " << AWI.CGI->Namespace << "::" 135 << AWI.CGI->TheDef->getName() << ":\n"; 136 for (unsigned i = 0, e = FirstInst.Operands.size(); i != e; ++i) { 137 if (i != DifferingOperand) { 138 // If the operand is the same for all instructions, just print it. 139 O << " " << FirstInst.Operands[i].getCode(PassSubtarget); 140 } else { 141 // If this is the operand that varies between all of the instructions, 142 // emit a switch for just this operand now. 143 O << " switch (MI->getOpcode()) {\n"; 144 O << " default: llvm_unreachable(\"Unexpected opcode.\");\n"; 145 std::vector<std::pair<std::string, AsmWriterOperand>> OpsToPrint; 146 OpsToPrint.push_back(std::make_pair(FirstInst.CGI->Namespace.str() + "::" + 147 FirstInst.CGI->TheDef->getName().str(), 148 FirstInst.Operands[i])); 149 150 for (const AsmWriterInst &AWI : SimilarInsts) { 151 OpsToPrint.push_back(std::make_pair(AWI.CGI->Namespace.str()+"::" + 152 AWI.CGI->TheDef->getName().str(), 153 AWI.Operands[i])); 154 } 155 std::reverse(OpsToPrint.begin(), OpsToPrint.end()); 156 while (!OpsToPrint.empty()) 157 PrintCases(OpsToPrint, O, PassSubtarget); 158 O << " }"; 159 } 160 O << "\n"; 161 } 162 O << " break;\n"; 163 } 164 165 void AsmWriterEmitter:: 166 FindUniqueOperandCommands(std::vector<std::string> &UniqueOperandCommands, 167 std::vector<std::vector<unsigned>> &InstIdxs, 168 std::vector<unsigned> &InstOpsUsed, 169 bool PassSubtarget) const { 170 // This vector parallels UniqueOperandCommands, keeping track of which 171 // instructions each case are used for. It is a comma separated string of 172 // enums. 173 std::vector<std::string> InstrsForCase; 174 InstrsForCase.resize(UniqueOperandCommands.size()); 175 InstOpsUsed.assign(UniqueOperandCommands.size(), 0); 176 177 for (size_t i = 0, e = Instructions.size(); i != e; ++i) { 178 const AsmWriterInst &Inst = Instructions[i]; 179 if (Inst.Operands.empty()) 180 continue; // Instruction already done. 181 182 std::string Command = " "+Inst.Operands[0].getCode(PassSubtarget)+"\n"; 183 184 // Check to see if we already have 'Command' in UniqueOperandCommands. 185 // If not, add it. 186 auto I = llvm::find(UniqueOperandCommands, Command); 187 if (I != UniqueOperandCommands.end()) { 188 size_t idx = I - UniqueOperandCommands.begin(); 189 InstrsForCase[idx] += ", "; 190 InstrsForCase[idx] += Inst.CGI->TheDef->getName(); 191 InstIdxs[idx].push_back(i); 192 } else { 193 UniqueOperandCommands.push_back(std::move(Command)); 194 InstrsForCase.push_back(std::string(Inst.CGI->TheDef->getName())); 195 InstIdxs.emplace_back(); 196 InstIdxs.back().push_back(i); 197 198 // This command matches one operand so far. 199 InstOpsUsed.push_back(1); 200 } 201 } 202 203 // For each entry of UniqueOperandCommands, there is a set of instructions 204 // that uses it. If the next command of all instructions in the set are 205 // identical, fold it into the command. 206 for (size_t CommandIdx = 0, e = UniqueOperandCommands.size(); 207 CommandIdx != e; ++CommandIdx) { 208 209 const auto &Idxs = InstIdxs[CommandIdx]; 210 211 for (unsigned Op = 1; ; ++Op) { 212 // Find the first instruction in the set. 213 const AsmWriterInst &FirstInst = Instructions[Idxs.front()]; 214 // If this instruction has no more operands, we isn't anything to merge 215 // into this command. 216 if (FirstInst.Operands.size() == Op) 217 break; 218 219 // Otherwise, scan to see if all of the other instructions in this command 220 // set share the operand. 221 if (any_of(drop_begin(Idxs), [&](unsigned Idx) { 222 const AsmWriterInst &OtherInst = Instructions[Idx]; 223 return OtherInst.Operands.size() == Op || 224 OtherInst.Operands[Op] != FirstInst.Operands[Op]; 225 })) 226 break; 227 228 // Okay, everything in this command set has the same next operand. Add it 229 // to UniqueOperandCommands and remember that it was consumed. 230 std::string Command = " " + 231 FirstInst.Operands[Op].getCode(PassSubtarget) + "\n"; 232 233 UniqueOperandCommands[CommandIdx] += Command; 234 InstOpsUsed[CommandIdx]++; 235 } 236 } 237 238 // Prepend some of the instructions each case is used for onto the case val. 239 for (unsigned i = 0, e = InstrsForCase.size(); i != e; ++i) { 240 std::string Instrs = InstrsForCase[i]; 241 if (Instrs.size() > 70) { 242 Instrs.erase(Instrs.begin()+70, Instrs.end()); 243 Instrs += "..."; 244 } 245 246 if (!Instrs.empty()) 247 UniqueOperandCommands[i] = " // " + Instrs + "\n" + 248 UniqueOperandCommands[i]; 249 } 250 } 251 252 static void UnescapeString(std::string &Str) { 253 for (unsigned i = 0; i != Str.size(); ++i) { 254 if (Str[i] == '\\' && i != Str.size()-1) { 255 switch (Str[i+1]) { 256 default: continue; // Don't execute the code after the switch. 257 case 'a': Str[i] = '\a'; break; 258 case 'b': Str[i] = '\b'; break; 259 case 'e': Str[i] = 27; break; 260 case 'f': Str[i] = '\f'; break; 261 case 'n': Str[i] = '\n'; break; 262 case 'r': Str[i] = '\r'; break; 263 case 't': Str[i] = '\t'; break; 264 case 'v': Str[i] = '\v'; break; 265 case '"': Str[i] = '\"'; break; 266 case '\'': Str[i] = '\''; break; 267 case '\\': Str[i] = '\\'; break; 268 } 269 // Nuke the second character. 270 Str.erase(Str.begin()+i+1); 271 } 272 } 273 } 274 275 /// UnescapeAliasString - Supports literal braces in InstAlias asm string which 276 /// are escaped with '\\' to avoid being interpreted as variants. Braces must 277 /// be unescaped before c++ code is generated as (e.g.): 278 /// 279 /// AsmString = "foo \{$\x01\}"; 280 /// 281 /// causes non-standard escape character warnings. 282 static void UnescapeAliasString(std::string &Str) { 283 for (unsigned i = 0; i != Str.size(); ++i) { 284 if (Str[i] == '\\' && i != Str.size()-1) { 285 switch (Str[i+1]) { 286 default: continue; // Don't execute the code after the switch. 287 case '{': Str[i] = '{'; break; 288 case '}': Str[i] = '}'; break; 289 } 290 // Nuke the second character. 291 Str.erase(Str.begin()+i+1); 292 } 293 } 294 } 295 296 void AsmWriterEmitter::EmitGetMnemonic( 297 raw_ostream &O, 298 std::vector<std::vector<std::string>> &TableDrivenOperandPrinters, 299 unsigned &BitsLeft, unsigned &AsmStrBits) { 300 Record *AsmWriter = Target.getAsmWriter(); 301 StringRef ClassName = AsmWriter->getValueAsString("AsmWriterClassName"); 302 bool PassSubtarget = AsmWriter->getValueAsInt("PassSubtarget"); 303 304 O << "/// getMnemonic - This method is automatically generated by " 305 "tablegen\n" 306 "/// from the instruction set description.\n" 307 "std::pair<const char *, uint64_t> " 308 << Target.getName() << ClassName << "::getMnemonic(const MCInst *MI) {\n"; 309 310 // Build an aggregate string, and build a table of offsets into it. 311 SequenceToOffsetTable<std::string> StringTable; 312 313 /// OpcodeInfo - This encodes the index of the string to use for the first 314 /// chunk of the output as well as indices used for operand printing. 315 std::vector<uint64_t> OpcodeInfo(NumberedInstructions.size()); 316 const unsigned OpcodeInfoBits = 64; 317 318 // Add all strings to the string table upfront so it can generate an optimized 319 // representation. 320 for (AsmWriterInst &AWI : Instructions) { 321 if (AWI.Operands[0].OperandType == 322 AsmWriterOperand::isLiteralTextOperand && 323 !AWI.Operands[0].Str.empty()) { 324 std::string Str = AWI.Operands[0].Str; 325 UnescapeString(Str); 326 StringTable.add(Str); 327 } 328 } 329 330 StringTable.layout(); 331 332 unsigned MaxStringIdx = 0; 333 for (AsmWriterInst &AWI : Instructions) { 334 unsigned Idx; 335 if (AWI.Operands[0].OperandType != AsmWriterOperand::isLiteralTextOperand || 336 AWI.Operands[0].Str.empty()) { 337 // Something handled by the asmwriter printer, but with no leading string. 338 Idx = StringTable.get(""); 339 } else { 340 std::string Str = AWI.Operands[0].Str; 341 UnescapeString(Str); 342 Idx = StringTable.get(Str); 343 MaxStringIdx = std::max(MaxStringIdx, Idx); 344 345 // Nuke the string from the operand list. It is now handled! 346 AWI.Operands.erase(AWI.Operands.begin()); 347 } 348 349 // Bias offset by one since we want 0 as a sentinel. 350 OpcodeInfo[AWI.CGIIndex] = Idx+1; 351 } 352 353 // Figure out how many bits we used for the string index. 354 AsmStrBits = Log2_32_Ceil(MaxStringIdx + 2); 355 356 // To reduce code size, we compactify common instructions into a few bits 357 // in the opcode-indexed table. 358 BitsLeft = OpcodeInfoBits - AsmStrBits; 359 360 while (true) { 361 std::vector<std::string> UniqueOperandCommands; 362 std::vector<std::vector<unsigned>> InstIdxs; 363 std::vector<unsigned> NumInstOpsHandled; 364 FindUniqueOperandCommands(UniqueOperandCommands, InstIdxs, 365 NumInstOpsHandled, PassSubtarget); 366 367 // If we ran out of operands to print, we're done. 368 if (UniqueOperandCommands.empty()) break; 369 370 // Compute the number of bits we need to represent these cases, this is 371 // ceil(log2(numentries)). 372 unsigned NumBits = Log2_32_Ceil(UniqueOperandCommands.size()); 373 374 // If we don't have enough bits for this operand, don't include it. 375 if (NumBits > BitsLeft) { 376 LLVM_DEBUG(errs() << "Not enough bits to densely encode " << NumBits 377 << " more bits\n"); 378 break; 379 } 380 381 // Otherwise, we can include this in the initial lookup table. Add it in. 382 for (size_t i = 0, e = InstIdxs.size(); i != e; ++i) { 383 unsigned NumOps = NumInstOpsHandled[i]; 384 for (unsigned Idx : InstIdxs[i]) { 385 OpcodeInfo[Instructions[Idx].CGIIndex] |= 386 (uint64_t)i << (OpcodeInfoBits-BitsLeft); 387 // Remove the info about this operand from the instruction. 388 AsmWriterInst &Inst = Instructions[Idx]; 389 if (!Inst.Operands.empty()) { 390 assert(NumOps <= Inst.Operands.size() && 391 "Can't remove this many ops!"); 392 Inst.Operands.erase(Inst.Operands.begin(), 393 Inst.Operands.begin()+NumOps); 394 } 395 } 396 } 397 BitsLeft -= NumBits; 398 399 // Remember the handlers for this set of operands. 400 TableDrivenOperandPrinters.push_back(std::move(UniqueOperandCommands)); 401 } 402 403 // Emit the string table itself. 404 StringTable.emitStringLiteralDef(O, " static const char AsmStrs[]"); 405 406 // Emit the lookup tables in pieces to minimize wasted bytes. 407 unsigned BytesNeeded = ((OpcodeInfoBits - BitsLeft) + 7) / 8; 408 unsigned Table = 0, Shift = 0; 409 SmallString<128> BitsString; 410 raw_svector_ostream BitsOS(BitsString); 411 // If the total bits is more than 32-bits we need to use a 64-bit type. 412 BitsOS << " uint" << ((BitsLeft < (OpcodeInfoBits - 32)) ? 64 : 32) 413 << "_t Bits = 0;\n"; 414 while (BytesNeeded != 0) { 415 // Figure out how big this table section needs to be, but no bigger than 4. 416 unsigned TableSize = std::min(1 << Log2_32(BytesNeeded), 4); 417 BytesNeeded -= TableSize; 418 TableSize *= 8; // Convert to bits; 419 uint64_t Mask = (1ULL << TableSize) - 1; 420 O << " static const uint" << TableSize << "_t OpInfo" << Table 421 << "[] = {\n"; 422 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) { 423 O << " " << ((OpcodeInfo[i] >> Shift) & Mask) << "U,\t// " 424 << NumberedInstructions[i]->TheDef->getName() << "\n"; 425 } 426 O << " };\n\n"; 427 // Emit string to combine the individual table lookups. 428 BitsOS << " Bits |= "; 429 // If the total bits is more than 32-bits we need to use a 64-bit type. 430 if (BitsLeft < (OpcodeInfoBits - 32)) 431 BitsOS << "(uint64_t)"; 432 BitsOS << "OpInfo" << Table << "[MI->getOpcode()] << " << Shift << ";\n"; 433 // Prepare the shift for the next iteration and increment the table count. 434 Shift += TableSize; 435 ++Table; 436 } 437 438 O << " // Emit the opcode for the instruction.\n"; 439 O << BitsString; 440 441 // Return mnemonic string and bits. 442 O << " return {AsmStrs+(Bits & " << (1 << AsmStrBits) - 1 443 << ")-1, Bits};\n\n"; 444 445 O << "}\n"; 446 } 447 448 /// EmitPrintInstruction - Generate the code for the "printInstruction" method 449 /// implementation. Destroys all instances of AsmWriterInst information, by 450 /// clearing the Instructions vector. 451 void AsmWriterEmitter::EmitPrintInstruction( 452 raw_ostream &O, 453 std::vector<std::vector<std::string>> &TableDrivenOperandPrinters, 454 unsigned &BitsLeft, unsigned &AsmStrBits) { 455 const unsigned OpcodeInfoBits = 64; 456 Record *AsmWriter = Target.getAsmWriter(); 457 StringRef ClassName = AsmWriter->getValueAsString("AsmWriterClassName"); 458 bool PassSubtarget = AsmWriter->getValueAsInt("PassSubtarget"); 459 460 // This function has some huge switch statements that causing excessive 461 // compile time in LLVM profile instrumenation build. This print function 462 // usually is not frequently called in compilation. Here we disable the 463 // profile instrumenation for this function. 464 O << "/// printInstruction - This method is automatically generated by " 465 "tablegen\n" 466 "/// from the instruction set description.\n" 467 "LLVM_NO_PROFILE_INSTRUMENT_FUNCTION\n" 468 "void " 469 << Target.getName() << ClassName 470 << "::printInstruction(const MCInst *MI, uint64_t Address, " 471 << (PassSubtarget ? "const MCSubtargetInfo &STI, " : "") 472 << "raw_ostream &O) {\n"; 473 474 // Emit the initial tab character. 475 O << " O << \"\\t\";\n\n"; 476 477 // Emit the starting string. 478 O << " auto MnemonicInfo = getMnemonic(MI);\n\n"; 479 O << " O << MnemonicInfo.first;\n\n"; 480 481 O << " uint" << ((BitsLeft < (OpcodeInfoBits - 32)) ? 64 : 32) 482 << "_t Bits = MnemonicInfo.second;\n" 483 << " assert(Bits != 0 && \"Cannot print this instruction.\");\n"; 484 485 // Output the table driven operand information. 486 BitsLeft = OpcodeInfoBits-AsmStrBits; 487 for (unsigned i = 0, e = TableDrivenOperandPrinters.size(); i != e; ++i) { 488 std::vector<std::string> &Commands = TableDrivenOperandPrinters[i]; 489 490 // Compute the number of bits we need to represent these cases, this is 491 // ceil(log2(numentries)). 492 unsigned NumBits = Log2_32_Ceil(Commands.size()); 493 assert(NumBits <= BitsLeft && "consistency error"); 494 495 // Emit code to extract this field from Bits. 496 O << "\n // Fragment " << i << " encoded into " << NumBits 497 << " bits for " << Commands.size() << " unique commands.\n"; 498 499 if (Commands.size() == 2) { 500 // Emit two possibilitys with if/else. 501 O << " if ((Bits >> " 502 << (OpcodeInfoBits-BitsLeft) << ") & " 503 << ((1 << NumBits)-1) << ") {\n" 504 << Commands[1] 505 << " } else {\n" 506 << Commands[0] 507 << " }\n\n"; 508 } else if (Commands.size() == 1) { 509 // Emit a single possibility. 510 O << Commands[0] << "\n\n"; 511 } else { 512 O << " switch ((Bits >> " 513 << (OpcodeInfoBits-BitsLeft) << ") & " 514 << ((1 << NumBits)-1) << ") {\n" 515 << " default: llvm_unreachable(\"Invalid command number.\");\n"; 516 517 // Print out all the cases. 518 for (unsigned j = 0, e = Commands.size(); j != e; ++j) { 519 O << " case " << j << ":\n"; 520 O << Commands[j]; 521 O << " break;\n"; 522 } 523 O << " }\n\n"; 524 } 525 BitsLeft -= NumBits; 526 } 527 528 // Okay, delete instructions with no operand info left. 529 llvm::erase_if(Instructions, 530 [](AsmWriterInst &Inst) { return Inst.Operands.empty(); }); 531 532 // Because this is a vector, we want to emit from the end. Reverse all of the 533 // elements in the vector. 534 std::reverse(Instructions.begin(), Instructions.end()); 535 536 537 // Now that we've emitted all of the operand info that fit into 64 bits, emit 538 // information for those instructions that are left. This is a less dense 539 // encoding, but we expect the main 64-bit table to handle the majority of 540 // instructions. 541 if (!Instructions.empty()) { 542 // Find the opcode # of inline asm. 543 O << " switch (MI->getOpcode()) {\n"; 544 O << " default: llvm_unreachable(\"Unexpected opcode.\");\n"; 545 while (!Instructions.empty()) 546 EmitInstructions(Instructions, O, PassSubtarget); 547 548 O << " }\n"; 549 } 550 551 O << "}\n"; 552 } 553 554 static void 555 emitRegisterNameString(raw_ostream &O, StringRef AltName, 556 const std::deque<CodeGenRegister> &Registers) { 557 SequenceToOffsetTable<std::string> StringTable; 558 SmallVector<std::string, 4> AsmNames(Registers.size()); 559 unsigned i = 0; 560 for (const auto &Reg : Registers) { 561 std::string &AsmName = AsmNames[i++]; 562 563 // "NoRegAltName" is special. We don't need to do a lookup for that, 564 // as it's just a reference to the default register name. 565 if (AltName == "" || AltName == "NoRegAltName") { 566 AsmName = std::string(Reg.TheDef->getValueAsString("AsmName")); 567 if (AsmName.empty()) 568 AsmName = std::string(Reg.getName()); 569 } else { 570 // Make sure the register has an alternate name for this index. 571 std::vector<Record*> AltNameList = 572 Reg.TheDef->getValueAsListOfDefs("RegAltNameIndices"); 573 unsigned Idx = 0, e; 574 for (e = AltNameList.size(); 575 Idx < e && (AltNameList[Idx]->getName() != AltName); 576 ++Idx) 577 ; 578 // If the register has an alternate name for this index, use it. 579 // Otherwise, leave it empty as an error flag. 580 if (Idx < e) { 581 std::vector<StringRef> AltNames = 582 Reg.TheDef->getValueAsListOfStrings("AltNames"); 583 if (AltNames.size() <= Idx) 584 PrintFatalError(Reg.TheDef->getLoc(), 585 "Register definition missing alt name for '" + 586 AltName + "'."); 587 AsmName = std::string(AltNames[Idx]); 588 } 589 } 590 StringTable.add(AsmName); 591 } 592 593 StringTable.layout(); 594 StringTable.emitStringLiteralDef(O, Twine(" static const char AsmStrs") + 595 AltName + "[]"); 596 597 O << " static const " << getMinimalTypeForRange(StringTable.size() - 1, 32) 598 << " RegAsmOffset" << AltName << "[] = {"; 599 for (unsigned i = 0, e = Registers.size(); i != e; ++i) { 600 if ((i % 14) == 0) 601 O << "\n "; 602 O << StringTable.get(AsmNames[i]) << ", "; 603 } 604 O << "\n };\n" 605 << "\n"; 606 } 607 608 void AsmWriterEmitter::EmitGetRegisterName(raw_ostream &O) { 609 Record *AsmWriter = Target.getAsmWriter(); 610 StringRef ClassName = AsmWriter->getValueAsString("AsmWriterClassName"); 611 const auto &Registers = Target.getRegBank().getRegisters(); 612 const std::vector<Record*> &AltNameIndices = Target.getRegAltNameIndices(); 613 bool hasAltNames = AltNameIndices.size() > 1; 614 StringRef Namespace = Registers.front().TheDef->getValueAsString("Namespace"); 615 616 O << 617 "\n\n/// getRegisterName - This method is automatically generated by tblgen\n" 618 "/// from the register set description. This returns the assembler name\n" 619 "/// for the specified register.\n" 620 "const char *" << Target.getName() << ClassName << "::"; 621 if (hasAltNames) 622 O << "\ngetRegisterName(unsigned RegNo, unsigned AltIdx) {\n"; 623 else 624 O << "getRegisterName(unsigned RegNo) {\n"; 625 O << " assert(RegNo && RegNo < " << (Registers.size()+1) 626 << " && \"Invalid register number!\");\n" 627 << "\n"; 628 629 if (hasAltNames) { 630 for (const Record *R : AltNameIndices) 631 emitRegisterNameString(O, R->getName(), Registers); 632 } else 633 emitRegisterNameString(O, "", Registers); 634 635 if (hasAltNames) { 636 O << " switch(AltIdx) {\n" 637 << " default: llvm_unreachable(\"Invalid register alt name index!\");\n"; 638 for (const Record *R : AltNameIndices) { 639 StringRef AltName = R->getName(); 640 O << " case "; 641 if (!Namespace.empty()) 642 O << Namespace << "::"; 643 O << AltName << ":\n"; 644 if (R->isValueUnset("FallbackRegAltNameIndex")) 645 O << " assert(*(AsmStrs" << AltName << "+RegAsmOffset" << AltName 646 << "[RegNo-1]) &&\n" 647 << " \"Invalid alt name index for register!\");\n"; 648 else { 649 O << " if (!*(AsmStrs" << AltName << "+RegAsmOffset" << AltName 650 << "[RegNo-1]))\n" 651 << " return getRegisterName(RegNo, "; 652 if (!Namespace.empty()) 653 O << Namespace << "::"; 654 O << R->getValueAsDef("FallbackRegAltNameIndex")->getName() << ");\n"; 655 } 656 O << " return AsmStrs" << AltName << "+RegAsmOffset" << AltName 657 << "[RegNo-1];\n"; 658 } 659 O << " }\n"; 660 } else { 661 O << " assert (*(AsmStrs+RegAsmOffset[RegNo-1]) &&\n" 662 << " \"Invalid alt name index for register!\");\n" 663 << " return AsmStrs+RegAsmOffset[RegNo-1];\n"; 664 } 665 O << "}\n"; 666 } 667 668 namespace { 669 670 // IAPrinter - Holds information about an InstAlias. Two InstAliases match if 671 // they both have the same conditionals. In which case, we cannot print out the 672 // alias for that pattern. 673 class IAPrinter { 674 std::map<StringRef, std::pair<int, int>> OpMap; 675 676 std::vector<std::string> Conds; 677 678 std::string Result; 679 std::string AsmString; 680 681 unsigned NumMIOps; 682 683 public: 684 IAPrinter(std::string R, std::string AS, unsigned NumMIOps) 685 : Result(std::move(R)), AsmString(std::move(AS)), NumMIOps(NumMIOps) {} 686 687 void addCond(std::string C) { Conds.push_back(std::move(C)); } 688 ArrayRef<std::string> getConds() const { return Conds; } 689 size_t getCondCount() const { return Conds.size(); } 690 691 void addOperand(StringRef Op, int OpIdx, int PrintMethodIdx = -1) { 692 assert(OpIdx >= 0 && OpIdx < 0xFE && "Idx out of range"); 693 assert(PrintMethodIdx >= -1 && PrintMethodIdx < 0xFF && 694 "Idx out of range"); 695 OpMap[Op] = std::make_pair(OpIdx, PrintMethodIdx); 696 } 697 698 unsigned getNumMIOps() { return NumMIOps; } 699 700 StringRef getResult() { return Result; } 701 702 bool isOpMapped(StringRef Op) { return OpMap.find(Op) != OpMap.end(); } 703 int getOpIndex(StringRef Op) { return OpMap[Op].first; } 704 std::pair<int, int> &getOpData(StringRef Op) { return OpMap[Op]; } 705 706 std::pair<StringRef, StringRef::iterator> parseName(StringRef::iterator Start, 707 StringRef::iterator End) { 708 StringRef::iterator I = Start; 709 StringRef::iterator Next; 710 if (*I == '{') { 711 // ${some_name} 712 Start = ++I; 713 while (I != End && *I != '}') 714 ++I; 715 Next = I; 716 // eat the final '}' 717 if (Next != End) 718 ++Next; 719 } else { 720 // $name, just eat the usual suspects. 721 while (I != End && (isAlnum(*I) || *I == '_')) 722 ++I; 723 Next = I; 724 } 725 726 return std::make_pair(StringRef(Start, I - Start), Next); 727 } 728 729 std::string formatAliasString(uint32_t &UnescapedSize) { 730 // Directly mangle mapped operands into the string. Each operand is 731 // identified by a '$' sign followed by a byte identifying the number of the 732 // operand. We add one to the index to avoid zero bytes. 733 StringRef ASM(AsmString); 734 std::string OutString; 735 raw_string_ostream OS(OutString); 736 for (StringRef::iterator I = ASM.begin(), E = ASM.end(); I != E;) { 737 OS << *I; 738 ++UnescapedSize; 739 if (*I == '$') { 740 StringRef Name; 741 std::tie(Name, I) = parseName(++I, E); 742 assert(isOpMapped(Name) && "Unmapped operand!"); 743 744 int OpIndex, PrintIndex; 745 std::tie(OpIndex, PrintIndex) = getOpData(Name); 746 if (PrintIndex == -1) { 747 // Can use the default printOperand route. 748 OS << format("\\x%02X", (unsigned char)OpIndex + 1); 749 ++UnescapedSize; 750 } else { 751 // 3 bytes if a PrintMethod is needed: 0xFF, the MCInst operand 752 // number, and which of our pre-detected Methods to call. 753 OS << format("\\xFF\\x%02X\\x%02X", OpIndex + 1, PrintIndex + 1); 754 UnescapedSize += 3; 755 } 756 } else { 757 ++I; 758 } 759 } 760 return OutString; 761 } 762 763 bool operator==(const IAPrinter &RHS) const { 764 if (NumMIOps != RHS.NumMIOps) 765 return false; 766 if (Conds.size() != RHS.Conds.size()) 767 return false; 768 769 unsigned Idx = 0; 770 for (const auto &str : Conds) 771 if (str != RHS.Conds[Idx++]) 772 return false; 773 774 return true; 775 } 776 }; 777 778 } // end anonymous namespace 779 780 static unsigned CountNumOperands(StringRef AsmString, unsigned Variant) { 781 return AsmString.count(' ') + AsmString.count('\t'); 782 } 783 784 namespace { 785 786 struct AliasPriorityComparator { 787 typedef std::pair<CodeGenInstAlias, int> ValueType; 788 bool operator()(const ValueType &LHS, const ValueType &RHS) const { 789 if (LHS.second == RHS.second) { 790 // We don't actually care about the order, but for consistency it 791 // shouldn't depend on pointer comparisons. 792 return LessRecordByID()(LHS.first.TheDef, RHS.first.TheDef); 793 } 794 795 // Aliases with larger priorities should be considered first. 796 return LHS.second > RHS.second; 797 } 798 }; 799 800 } // end anonymous namespace 801 802 void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) { 803 Record *AsmWriter = Target.getAsmWriter(); 804 805 O << "\n#ifdef PRINT_ALIAS_INSTR\n"; 806 O << "#undef PRINT_ALIAS_INSTR\n\n"; 807 808 ////////////////////////////// 809 // Gather information about aliases we need to print 810 ////////////////////////////// 811 812 // Emit the method that prints the alias instruction. 813 StringRef ClassName = AsmWriter->getValueAsString("AsmWriterClassName"); 814 unsigned Variant = AsmWriter->getValueAsInt("Variant"); 815 bool PassSubtarget = AsmWriter->getValueAsInt("PassSubtarget"); 816 817 std::vector<Record*> AllInstAliases = 818 Records.getAllDerivedDefinitions("InstAlias"); 819 820 // Create a map from the qualified name to a list of potential matches. 821 typedef std::set<std::pair<CodeGenInstAlias, int>, AliasPriorityComparator> 822 AliasWithPriority; 823 std::map<std::string, AliasWithPriority> AliasMap; 824 for (Record *R : AllInstAliases) { 825 int Priority = R->getValueAsInt("EmitPriority"); 826 if (Priority < 1) 827 continue; // Aliases with priority 0 are never emitted. 828 829 const DagInit *DI = R->getValueAsDag("ResultInst"); 830 AliasMap[getQualifiedName(DI->getOperatorAsDef(R->getLoc()))].insert( 831 std::make_pair(CodeGenInstAlias(R, Target), Priority)); 832 } 833 834 // A map of which conditions need to be met for each instruction operand 835 // before it can be matched to the mnemonic. 836 std::map<std::string, std::vector<IAPrinter>> IAPrinterMap; 837 838 std::vector<std::pair<std::string, bool>> PrintMethods; 839 840 // A list of MCOperandPredicates for all operands in use, and the reverse map 841 std::vector<const Record*> MCOpPredicates; 842 DenseMap<const Record*, unsigned> MCOpPredicateMap; 843 844 for (auto &Aliases : AliasMap) { 845 // Collection of instruction alias rules. May contain ambiguous rules. 846 std::vector<IAPrinter> IAPs; 847 848 for (auto &Alias : Aliases.second) { 849 const CodeGenInstAlias &CGA = Alias.first; 850 unsigned LastOpNo = CGA.ResultInstOperandIndex.size(); 851 std::string FlatInstAsmString = 852 CodeGenInstruction::FlattenAsmStringVariants(CGA.ResultInst->AsmString, 853 Variant); 854 unsigned NumResultOps = CountNumOperands(FlatInstAsmString, Variant); 855 856 std::string FlatAliasAsmString = 857 CodeGenInstruction::FlattenAsmStringVariants(CGA.AsmString, Variant); 858 UnescapeAliasString(FlatAliasAsmString); 859 860 // Don't emit the alias if it has more operands than what it's aliasing. 861 if (NumResultOps < CountNumOperands(FlatAliasAsmString, Variant)) 862 continue; 863 864 StringRef Namespace = Target.getName(); 865 unsigned NumMIOps = 0; 866 for (auto &ResultInstOpnd : CGA.ResultInst->Operands) 867 NumMIOps += ResultInstOpnd.MINumOperands; 868 869 IAPrinter IAP(CGA.Result->getAsString(), FlatAliasAsmString, NumMIOps); 870 871 bool CantHandle = false; 872 873 unsigned MIOpNum = 0; 874 for (unsigned i = 0, e = LastOpNo; i != e; ++i) { 875 // Skip over tied operands as they're not part of an alias declaration. 876 auto &Operands = CGA.ResultInst->Operands; 877 while (true) { 878 unsigned OpNum = Operands.getSubOperandNumber(MIOpNum).first; 879 if (Operands[OpNum].MINumOperands == 1 && 880 Operands[OpNum].getTiedRegister() != -1) { 881 // Tied operands of different RegisterClass should be explicit within 882 // an instruction's syntax and so cannot be skipped. 883 int TiedOpNum = Operands[OpNum].getTiedRegister(); 884 if (Operands[OpNum].Rec->getName() == 885 Operands[TiedOpNum].Rec->getName()) { 886 ++MIOpNum; 887 continue; 888 } 889 } 890 break; 891 } 892 893 // Ignore unchecked result operands. 894 while (IAP.getCondCount() < MIOpNum) 895 IAP.addCond("AliasPatternCond::K_Ignore, 0"); 896 897 const CodeGenInstAlias::ResultOperand &RO = CGA.ResultOperands[i]; 898 899 switch (RO.Kind) { 900 case CodeGenInstAlias::ResultOperand::K_Record: { 901 const Record *Rec = RO.getRecord(); 902 StringRef ROName = RO.getName(); 903 int PrintMethodIdx = -1; 904 905 // These two may have a PrintMethod, which we want to record (if it's 906 // the first time we've seen it) and provide an index for the aliasing 907 // code to use. 908 if (Rec->isSubClassOf("RegisterOperand") || 909 Rec->isSubClassOf("Operand")) { 910 StringRef PrintMethod = Rec->getValueAsString("PrintMethod"); 911 bool IsPCRel = 912 Rec->getValueAsString("OperandType") == "OPERAND_PCREL"; 913 if (PrintMethod != "" && PrintMethod != "printOperand") { 914 PrintMethodIdx = llvm::find_if(PrintMethods, 915 [&](auto &X) { 916 return X.first == PrintMethod; 917 }) - 918 PrintMethods.begin(); 919 if (static_cast<unsigned>(PrintMethodIdx) == PrintMethods.size()) 920 PrintMethods.emplace_back(std::string(PrintMethod), IsPCRel); 921 } 922 } 923 924 if (Rec->isSubClassOf("RegisterOperand")) 925 Rec = Rec->getValueAsDef("RegClass"); 926 if (Rec->isSubClassOf("RegisterClass")) { 927 if (!IAP.isOpMapped(ROName)) { 928 IAP.addOperand(ROName, MIOpNum, PrintMethodIdx); 929 Record *R = CGA.ResultOperands[i].getRecord(); 930 if (R->isSubClassOf("RegisterOperand")) 931 R = R->getValueAsDef("RegClass"); 932 IAP.addCond(std::string( 933 formatv("AliasPatternCond::K_RegClass, {0}::{1}RegClassID", 934 Namespace, R->getName()))); 935 } else { 936 IAP.addCond(std::string(formatv( 937 "AliasPatternCond::K_TiedReg, {0}", IAP.getOpIndex(ROName)))); 938 } 939 } else { 940 // Assume all printable operands are desired for now. This can be 941 // overridden in the InstAlias instantiation if necessary. 942 IAP.addOperand(ROName, MIOpNum, PrintMethodIdx); 943 944 // There might be an additional predicate on the MCOperand 945 unsigned Entry = MCOpPredicateMap[Rec]; 946 if (!Entry) { 947 if (!Rec->isValueUnset("MCOperandPredicate")) { 948 MCOpPredicates.push_back(Rec); 949 Entry = MCOpPredicates.size(); 950 MCOpPredicateMap[Rec] = Entry; 951 } else 952 break; // No conditions on this operand at all 953 } 954 IAP.addCond( 955 std::string(formatv("AliasPatternCond::K_Custom, {0}", Entry))); 956 } 957 break; 958 } 959 case CodeGenInstAlias::ResultOperand::K_Imm: { 960 // Just because the alias has an immediate result, doesn't mean the 961 // MCInst will. An MCExpr could be present, for example. 962 auto Imm = CGA.ResultOperands[i].getImm(); 963 int32_t Imm32 = int32_t(Imm); 964 if (Imm != Imm32) 965 PrintFatalError("Matching an alias with an immediate out of the " 966 "range of int32_t is not supported"); 967 IAP.addCond(std::string( 968 formatv("AliasPatternCond::K_Imm, uint32_t({0})", Imm32))); 969 break; 970 } 971 case CodeGenInstAlias::ResultOperand::K_Reg: 972 // If this is zero_reg, something's playing tricks we're not 973 // equipped to handle. 974 if (!CGA.ResultOperands[i].getRegister()) { 975 CantHandle = true; 976 break; 977 } 978 979 StringRef Reg = CGA.ResultOperands[i].getRegister()->getName(); 980 IAP.addCond(std::string( 981 formatv("AliasPatternCond::K_Reg, {0}::{1}", Namespace, Reg))); 982 break; 983 } 984 985 MIOpNum += RO.getMINumOperands(); 986 } 987 988 if (CantHandle) continue; 989 990 std::vector<Record *> ReqFeatures; 991 if (PassSubtarget) { 992 // We only consider ReqFeatures predicates if PassSubtarget 993 std::vector<Record *> RF = 994 CGA.TheDef->getValueAsListOfDefs("Predicates"); 995 copy_if(RF, std::back_inserter(ReqFeatures), [](Record *R) { 996 return R->getValueAsBit("AssemblerMatcherPredicate"); 997 }); 998 } 999 1000 for (Record *const R : ReqFeatures) { 1001 const DagInit *D = R->getValueAsDag("AssemblerCondDag"); 1002 std::string CombineType = D->getOperator()->getAsString(); 1003 if (CombineType != "any_of" && CombineType != "all_of") 1004 PrintFatalError(R->getLoc(), "Invalid AssemblerCondDag!"); 1005 if (D->getNumArgs() == 0) 1006 PrintFatalError(R->getLoc(), "Invalid AssemblerCondDag!"); 1007 bool IsOr = CombineType == "any_of"; 1008 1009 for (auto *Arg : D->getArgs()) { 1010 bool IsNeg = false; 1011 if (auto *NotArg = dyn_cast<DagInit>(Arg)) { 1012 if (NotArg->getOperator()->getAsString() != "not" || 1013 NotArg->getNumArgs() != 1) 1014 PrintFatalError(R->getLoc(), "Invalid AssemblerCondDag!"); 1015 Arg = NotArg->getArg(0); 1016 IsNeg = true; 1017 } 1018 if (!isa<DefInit>(Arg) || 1019 !cast<DefInit>(Arg)->getDef()->isSubClassOf("SubtargetFeature")) 1020 PrintFatalError(R->getLoc(), "Invalid AssemblerCondDag!"); 1021 1022 IAP.addCond(std::string(formatv( 1023 "AliasPatternCond::K_{0}{1}Feature, {2}::{3}", IsOr ? "Or" : "", 1024 IsNeg ? "Neg" : "", Namespace, Arg->getAsString()))); 1025 } 1026 // If an AssemblerPredicate with ors is used, note end of list should 1027 // these be combined. 1028 if (IsOr) 1029 IAP.addCond("AliasPatternCond::K_EndOrFeatures, 0"); 1030 } 1031 1032 IAPrinterMap[Aliases.first].push_back(std::move(IAP)); 1033 } 1034 } 1035 1036 ////////////////////////////// 1037 // Write out the printAliasInstr function 1038 ////////////////////////////// 1039 1040 std::string Header; 1041 raw_string_ostream HeaderO(Header); 1042 1043 HeaderO << "bool " << Target.getName() << ClassName 1044 << "::printAliasInstr(const MCInst" 1045 << " *MI, uint64_t Address, " 1046 << (PassSubtarget ? "const MCSubtargetInfo &STI, " : "") 1047 << "raw_ostream &OS) {\n"; 1048 1049 std::string PatternsForOpcode; 1050 raw_string_ostream OpcodeO(PatternsForOpcode); 1051 1052 unsigned PatternCount = 0; 1053 std::string Patterns; 1054 raw_string_ostream PatternO(Patterns); 1055 1056 unsigned CondCount = 0; 1057 std::string Conds; 1058 raw_string_ostream CondO(Conds); 1059 1060 // All flattened alias strings. 1061 std::map<std::string, uint32_t> AsmStringOffsets; 1062 std::vector<std::pair<uint32_t, std::string>> AsmStrings; 1063 size_t AsmStringsSize = 0; 1064 1065 // Iterate over the opcodes in enum order so they are sorted by opcode for 1066 // binary search. 1067 for (const CodeGenInstruction *Inst : NumberedInstructions) { 1068 auto It = IAPrinterMap.find(getQualifiedName(Inst->TheDef)); 1069 if (It == IAPrinterMap.end()) 1070 continue; 1071 std::vector<IAPrinter> &IAPs = It->second; 1072 std::vector<IAPrinter*> UniqueIAPs; 1073 1074 // Remove any ambiguous alias rules. 1075 for (auto &LHS : IAPs) { 1076 bool IsDup = false; 1077 for (const auto &RHS : IAPs) { 1078 if (&LHS != &RHS && LHS == RHS) { 1079 IsDup = true; 1080 break; 1081 } 1082 } 1083 1084 if (!IsDup) 1085 UniqueIAPs.push_back(&LHS); 1086 } 1087 1088 if (UniqueIAPs.empty()) continue; 1089 1090 unsigned PatternStart = PatternCount; 1091 1092 // Insert the pattern start and opcode in the pattern list for debugging. 1093 PatternO << formatv(" // {0} - {1}\n", It->first, PatternStart); 1094 1095 for (IAPrinter *IAP : UniqueIAPs) { 1096 // Start each condition list with a comment of the resulting pattern that 1097 // we're trying to match. 1098 unsigned CondStart = CondCount; 1099 CondO << formatv(" // {0} - {1}\n", IAP->getResult(), CondStart); 1100 for (const auto &Cond : IAP->getConds()) 1101 CondO << " {" << Cond << "},\n"; 1102 CondCount += IAP->getCondCount(); 1103 1104 // After operands have been examined, re-encode the alias string with 1105 // escapes indicating how operands should be printed. 1106 uint32_t UnescapedSize = 0; 1107 std::string EncodedAsmString = IAP->formatAliasString(UnescapedSize); 1108 auto Insertion = 1109 AsmStringOffsets.insert({EncodedAsmString, AsmStringsSize}); 1110 if (Insertion.second) { 1111 // If the string is new, add it to the vector. 1112 AsmStrings.push_back({AsmStringsSize, EncodedAsmString}); 1113 AsmStringsSize += UnescapedSize + 1; 1114 } 1115 unsigned AsmStrOffset = Insertion.first->second; 1116 1117 PatternO << formatv(" {{{0}, {1}, {2}, {3} },\n", AsmStrOffset, 1118 CondStart, IAP->getNumMIOps(), IAP->getCondCount()); 1119 ++PatternCount; 1120 } 1121 1122 OpcodeO << formatv(" {{{0}, {1}, {2} },\n", It->first, PatternStart, 1123 PatternCount - PatternStart); 1124 } 1125 1126 if (OpcodeO.str().empty()) { 1127 O << HeaderO.str(); 1128 O << " return false;\n"; 1129 O << "}\n\n"; 1130 O << "#endif // PRINT_ALIAS_INSTR\n"; 1131 return; 1132 } 1133 1134 // Forward declare the validation method if needed. 1135 if (!MCOpPredicates.empty()) 1136 O << "static bool " << Target.getName() << ClassName 1137 << "ValidateMCOperand(const MCOperand &MCOp,\n" 1138 << " const MCSubtargetInfo &STI,\n" 1139 << " unsigned PredicateIndex);\n"; 1140 1141 O << HeaderO.str(); 1142 O.indent(2) << "static const PatternsForOpcode OpToPatterns[] = {\n"; 1143 O << OpcodeO.str(); 1144 O.indent(2) << "};\n\n"; 1145 O.indent(2) << "static const AliasPattern Patterns[] = {\n"; 1146 O << PatternO.str(); 1147 O.indent(2) << "};\n\n"; 1148 O.indent(2) << "static const AliasPatternCond Conds[] = {\n"; 1149 O << CondO.str(); 1150 O.indent(2) << "};\n\n"; 1151 O.indent(2) << "static const char AsmStrings[] =\n"; 1152 for (const auto &P : AsmStrings) { 1153 O.indent(4) << "/* " << P.first << " */ \"" << P.second << "\\0\"\n"; 1154 } 1155 1156 O.indent(2) << ";\n\n"; 1157 1158 // Assert that the opcode table is sorted. Use a static local constructor to 1159 // ensure that the check only happens once on first run. 1160 O << "#ifndef NDEBUG\n"; 1161 O.indent(2) << "static struct SortCheck {\n"; 1162 O.indent(2) << " SortCheck(ArrayRef<PatternsForOpcode> OpToPatterns) {\n"; 1163 O.indent(2) << " assert(std::is_sorted(\n"; 1164 O.indent(2) << " OpToPatterns.begin(), OpToPatterns.end(),\n"; 1165 O.indent(2) << " [](const PatternsForOpcode &L, const " 1166 "PatternsForOpcode &R) {\n"; 1167 O.indent(2) << " return L.Opcode < R.Opcode;\n"; 1168 O.indent(2) << " }) &&\n"; 1169 O.indent(2) << " \"tablegen failed to sort opcode patterns\");\n"; 1170 O.indent(2) << " }\n"; 1171 O.indent(2) << "} sortCheckVar(OpToPatterns);\n"; 1172 O << "#endif\n\n"; 1173 1174 O.indent(2) << "AliasMatchingData M {\n"; 1175 O.indent(2) << " makeArrayRef(OpToPatterns),\n"; 1176 O.indent(2) << " makeArrayRef(Patterns),\n"; 1177 O.indent(2) << " makeArrayRef(Conds),\n"; 1178 O.indent(2) << " StringRef(AsmStrings, array_lengthof(AsmStrings)),\n"; 1179 if (MCOpPredicates.empty()) 1180 O.indent(2) << " nullptr,\n"; 1181 else 1182 O.indent(2) << " &" << Target.getName() << ClassName << "ValidateMCOperand,\n"; 1183 O.indent(2) << "};\n"; 1184 1185 O.indent(2) << "const char *AsmString = matchAliasPatterns(MI, " 1186 << (PassSubtarget ? "&STI" : "nullptr") << ", M);\n"; 1187 O.indent(2) << "if (!AsmString) return false;\n\n"; 1188 1189 // Code that prints the alias, replacing the operands with the ones from the 1190 // MCInst. 1191 O << " unsigned I = 0;\n"; 1192 O << " while (AsmString[I] != ' ' && AsmString[I] != '\\t' &&\n"; 1193 O << " AsmString[I] != '$' && AsmString[I] != '\\0')\n"; 1194 O << " ++I;\n"; 1195 O << " OS << '\\t' << StringRef(AsmString, I);\n"; 1196 1197 O << " if (AsmString[I] != '\\0') {\n"; 1198 O << " if (AsmString[I] == ' ' || AsmString[I] == '\\t') {\n"; 1199 O << " OS << '\\t';\n"; 1200 O << " ++I;\n"; 1201 O << " }\n"; 1202 O << " do {\n"; 1203 O << " if (AsmString[I] == '$') {\n"; 1204 O << " ++I;\n"; 1205 O << " if (AsmString[I] == (char)0xff) {\n"; 1206 O << " ++I;\n"; 1207 O << " int OpIdx = AsmString[I++] - 1;\n"; 1208 O << " int PrintMethodIdx = AsmString[I++] - 1;\n"; 1209 O << " printCustomAliasOperand(MI, Address, OpIdx, PrintMethodIdx, "; 1210 O << (PassSubtarget ? "STI, " : ""); 1211 O << "OS);\n"; 1212 O << " } else\n"; 1213 O << " printOperand(MI, unsigned(AsmString[I++]) - 1, "; 1214 O << (PassSubtarget ? "STI, " : ""); 1215 O << "OS);\n"; 1216 O << " } else {\n"; 1217 O << " OS << AsmString[I++];\n"; 1218 O << " }\n"; 1219 O << " } while (AsmString[I] != '\\0');\n"; 1220 O << " }\n\n"; 1221 1222 O << " return true;\n"; 1223 O << "}\n\n"; 1224 1225 ////////////////////////////// 1226 // Write out the printCustomAliasOperand function 1227 ////////////////////////////// 1228 1229 O << "void " << Target.getName() << ClassName << "::" 1230 << "printCustomAliasOperand(\n" 1231 << " const MCInst *MI, uint64_t Address, unsigned OpIdx,\n" 1232 << " unsigned PrintMethodIdx,\n" 1233 << (PassSubtarget ? " const MCSubtargetInfo &STI,\n" : "") 1234 << " raw_ostream &OS) {\n"; 1235 if (PrintMethods.empty()) 1236 O << " llvm_unreachable(\"Unknown PrintMethod kind\");\n"; 1237 else { 1238 O << " switch (PrintMethodIdx) {\n" 1239 << " default:\n" 1240 << " llvm_unreachable(\"Unknown PrintMethod kind\");\n" 1241 << " break;\n"; 1242 1243 for (unsigned i = 0; i < PrintMethods.size(); ++i) { 1244 O << " case " << i << ":\n" 1245 << " " << PrintMethods[i].first << "(MI, " 1246 << (PrintMethods[i].second ? "Address, " : "") << "OpIdx, " 1247 << (PassSubtarget ? "STI, " : "") << "OS);\n" 1248 << " break;\n"; 1249 } 1250 O << " }\n"; 1251 } 1252 O << "}\n\n"; 1253 1254 if (!MCOpPredicates.empty()) { 1255 O << "static bool " << Target.getName() << ClassName 1256 << "ValidateMCOperand(const MCOperand &MCOp,\n" 1257 << " const MCSubtargetInfo &STI,\n" 1258 << " unsigned PredicateIndex) {\n" 1259 << " switch (PredicateIndex) {\n" 1260 << " default:\n" 1261 << " llvm_unreachable(\"Unknown MCOperandPredicate kind\");\n" 1262 << " break;\n"; 1263 1264 for (unsigned i = 0; i < MCOpPredicates.size(); ++i) { 1265 StringRef MCOpPred = MCOpPredicates[i]->getValueAsString("MCOperandPredicate"); 1266 O << " case " << i + 1 << ": {\n" 1267 << MCOpPred.data() << "\n" 1268 << " }\n"; 1269 } 1270 O << " }\n" 1271 << "}\n\n"; 1272 } 1273 1274 O << "#endif // PRINT_ALIAS_INSTR\n"; 1275 } 1276 1277 AsmWriterEmitter::AsmWriterEmitter(RecordKeeper &R) : Records(R), Target(R) { 1278 Record *AsmWriter = Target.getAsmWriter(); 1279 unsigned Variant = AsmWriter->getValueAsInt("Variant"); 1280 1281 // Get the instruction numbering. 1282 NumberedInstructions = Target.getInstructionsByEnumValue(); 1283 1284 for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) { 1285 const CodeGenInstruction *I = NumberedInstructions[i]; 1286 if (!I->AsmString.empty() && I->TheDef->getName() != "PHI") 1287 Instructions.emplace_back(*I, i, Variant); 1288 } 1289 } 1290 1291 void AsmWriterEmitter::run(raw_ostream &O) { 1292 std::vector<std::vector<std::string>> TableDrivenOperandPrinters; 1293 unsigned BitsLeft = 0; 1294 unsigned AsmStrBits = 0; 1295 EmitGetMnemonic(O, TableDrivenOperandPrinters, BitsLeft, AsmStrBits); 1296 EmitPrintInstruction(O, TableDrivenOperandPrinters, BitsLeft, AsmStrBits); 1297 EmitGetRegisterName(O); 1298 EmitPrintAliasInstruction(O); 1299 } 1300 1301 namespace llvm { 1302 1303 void EmitAsmWriter(RecordKeeper &RK, raw_ostream &OS) { 1304 emitSourceFileHeader("Assembly Writer Source Fragment", OS); 1305 AsmWriterEmitter(RK).run(OS); 1306 } 1307 1308 } // end namespace llvm 1309