xref: /freebsd/contrib/llvm-project/llvm/utils/TableGen/AsmMatcherEmitter.cpp (revision 85868e8a1daeaae7a0e48effb2ea2310ae3b02c6)
1 //===- AsmMatcherEmitter.cpp - Generate an assembly matcher ---------------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This tablegen backend emits a target specifier matcher for converting parsed
10 // assembly operands in the MCInst structures. It also emits a matcher for
11 // custom operand parsing.
12 //
13 // Converting assembly operands into MCInst structures
14 // ---------------------------------------------------
15 //
16 // The input to the target specific matcher is a list of literal tokens and
17 // operands. The target specific parser should generally eliminate any syntax
18 // which is not relevant for matching; for example, comma tokens should have
19 // already been consumed and eliminated by the parser. Most instructions will
20 // end up with a single literal token (the instruction name) and some number of
21 // operands.
22 //
23 // Some example inputs, for X86:
24 //   'addl' (immediate ...) (register ...)
25 //   'add' (immediate ...) (memory ...)
26 //   'call' '*' %epc
27 //
28 // The assembly matcher is responsible for converting this input into a precise
29 // machine instruction (i.e., an instruction with a well defined encoding). This
30 // mapping has several properties which complicate matching:
31 //
32 //  - It may be ambiguous; many architectures can legally encode particular
33 //    variants of an instruction in different ways (for example, using a smaller
34 //    encoding for small immediates). Such ambiguities should never be
35 //    arbitrarily resolved by the assembler, the assembler is always responsible
36 //    for choosing the "best" available instruction.
37 //
38 //  - It may depend on the subtarget or the assembler context. Instructions
39 //    which are invalid for the current mode, but otherwise unambiguous (e.g.,
40 //    an SSE instruction in a file being assembled for i486) should be accepted
41 //    and rejected by the assembler front end. However, if the proper encoding
42 //    for an instruction is dependent on the assembler context then the matcher
43 //    is responsible for selecting the correct machine instruction for the
44 //    current mode.
45 //
46 // The core matching algorithm attempts to exploit the regularity in most
47 // instruction sets to quickly determine the set of possibly matching
48 // instructions, and the simplify the generated code. Additionally, this helps
49 // to ensure that the ambiguities are intentionally resolved by the user.
50 //
51 // The matching is divided into two distinct phases:
52 //
53 //   1. Classification: Each operand is mapped to the unique set which (a)
54 //      contains it, and (b) is the largest such subset for which a single
55 //      instruction could match all members.
56 //
57 //      For register classes, we can generate these subgroups automatically. For
58 //      arbitrary operands, we expect the user to define the classes and their
59 //      relations to one another (for example, 8-bit signed immediates as a
60 //      subset of 32-bit immediates).
61 //
62 //      By partitioning the operands in this way, we guarantee that for any
63 //      tuple of classes, any single instruction must match either all or none
64 //      of the sets of operands which could classify to that tuple.
65 //
66 //      In addition, the subset relation amongst classes induces a partial order
67 //      on such tuples, which we use to resolve ambiguities.
68 //
69 //   2. The input can now be treated as a tuple of classes (static tokens are
70 //      simple singleton sets). Each such tuple should generally map to a single
71 //      instruction (we currently ignore cases where this isn't true, whee!!!),
72 //      which we can emit a simple matcher for.
73 //
74 // Custom Operand Parsing
75 // ----------------------
76 //
77 //  Some targets need a custom way to parse operands, some specific instructions
78 //  can contain arguments that can represent processor flags and other kinds of
79 //  identifiers that need to be mapped to specific values in the final encoded
80 //  instructions. The target specific custom operand parsing works in the
81 //  following way:
82 //
83 //   1. A operand match table is built, each entry contains a mnemonic, an
84 //      operand class, a mask for all operand positions for that same
85 //      class/mnemonic and target features to be checked while trying to match.
86 //
87 //   2. The operand matcher will try every possible entry with the same
88 //      mnemonic and will check if the target feature for this mnemonic also
89 //      matches. After that, if the operand to be matched has its index
90 //      present in the mask, a successful match occurs. Otherwise, fallback
91 //      to the regular operand parsing.
92 //
93 //   3. For a match success, each operand class that has a 'ParserMethod'
94 //      becomes part of a switch from where the custom method is called.
95 //
96 //===----------------------------------------------------------------------===//
97 
98 #include "CodeGenTarget.h"
99 #include "SubtargetFeatureInfo.h"
100 #include "Types.h"
101 #include "llvm/ADT/CachedHashString.h"
102 #include "llvm/ADT/PointerUnion.h"
103 #include "llvm/ADT/STLExtras.h"
104 #include "llvm/ADT/SmallPtrSet.h"
105 #include "llvm/ADT/SmallVector.h"
106 #include "llvm/ADT/StringExtras.h"
107 #include "llvm/Config/llvm-config.h"
108 #include "llvm/Support/CommandLine.h"
109 #include "llvm/Support/Debug.h"
110 #include "llvm/Support/ErrorHandling.h"
111 #include "llvm/TableGen/Error.h"
112 #include "llvm/TableGen/Record.h"
113 #include "llvm/TableGen/StringMatcher.h"
114 #include "llvm/TableGen/StringToOffsetTable.h"
115 #include "llvm/TableGen/TableGenBackend.h"
116 #include <cassert>
117 #include <cctype>
118 #include <forward_list>
119 #include <map>
120 #include <set>
121 
122 using namespace llvm;
123 
124 #define DEBUG_TYPE "asm-matcher-emitter"
125 
126 cl::OptionCategory AsmMatcherEmitterCat("Options for -gen-asm-matcher");
127 
128 static cl::opt<std::string>
129     MatchPrefix("match-prefix", cl::init(""),
130                 cl::desc("Only match instructions with the given prefix"),
131                 cl::cat(AsmMatcherEmitterCat));
132 
133 namespace {
134 class AsmMatcherInfo;
135 
136 // Register sets are used as keys in some second-order sets TableGen creates
137 // when generating its data structures. This means that the order of two
138 // RegisterSets can be seen in the outputted AsmMatcher tables occasionally, and
139 // can even affect compiler output (at least seen in diagnostics produced when
140 // all matches fail). So we use a type that sorts them consistently.
141 typedef std::set<Record*, LessRecordByID> RegisterSet;
142 
143 class AsmMatcherEmitter {
144   RecordKeeper &Records;
145 public:
146   AsmMatcherEmitter(RecordKeeper &R) : Records(R) {}
147 
148   void run(raw_ostream &o);
149 };
150 
151 /// ClassInfo - Helper class for storing the information about a particular
152 /// class of operands which can be matched.
153 struct ClassInfo {
154   enum ClassInfoKind {
155     /// Invalid kind, for use as a sentinel value.
156     Invalid = 0,
157 
158     /// The class for a particular token.
159     Token,
160 
161     /// The (first) register class, subsequent register classes are
162     /// RegisterClass0+1, and so on.
163     RegisterClass0,
164 
165     /// The (first) user defined class, subsequent user defined classes are
166     /// UserClass0+1, and so on.
167     UserClass0 = 1<<16
168   };
169 
170   /// Kind - The class kind, which is either a predefined kind, or (UserClass0 +
171   /// N) for the Nth user defined class.
172   unsigned Kind;
173 
174   /// SuperClasses - The super classes of this class. Note that for simplicities
175   /// sake user operands only record their immediate super class, while register
176   /// operands include all superclasses.
177   std::vector<ClassInfo*> SuperClasses;
178 
179   /// Name - The full class name, suitable for use in an enum.
180   std::string Name;
181 
182   /// ClassName - The unadorned generic name for this class (e.g., Token).
183   std::string ClassName;
184 
185   /// ValueName - The name of the value this class represents; for a token this
186   /// is the literal token string, for an operand it is the TableGen class (or
187   /// empty if this is a derived class).
188   std::string ValueName;
189 
190   /// PredicateMethod - The name of the operand method to test whether the
191   /// operand matches this class; this is not valid for Token or register kinds.
192   std::string PredicateMethod;
193 
194   /// RenderMethod - The name of the operand method to add this operand to an
195   /// MCInst; this is not valid for Token or register kinds.
196   std::string RenderMethod;
197 
198   /// ParserMethod - The name of the operand method to do a target specific
199   /// parsing on the operand.
200   std::string ParserMethod;
201 
202   /// For register classes: the records for all the registers in this class.
203   RegisterSet Registers;
204 
205   /// For custom match classes: the diagnostic kind for when the predicate fails.
206   std::string DiagnosticType;
207 
208   /// For custom match classes: the diagnostic string for when the predicate fails.
209   std::string DiagnosticString;
210 
211   /// Is this operand optional and not always required.
212   bool IsOptional;
213 
214   /// DefaultMethod - The name of the method that returns the default operand
215   /// for optional operand
216   std::string DefaultMethod;
217 
218 public:
219   /// isRegisterClass() - Check if this is a register class.
220   bool isRegisterClass() const {
221     return Kind >= RegisterClass0 && Kind < UserClass0;
222   }
223 
224   /// isUserClass() - Check if this is a user defined class.
225   bool isUserClass() const {
226     return Kind >= UserClass0;
227   }
228 
229   /// isRelatedTo - Check whether this class is "related" to \p RHS. Classes
230   /// are related if they are in the same class hierarchy.
231   bool isRelatedTo(const ClassInfo &RHS) const {
232     // Tokens are only related to tokens.
233     if (Kind == Token || RHS.Kind == Token)
234       return Kind == Token && RHS.Kind == Token;
235 
236     // Registers classes are only related to registers classes, and only if
237     // their intersection is non-empty.
238     if (isRegisterClass() || RHS.isRegisterClass()) {
239       if (!isRegisterClass() || !RHS.isRegisterClass())
240         return false;
241 
242       RegisterSet Tmp;
243       std::insert_iterator<RegisterSet> II(Tmp, Tmp.begin());
244       std::set_intersection(Registers.begin(), Registers.end(),
245                             RHS.Registers.begin(), RHS.Registers.end(),
246                             II, LessRecordByID());
247 
248       return !Tmp.empty();
249     }
250 
251     // Otherwise we have two users operands; they are related if they are in the
252     // same class hierarchy.
253     //
254     // FIXME: This is an oversimplification, they should only be related if they
255     // intersect, however we don't have that information.
256     assert(isUserClass() && RHS.isUserClass() && "Unexpected class!");
257     const ClassInfo *Root = this;
258     while (!Root->SuperClasses.empty())
259       Root = Root->SuperClasses.front();
260 
261     const ClassInfo *RHSRoot = &RHS;
262     while (!RHSRoot->SuperClasses.empty())
263       RHSRoot = RHSRoot->SuperClasses.front();
264 
265     return Root == RHSRoot;
266   }
267 
268   /// isSubsetOf - Test whether this class is a subset of \p RHS.
269   bool isSubsetOf(const ClassInfo &RHS) const {
270     // This is a subset of RHS if it is the same class...
271     if (this == &RHS)
272       return true;
273 
274     // ... or if any of its super classes are a subset of RHS.
275     SmallVector<const ClassInfo *, 16> Worklist(SuperClasses.begin(),
276                                                 SuperClasses.end());
277     SmallPtrSet<const ClassInfo *, 16> Visited;
278     while (!Worklist.empty()) {
279       auto *CI = Worklist.pop_back_val();
280       if (CI == &RHS)
281         return true;
282       for (auto *Super : CI->SuperClasses)
283         if (Visited.insert(Super).second)
284           Worklist.push_back(Super);
285     }
286 
287     return false;
288   }
289 
290   int getTreeDepth() const {
291     int Depth = 0;
292     const ClassInfo *Root = this;
293     while (!Root->SuperClasses.empty()) {
294       Depth++;
295       Root = Root->SuperClasses.front();
296     }
297     return Depth;
298   }
299 
300   const ClassInfo *findRoot() const {
301     const ClassInfo *Root = this;
302     while (!Root->SuperClasses.empty())
303       Root = Root->SuperClasses.front();
304     return Root;
305   }
306 
307   /// Compare two classes. This does not produce a total ordering, but does
308   /// guarantee that subclasses are sorted before their parents, and that the
309   /// ordering is transitive.
310   bool operator<(const ClassInfo &RHS) const {
311     if (this == &RHS)
312       return false;
313 
314     // First, enforce the ordering between the three different types of class.
315     // Tokens sort before registers, which sort before user classes.
316     if (Kind == Token) {
317       if (RHS.Kind != Token)
318         return true;
319       assert(RHS.Kind == Token);
320     } else if (isRegisterClass()) {
321       if (RHS.Kind == Token)
322         return false;
323       else if (RHS.isUserClass())
324         return true;
325       assert(RHS.isRegisterClass());
326     } else if (isUserClass()) {
327       if (!RHS.isUserClass())
328         return false;
329       assert(RHS.isUserClass());
330     } else {
331       llvm_unreachable("Unknown ClassInfoKind");
332     }
333 
334     if (Kind == Token || isUserClass()) {
335       // Related tokens and user classes get sorted by depth in the inheritence
336       // tree (so that subclasses are before their parents).
337       if (isRelatedTo(RHS)) {
338         if (getTreeDepth() > RHS.getTreeDepth())
339           return true;
340         if (getTreeDepth() < RHS.getTreeDepth())
341           return false;
342       } else {
343         // Unrelated tokens and user classes are ordered by the name of their
344         // root nodes, so that there is a consistent ordering between
345         // unconnected trees.
346         return findRoot()->ValueName < RHS.findRoot()->ValueName;
347       }
348     } else if (isRegisterClass()) {
349       // For register sets, sort by number of registers. This guarantees that
350       // a set will always sort before all of it's strict supersets.
351       if (Registers.size() != RHS.Registers.size())
352         return Registers.size() < RHS.Registers.size();
353     } else {
354       llvm_unreachable("Unknown ClassInfoKind");
355     }
356 
357     // FIXME: We should be able to just return false here, as we only need a
358     // partial order (we use stable sorts, so this is deterministic) and the
359     // name of a class shouldn't be significant. However, some of the backends
360     // accidentally rely on this behaviour, so it will have to stay like this
361     // until they are fixed.
362     return ValueName < RHS.ValueName;
363   }
364 };
365 
366 class AsmVariantInfo {
367 public:
368   StringRef RegisterPrefix;
369   StringRef TokenizingCharacters;
370   StringRef SeparatorCharacters;
371   StringRef BreakCharacters;
372   StringRef Name;
373   int AsmVariantNo;
374 };
375 
376 /// MatchableInfo - Helper class for storing the necessary information for an
377 /// instruction or alias which is capable of being matched.
378 struct MatchableInfo {
379   struct AsmOperand {
380     /// Token - This is the token that the operand came from.
381     StringRef Token;
382 
383     /// The unique class instance this operand should match.
384     ClassInfo *Class;
385 
386     /// The operand name this is, if anything.
387     StringRef SrcOpName;
388 
389     /// The operand name this is, before renaming for tied operands.
390     StringRef OrigSrcOpName;
391 
392     /// The suboperand index within SrcOpName, or -1 for the entire operand.
393     int SubOpIdx;
394 
395     /// Whether the token is "isolated", i.e., it is preceded and followed
396     /// by separators.
397     bool IsIsolatedToken;
398 
399     /// Register record if this token is singleton register.
400     Record *SingletonReg;
401 
402     explicit AsmOperand(bool IsIsolatedToken, StringRef T)
403         : Token(T), Class(nullptr), SubOpIdx(-1),
404           IsIsolatedToken(IsIsolatedToken), SingletonReg(nullptr) {}
405   };
406 
407   /// ResOperand - This represents a single operand in the result instruction
408   /// generated by the match.  In cases (like addressing modes) where a single
409   /// assembler operand expands to multiple MCOperands, this represents the
410   /// single assembler operand, not the MCOperand.
411   struct ResOperand {
412     enum {
413       /// RenderAsmOperand - This represents an operand result that is
414       /// generated by calling the render method on the assembly operand.  The
415       /// corresponding AsmOperand is specified by AsmOperandNum.
416       RenderAsmOperand,
417 
418       /// TiedOperand - This represents a result operand that is a duplicate of
419       /// a previous result operand.
420       TiedOperand,
421 
422       /// ImmOperand - This represents an immediate value that is dumped into
423       /// the operand.
424       ImmOperand,
425 
426       /// RegOperand - This represents a fixed register that is dumped in.
427       RegOperand
428     } Kind;
429 
430     /// Tuple containing the index of the (earlier) result operand that should
431     /// be copied from, as well as the indices of the corresponding (parsed)
432     /// operands in the asm string.
433     struct TiedOperandsTuple {
434       unsigned ResOpnd;
435       unsigned SrcOpnd1Idx;
436       unsigned SrcOpnd2Idx;
437     };
438 
439     union {
440       /// This is the operand # in the AsmOperands list that this should be
441       /// copied from.
442       unsigned AsmOperandNum;
443 
444       /// Description of tied operands.
445       TiedOperandsTuple TiedOperands;
446 
447       /// ImmVal - This is the immediate value added to the instruction.
448       int64_t ImmVal;
449 
450       /// Register - This is the register record.
451       Record *Register;
452     };
453 
454     /// MINumOperands - The number of MCInst operands populated by this
455     /// operand.
456     unsigned MINumOperands;
457 
458     static ResOperand getRenderedOp(unsigned AsmOpNum, unsigned NumOperands) {
459       ResOperand X;
460       X.Kind = RenderAsmOperand;
461       X.AsmOperandNum = AsmOpNum;
462       X.MINumOperands = NumOperands;
463       return X;
464     }
465 
466     static ResOperand getTiedOp(unsigned TiedOperandNum, unsigned SrcOperand1,
467                                 unsigned SrcOperand2) {
468       ResOperand X;
469       X.Kind = TiedOperand;
470       X.TiedOperands = { TiedOperandNum, SrcOperand1, SrcOperand2 };
471       X.MINumOperands = 1;
472       return X;
473     }
474 
475     static ResOperand getImmOp(int64_t Val) {
476       ResOperand X;
477       X.Kind = ImmOperand;
478       X.ImmVal = Val;
479       X.MINumOperands = 1;
480       return X;
481     }
482 
483     static ResOperand getRegOp(Record *Reg) {
484       ResOperand X;
485       X.Kind = RegOperand;
486       X.Register = Reg;
487       X.MINumOperands = 1;
488       return X;
489     }
490   };
491 
492   /// AsmVariantID - Target's assembly syntax variant no.
493   int AsmVariantID;
494 
495   /// AsmString - The assembly string for this instruction (with variants
496   /// removed), e.g. "movsx $src, $dst".
497   std::string AsmString;
498 
499   /// TheDef - This is the definition of the instruction or InstAlias that this
500   /// matchable came from.
501   Record *const TheDef;
502 
503   /// DefRec - This is the definition that it came from.
504   PointerUnion<const CodeGenInstruction*, const CodeGenInstAlias*> DefRec;
505 
506   const CodeGenInstruction *getResultInst() const {
507     if (DefRec.is<const CodeGenInstruction*>())
508       return DefRec.get<const CodeGenInstruction*>();
509     return DefRec.get<const CodeGenInstAlias*>()->ResultInst;
510   }
511 
512   /// ResOperands - This is the operand list that should be built for the result
513   /// MCInst.
514   SmallVector<ResOperand, 8> ResOperands;
515 
516   /// Mnemonic - This is the first token of the matched instruction, its
517   /// mnemonic.
518   StringRef Mnemonic;
519 
520   /// AsmOperands - The textual operands that this instruction matches,
521   /// annotated with a class and where in the OperandList they were defined.
522   /// This directly corresponds to the tokenized AsmString after the mnemonic is
523   /// removed.
524   SmallVector<AsmOperand, 8> AsmOperands;
525 
526   /// Predicates - The required subtarget features to match this instruction.
527   SmallVector<const SubtargetFeatureInfo *, 4> RequiredFeatures;
528 
529   /// ConversionFnKind - The enum value which is passed to the generated
530   /// convertToMCInst to convert parsed operands into an MCInst for this
531   /// function.
532   std::string ConversionFnKind;
533 
534   /// If this instruction is deprecated in some form.
535   bool HasDeprecation;
536 
537   /// If this is an alias, this is use to determine whether or not to using
538   /// the conversion function defined by the instruction's AsmMatchConverter
539   /// or to use the function generated by the alias.
540   bool UseInstAsmMatchConverter;
541 
542   MatchableInfo(const CodeGenInstruction &CGI)
543     : AsmVariantID(0), AsmString(CGI.AsmString), TheDef(CGI.TheDef), DefRec(&CGI),
544       UseInstAsmMatchConverter(true) {
545   }
546 
547   MatchableInfo(std::unique_ptr<const CodeGenInstAlias> Alias)
548     : AsmVariantID(0), AsmString(Alias->AsmString), TheDef(Alias->TheDef),
549       DefRec(Alias.release()),
550       UseInstAsmMatchConverter(
551         TheDef->getValueAsBit("UseInstAsmMatchConverter")) {
552   }
553 
554   // Could remove this and the dtor if PointerUnion supported unique_ptr
555   // elements with a dynamic failure/assertion (like the one below) in the case
556   // where it was copied while being in an owning state.
557   MatchableInfo(const MatchableInfo &RHS)
558       : AsmVariantID(RHS.AsmVariantID), AsmString(RHS.AsmString),
559         TheDef(RHS.TheDef), DefRec(RHS.DefRec), ResOperands(RHS.ResOperands),
560         Mnemonic(RHS.Mnemonic), AsmOperands(RHS.AsmOperands),
561         RequiredFeatures(RHS.RequiredFeatures),
562         ConversionFnKind(RHS.ConversionFnKind),
563         HasDeprecation(RHS.HasDeprecation),
564         UseInstAsmMatchConverter(RHS.UseInstAsmMatchConverter) {
565     assert(!DefRec.is<const CodeGenInstAlias *>());
566   }
567 
568   ~MatchableInfo() {
569     delete DefRec.dyn_cast<const CodeGenInstAlias*>();
570   }
571 
572   // Two-operand aliases clone from the main matchable, but mark the second
573   // operand as a tied operand of the first for purposes of the assembler.
574   void formTwoOperandAlias(StringRef Constraint);
575 
576   void initialize(const AsmMatcherInfo &Info,
577                   SmallPtrSetImpl<Record*> &SingletonRegisters,
578                   AsmVariantInfo const &Variant,
579                   bool HasMnemonicFirst);
580 
581   /// validate - Return true if this matchable is a valid thing to match against
582   /// and perform a bunch of validity checking.
583   bool validate(StringRef CommentDelimiter, bool IsAlias) const;
584 
585   /// findAsmOperand - Find the AsmOperand with the specified name and
586   /// suboperand index.
587   int findAsmOperand(StringRef N, int SubOpIdx) const {
588     auto I = find_if(AsmOperands, [&](const AsmOperand &Op) {
589       return Op.SrcOpName == N && Op.SubOpIdx == SubOpIdx;
590     });
591     return (I != AsmOperands.end()) ? I - AsmOperands.begin() : -1;
592   }
593 
594   /// findAsmOperandNamed - Find the first AsmOperand with the specified name.
595   /// This does not check the suboperand index.
596   int findAsmOperandNamed(StringRef N, int LastIdx = -1) const {
597     auto I = std::find_if(AsmOperands.begin() + LastIdx + 1, AsmOperands.end(),
598                      [&](const AsmOperand &Op) { return Op.SrcOpName == N; });
599     return (I != AsmOperands.end()) ? I - AsmOperands.begin() : -1;
600   }
601 
602   int findAsmOperandOriginallyNamed(StringRef N) const {
603     auto I =
604         find_if(AsmOperands,
605                 [&](const AsmOperand &Op) { return Op.OrigSrcOpName == N; });
606     return (I != AsmOperands.end()) ? I - AsmOperands.begin() : -1;
607   }
608 
609   void buildInstructionResultOperands();
610   void buildAliasResultOperands(bool AliasConstraintsAreChecked);
611 
612   /// operator< - Compare two matchables.
613   bool operator<(const MatchableInfo &RHS) const {
614     // The primary comparator is the instruction mnemonic.
615     if (int Cmp = Mnemonic.compare(RHS.Mnemonic))
616       return Cmp == -1;
617 
618     if (AsmOperands.size() != RHS.AsmOperands.size())
619       return AsmOperands.size() < RHS.AsmOperands.size();
620 
621     // Compare lexicographically by operand. The matcher validates that other
622     // orderings wouldn't be ambiguous using \see couldMatchAmbiguouslyWith().
623     for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
624       if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class)
625         return true;
626       if (*RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
627         return false;
628     }
629 
630     // Give matches that require more features higher precedence. This is useful
631     // because we cannot define AssemblerPredicates with the negation of
632     // processor features. For example, ARM v6 "nop" may be either a HINT or
633     // MOV. With v6, we want to match HINT. The assembler has no way to
634     // predicate MOV under "NoV6", but HINT will always match first because it
635     // requires V6 while MOV does not.
636     if (RequiredFeatures.size() != RHS.RequiredFeatures.size())
637       return RequiredFeatures.size() > RHS.RequiredFeatures.size();
638 
639     return false;
640   }
641 
642   /// couldMatchAmbiguouslyWith - Check whether this matchable could
643   /// ambiguously match the same set of operands as \p RHS (without being a
644   /// strictly superior match).
645   bool couldMatchAmbiguouslyWith(const MatchableInfo &RHS) const {
646     // The primary comparator is the instruction mnemonic.
647     if (Mnemonic != RHS.Mnemonic)
648       return false;
649 
650     // Different variants can't conflict.
651     if (AsmVariantID != RHS.AsmVariantID)
652       return false;
653 
654     // The number of operands is unambiguous.
655     if (AsmOperands.size() != RHS.AsmOperands.size())
656       return false;
657 
658     // Otherwise, make sure the ordering of the two instructions is unambiguous
659     // by checking that either (a) a token or operand kind discriminates them,
660     // or (b) the ordering among equivalent kinds is consistent.
661 
662     // Tokens and operand kinds are unambiguous (assuming a correct target
663     // specific parser).
664     for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i)
665       if (AsmOperands[i].Class->Kind != RHS.AsmOperands[i].Class->Kind ||
666           AsmOperands[i].Class->Kind == ClassInfo::Token)
667         if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class ||
668             *RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
669           return false;
670 
671     // Otherwise, this operand could commute if all operands are equivalent, or
672     // there is a pair of operands that compare less than and a pair that
673     // compare greater than.
674     bool HasLT = false, HasGT = false;
675     for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
676       if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class)
677         HasLT = true;
678       if (*RHS.AsmOperands[i].Class < *AsmOperands[i].Class)
679         HasGT = true;
680     }
681 
682     return HasLT == HasGT;
683   }
684 
685   void dump() const;
686 
687 private:
688   void tokenizeAsmString(AsmMatcherInfo const &Info,
689                          AsmVariantInfo const &Variant);
690   void addAsmOperand(StringRef Token, bool IsIsolatedToken = false);
691 };
692 
693 struct OperandMatchEntry {
694   unsigned OperandMask;
695   const MatchableInfo* MI;
696   ClassInfo *CI;
697 
698   static OperandMatchEntry create(const MatchableInfo *mi, ClassInfo *ci,
699                                   unsigned opMask) {
700     OperandMatchEntry X;
701     X.OperandMask = opMask;
702     X.CI = ci;
703     X.MI = mi;
704     return X;
705   }
706 };
707 
708 class AsmMatcherInfo {
709 public:
710   /// Tracked Records
711   RecordKeeper &Records;
712 
713   /// The tablegen AsmParser record.
714   Record *AsmParser;
715 
716   /// Target - The target information.
717   CodeGenTarget &Target;
718 
719   /// The classes which are needed for matching.
720   std::forward_list<ClassInfo> Classes;
721 
722   /// The information on the matchables to match.
723   std::vector<std::unique_ptr<MatchableInfo>> Matchables;
724 
725   /// Info for custom matching operands by user defined methods.
726   std::vector<OperandMatchEntry> OperandMatchInfo;
727 
728   /// Map of Register records to their class information.
729   typedef std::map<Record*, ClassInfo*, LessRecordByID> RegisterClassesTy;
730   RegisterClassesTy RegisterClasses;
731 
732   /// Map of Predicate records to their subtarget information.
733   std::map<Record *, SubtargetFeatureInfo, LessRecordByID> SubtargetFeatures;
734 
735   /// Map of AsmOperandClass records to their class information.
736   std::map<Record*, ClassInfo*> AsmOperandClasses;
737 
738   /// Map of RegisterClass records to their class information.
739   std::map<Record*, ClassInfo*> RegisterClassClasses;
740 
741 private:
742   /// Map of token to class information which has already been constructed.
743   std::map<std::string, ClassInfo*> TokenClasses;
744 
745 private:
746   /// getTokenClass - Lookup or create the class for the given token.
747   ClassInfo *getTokenClass(StringRef Token);
748 
749   /// getOperandClass - Lookup or create the class for the given operand.
750   ClassInfo *getOperandClass(const CGIOperandList::OperandInfo &OI,
751                              int SubOpIdx);
752   ClassInfo *getOperandClass(Record *Rec, int SubOpIdx);
753 
754   /// buildRegisterClasses - Build the ClassInfo* instances for register
755   /// classes.
756   void buildRegisterClasses(SmallPtrSetImpl<Record*> &SingletonRegisters);
757 
758   /// buildOperandClasses - Build the ClassInfo* instances for user defined
759   /// operand classes.
760   void buildOperandClasses();
761 
762   void buildInstructionOperandReference(MatchableInfo *II, StringRef OpName,
763                                         unsigned AsmOpIdx);
764   void buildAliasOperandReference(MatchableInfo *II, StringRef OpName,
765                                   MatchableInfo::AsmOperand &Op);
766 
767 public:
768   AsmMatcherInfo(Record *AsmParser,
769                  CodeGenTarget &Target,
770                  RecordKeeper &Records);
771 
772   /// Construct the various tables used during matching.
773   void buildInfo();
774 
775   /// buildOperandMatchInfo - Build the necessary information to handle user
776   /// defined operand parsing methods.
777   void buildOperandMatchInfo();
778 
779   /// getSubtargetFeature - Lookup or create the subtarget feature info for the
780   /// given operand.
781   const SubtargetFeatureInfo *getSubtargetFeature(Record *Def) const {
782     assert(Def->isSubClassOf("Predicate") && "Invalid predicate type!");
783     const auto &I = SubtargetFeatures.find(Def);
784     return I == SubtargetFeatures.end() ? nullptr : &I->second;
785   }
786 
787   RecordKeeper &getRecords() const {
788     return Records;
789   }
790 
791   bool hasOptionalOperands() const {
792     return find_if(Classes, [](const ClassInfo &Class) {
793              return Class.IsOptional;
794            }) != Classes.end();
795   }
796 };
797 
798 } // end anonymous namespace
799 
800 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
801 LLVM_DUMP_METHOD void MatchableInfo::dump() const {
802   errs() << TheDef->getName() << " -- " << "flattened:\"" << AsmString <<"\"\n";
803 
804   errs() << "  variant: " << AsmVariantID << "\n";
805 
806   for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) {
807     const AsmOperand &Op = AsmOperands[i];
808     errs() << "  op[" << i << "] = " << Op.Class->ClassName << " - ";
809     errs() << '\"' << Op.Token << "\"\n";
810   }
811 }
812 #endif
813 
814 static std::pair<StringRef, StringRef>
815 parseTwoOperandConstraint(StringRef S, ArrayRef<SMLoc> Loc) {
816   // Split via the '='.
817   std::pair<StringRef, StringRef> Ops = S.split('=');
818   if (Ops.second == "")
819     PrintFatalError(Loc, "missing '=' in two-operand alias constraint");
820   // Trim whitespace and the leading '$' on the operand names.
821   size_t start = Ops.first.find_first_of('$');
822   if (start == std::string::npos)
823     PrintFatalError(Loc, "expected '$' prefix on asm operand name");
824   Ops.first = Ops.first.slice(start + 1, std::string::npos);
825   size_t end = Ops.first.find_last_of(" \t");
826   Ops.first = Ops.first.slice(0, end);
827   // Now the second operand.
828   start = Ops.second.find_first_of('$');
829   if (start == std::string::npos)
830     PrintFatalError(Loc, "expected '$' prefix on asm operand name");
831   Ops.second = Ops.second.slice(start + 1, std::string::npos);
832   end = Ops.second.find_last_of(" \t");
833   Ops.first = Ops.first.slice(0, end);
834   return Ops;
835 }
836 
837 void MatchableInfo::formTwoOperandAlias(StringRef Constraint) {
838   // Figure out which operands are aliased and mark them as tied.
839   std::pair<StringRef, StringRef> Ops =
840     parseTwoOperandConstraint(Constraint, TheDef->getLoc());
841 
842   // Find the AsmOperands that refer to the operands we're aliasing.
843   int SrcAsmOperand = findAsmOperandNamed(Ops.first);
844   int DstAsmOperand = findAsmOperandNamed(Ops.second);
845   if (SrcAsmOperand == -1)
846     PrintFatalError(TheDef->getLoc(),
847                     "unknown source two-operand alias operand '" + Ops.first +
848                     "'.");
849   if (DstAsmOperand == -1)
850     PrintFatalError(TheDef->getLoc(),
851                     "unknown destination two-operand alias operand '" +
852                     Ops.second + "'.");
853 
854   // Find the ResOperand that refers to the operand we're aliasing away
855   // and update it to refer to the combined operand instead.
856   for (ResOperand &Op : ResOperands) {
857     if (Op.Kind == ResOperand::RenderAsmOperand &&
858         Op.AsmOperandNum == (unsigned)SrcAsmOperand) {
859       Op.AsmOperandNum = DstAsmOperand;
860       break;
861     }
862   }
863   // Remove the AsmOperand for the alias operand.
864   AsmOperands.erase(AsmOperands.begin() + SrcAsmOperand);
865   // Adjust the ResOperand references to any AsmOperands that followed
866   // the one we just deleted.
867   for (ResOperand &Op : ResOperands) {
868     switch(Op.Kind) {
869     default:
870       // Nothing to do for operands that don't reference AsmOperands.
871       break;
872     case ResOperand::RenderAsmOperand:
873       if (Op.AsmOperandNum > (unsigned)SrcAsmOperand)
874         --Op.AsmOperandNum;
875       break;
876     }
877   }
878 }
879 
880 /// extractSingletonRegisterForAsmOperand - Extract singleton register,
881 /// if present, from specified token.
882 static void
883 extractSingletonRegisterForAsmOperand(MatchableInfo::AsmOperand &Op,
884                                       const AsmMatcherInfo &Info,
885                                       StringRef RegisterPrefix) {
886   StringRef Tok = Op.Token;
887 
888   // If this token is not an isolated token, i.e., it isn't separated from
889   // other tokens (e.g. with whitespace), don't interpret it as a register name.
890   if (!Op.IsIsolatedToken)
891     return;
892 
893   if (RegisterPrefix.empty()) {
894     std::string LoweredTok = Tok.lower();
895     if (const CodeGenRegister *Reg = Info.Target.getRegisterByName(LoweredTok))
896       Op.SingletonReg = Reg->TheDef;
897     return;
898   }
899 
900   if (!Tok.startswith(RegisterPrefix))
901     return;
902 
903   StringRef RegName = Tok.substr(RegisterPrefix.size());
904   if (const CodeGenRegister *Reg = Info.Target.getRegisterByName(RegName))
905     Op.SingletonReg = Reg->TheDef;
906 
907   // If there is no register prefix (i.e. "%" in "%eax"), then this may
908   // be some random non-register token, just ignore it.
909 }
910 
911 void MatchableInfo::initialize(const AsmMatcherInfo &Info,
912                                SmallPtrSetImpl<Record*> &SingletonRegisters,
913                                AsmVariantInfo const &Variant,
914                                bool HasMnemonicFirst) {
915   AsmVariantID = Variant.AsmVariantNo;
916   AsmString =
917     CodeGenInstruction::FlattenAsmStringVariants(AsmString,
918                                                  Variant.AsmVariantNo);
919 
920   tokenizeAsmString(Info, Variant);
921 
922   // The first token of the instruction is the mnemonic, which must be a
923   // simple string, not a $foo variable or a singleton register.
924   if (AsmOperands.empty())
925     PrintFatalError(TheDef->getLoc(),
926                   "Instruction '" + TheDef->getName() + "' has no tokens");
927 
928   assert(!AsmOperands[0].Token.empty());
929   if (HasMnemonicFirst) {
930     Mnemonic = AsmOperands[0].Token;
931     if (Mnemonic[0] == '$')
932       PrintFatalError(TheDef->getLoc(),
933                       "Invalid instruction mnemonic '" + Mnemonic + "'!");
934 
935     // Remove the first operand, it is tracked in the mnemonic field.
936     AsmOperands.erase(AsmOperands.begin());
937   } else if (AsmOperands[0].Token[0] != '$')
938     Mnemonic = AsmOperands[0].Token;
939 
940   // Compute the require features.
941   for (Record *Predicate : TheDef->getValueAsListOfDefs("Predicates"))
942     if (const SubtargetFeatureInfo *Feature =
943             Info.getSubtargetFeature(Predicate))
944       RequiredFeatures.push_back(Feature);
945 
946   // Collect singleton registers, if used.
947   for (MatchableInfo::AsmOperand &Op : AsmOperands) {
948     extractSingletonRegisterForAsmOperand(Op, Info, Variant.RegisterPrefix);
949     if (Record *Reg = Op.SingletonReg)
950       SingletonRegisters.insert(Reg);
951   }
952 
953   const RecordVal *DepMask = TheDef->getValue("DeprecatedFeatureMask");
954   if (!DepMask)
955     DepMask = TheDef->getValue("ComplexDeprecationPredicate");
956 
957   HasDeprecation =
958       DepMask ? !DepMask->getValue()->getAsUnquotedString().empty() : false;
959 }
960 
961 /// Append an AsmOperand for the given substring of AsmString.
962 void MatchableInfo::addAsmOperand(StringRef Token, bool IsIsolatedToken) {
963   AsmOperands.push_back(AsmOperand(IsIsolatedToken, Token));
964 }
965 
966 /// tokenizeAsmString - Tokenize a simplified assembly string.
967 void MatchableInfo::tokenizeAsmString(const AsmMatcherInfo &Info,
968                                       AsmVariantInfo const &Variant) {
969   StringRef String = AsmString;
970   size_t Prev = 0;
971   bool InTok = false;
972   bool IsIsolatedToken = true;
973   for (size_t i = 0, e = String.size(); i != e; ++i) {
974     char Char = String[i];
975     if (Variant.BreakCharacters.find(Char) != std::string::npos) {
976       if (InTok) {
977         addAsmOperand(String.slice(Prev, i), false);
978         Prev = i;
979         IsIsolatedToken = false;
980       }
981       InTok = true;
982       continue;
983     }
984     if (Variant.TokenizingCharacters.find(Char) != std::string::npos) {
985       if (InTok) {
986         addAsmOperand(String.slice(Prev, i), IsIsolatedToken);
987         InTok = false;
988         IsIsolatedToken = false;
989       }
990       addAsmOperand(String.slice(i, i + 1), IsIsolatedToken);
991       Prev = i + 1;
992       IsIsolatedToken = true;
993       continue;
994     }
995     if (Variant.SeparatorCharacters.find(Char) != std::string::npos) {
996       if (InTok) {
997         addAsmOperand(String.slice(Prev, i), IsIsolatedToken);
998         InTok = false;
999       }
1000       Prev = i + 1;
1001       IsIsolatedToken = true;
1002       continue;
1003     }
1004 
1005     switch (Char) {
1006     case '\\':
1007       if (InTok) {
1008         addAsmOperand(String.slice(Prev, i), false);
1009         InTok = false;
1010         IsIsolatedToken = false;
1011       }
1012       ++i;
1013       assert(i != String.size() && "Invalid quoted character");
1014       addAsmOperand(String.slice(i, i + 1), IsIsolatedToken);
1015       Prev = i + 1;
1016       IsIsolatedToken = false;
1017       break;
1018 
1019     case '$': {
1020       if (InTok) {
1021         addAsmOperand(String.slice(Prev, i), false);
1022         InTok = false;
1023         IsIsolatedToken = false;
1024       }
1025 
1026       // If this isn't "${", start new identifier looking like "$xxx"
1027       if (i + 1 == String.size() || String[i + 1] != '{') {
1028         Prev = i;
1029         break;
1030       }
1031 
1032       size_t EndPos = String.find('}', i);
1033       assert(EndPos != StringRef::npos &&
1034              "Missing brace in operand reference!");
1035       addAsmOperand(String.slice(i, EndPos+1), IsIsolatedToken);
1036       Prev = EndPos + 1;
1037       i = EndPos;
1038       IsIsolatedToken = false;
1039       break;
1040     }
1041 
1042     default:
1043       InTok = true;
1044       break;
1045     }
1046   }
1047   if (InTok && Prev != String.size())
1048     addAsmOperand(String.substr(Prev), IsIsolatedToken);
1049 }
1050 
1051 bool MatchableInfo::validate(StringRef CommentDelimiter, bool IsAlias) const {
1052   // Reject matchables with no .s string.
1053   if (AsmString.empty())
1054     PrintFatalError(TheDef->getLoc(), "instruction with empty asm string");
1055 
1056   // Reject any matchables with a newline in them, they should be marked
1057   // isCodeGenOnly if they are pseudo instructions.
1058   if (AsmString.find('\n') != std::string::npos)
1059     PrintFatalError(TheDef->getLoc(),
1060                   "multiline instruction is not valid for the asmparser, "
1061                   "mark it isCodeGenOnly");
1062 
1063   // Remove comments from the asm string.  We know that the asmstring only
1064   // has one line.
1065   if (!CommentDelimiter.empty() &&
1066       StringRef(AsmString).find(CommentDelimiter) != StringRef::npos)
1067     PrintFatalError(TheDef->getLoc(),
1068                   "asmstring for instruction has comment character in it, "
1069                   "mark it isCodeGenOnly");
1070 
1071   // Reject matchables with operand modifiers, these aren't something we can
1072   // handle, the target should be refactored to use operands instead of
1073   // modifiers.
1074   //
1075   // Also, check for instructions which reference the operand multiple times,
1076   // if they don't define a custom AsmMatcher: this implies a constraint that
1077   // the built-in matching code would not honor.
1078   std::set<std::string> OperandNames;
1079   for (const AsmOperand &Op : AsmOperands) {
1080     StringRef Tok = Op.Token;
1081     if (Tok[0] == '$' && Tok.find(':') != StringRef::npos)
1082       PrintFatalError(TheDef->getLoc(),
1083                       "matchable with operand modifier '" + Tok +
1084                       "' not supported by asm matcher.  Mark isCodeGenOnly!");
1085     // Verify that any operand is only mentioned once.
1086     // We reject aliases and ignore instructions for now.
1087     if (!IsAlias && TheDef->getValueAsString("AsmMatchConverter").empty() &&
1088         Tok[0] == '$' && !OperandNames.insert(Tok).second) {
1089       LLVM_DEBUG({
1090         errs() << "warning: '" << TheDef->getName() << "': "
1091                << "ignoring instruction with tied operand '"
1092                << Tok << "'\n";
1093       });
1094       return false;
1095     }
1096   }
1097 
1098   return true;
1099 }
1100 
1101 static std::string getEnumNameForToken(StringRef Str) {
1102   std::string Res;
1103 
1104   for (StringRef::iterator it = Str.begin(), ie = Str.end(); it != ie; ++it) {
1105     switch (*it) {
1106     case '*': Res += "_STAR_"; break;
1107     case '%': Res += "_PCT_"; break;
1108     case ':': Res += "_COLON_"; break;
1109     case '!': Res += "_EXCLAIM_"; break;
1110     case '.': Res += "_DOT_"; break;
1111     case '<': Res += "_LT_"; break;
1112     case '>': Res += "_GT_"; break;
1113     case '-': Res += "_MINUS_"; break;
1114     case '#': Res += "_HASH_"; break;
1115     default:
1116       if ((*it >= 'A' && *it <= 'Z') ||
1117           (*it >= 'a' && *it <= 'z') ||
1118           (*it >= '0' && *it <= '9'))
1119         Res += *it;
1120       else
1121         Res += "_" + utostr((unsigned) *it) + "_";
1122     }
1123   }
1124 
1125   return Res;
1126 }
1127 
1128 ClassInfo *AsmMatcherInfo::getTokenClass(StringRef Token) {
1129   ClassInfo *&Entry = TokenClasses[Token];
1130 
1131   if (!Entry) {
1132     Classes.emplace_front();
1133     Entry = &Classes.front();
1134     Entry->Kind = ClassInfo::Token;
1135     Entry->ClassName = "Token";
1136     Entry->Name = "MCK_" + getEnumNameForToken(Token);
1137     Entry->ValueName = Token;
1138     Entry->PredicateMethod = "<invalid>";
1139     Entry->RenderMethod = "<invalid>";
1140     Entry->ParserMethod = "";
1141     Entry->DiagnosticType = "";
1142     Entry->IsOptional = false;
1143     Entry->DefaultMethod = "<invalid>";
1144   }
1145 
1146   return Entry;
1147 }
1148 
1149 ClassInfo *
1150 AsmMatcherInfo::getOperandClass(const CGIOperandList::OperandInfo &OI,
1151                                 int SubOpIdx) {
1152   Record *Rec = OI.Rec;
1153   if (SubOpIdx != -1)
1154     Rec = cast<DefInit>(OI.MIOperandInfo->getArg(SubOpIdx))->getDef();
1155   return getOperandClass(Rec, SubOpIdx);
1156 }
1157 
1158 ClassInfo *
1159 AsmMatcherInfo::getOperandClass(Record *Rec, int SubOpIdx) {
1160   if (Rec->isSubClassOf("RegisterOperand")) {
1161     // RegisterOperand may have an associated ParserMatchClass. If it does,
1162     // use it, else just fall back to the underlying register class.
1163     const RecordVal *R = Rec->getValue("ParserMatchClass");
1164     if (!R || !R->getValue())
1165       PrintFatalError(Rec->getLoc(),
1166                       "Record `" + Rec->getName() +
1167                           "' does not have a ParserMatchClass!\n");
1168 
1169     if (DefInit *DI= dyn_cast<DefInit>(R->getValue())) {
1170       Record *MatchClass = DI->getDef();
1171       if (ClassInfo *CI = AsmOperandClasses[MatchClass])
1172         return CI;
1173     }
1174 
1175     // No custom match class. Just use the register class.
1176     Record *ClassRec = Rec->getValueAsDef("RegClass");
1177     if (!ClassRec)
1178       PrintFatalError(Rec->getLoc(), "RegisterOperand `" + Rec->getName() +
1179                     "' has no associated register class!\n");
1180     if (ClassInfo *CI = RegisterClassClasses[ClassRec])
1181       return CI;
1182     PrintFatalError(Rec->getLoc(), "register class has no class info!");
1183   }
1184 
1185   if (Rec->isSubClassOf("RegisterClass")) {
1186     if (ClassInfo *CI = RegisterClassClasses[Rec])
1187       return CI;
1188     PrintFatalError(Rec->getLoc(), "register class has no class info!");
1189   }
1190 
1191   if (!Rec->isSubClassOf("Operand"))
1192     PrintFatalError(Rec->getLoc(), "Operand `" + Rec->getName() +
1193                   "' does not derive from class Operand!\n");
1194   Record *MatchClass = Rec->getValueAsDef("ParserMatchClass");
1195   if (ClassInfo *CI = AsmOperandClasses[MatchClass])
1196     return CI;
1197 
1198   PrintFatalError(Rec->getLoc(), "operand has no match class!");
1199 }
1200 
1201 struct LessRegisterSet {
1202   bool operator() (const RegisterSet &LHS, const RegisterSet & RHS) const {
1203     // std::set<T> defines its own compariso "operator<", but it
1204     // performs a lexicographical comparison by T's innate comparison
1205     // for some reason. We don't want non-deterministic pointer
1206     // comparisons so use this instead.
1207     return std::lexicographical_compare(LHS.begin(), LHS.end(),
1208                                         RHS.begin(), RHS.end(),
1209                                         LessRecordByID());
1210   }
1211 };
1212 
1213 void AsmMatcherInfo::
1214 buildRegisterClasses(SmallPtrSetImpl<Record*> &SingletonRegisters) {
1215   const auto &Registers = Target.getRegBank().getRegisters();
1216   auto &RegClassList = Target.getRegBank().getRegClasses();
1217 
1218   typedef std::set<RegisterSet, LessRegisterSet> RegisterSetSet;
1219 
1220   // The register sets used for matching.
1221   RegisterSetSet RegisterSets;
1222 
1223   // Gather the defined sets.
1224   for (const CodeGenRegisterClass &RC : RegClassList)
1225     RegisterSets.insert(
1226         RegisterSet(RC.getOrder().begin(), RC.getOrder().end()));
1227 
1228   // Add any required singleton sets.
1229   for (Record *Rec : SingletonRegisters) {
1230     RegisterSets.insert(RegisterSet(&Rec, &Rec + 1));
1231   }
1232 
1233   // Introduce derived sets where necessary (when a register does not determine
1234   // a unique register set class), and build the mapping of registers to the set
1235   // they should classify to.
1236   std::map<Record*, RegisterSet> RegisterMap;
1237   for (const CodeGenRegister &CGR : Registers) {
1238     // Compute the intersection of all sets containing this register.
1239     RegisterSet ContainingSet;
1240 
1241     for (const RegisterSet &RS : RegisterSets) {
1242       if (!RS.count(CGR.TheDef))
1243         continue;
1244 
1245       if (ContainingSet.empty()) {
1246         ContainingSet = RS;
1247         continue;
1248       }
1249 
1250       RegisterSet Tmp;
1251       std::swap(Tmp, ContainingSet);
1252       std::insert_iterator<RegisterSet> II(ContainingSet,
1253                                            ContainingSet.begin());
1254       std::set_intersection(Tmp.begin(), Tmp.end(), RS.begin(), RS.end(), II,
1255                             LessRecordByID());
1256     }
1257 
1258     if (!ContainingSet.empty()) {
1259       RegisterSets.insert(ContainingSet);
1260       RegisterMap.insert(std::make_pair(CGR.TheDef, ContainingSet));
1261     }
1262   }
1263 
1264   // Construct the register classes.
1265   std::map<RegisterSet, ClassInfo*, LessRegisterSet> RegisterSetClasses;
1266   unsigned Index = 0;
1267   for (const RegisterSet &RS : RegisterSets) {
1268     Classes.emplace_front();
1269     ClassInfo *CI = &Classes.front();
1270     CI->Kind = ClassInfo::RegisterClass0 + Index;
1271     CI->ClassName = "Reg" + utostr(Index);
1272     CI->Name = "MCK_Reg" + utostr(Index);
1273     CI->ValueName = "";
1274     CI->PredicateMethod = ""; // unused
1275     CI->RenderMethod = "addRegOperands";
1276     CI->Registers = RS;
1277     // FIXME: diagnostic type.
1278     CI->DiagnosticType = "";
1279     CI->IsOptional = false;
1280     CI->DefaultMethod = ""; // unused
1281     RegisterSetClasses.insert(std::make_pair(RS, CI));
1282     ++Index;
1283   }
1284 
1285   // Find the superclasses; we could compute only the subgroup lattice edges,
1286   // but there isn't really a point.
1287   for (const RegisterSet &RS : RegisterSets) {
1288     ClassInfo *CI = RegisterSetClasses[RS];
1289     for (const RegisterSet &RS2 : RegisterSets)
1290       if (RS != RS2 &&
1291           std::includes(RS2.begin(), RS2.end(), RS.begin(), RS.end(),
1292                         LessRecordByID()))
1293         CI->SuperClasses.push_back(RegisterSetClasses[RS2]);
1294   }
1295 
1296   // Name the register classes which correspond to a user defined RegisterClass.
1297   for (const CodeGenRegisterClass &RC : RegClassList) {
1298     // Def will be NULL for non-user defined register classes.
1299     Record *Def = RC.getDef();
1300     if (!Def)
1301       continue;
1302     ClassInfo *CI = RegisterSetClasses[RegisterSet(RC.getOrder().begin(),
1303                                                    RC.getOrder().end())];
1304     if (CI->ValueName.empty()) {
1305       CI->ClassName = RC.getName();
1306       CI->Name = "MCK_" + RC.getName();
1307       CI->ValueName = RC.getName();
1308     } else
1309       CI->ValueName = CI->ValueName + "," + RC.getName();
1310 
1311     Init *DiagnosticType = Def->getValueInit("DiagnosticType");
1312     if (StringInit *SI = dyn_cast<StringInit>(DiagnosticType))
1313       CI->DiagnosticType = SI->getValue();
1314 
1315     Init *DiagnosticString = Def->getValueInit("DiagnosticString");
1316     if (StringInit *SI = dyn_cast<StringInit>(DiagnosticString))
1317       CI->DiagnosticString = SI->getValue();
1318 
1319     // If we have a diagnostic string but the diagnostic type is not specified
1320     // explicitly, create an anonymous diagnostic type.
1321     if (!CI->DiagnosticString.empty() && CI->DiagnosticType.empty())
1322       CI->DiagnosticType = RC.getName();
1323 
1324     RegisterClassClasses.insert(std::make_pair(Def, CI));
1325   }
1326 
1327   // Populate the map for individual registers.
1328   for (std::map<Record*, RegisterSet>::iterator it = RegisterMap.begin(),
1329          ie = RegisterMap.end(); it != ie; ++it)
1330     RegisterClasses[it->first] = RegisterSetClasses[it->second];
1331 
1332   // Name the register classes which correspond to singleton registers.
1333   for (Record *Rec : SingletonRegisters) {
1334     ClassInfo *CI = RegisterClasses[Rec];
1335     assert(CI && "Missing singleton register class info!");
1336 
1337     if (CI->ValueName.empty()) {
1338       CI->ClassName = Rec->getName();
1339       CI->Name = "MCK_" + Rec->getName().str();
1340       CI->ValueName = Rec->getName();
1341     } else
1342       CI->ValueName = CI->ValueName + "," + Rec->getName().str();
1343   }
1344 }
1345 
1346 void AsmMatcherInfo::buildOperandClasses() {
1347   std::vector<Record*> AsmOperands =
1348     Records.getAllDerivedDefinitions("AsmOperandClass");
1349 
1350   // Pre-populate AsmOperandClasses map.
1351   for (Record *Rec : AsmOperands) {
1352     Classes.emplace_front();
1353     AsmOperandClasses[Rec] = &Classes.front();
1354   }
1355 
1356   unsigned Index = 0;
1357   for (Record *Rec : AsmOperands) {
1358     ClassInfo *CI = AsmOperandClasses[Rec];
1359     CI->Kind = ClassInfo::UserClass0 + Index;
1360 
1361     ListInit *Supers = Rec->getValueAsListInit("SuperClasses");
1362     for (Init *I : Supers->getValues()) {
1363       DefInit *DI = dyn_cast<DefInit>(I);
1364       if (!DI) {
1365         PrintError(Rec->getLoc(), "Invalid super class reference!");
1366         continue;
1367       }
1368 
1369       ClassInfo *SC = AsmOperandClasses[DI->getDef()];
1370       if (!SC)
1371         PrintError(Rec->getLoc(), "Invalid super class reference!");
1372       else
1373         CI->SuperClasses.push_back(SC);
1374     }
1375     CI->ClassName = Rec->getValueAsString("Name");
1376     CI->Name = "MCK_" + CI->ClassName;
1377     CI->ValueName = Rec->getName();
1378 
1379     // Get or construct the predicate method name.
1380     Init *PMName = Rec->getValueInit("PredicateMethod");
1381     if (StringInit *SI = dyn_cast<StringInit>(PMName)) {
1382       CI->PredicateMethod = SI->getValue();
1383     } else {
1384       assert(isa<UnsetInit>(PMName) && "Unexpected PredicateMethod field!");
1385       CI->PredicateMethod = "is" + CI->ClassName;
1386     }
1387 
1388     // Get or construct the render method name.
1389     Init *RMName = Rec->getValueInit("RenderMethod");
1390     if (StringInit *SI = dyn_cast<StringInit>(RMName)) {
1391       CI->RenderMethod = SI->getValue();
1392     } else {
1393       assert(isa<UnsetInit>(RMName) && "Unexpected RenderMethod field!");
1394       CI->RenderMethod = "add" + CI->ClassName + "Operands";
1395     }
1396 
1397     // Get the parse method name or leave it as empty.
1398     Init *PRMName = Rec->getValueInit("ParserMethod");
1399     if (StringInit *SI = dyn_cast<StringInit>(PRMName))
1400       CI->ParserMethod = SI->getValue();
1401 
1402     // Get the diagnostic type and string or leave them as empty.
1403     Init *DiagnosticType = Rec->getValueInit("DiagnosticType");
1404     if (StringInit *SI = dyn_cast<StringInit>(DiagnosticType))
1405       CI->DiagnosticType = SI->getValue();
1406     Init *DiagnosticString = Rec->getValueInit("DiagnosticString");
1407     if (StringInit *SI = dyn_cast<StringInit>(DiagnosticString))
1408       CI->DiagnosticString = SI->getValue();
1409     // If we have a DiagnosticString, we need a DiagnosticType for use within
1410     // the matcher.
1411     if (!CI->DiagnosticString.empty() && CI->DiagnosticType.empty())
1412       CI->DiagnosticType = CI->ClassName;
1413 
1414     Init *IsOptional = Rec->getValueInit("IsOptional");
1415     if (BitInit *BI = dyn_cast<BitInit>(IsOptional))
1416       CI->IsOptional = BI->getValue();
1417 
1418     // Get or construct the default method name.
1419     Init *DMName = Rec->getValueInit("DefaultMethod");
1420     if (StringInit *SI = dyn_cast<StringInit>(DMName)) {
1421       CI->DefaultMethod = SI->getValue();
1422     } else {
1423       assert(isa<UnsetInit>(DMName) && "Unexpected DefaultMethod field!");
1424       CI->DefaultMethod = "default" + CI->ClassName + "Operands";
1425     }
1426 
1427     ++Index;
1428   }
1429 }
1430 
1431 AsmMatcherInfo::AsmMatcherInfo(Record *asmParser,
1432                                CodeGenTarget &target,
1433                                RecordKeeper &records)
1434   : Records(records), AsmParser(asmParser), Target(target) {
1435 }
1436 
1437 /// buildOperandMatchInfo - Build the necessary information to handle user
1438 /// defined operand parsing methods.
1439 void AsmMatcherInfo::buildOperandMatchInfo() {
1440 
1441   /// Map containing a mask with all operands indices that can be found for
1442   /// that class inside a instruction.
1443   typedef std::map<ClassInfo *, unsigned, deref<std::less<>>> OpClassMaskTy;
1444   OpClassMaskTy OpClassMask;
1445 
1446   for (const auto &MI : Matchables) {
1447     OpClassMask.clear();
1448 
1449     // Keep track of all operands of this instructions which belong to the
1450     // same class.
1451     for (unsigned i = 0, e = MI->AsmOperands.size(); i != e; ++i) {
1452       const MatchableInfo::AsmOperand &Op = MI->AsmOperands[i];
1453       if (Op.Class->ParserMethod.empty())
1454         continue;
1455       unsigned &OperandMask = OpClassMask[Op.Class];
1456       OperandMask |= (1 << i);
1457     }
1458 
1459     // Generate operand match info for each mnemonic/operand class pair.
1460     for (const auto &OCM : OpClassMask) {
1461       unsigned OpMask = OCM.second;
1462       ClassInfo *CI = OCM.first;
1463       OperandMatchInfo.push_back(OperandMatchEntry::create(MI.get(), CI,
1464                                                            OpMask));
1465     }
1466   }
1467 }
1468 
1469 void AsmMatcherInfo::buildInfo() {
1470   // Build information about all of the AssemblerPredicates.
1471   const std::vector<std::pair<Record *, SubtargetFeatureInfo>>
1472       &SubtargetFeaturePairs = SubtargetFeatureInfo::getAll(Records);
1473   SubtargetFeatures.insert(SubtargetFeaturePairs.begin(),
1474                            SubtargetFeaturePairs.end());
1475 #ifndef NDEBUG
1476   for (const auto &Pair : SubtargetFeatures)
1477     LLVM_DEBUG(Pair.second.dump());
1478 #endif // NDEBUG
1479 
1480   bool HasMnemonicFirst = AsmParser->getValueAsBit("HasMnemonicFirst");
1481   bool ReportMultipleNearMisses =
1482       AsmParser->getValueAsBit("ReportMultipleNearMisses");
1483 
1484   // Parse the instructions; we need to do this first so that we can gather the
1485   // singleton register classes.
1486   SmallPtrSet<Record*, 16> SingletonRegisters;
1487   unsigned VariantCount = Target.getAsmParserVariantCount();
1488   for (unsigned VC = 0; VC != VariantCount; ++VC) {
1489     Record *AsmVariant = Target.getAsmParserVariant(VC);
1490     StringRef CommentDelimiter =
1491         AsmVariant->getValueAsString("CommentDelimiter");
1492     AsmVariantInfo Variant;
1493     Variant.RegisterPrefix = AsmVariant->getValueAsString("RegisterPrefix");
1494     Variant.TokenizingCharacters =
1495         AsmVariant->getValueAsString("TokenizingCharacters");
1496     Variant.SeparatorCharacters =
1497         AsmVariant->getValueAsString("SeparatorCharacters");
1498     Variant.BreakCharacters =
1499         AsmVariant->getValueAsString("BreakCharacters");
1500     Variant.Name = AsmVariant->getValueAsString("Name");
1501     Variant.AsmVariantNo = AsmVariant->getValueAsInt("Variant");
1502 
1503     for (const CodeGenInstruction *CGI : Target.getInstructionsByEnumValue()) {
1504 
1505       // If the tblgen -match-prefix option is specified (for tblgen hackers),
1506       // filter the set of instructions we consider.
1507       if (!StringRef(CGI->TheDef->getName()).startswith(MatchPrefix))
1508         continue;
1509 
1510       // Ignore "codegen only" instructions.
1511       if (CGI->TheDef->getValueAsBit("isCodeGenOnly"))
1512         continue;
1513 
1514       // Ignore instructions for different instructions
1515       StringRef V = CGI->TheDef->getValueAsString("AsmVariantName");
1516       if (!V.empty() && V != Variant.Name)
1517         continue;
1518 
1519       auto II = std::make_unique<MatchableInfo>(*CGI);
1520 
1521       II->initialize(*this, SingletonRegisters, Variant, HasMnemonicFirst);
1522 
1523       // Ignore instructions which shouldn't be matched and diagnose invalid
1524       // instruction definitions with an error.
1525       if (!II->validate(CommentDelimiter, false))
1526         continue;
1527 
1528       Matchables.push_back(std::move(II));
1529     }
1530 
1531     // Parse all of the InstAlias definitions and stick them in the list of
1532     // matchables.
1533     std::vector<Record*> AllInstAliases =
1534       Records.getAllDerivedDefinitions("InstAlias");
1535     for (unsigned i = 0, e = AllInstAliases.size(); i != e; ++i) {
1536       auto Alias = std::make_unique<CodeGenInstAlias>(AllInstAliases[i],
1537                                                        Target);
1538 
1539       // If the tblgen -match-prefix option is specified (for tblgen hackers),
1540       // filter the set of instruction aliases we consider, based on the target
1541       // instruction.
1542       if (!StringRef(Alias->ResultInst->TheDef->getName())
1543             .startswith( MatchPrefix))
1544         continue;
1545 
1546       StringRef V = Alias->TheDef->getValueAsString("AsmVariantName");
1547       if (!V.empty() && V != Variant.Name)
1548         continue;
1549 
1550       auto II = std::make_unique<MatchableInfo>(std::move(Alias));
1551 
1552       II->initialize(*this, SingletonRegisters, Variant, HasMnemonicFirst);
1553 
1554       // Validate the alias definitions.
1555       II->validate(CommentDelimiter, true);
1556 
1557       Matchables.push_back(std::move(II));
1558     }
1559   }
1560 
1561   // Build info for the register classes.
1562   buildRegisterClasses(SingletonRegisters);
1563 
1564   // Build info for the user defined assembly operand classes.
1565   buildOperandClasses();
1566 
1567   // Build the information about matchables, now that we have fully formed
1568   // classes.
1569   std::vector<std::unique_ptr<MatchableInfo>> NewMatchables;
1570   for (auto &II : Matchables) {
1571     // Parse the tokens after the mnemonic.
1572     // Note: buildInstructionOperandReference may insert new AsmOperands, so
1573     // don't precompute the loop bound.
1574     for (unsigned i = 0; i != II->AsmOperands.size(); ++i) {
1575       MatchableInfo::AsmOperand &Op = II->AsmOperands[i];
1576       StringRef Token = Op.Token;
1577 
1578       // Check for singleton registers.
1579       if (Record *RegRecord = Op.SingletonReg) {
1580         Op.Class = RegisterClasses[RegRecord];
1581         assert(Op.Class && Op.Class->Registers.size() == 1 &&
1582                "Unexpected class for singleton register");
1583         continue;
1584       }
1585 
1586       // Check for simple tokens.
1587       if (Token[0] != '$') {
1588         Op.Class = getTokenClass(Token);
1589         continue;
1590       }
1591 
1592       if (Token.size() > 1 && isdigit(Token[1])) {
1593         Op.Class = getTokenClass(Token);
1594         continue;
1595       }
1596 
1597       // Otherwise this is an operand reference.
1598       StringRef OperandName;
1599       if (Token[1] == '{')
1600         OperandName = Token.substr(2, Token.size() - 3);
1601       else
1602         OperandName = Token.substr(1);
1603 
1604       if (II->DefRec.is<const CodeGenInstruction*>())
1605         buildInstructionOperandReference(II.get(), OperandName, i);
1606       else
1607         buildAliasOperandReference(II.get(), OperandName, Op);
1608     }
1609 
1610     if (II->DefRec.is<const CodeGenInstruction*>()) {
1611       II->buildInstructionResultOperands();
1612       // If the instruction has a two-operand alias, build up the
1613       // matchable here. We'll add them in bulk at the end to avoid
1614       // confusing this loop.
1615       StringRef Constraint =
1616           II->TheDef->getValueAsString("TwoOperandAliasConstraint");
1617       if (Constraint != "") {
1618         // Start by making a copy of the original matchable.
1619         auto AliasII = std::make_unique<MatchableInfo>(*II);
1620 
1621         // Adjust it to be a two-operand alias.
1622         AliasII->formTwoOperandAlias(Constraint);
1623 
1624         // Add the alias to the matchables list.
1625         NewMatchables.push_back(std::move(AliasII));
1626       }
1627     } else
1628       // FIXME: The tied operands checking is not yet integrated with the
1629       // framework for reporting multiple near misses. To prevent invalid
1630       // formats from being matched with an alias if a tied-operands check
1631       // would otherwise have disallowed it, we just disallow such constructs
1632       // in TableGen completely.
1633       II->buildAliasResultOperands(!ReportMultipleNearMisses);
1634   }
1635   if (!NewMatchables.empty())
1636     Matchables.insert(Matchables.end(),
1637                       std::make_move_iterator(NewMatchables.begin()),
1638                       std::make_move_iterator(NewMatchables.end()));
1639 
1640   // Process token alias definitions and set up the associated superclass
1641   // information.
1642   std::vector<Record*> AllTokenAliases =
1643     Records.getAllDerivedDefinitions("TokenAlias");
1644   for (Record *Rec : AllTokenAliases) {
1645     ClassInfo *FromClass = getTokenClass(Rec->getValueAsString("FromToken"));
1646     ClassInfo *ToClass = getTokenClass(Rec->getValueAsString("ToToken"));
1647     if (FromClass == ToClass)
1648       PrintFatalError(Rec->getLoc(),
1649                     "error: Destination value identical to source value.");
1650     FromClass->SuperClasses.push_back(ToClass);
1651   }
1652 
1653   // Reorder classes so that classes precede super classes.
1654   Classes.sort();
1655 
1656 #ifdef EXPENSIVE_CHECKS
1657   // Verify that the table is sorted and operator < works transitively.
1658   for (auto I = Classes.begin(), E = Classes.end(); I != E; ++I) {
1659     for (auto J = I; J != E; ++J) {
1660       assert(!(*J < *I));
1661       assert(I == J || !J->isSubsetOf(*I));
1662     }
1663   }
1664 #endif
1665 }
1666 
1667 /// buildInstructionOperandReference - The specified operand is a reference to a
1668 /// named operand such as $src.  Resolve the Class and OperandInfo pointers.
1669 void AsmMatcherInfo::
1670 buildInstructionOperandReference(MatchableInfo *II,
1671                                  StringRef OperandName,
1672                                  unsigned AsmOpIdx) {
1673   const CodeGenInstruction &CGI = *II->DefRec.get<const CodeGenInstruction*>();
1674   const CGIOperandList &Operands = CGI.Operands;
1675   MatchableInfo::AsmOperand *Op = &II->AsmOperands[AsmOpIdx];
1676 
1677   // Map this token to an operand.
1678   unsigned Idx;
1679   if (!Operands.hasOperandNamed(OperandName, Idx))
1680     PrintFatalError(II->TheDef->getLoc(),
1681                     "error: unable to find operand: '" + OperandName + "'");
1682 
1683   // If the instruction operand has multiple suboperands, but the parser
1684   // match class for the asm operand is still the default "ImmAsmOperand",
1685   // then handle each suboperand separately.
1686   if (Op->SubOpIdx == -1 && Operands[Idx].MINumOperands > 1) {
1687     Record *Rec = Operands[Idx].Rec;
1688     assert(Rec->isSubClassOf("Operand") && "Unexpected operand!");
1689     Record *MatchClass = Rec->getValueAsDef("ParserMatchClass");
1690     if (MatchClass && MatchClass->getValueAsString("Name") == "Imm") {
1691       // Insert remaining suboperands after AsmOpIdx in II->AsmOperands.
1692       StringRef Token = Op->Token; // save this in case Op gets moved
1693       for (unsigned SI = 1, SE = Operands[Idx].MINumOperands; SI != SE; ++SI) {
1694         MatchableInfo::AsmOperand NewAsmOp(/*IsIsolatedToken=*/true, Token);
1695         NewAsmOp.SubOpIdx = SI;
1696         II->AsmOperands.insert(II->AsmOperands.begin()+AsmOpIdx+SI, NewAsmOp);
1697       }
1698       // Replace Op with first suboperand.
1699       Op = &II->AsmOperands[AsmOpIdx]; // update the pointer in case it moved
1700       Op->SubOpIdx = 0;
1701     }
1702   }
1703 
1704   // Set up the operand class.
1705   Op->Class = getOperandClass(Operands[Idx], Op->SubOpIdx);
1706   Op->OrigSrcOpName = OperandName;
1707 
1708   // If the named operand is tied, canonicalize it to the untied operand.
1709   // For example, something like:
1710   //   (outs GPR:$dst), (ins GPR:$src)
1711   // with an asmstring of
1712   //   "inc $src"
1713   // we want to canonicalize to:
1714   //   "inc $dst"
1715   // so that we know how to provide the $dst operand when filling in the result.
1716   int OITied = -1;
1717   if (Operands[Idx].MINumOperands == 1)
1718     OITied = Operands[Idx].getTiedRegister();
1719   if (OITied != -1) {
1720     // The tied operand index is an MIOperand index, find the operand that
1721     // contains it.
1722     std::pair<unsigned, unsigned> Idx = Operands.getSubOperandNumber(OITied);
1723     OperandName = Operands[Idx.first].Name;
1724     Op->SubOpIdx = Idx.second;
1725   }
1726 
1727   Op->SrcOpName = OperandName;
1728 }
1729 
1730 /// buildAliasOperandReference - When parsing an operand reference out of the
1731 /// matching string (e.g. "movsx $src, $dst"), determine what the class of the
1732 /// operand reference is by looking it up in the result pattern definition.
1733 void AsmMatcherInfo::buildAliasOperandReference(MatchableInfo *II,
1734                                                 StringRef OperandName,
1735                                                 MatchableInfo::AsmOperand &Op) {
1736   const CodeGenInstAlias &CGA = *II->DefRec.get<const CodeGenInstAlias*>();
1737 
1738   // Set up the operand class.
1739   for (unsigned i = 0, e = CGA.ResultOperands.size(); i != e; ++i)
1740     if (CGA.ResultOperands[i].isRecord() &&
1741         CGA.ResultOperands[i].getName() == OperandName) {
1742       // It's safe to go with the first one we find, because CodeGenInstAlias
1743       // validates that all operands with the same name have the same record.
1744       Op.SubOpIdx = CGA.ResultInstOperandIndex[i].second;
1745       // Use the match class from the Alias definition, not the
1746       // destination instruction, as we may have an immediate that's
1747       // being munged by the match class.
1748       Op.Class = getOperandClass(CGA.ResultOperands[i].getRecord(),
1749                                  Op.SubOpIdx);
1750       Op.SrcOpName = OperandName;
1751       Op.OrigSrcOpName = OperandName;
1752       return;
1753     }
1754 
1755   PrintFatalError(II->TheDef->getLoc(),
1756                   "error: unable to find operand: '" + OperandName + "'");
1757 }
1758 
1759 void MatchableInfo::buildInstructionResultOperands() {
1760   const CodeGenInstruction *ResultInst = getResultInst();
1761 
1762   // Loop over all operands of the result instruction, determining how to
1763   // populate them.
1764   for (const CGIOperandList::OperandInfo &OpInfo : ResultInst->Operands) {
1765     // If this is a tied operand, just copy from the previously handled operand.
1766     int TiedOp = -1;
1767     if (OpInfo.MINumOperands == 1)
1768       TiedOp = OpInfo.getTiedRegister();
1769     if (TiedOp != -1) {
1770       int TiedSrcOperand = findAsmOperandOriginallyNamed(OpInfo.Name);
1771       if (TiedSrcOperand != -1 &&
1772           ResOperands[TiedOp].Kind == ResOperand::RenderAsmOperand)
1773         ResOperands.push_back(ResOperand::getTiedOp(
1774             TiedOp, ResOperands[TiedOp].AsmOperandNum, TiedSrcOperand));
1775       else
1776         ResOperands.push_back(ResOperand::getTiedOp(TiedOp, 0, 0));
1777       continue;
1778     }
1779 
1780     int SrcOperand = findAsmOperandNamed(OpInfo.Name);
1781     if (OpInfo.Name.empty() || SrcOperand == -1) {
1782       // This may happen for operands that are tied to a suboperand of a
1783       // complex operand.  Simply use a dummy value here; nobody should
1784       // use this operand slot.
1785       // FIXME: The long term goal is for the MCOperand list to not contain
1786       // tied operands at all.
1787       ResOperands.push_back(ResOperand::getImmOp(0));
1788       continue;
1789     }
1790 
1791     // Check if the one AsmOperand populates the entire operand.
1792     unsigned NumOperands = OpInfo.MINumOperands;
1793     if (AsmOperands[SrcOperand].SubOpIdx == -1) {
1794       ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand, NumOperands));
1795       continue;
1796     }
1797 
1798     // Add a separate ResOperand for each suboperand.
1799     for (unsigned AI = 0; AI < NumOperands; ++AI) {
1800       assert(AsmOperands[SrcOperand+AI].SubOpIdx == (int)AI &&
1801              AsmOperands[SrcOperand+AI].SrcOpName == OpInfo.Name &&
1802              "unexpected AsmOperands for suboperands");
1803       ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand + AI, 1));
1804     }
1805   }
1806 }
1807 
1808 void MatchableInfo::buildAliasResultOperands(bool AliasConstraintsAreChecked) {
1809   const CodeGenInstAlias &CGA = *DefRec.get<const CodeGenInstAlias*>();
1810   const CodeGenInstruction *ResultInst = getResultInst();
1811 
1812   // Map of:  $reg -> #lastref
1813   //   where $reg is the name of the operand in the asm string
1814   //   where #lastref is the last processed index where $reg was referenced in
1815   //   the asm string.
1816   SmallDenseMap<StringRef, int> OperandRefs;
1817 
1818   // Loop over all operands of the result instruction, determining how to
1819   // populate them.
1820   unsigned AliasOpNo = 0;
1821   unsigned LastOpNo = CGA.ResultInstOperandIndex.size();
1822   for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) {
1823     const CGIOperandList::OperandInfo *OpInfo = &ResultInst->Operands[i];
1824 
1825     // If this is a tied operand, just copy from the previously handled operand.
1826     int TiedOp = -1;
1827     if (OpInfo->MINumOperands == 1)
1828       TiedOp = OpInfo->getTiedRegister();
1829     if (TiedOp != -1) {
1830       unsigned SrcOp1 = 0;
1831       unsigned SrcOp2 = 0;
1832 
1833       // If an operand has been specified twice in the asm string,
1834       // add the two source operand's indices to the TiedOp so that
1835       // at runtime the 'tied' constraint is checked.
1836       if (ResOperands[TiedOp].Kind == ResOperand::RenderAsmOperand) {
1837         SrcOp1 = ResOperands[TiedOp].AsmOperandNum;
1838 
1839         // Find the next operand (similarly named operand) in the string.
1840         StringRef Name = AsmOperands[SrcOp1].SrcOpName;
1841         auto Insert = OperandRefs.try_emplace(Name, SrcOp1);
1842         SrcOp2 = findAsmOperandNamed(Name, Insert.first->second);
1843 
1844         // Not updating the record in OperandRefs will cause TableGen
1845         // to fail with an error at the end of this function.
1846         if (AliasConstraintsAreChecked)
1847           Insert.first->second = SrcOp2;
1848 
1849         // In case it only has one reference in the asm string,
1850         // it doesn't need to be checked for tied constraints.
1851         SrcOp2 = (SrcOp2 == (unsigned)-1) ? SrcOp1 : SrcOp2;
1852       }
1853 
1854       // If the alias operand is of a different operand class, we only want
1855       // to benefit from the tied-operands check and just match the operand
1856       // as a normal, but not copy the original (TiedOp) to the result
1857       // instruction. We do this by passing -1 as the tied operand to copy.
1858       if (ResultInst->Operands[i].Rec->getName() !=
1859           ResultInst->Operands[TiedOp].Rec->getName()) {
1860         SrcOp1 = ResOperands[TiedOp].AsmOperandNum;
1861         int SubIdx = CGA.ResultInstOperandIndex[AliasOpNo].second;
1862         StringRef Name = CGA.ResultOperands[AliasOpNo].getName();
1863         SrcOp2 = findAsmOperand(Name, SubIdx);
1864         ResOperands.push_back(
1865             ResOperand::getTiedOp((unsigned)-1, SrcOp1, SrcOp2));
1866       } else {
1867         ResOperands.push_back(ResOperand::getTiedOp(TiedOp, SrcOp1, SrcOp2));
1868         continue;
1869       }
1870     }
1871 
1872     // Handle all the suboperands for this operand.
1873     const std::string &OpName = OpInfo->Name;
1874     for ( ; AliasOpNo <  LastOpNo &&
1875             CGA.ResultInstOperandIndex[AliasOpNo].first == i; ++AliasOpNo) {
1876       int SubIdx = CGA.ResultInstOperandIndex[AliasOpNo].second;
1877 
1878       // Find out what operand from the asmparser that this MCInst operand
1879       // comes from.
1880       switch (CGA.ResultOperands[AliasOpNo].Kind) {
1881       case CodeGenInstAlias::ResultOperand::K_Record: {
1882         StringRef Name = CGA.ResultOperands[AliasOpNo].getName();
1883         int SrcOperand = findAsmOperand(Name, SubIdx);
1884         if (SrcOperand == -1)
1885           PrintFatalError(TheDef->getLoc(), "Instruction '" +
1886                         TheDef->getName() + "' has operand '" + OpName +
1887                         "' that doesn't appear in asm string!");
1888 
1889         // Add it to the operand references. If it is added a second time, the
1890         // record won't be updated and it will fail later on.
1891         OperandRefs.try_emplace(Name, SrcOperand);
1892 
1893         unsigned NumOperands = (SubIdx == -1 ? OpInfo->MINumOperands : 1);
1894         ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand,
1895                                                         NumOperands));
1896         break;
1897       }
1898       case CodeGenInstAlias::ResultOperand::K_Imm: {
1899         int64_t ImmVal = CGA.ResultOperands[AliasOpNo].getImm();
1900         ResOperands.push_back(ResOperand::getImmOp(ImmVal));
1901         break;
1902       }
1903       case CodeGenInstAlias::ResultOperand::K_Reg: {
1904         Record *Reg = CGA.ResultOperands[AliasOpNo].getRegister();
1905         ResOperands.push_back(ResOperand::getRegOp(Reg));
1906         break;
1907       }
1908       }
1909     }
1910   }
1911 
1912   // Check that operands are not repeated more times than is supported.
1913   for (auto &T : OperandRefs) {
1914     if (T.second != -1 && findAsmOperandNamed(T.first, T.second) != -1)
1915       PrintFatalError(TheDef->getLoc(),
1916                       "Operand '" + T.first + "' can never be matched");
1917   }
1918 }
1919 
1920 static unsigned
1921 getConverterOperandID(const std::string &Name,
1922                       SmallSetVector<CachedHashString, 16> &Table,
1923                       bool &IsNew) {
1924   IsNew = Table.insert(CachedHashString(Name));
1925 
1926   unsigned ID = IsNew ? Table.size() - 1 : find(Table, Name) - Table.begin();
1927 
1928   assert(ID < Table.size());
1929 
1930   return ID;
1931 }
1932 
1933 static unsigned
1934 emitConvertFuncs(CodeGenTarget &Target, StringRef ClassName,
1935                  std::vector<std::unique_ptr<MatchableInfo>> &Infos,
1936                  bool HasMnemonicFirst, bool HasOptionalOperands,
1937                  raw_ostream &OS) {
1938   SmallSetVector<CachedHashString, 16> OperandConversionKinds;
1939   SmallSetVector<CachedHashString, 16> InstructionConversionKinds;
1940   std::vector<std::vector<uint8_t> > ConversionTable;
1941   size_t MaxRowLength = 2; // minimum is custom converter plus terminator.
1942 
1943   // TargetOperandClass - This is the target's operand class, like X86Operand.
1944   std::string TargetOperandClass = Target.getName().str() + "Operand";
1945 
1946   // Write the convert function to a separate stream, so we can drop it after
1947   // the enum. We'll build up the conversion handlers for the individual
1948   // operand types opportunistically as we encounter them.
1949   std::string ConvertFnBody;
1950   raw_string_ostream CvtOS(ConvertFnBody);
1951   // Start the unified conversion function.
1952   if (HasOptionalOperands) {
1953     CvtOS << "void " << Target.getName() << ClassName << "::\n"
1954           << "convertToMCInst(unsigned Kind, MCInst &Inst, "
1955           << "unsigned Opcode,\n"
1956           << "                const OperandVector &Operands,\n"
1957           << "                const SmallBitVector &OptionalOperandsMask) {\n";
1958   } else {
1959     CvtOS << "void " << Target.getName() << ClassName << "::\n"
1960           << "convertToMCInst(unsigned Kind, MCInst &Inst, "
1961           << "unsigned Opcode,\n"
1962           << "                const OperandVector &Operands) {\n";
1963   }
1964   CvtOS << "  assert(Kind < CVT_NUM_SIGNATURES && \"Invalid signature!\");\n";
1965   CvtOS << "  const uint8_t *Converter = ConversionTable[Kind];\n";
1966   if (HasOptionalOperands) {
1967     size_t MaxNumOperands = 0;
1968     for (const auto &MI : Infos) {
1969       MaxNumOperands = std::max(MaxNumOperands, MI->AsmOperands.size());
1970     }
1971     CvtOS << "  unsigned DefaultsOffset[" << (MaxNumOperands + 1)
1972           << "] = { 0 };\n";
1973     CvtOS << "  assert(OptionalOperandsMask.size() == " << (MaxNumOperands)
1974           << ");\n";
1975     CvtOS << "  for (unsigned i = 0, NumDefaults = 0; i < " << (MaxNumOperands)
1976           << "; ++i) {\n";
1977     CvtOS << "    DefaultsOffset[i + 1] = NumDefaults;\n";
1978     CvtOS << "    NumDefaults += (OptionalOperandsMask[i] ? 1 : 0);\n";
1979     CvtOS << "  }\n";
1980   }
1981   CvtOS << "  unsigned OpIdx;\n";
1982   CvtOS << "  Inst.setOpcode(Opcode);\n";
1983   CvtOS << "  for (const uint8_t *p = Converter; *p; p+= 2) {\n";
1984   if (HasOptionalOperands) {
1985     CvtOS << "    OpIdx = *(p + 1) - DefaultsOffset[*(p + 1)];\n";
1986   } else {
1987     CvtOS << "    OpIdx = *(p + 1);\n";
1988   }
1989   CvtOS << "    switch (*p) {\n";
1990   CvtOS << "    default: llvm_unreachable(\"invalid conversion entry!\");\n";
1991   CvtOS << "    case CVT_Reg:\n";
1992   CvtOS << "      static_cast<" << TargetOperandClass
1993         << "&>(*Operands[OpIdx]).addRegOperands(Inst, 1);\n";
1994   CvtOS << "      break;\n";
1995   CvtOS << "    case CVT_Tied: {\n";
1996   CvtOS << "      assert(OpIdx < (size_t)(std::end(TiedAsmOperandTable) -\n";
1997   CvtOS << "                          std::begin(TiedAsmOperandTable)) &&\n";
1998   CvtOS << "             \"Tied operand not found\");\n";
1999   CvtOS << "      unsigned TiedResOpnd = TiedAsmOperandTable[OpIdx][0];\n";
2000   CvtOS << "      if (TiedResOpnd != (uint8_t) -1)\n";
2001   CvtOS << "        Inst.addOperand(Inst.getOperand(TiedResOpnd));\n";
2002   CvtOS << "      break;\n";
2003   CvtOS << "    }\n";
2004 
2005   std::string OperandFnBody;
2006   raw_string_ostream OpOS(OperandFnBody);
2007   // Start the operand number lookup function.
2008   OpOS << "void " << Target.getName() << ClassName << "::\n"
2009        << "convertToMapAndConstraints(unsigned Kind,\n";
2010   OpOS.indent(27);
2011   OpOS << "const OperandVector &Operands) {\n"
2012        << "  assert(Kind < CVT_NUM_SIGNATURES && \"Invalid signature!\");\n"
2013        << "  unsigned NumMCOperands = 0;\n"
2014        << "  const uint8_t *Converter = ConversionTable[Kind];\n"
2015        << "  for (const uint8_t *p = Converter; *p; p+= 2) {\n"
2016        << "    switch (*p) {\n"
2017        << "    default: llvm_unreachable(\"invalid conversion entry!\");\n"
2018        << "    case CVT_Reg:\n"
2019        << "      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n"
2020        << "      Operands[*(p + 1)]->setConstraint(\"r\");\n"
2021        << "      ++NumMCOperands;\n"
2022        << "      break;\n"
2023        << "    case CVT_Tied:\n"
2024        << "      ++NumMCOperands;\n"
2025        << "      break;\n";
2026 
2027   // Pre-populate the operand conversion kinds with the standard always
2028   // available entries.
2029   OperandConversionKinds.insert(CachedHashString("CVT_Done"));
2030   OperandConversionKinds.insert(CachedHashString("CVT_Reg"));
2031   OperandConversionKinds.insert(CachedHashString("CVT_Tied"));
2032   enum { CVT_Done, CVT_Reg, CVT_Tied };
2033 
2034   // Map of e.g. <0, 2, 3> -> "Tie_0_2_3" enum label.
2035   std::map<std::tuple<uint8_t, uint8_t, uint8_t>, std::string>
2036   TiedOperandsEnumMap;
2037 
2038   for (auto &II : Infos) {
2039     // Check if we have a custom match function.
2040     StringRef AsmMatchConverter =
2041         II->getResultInst()->TheDef->getValueAsString("AsmMatchConverter");
2042     if (!AsmMatchConverter.empty() && II->UseInstAsmMatchConverter) {
2043       std::string Signature = ("ConvertCustom_" + AsmMatchConverter).str();
2044       II->ConversionFnKind = Signature;
2045 
2046       // Check if we have already generated this signature.
2047       if (!InstructionConversionKinds.insert(CachedHashString(Signature)))
2048         continue;
2049 
2050       // Remember this converter for the kind enum.
2051       unsigned KindID = OperandConversionKinds.size();
2052       OperandConversionKinds.insert(
2053           CachedHashString("CVT_" + getEnumNameForToken(AsmMatchConverter)));
2054 
2055       // Add the converter row for this instruction.
2056       ConversionTable.emplace_back();
2057       ConversionTable.back().push_back(KindID);
2058       ConversionTable.back().push_back(CVT_Done);
2059 
2060       // Add the handler to the conversion driver function.
2061       CvtOS << "    case CVT_"
2062             << getEnumNameForToken(AsmMatchConverter) << ":\n"
2063             << "      " << AsmMatchConverter << "(Inst, Operands);\n"
2064             << "      break;\n";
2065 
2066       // FIXME: Handle the operand number lookup for custom match functions.
2067       continue;
2068     }
2069 
2070     // Build the conversion function signature.
2071     std::string Signature = "Convert";
2072 
2073     std::vector<uint8_t> ConversionRow;
2074 
2075     // Compute the convert enum and the case body.
2076     MaxRowLength = std::max(MaxRowLength, II->ResOperands.size()*2 + 1 );
2077 
2078     for (unsigned i = 0, e = II->ResOperands.size(); i != e; ++i) {
2079       const MatchableInfo::ResOperand &OpInfo = II->ResOperands[i];
2080 
2081       // Generate code to populate each result operand.
2082       switch (OpInfo.Kind) {
2083       case MatchableInfo::ResOperand::RenderAsmOperand: {
2084         // This comes from something we parsed.
2085         const MatchableInfo::AsmOperand &Op =
2086           II->AsmOperands[OpInfo.AsmOperandNum];
2087 
2088         // Registers are always converted the same, don't duplicate the
2089         // conversion function based on them.
2090         Signature += "__";
2091         std::string Class;
2092         Class = Op.Class->isRegisterClass() ? "Reg" : Op.Class->ClassName;
2093         Signature += Class;
2094         Signature += utostr(OpInfo.MINumOperands);
2095         Signature += "_" + itostr(OpInfo.AsmOperandNum);
2096 
2097         // Add the conversion kind, if necessary, and get the associated ID
2098         // the index of its entry in the vector).
2099         std::string Name = "CVT_" + (Op.Class->isRegisterClass() ? "Reg" :
2100                                      Op.Class->RenderMethod);
2101         if (Op.Class->IsOptional) {
2102           // For optional operands we must also care about DefaultMethod
2103           assert(HasOptionalOperands);
2104           Name += "_" + Op.Class->DefaultMethod;
2105         }
2106         Name = getEnumNameForToken(Name);
2107 
2108         bool IsNewConverter = false;
2109         unsigned ID = getConverterOperandID(Name, OperandConversionKinds,
2110                                             IsNewConverter);
2111 
2112         // Add the operand entry to the instruction kind conversion row.
2113         ConversionRow.push_back(ID);
2114         ConversionRow.push_back(OpInfo.AsmOperandNum + HasMnemonicFirst);
2115 
2116         if (!IsNewConverter)
2117           break;
2118 
2119         // This is a new operand kind. Add a handler for it to the
2120         // converter driver.
2121         CvtOS << "    case " << Name << ":\n";
2122         if (Op.Class->IsOptional) {
2123           // If optional operand is not present in actual instruction then we
2124           // should call its DefaultMethod before RenderMethod
2125           assert(HasOptionalOperands);
2126           CvtOS << "      if (OptionalOperandsMask[*(p + 1) - 1]) {\n"
2127                 << "        " << Op.Class->DefaultMethod << "()"
2128                 << "->" << Op.Class->RenderMethod << "(Inst, "
2129                 << OpInfo.MINumOperands << ");\n"
2130                 << "      } else {\n"
2131                 << "        static_cast<" << TargetOperandClass
2132                 << "&>(*Operands[OpIdx])." << Op.Class->RenderMethod
2133                 << "(Inst, " << OpInfo.MINumOperands << ");\n"
2134                 << "      }\n";
2135         } else {
2136           CvtOS << "      static_cast<" << TargetOperandClass
2137                 << "&>(*Operands[OpIdx])." << Op.Class->RenderMethod
2138                 << "(Inst, " << OpInfo.MINumOperands << ");\n";
2139         }
2140         CvtOS << "      break;\n";
2141 
2142         // Add a handler for the operand number lookup.
2143         OpOS << "    case " << Name << ":\n"
2144              << "      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n";
2145 
2146         if (Op.Class->isRegisterClass())
2147           OpOS << "      Operands[*(p + 1)]->setConstraint(\"r\");\n";
2148         else
2149           OpOS << "      Operands[*(p + 1)]->setConstraint(\"m\");\n";
2150         OpOS << "      NumMCOperands += " << OpInfo.MINumOperands << ";\n"
2151              << "      break;\n";
2152         break;
2153       }
2154       case MatchableInfo::ResOperand::TiedOperand: {
2155         // If this operand is tied to a previous one, just copy the MCInst
2156         // operand from the earlier one.We can only tie single MCOperand values.
2157         assert(OpInfo.MINumOperands == 1 && "Not a singular MCOperand");
2158         uint8_t TiedOp = OpInfo.TiedOperands.ResOpnd;
2159         uint8_t SrcOp1 =
2160             OpInfo.TiedOperands.SrcOpnd1Idx + HasMnemonicFirst;
2161         uint8_t SrcOp2 =
2162             OpInfo.TiedOperands.SrcOpnd2Idx + HasMnemonicFirst;
2163         assert((i > TiedOp || TiedOp == (uint8_t)-1) &&
2164                "Tied operand precedes its target!");
2165         auto TiedTupleName = std::string("Tie") + utostr(TiedOp) + '_' +
2166                              utostr(SrcOp1) + '_' + utostr(SrcOp2);
2167         Signature += "__" + TiedTupleName;
2168         ConversionRow.push_back(CVT_Tied);
2169         ConversionRow.push_back(TiedOp);
2170         ConversionRow.push_back(SrcOp1);
2171         ConversionRow.push_back(SrcOp2);
2172 
2173         // Also create an 'enum' for this combination of tied operands.
2174         auto Key = std::make_tuple(TiedOp, SrcOp1, SrcOp2);
2175         TiedOperandsEnumMap.emplace(Key, TiedTupleName);
2176         break;
2177       }
2178       case MatchableInfo::ResOperand::ImmOperand: {
2179         int64_t Val = OpInfo.ImmVal;
2180         std::string Ty = "imm_" + itostr(Val);
2181         Ty = getEnumNameForToken(Ty);
2182         Signature += "__" + Ty;
2183 
2184         std::string Name = "CVT_" + Ty;
2185         bool IsNewConverter = false;
2186         unsigned ID = getConverterOperandID(Name, OperandConversionKinds,
2187                                             IsNewConverter);
2188         // Add the operand entry to the instruction kind conversion row.
2189         ConversionRow.push_back(ID);
2190         ConversionRow.push_back(0);
2191 
2192         if (!IsNewConverter)
2193           break;
2194 
2195         CvtOS << "    case " << Name << ":\n"
2196               << "      Inst.addOperand(MCOperand::createImm(" << Val << "));\n"
2197               << "      break;\n";
2198 
2199         OpOS << "    case " << Name << ":\n"
2200              << "      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n"
2201              << "      Operands[*(p + 1)]->setConstraint(\"\");\n"
2202              << "      ++NumMCOperands;\n"
2203              << "      break;\n";
2204         break;
2205       }
2206       case MatchableInfo::ResOperand::RegOperand: {
2207         std::string Reg, Name;
2208         if (!OpInfo.Register) {
2209           Name = "reg0";
2210           Reg = "0";
2211         } else {
2212           Reg = getQualifiedName(OpInfo.Register);
2213           Name = "reg" + OpInfo.Register->getName().str();
2214         }
2215         Signature += "__" + Name;
2216         Name = "CVT_" + Name;
2217         bool IsNewConverter = false;
2218         unsigned ID = getConverterOperandID(Name, OperandConversionKinds,
2219                                             IsNewConverter);
2220         // Add the operand entry to the instruction kind conversion row.
2221         ConversionRow.push_back(ID);
2222         ConversionRow.push_back(0);
2223 
2224         if (!IsNewConverter)
2225           break;
2226         CvtOS << "    case " << Name << ":\n"
2227               << "      Inst.addOperand(MCOperand::createReg(" << Reg << "));\n"
2228               << "      break;\n";
2229 
2230         OpOS << "    case " << Name << ":\n"
2231              << "      Operands[*(p + 1)]->setMCOperandNum(NumMCOperands);\n"
2232              << "      Operands[*(p + 1)]->setConstraint(\"m\");\n"
2233              << "      ++NumMCOperands;\n"
2234              << "      break;\n";
2235       }
2236       }
2237     }
2238 
2239     // If there were no operands, add to the signature to that effect
2240     if (Signature == "Convert")
2241       Signature += "_NoOperands";
2242 
2243     II->ConversionFnKind = Signature;
2244 
2245     // Save the signature. If we already have it, don't add a new row
2246     // to the table.
2247     if (!InstructionConversionKinds.insert(CachedHashString(Signature)))
2248       continue;
2249 
2250     // Add the row to the table.
2251     ConversionTable.push_back(std::move(ConversionRow));
2252   }
2253 
2254   // Finish up the converter driver function.
2255   CvtOS << "    }\n  }\n}\n\n";
2256 
2257   // Finish up the operand number lookup function.
2258   OpOS << "    }\n  }\n}\n\n";
2259 
2260   // Output a static table for tied operands.
2261   if (TiedOperandsEnumMap.size()) {
2262     // The number of tied operand combinations will be small in practice,
2263     // but just add the assert to be sure.
2264     assert(TiedOperandsEnumMap.size() <= 254 &&
2265            "Too many tied-operand combinations to reference with "
2266            "an 8bit offset from the conversion table, where index "
2267            "'255' is reserved as operand not to be copied.");
2268 
2269     OS << "enum {\n";
2270     for (auto &KV : TiedOperandsEnumMap) {
2271       OS << "  " << KV.second << ",\n";
2272     }
2273     OS << "};\n\n";
2274 
2275     OS << "static const uint8_t TiedAsmOperandTable[][3] = {\n";
2276     for (auto &KV : TiedOperandsEnumMap) {
2277       OS << "  /* " << KV.second << " */ { "
2278          << utostr(std::get<0>(KV.first)) << ", "
2279          << utostr(std::get<1>(KV.first)) << ", "
2280          << utostr(std::get<2>(KV.first)) << " },\n";
2281     }
2282     OS << "};\n\n";
2283   } else
2284     OS << "static const uint8_t TiedAsmOperandTable[][3] = "
2285           "{ /* empty  */ {0, 0, 0} };\n\n";
2286 
2287   OS << "namespace {\n";
2288 
2289   // Output the operand conversion kind enum.
2290   OS << "enum OperatorConversionKind {\n";
2291   for (const auto &Converter : OperandConversionKinds)
2292     OS << "  " << Converter << ",\n";
2293   OS << "  CVT_NUM_CONVERTERS\n";
2294   OS << "};\n\n";
2295 
2296   // Output the instruction conversion kind enum.
2297   OS << "enum InstructionConversionKind {\n";
2298   for (const auto &Signature : InstructionConversionKinds)
2299     OS << "  " << Signature << ",\n";
2300   OS << "  CVT_NUM_SIGNATURES\n";
2301   OS << "};\n\n";
2302 
2303   OS << "} // end anonymous namespace\n\n";
2304 
2305   // Output the conversion table.
2306   OS << "static const uint8_t ConversionTable[CVT_NUM_SIGNATURES]["
2307      << MaxRowLength << "] = {\n";
2308 
2309   for (unsigned Row = 0, ERow = ConversionTable.size(); Row != ERow; ++Row) {
2310     assert(ConversionTable[Row].size() % 2 == 0 && "bad conversion row!");
2311     OS << "  // " << InstructionConversionKinds[Row] << "\n";
2312     OS << "  { ";
2313     for (unsigned i = 0, e = ConversionTable[Row].size(); i != e; i += 2) {
2314       OS << OperandConversionKinds[ConversionTable[Row][i]] << ", ";
2315       if (OperandConversionKinds[ConversionTable[Row][i]] !=
2316           CachedHashString("CVT_Tied")) {
2317         OS << (unsigned)(ConversionTable[Row][i + 1]) << ", ";
2318         continue;
2319       }
2320 
2321       // For a tied operand, emit a reference to the TiedAsmOperandTable
2322       // that contains the operand to copy, and the parsed operands to
2323       // check for their tied constraints.
2324       auto Key = std::make_tuple((uint8_t)ConversionTable[Row][i + 1],
2325                                  (uint8_t)ConversionTable[Row][i + 2],
2326                                  (uint8_t)ConversionTable[Row][i + 3]);
2327       auto TiedOpndEnum = TiedOperandsEnumMap.find(Key);
2328       assert(TiedOpndEnum != TiedOperandsEnumMap.end() &&
2329              "No record for tied operand pair");
2330       OS << TiedOpndEnum->second << ", ";
2331       i += 2;
2332     }
2333     OS << "CVT_Done },\n";
2334   }
2335 
2336   OS << "};\n\n";
2337 
2338   // Spit out the conversion driver function.
2339   OS << CvtOS.str();
2340 
2341   // Spit out the operand number lookup function.
2342   OS << OpOS.str();
2343 
2344   return ConversionTable.size();
2345 }
2346 
2347 /// emitMatchClassEnumeration - Emit the enumeration for match class kinds.
2348 static void emitMatchClassEnumeration(CodeGenTarget &Target,
2349                                       std::forward_list<ClassInfo> &Infos,
2350                                       raw_ostream &OS) {
2351   OS << "namespace {\n\n";
2352 
2353   OS << "/// MatchClassKind - The kinds of classes which participate in\n"
2354      << "/// instruction matching.\n";
2355   OS << "enum MatchClassKind {\n";
2356   OS << "  InvalidMatchClass = 0,\n";
2357   OS << "  OptionalMatchClass = 1,\n";
2358   ClassInfo::ClassInfoKind LastKind = ClassInfo::Token;
2359   StringRef LastName = "OptionalMatchClass";
2360   for (const auto &CI : Infos) {
2361     if (LastKind == ClassInfo::Token && CI.Kind != ClassInfo::Token) {
2362       OS << "  MCK_LAST_TOKEN = " << LastName << ",\n";
2363     } else if (LastKind < ClassInfo::UserClass0 &&
2364                CI.Kind >= ClassInfo::UserClass0) {
2365       OS << "  MCK_LAST_REGISTER = " << LastName << ",\n";
2366     }
2367     LastKind = (ClassInfo::ClassInfoKind)CI.Kind;
2368     LastName = CI.Name;
2369 
2370     OS << "  " << CI.Name << ", // ";
2371     if (CI.Kind == ClassInfo::Token) {
2372       OS << "'" << CI.ValueName << "'\n";
2373     } else if (CI.isRegisterClass()) {
2374       if (!CI.ValueName.empty())
2375         OS << "register class '" << CI.ValueName << "'\n";
2376       else
2377         OS << "derived register class\n";
2378     } else {
2379       OS << "user defined class '" << CI.ValueName << "'\n";
2380     }
2381   }
2382   OS << "  NumMatchClassKinds\n";
2383   OS << "};\n\n";
2384 
2385   OS << "} // end anonymous namespace\n\n";
2386 }
2387 
2388 /// emitMatchClassDiagStrings - Emit a function to get the diagnostic text to be
2389 /// used when an assembly operand does not match the expected operand class.
2390 static void emitOperandMatchErrorDiagStrings(AsmMatcherInfo &Info, raw_ostream &OS) {
2391   // If the target does not use DiagnosticString for any operands, don't emit
2392   // an unused function.
2393   if (std::all_of(
2394           Info.Classes.begin(), Info.Classes.end(),
2395           [](const ClassInfo &CI) { return CI.DiagnosticString.empty(); }))
2396     return;
2397 
2398   OS << "static const char *getMatchKindDiag(" << Info.Target.getName()
2399      << "AsmParser::" << Info.Target.getName()
2400      << "MatchResultTy MatchResult) {\n";
2401   OS << "  switch (MatchResult) {\n";
2402 
2403   for (const auto &CI: Info.Classes) {
2404     if (!CI.DiagnosticString.empty()) {
2405       assert(!CI.DiagnosticType.empty() &&
2406              "DiagnosticString set without DiagnosticType");
2407       OS << "  case " << Info.Target.getName()
2408          << "AsmParser::Match_" << CI.DiagnosticType << ":\n";
2409       OS << "    return \"" << CI.DiagnosticString << "\";\n";
2410     }
2411   }
2412 
2413   OS << "  default:\n";
2414   OS << "    return nullptr;\n";
2415 
2416   OS << "  }\n";
2417   OS << "}\n\n";
2418 }
2419 
2420 static void emitRegisterMatchErrorFunc(AsmMatcherInfo &Info, raw_ostream &OS) {
2421   OS << "static unsigned getDiagKindFromRegisterClass(MatchClassKind "
2422         "RegisterClass) {\n";
2423   if (none_of(Info.Classes, [](const ClassInfo &CI) {
2424         return CI.isRegisterClass() && !CI.DiagnosticType.empty();
2425       })) {
2426     OS << "  return MCTargetAsmParser::Match_InvalidOperand;\n";
2427   } else {
2428     OS << "  switch (RegisterClass) {\n";
2429     for (const auto &CI: Info.Classes) {
2430       if (CI.isRegisterClass() && !CI.DiagnosticType.empty()) {
2431         OS << "  case " << CI.Name << ":\n";
2432         OS << "    return " << Info.Target.getName() << "AsmParser::Match_"
2433            << CI.DiagnosticType << ";\n";
2434       }
2435     }
2436 
2437     OS << "  default:\n";
2438     OS << "    return MCTargetAsmParser::Match_InvalidOperand;\n";
2439 
2440     OS << "  }\n";
2441   }
2442   OS << "}\n\n";
2443 }
2444 
2445 /// emitValidateOperandClass - Emit the function to validate an operand class.
2446 static void emitValidateOperandClass(AsmMatcherInfo &Info,
2447                                      raw_ostream &OS) {
2448   OS << "static unsigned validateOperandClass(MCParsedAsmOperand &GOp, "
2449      << "MatchClassKind Kind) {\n";
2450   OS << "  " << Info.Target.getName() << "Operand &Operand = ("
2451      << Info.Target.getName() << "Operand&)GOp;\n";
2452 
2453   // The InvalidMatchClass is not to match any operand.
2454   OS << "  if (Kind == InvalidMatchClass)\n";
2455   OS << "    return MCTargetAsmParser::Match_InvalidOperand;\n\n";
2456 
2457   // Check for Token operands first.
2458   // FIXME: Use a more specific diagnostic type.
2459   OS << "  if (Operand.isToken() && Kind <= MCK_LAST_TOKEN)\n";
2460   OS << "    return isSubclass(matchTokenString(Operand.getToken()), Kind) ?\n"
2461      << "             MCTargetAsmParser::Match_Success :\n"
2462      << "             MCTargetAsmParser::Match_InvalidOperand;\n\n";
2463 
2464   // Check the user classes. We don't care what order since we're only
2465   // actually matching against one of them.
2466   OS << "  switch (Kind) {\n"
2467         "  default: break;\n";
2468   for (const auto &CI : Info.Classes) {
2469     if (!CI.isUserClass())
2470       continue;
2471 
2472     OS << "  // '" << CI.ClassName << "' class\n";
2473     OS << "  case " << CI.Name << ": {\n";
2474     OS << "    DiagnosticPredicate DP(Operand." << CI.PredicateMethod
2475        << "());\n";
2476     OS << "    if (DP.isMatch())\n";
2477     OS << "      return MCTargetAsmParser::Match_Success;\n";
2478     if (!CI.DiagnosticType.empty()) {
2479       OS << "    if (DP.isNearMatch())\n";
2480       OS << "      return " << Info.Target.getName() << "AsmParser::Match_"
2481          << CI.DiagnosticType << ";\n";
2482       OS << "    break;\n";
2483     }
2484     else
2485       OS << "    break;\n";
2486     OS << "    }\n";
2487   }
2488   OS << "  } // end switch (Kind)\n\n";
2489 
2490   // Check for register operands, including sub-classes.
2491   OS << "  if (Operand.isReg()) {\n";
2492   OS << "    MatchClassKind OpKind;\n";
2493   OS << "    switch (Operand.getReg()) {\n";
2494   OS << "    default: OpKind = InvalidMatchClass; break;\n";
2495   for (const auto &RC : Info.RegisterClasses)
2496     OS << "    case " << RC.first->getValueAsString("Namespace") << "::"
2497        << RC.first->getName() << ": OpKind = " << RC.second->Name
2498        << "; break;\n";
2499   OS << "    }\n";
2500   OS << "    return isSubclass(OpKind, Kind) ? "
2501      << "(unsigned)MCTargetAsmParser::Match_Success :\n                     "
2502      << "                 getDiagKindFromRegisterClass(Kind);\n  }\n\n";
2503 
2504   // Expected operand is a register, but actual is not.
2505   OS << "  if (Kind > MCK_LAST_TOKEN && Kind <= MCK_LAST_REGISTER)\n";
2506   OS << "    return getDiagKindFromRegisterClass(Kind);\n\n";
2507 
2508   // Generic fallthrough match failure case for operands that don't have
2509   // specialized diagnostic types.
2510   OS << "  return MCTargetAsmParser::Match_InvalidOperand;\n";
2511   OS << "}\n\n";
2512 }
2513 
2514 /// emitIsSubclass - Emit the subclass predicate function.
2515 static void emitIsSubclass(CodeGenTarget &Target,
2516                            std::forward_list<ClassInfo> &Infos,
2517                            raw_ostream &OS) {
2518   OS << "/// isSubclass - Compute whether \\p A is a subclass of \\p B.\n";
2519   OS << "static bool isSubclass(MatchClassKind A, MatchClassKind B) {\n";
2520   OS << "  if (A == B)\n";
2521   OS << "    return true;\n\n";
2522 
2523   bool EmittedSwitch = false;
2524   for (const auto &A : Infos) {
2525     std::vector<StringRef> SuperClasses;
2526     if (A.IsOptional)
2527       SuperClasses.push_back("OptionalMatchClass");
2528     for (const auto &B : Infos) {
2529       if (&A != &B && A.isSubsetOf(B))
2530         SuperClasses.push_back(B.Name);
2531     }
2532 
2533     if (SuperClasses.empty())
2534       continue;
2535 
2536     // If this is the first SuperClass, emit the switch header.
2537     if (!EmittedSwitch) {
2538       OS << "  switch (A) {\n";
2539       OS << "  default:\n";
2540       OS << "    return false;\n";
2541       EmittedSwitch = true;
2542     }
2543 
2544     OS << "\n  case " << A.Name << ":\n";
2545 
2546     if (SuperClasses.size() == 1) {
2547       OS << "    return B == " << SuperClasses.back() << ";\n";
2548       continue;
2549     }
2550 
2551     if (!SuperClasses.empty()) {
2552       OS << "    switch (B) {\n";
2553       OS << "    default: return false;\n";
2554       for (StringRef SC : SuperClasses)
2555         OS << "    case " << SC << ": return true;\n";
2556       OS << "    }\n";
2557     } else {
2558       // No case statement to emit
2559       OS << "    return false;\n";
2560     }
2561   }
2562 
2563   // If there were case statements emitted into the string stream write the
2564   // default.
2565   if (EmittedSwitch)
2566     OS << "  }\n";
2567   else
2568     OS << "  return false;\n";
2569 
2570   OS << "}\n\n";
2571 }
2572 
2573 /// emitMatchTokenString - Emit the function to match a token string to the
2574 /// appropriate match class value.
2575 static void emitMatchTokenString(CodeGenTarget &Target,
2576                                  std::forward_list<ClassInfo> &Infos,
2577                                  raw_ostream &OS) {
2578   // Construct the match list.
2579   std::vector<StringMatcher::StringPair> Matches;
2580   for (const auto &CI : Infos) {
2581     if (CI.Kind == ClassInfo::Token)
2582       Matches.emplace_back(CI.ValueName, "return " + CI.Name + ";");
2583   }
2584 
2585   OS << "static MatchClassKind matchTokenString(StringRef Name) {\n";
2586 
2587   StringMatcher("Name", Matches, OS).Emit();
2588 
2589   OS << "  return InvalidMatchClass;\n";
2590   OS << "}\n\n";
2591 }
2592 
2593 /// emitMatchRegisterName - Emit the function to match a string to the target
2594 /// specific register enum.
2595 static void emitMatchRegisterName(CodeGenTarget &Target, Record *AsmParser,
2596                                   raw_ostream &OS) {
2597   // Construct the match list.
2598   std::vector<StringMatcher::StringPair> Matches;
2599   const auto &Regs = Target.getRegBank().getRegisters();
2600   for (const CodeGenRegister &Reg : Regs) {
2601     if (Reg.TheDef->getValueAsString("AsmName").empty())
2602       continue;
2603 
2604     Matches.emplace_back(Reg.TheDef->getValueAsString("AsmName"),
2605                          "return " + utostr(Reg.EnumValue) + ";");
2606   }
2607 
2608   OS << "static unsigned MatchRegisterName(StringRef Name) {\n";
2609 
2610   bool IgnoreDuplicates =
2611       AsmParser->getValueAsBit("AllowDuplicateRegisterNames");
2612   StringMatcher("Name", Matches, OS).Emit(0, IgnoreDuplicates);
2613 
2614   OS << "  return 0;\n";
2615   OS << "}\n\n";
2616 }
2617 
2618 /// Emit the function to match a string to the target
2619 /// specific register enum.
2620 static void emitMatchRegisterAltName(CodeGenTarget &Target, Record *AsmParser,
2621                                      raw_ostream &OS) {
2622   // Construct the match list.
2623   std::vector<StringMatcher::StringPair> Matches;
2624   const auto &Regs = Target.getRegBank().getRegisters();
2625   for (const CodeGenRegister &Reg : Regs) {
2626 
2627     auto AltNames = Reg.TheDef->getValueAsListOfStrings("AltNames");
2628 
2629     for (auto AltName : AltNames) {
2630       AltName = StringRef(AltName).trim();
2631 
2632       // don't handle empty alternative names
2633       if (AltName.empty())
2634         continue;
2635 
2636       Matches.emplace_back(AltName,
2637                            "return " + utostr(Reg.EnumValue) + ";");
2638     }
2639   }
2640 
2641   OS << "static unsigned MatchRegisterAltName(StringRef Name) {\n";
2642 
2643   bool IgnoreDuplicates =
2644       AsmParser->getValueAsBit("AllowDuplicateRegisterNames");
2645   StringMatcher("Name", Matches, OS).Emit(0, IgnoreDuplicates);
2646 
2647   OS << "  return 0;\n";
2648   OS << "}\n\n";
2649 }
2650 
2651 /// emitOperandDiagnosticTypes - Emit the operand matching diagnostic types.
2652 static void emitOperandDiagnosticTypes(AsmMatcherInfo &Info, raw_ostream &OS) {
2653   // Get the set of diagnostic types from all of the operand classes.
2654   std::set<StringRef> Types;
2655   for (const auto &OpClassEntry : Info.AsmOperandClasses) {
2656     if (!OpClassEntry.second->DiagnosticType.empty())
2657       Types.insert(OpClassEntry.second->DiagnosticType);
2658   }
2659   for (const auto &OpClassEntry : Info.RegisterClassClasses) {
2660     if (!OpClassEntry.second->DiagnosticType.empty())
2661       Types.insert(OpClassEntry.second->DiagnosticType);
2662   }
2663 
2664   if (Types.empty()) return;
2665 
2666   // Now emit the enum entries.
2667   for (StringRef Type : Types)
2668     OS << "  Match_" << Type << ",\n";
2669   OS << "  END_OPERAND_DIAGNOSTIC_TYPES\n";
2670 }
2671 
2672 /// emitGetSubtargetFeatureName - Emit the helper function to get the
2673 /// user-level name for a subtarget feature.
2674 static void emitGetSubtargetFeatureName(AsmMatcherInfo &Info, raw_ostream &OS) {
2675   OS << "// User-level names for subtarget features that participate in\n"
2676      << "// instruction matching.\n"
2677      << "static const char *getSubtargetFeatureName(uint64_t Val) {\n";
2678   if (!Info.SubtargetFeatures.empty()) {
2679     OS << "  switch(Val) {\n";
2680     for (const auto &SF : Info.SubtargetFeatures) {
2681       const SubtargetFeatureInfo &SFI = SF.second;
2682       // FIXME: Totally just a placeholder name to get the algorithm working.
2683       OS << "  case " << SFI.getEnumBitName() << ": return \""
2684          << SFI.TheDef->getValueAsString("PredicateName") << "\";\n";
2685     }
2686     OS << "  default: return \"(unknown)\";\n";
2687     OS << "  }\n";
2688   } else {
2689     // Nothing to emit, so skip the switch
2690     OS << "  return \"(unknown)\";\n";
2691   }
2692   OS << "}\n\n";
2693 }
2694 
2695 static std::string GetAliasRequiredFeatures(Record *R,
2696                                             const AsmMatcherInfo &Info) {
2697   std::vector<Record*> ReqFeatures = R->getValueAsListOfDefs("Predicates");
2698   std::string Result;
2699 
2700   if (ReqFeatures.empty())
2701     return Result;
2702 
2703   for (unsigned i = 0, e = ReqFeatures.size(); i != e; ++i) {
2704     const SubtargetFeatureInfo *F = Info.getSubtargetFeature(ReqFeatures[i]);
2705 
2706     if (!F)
2707       PrintFatalError(R->getLoc(), "Predicate '" + ReqFeatures[i]->getName() +
2708                     "' is not marked as an AssemblerPredicate!");
2709 
2710     if (i)
2711       Result += " && ";
2712 
2713     Result += "Features.test(" + F->getEnumBitName() + ')';
2714   }
2715 
2716   return Result;
2717 }
2718 
2719 static void emitMnemonicAliasVariant(raw_ostream &OS,const AsmMatcherInfo &Info,
2720                                      std::vector<Record*> &Aliases,
2721                                      unsigned Indent = 0,
2722                                   StringRef AsmParserVariantName = StringRef()){
2723   // Keep track of all the aliases from a mnemonic.  Use an std::map so that the
2724   // iteration order of the map is stable.
2725   std::map<std::string, std::vector<Record*> > AliasesFromMnemonic;
2726 
2727   for (Record *R : Aliases) {
2728     // FIXME: Allow AssemblerVariantName to be a comma separated list.
2729     StringRef AsmVariantName = R->getValueAsString("AsmVariantName");
2730     if (AsmVariantName != AsmParserVariantName)
2731       continue;
2732     AliasesFromMnemonic[R->getValueAsString("FromMnemonic")].push_back(R);
2733   }
2734   if (AliasesFromMnemonic.empty())
2735     return;
2736 
2737   // Process each alias a "from" mnemonic at a time, building the code executed
2738   // by the string remapper.
2739   std::vector<StringMatcher::StringPair> Cases;
2740   for (const auto &AliasEntry : AliasesFromMnemonic) {
2741     const std::vector<Record*> &ToVec = AliasEntry.second;
2742 
2743     // Loop through each alias and emit code that handles each case.  If there
2744     // are two instructions without predicates, emit an error.  If there is one,
2745     // emit it last.
2746     std::string MatchCode;
2747     int AliasWithNoPredicate = -1;
2748 
2749     for (unsigned i = 0, e = ToVec.size(); i != e; ++i) {
2750       Record *R = ToVec[i];
2751       std::string FeatureMask = GetAliasRequiredFeatures(R, Info);
2752 
2753       // If this unconditionally matches, remember it for later and diagnose
2754       // duplicates.
2755       if (FeatureMask.empty()) {
2756         if (AliasWithNoPredicate != -1) {
2757           // We can't have two aliases from the same mnemonic with no predicate.
2758           PrintError(ToVec[AliasWithNoPredicate]->getLoc(),
2759                      "two MnemonicAliases with the same 'from' mnemonic!");
2760           PrintFatalError(R->getLoc(), "this is the other MnemonicAlias.");
2761         }
2762 
2763         AliasWithNoPredicate = i;
2764         continue;
2765       }
2766       if (R->getValueAsString("ToMnemonic") == AliasEntry.first)
2767         PrintFatalError(R->getLoc(), "MnemonicAlias to the same string");
2768 
2769       if (!MatchCode.empty())
2770         MatchCode += "else ";
2771       MatchCode += "if (" + FeatureMask + ")\n";
2772       MatchCode += "  Mnemonic = \"";
2773       MatchCode += R->getValueAsString("ToMnemonic");
2774       MatchCode += "\";\n";
2775     }
2776 
2777     if (AliasWithNoPredicate != -1) {
2778       Record *R = ToVec[AliasWithNoPredicate];
2779       if (!MatchCode.empty())
2780         MatchCode += "else\n  ";
2781       MatchCode += "Mnemonic = \"";
2782       MatchCode += R->getValueAsString("ToMnemonic");
2783       MatchCode += "\";\n";
2784     }
2785 
2786     MatchCode += "return;";
2787 
2788     Cases.push_back(std::make_pair(AliasEntry.first, MatchCode));
2789   }
2790   StringMatcher("Mnemonic", Cases, OS).Emit(Indent);
2791 }
2792 
2793 /// emitMnemonicAliases - If the target has any MnemonicAlias<> definitions,
2794 /// emit a function for them and return true, otherwise return false.
2795 static bool emitMnemonicAliases(raw_ostream &OS, const AsmMatcherInfo &Info,
2796                                 CodeGenTarget &Target) {
2797   // Ignore aliases when match-prefix is set.
2798   if (!MatchPrefix.empty())
2799     return false;
2800 
2801   std::vector<Record*> Aliases =
2802     Info.getRecords().getAllDerivedDefinitions("MnemonicAlias");
2803   if (Aliases.empty()) return false;
2804 
2805   OS << "static void applyMnemonicAliases(StringRef &Mnemonic, "
2806     "const FeatureBitset &Features, unsigned VariantID) {\n";
2807   OS << "  switch (VariantID) {\n";
2808   unsigned VariantCount = Target.getAsmParserVariantCount();
2809   for (unsigned VC = 0; VC != VariantCount; ++VC) {
2810     Record *AsmVariant = Target.getAsmParserVariant(VC);
2811     int AsmParserVariantNo = AsmVariant->getValueAsInt("Variant");
2812     StringRef AsmParserVariantName = AsmVariant->getValueAsString("Name");
2813     OS << "    case " << AsmParserVariantNo << ":\n";
2814     emitMnemonicAliasVariant(OS, Info, Aliases, /*Indent=*/2,
2815                              AsmParserVariantName);
2816     OS << "    break;\n";
2817   }
2818   OS << "  }\n";
2819 
2820   // Emit aliases that apply to all variants.
2821   emitMnemonicAliasVariant(OS, Info, Aliases);
2822 
2823   OS << "}\n\n";
2824 
2825   return true;
2826 }
2827 
2828 static void emitCustomOperandParsing(raw_ostream &OS, CodeGenTarget &Target,
2829                               const AsmMatcherInfo &Info, StringRef ClassName,
2830                               StringToOffsetTable &StringTable,
2831                               unsigned MaxMnemonicIndex,
2832                               unsigned MaxFeaturesIndex,
2833                               bool HasMnemonicFirst) {
2834   unsigned MaxMask = 0;
2835   for (const OperandMatchEntry &OMI : Info.OperandMatchInfo) {
2836     MaxMask |= OMI.OperandMask;
2837   }
2838 
2839   // Emit the static custom operand parsing table;
2840   OS << "namespace {\n";
2841   OS << "  struct OperandMatchEntry {\n";
2842   OS << "    " << getMinimalTypeForRange(MaxMnemonicIndex)
2843                << " Mnemonic;\n";
2844   OS << "    " << getMinimalTypeForRange(MaxMask)
2845                << " OperandMask;\n";
2846   OS << "    " << getMinimalTypeForRange(std::distance(
2847                       Info.Classes.begin(), Info.Classes.end())) << " Class;\n";
2848   OS << "    " << getMinimalTypeForRange(MaxFeaturesIndex)
2849                << " RequiredFeaturesIdx;\n\n";
2850   OS << "    StringRef getMnemonic() const {\n";
2851   OS << "      return StringRef(MnemonicTable + Mnemonic + 1,\n";
2852   OS << "                       MnemonicTable[Mnemonic]);\n";
2853   OS << "    }\n";
2854   OS << "  };\n\n";
2855 
2856   OS << "  // Predicate for searching for an opcode.\n";
2857   OS << "  struct LessOpcodeOperand {\n";
2858   OS << "    bool operator()(const OperandMatchEntry &LHS, StringRef RHS) {\n";
2859   OS << "      return LHS.getMnemonic()  < RHS;\n";
2860   OS << "    }\n";
2861   OS << "    bool operator()(StringRef LHS, const OperandMatchEntry &RHS) {\n";
2862   OS << "      return LHS < RHS.getMnemonic();\n";
2863   OS << "    }\n";
2864   OS << "    bool operator()(const OperandMatchEntry &LHS,";
2865   OS << " const OperandMatchEntry &RHS) {\n";
2866   OS << "      return LHS.getMnemonic() < RHS.getMnemonic();\n";
2867   OS << "    }\n";
2868   OS << "  };\n";
2869 
2870   OS << "} // end anonymous namespace\n\n";
2871 
2872   OS << "static const OperandMatchEntry OperandMatchTable["
2873      << Info.OperandMatchInfo.size() << "] = {\n";
2874 
2875   OS << "  /* Operand List Mnemonic, Mask, Operand Class, Features */\n";
2876   for (const OperandMatchEntry &OMI : Info.OperandMatchInfo) {
2877     const MatchableInfo &II = *OMI.MI;
2878 
2879     OS << "  { ";
2880 
2881     // Store a pascal-style length byte in the mnemonic.
2882     std::string LenMnemonic = char(II.Mnemonic.size()) + II.Mnemonic.str();
2883     OS << StringTable.GetOrAddStringOffset(LenMnemonic, false)
2884        << " /* " << II.Mnemonic << " */, ";
2885 
2886     OS << OMI.OperandMask;
2887     OS << " /* ";
2888     bool printComma = false;
2889     for (int i = 0, e = 31; i !=e; ++i)
2890       if (OMI.OperandMask & (1 << i)) {
2891         if (printComma)
2892           OS << ", ";
2893         OS << i;
2894         printComma = true;
2895       }
2896     OS << " */, ";
2897 
2898     OS << OMI.CI->Name;
2899 
2900     // Write the required features mask.
2901     OS << ", AMFBS";
2902     if (II.RequiredFeatures.empty())
2903       OS << "_None";
2904     else
2905       for (unsigned i = 0, e = II.RequiredFeatures.size(); i != e; ++i)
2906         OS << '_' << II.RequiredFeatures[i]->TheDef->getName();
2907 
2908     OS << " },\n";
2909   }
2910   OS << "};\n\n";
2911 
2912   // Emit the operand class switch to call the correct custom parser for
2913   // the found operand class.
2914   OS << "OperandMatchResultTy " << Target.getName() << ClassName << "::\n"
2915      << "tryCustomParseOperand(OperandVector"
2916      << " &Operands,\n                      unsigned MCK) {\n\n"
2917      << "  switch(MCK) {\n";
2918 
2919   for (const auto &CI : Info.Classes) {
2920     if (CI.ParserMethod.empty())
2921       continue;
2922     OS << "  case " << CI.Name << ":\n"
2923        << "    return " << CI.ParserMethod << "(Operands);\n";
2924   }
2925 
2926   OS << "  default:\n";
2927   OS << "    return MatchOperand_NoMatch;\n";
2928   OS << "  }\n";
2929   OS << "  return MatchOperand_NoMatch;\n";
2930   OS << "}\n\n";
2931 
2932   // Emit the static custom operand parser. This code is very similar with
2933   // the other matcher. Also use MatchResultTy here just in case we go for
2934   // a better error handling.
2935   OS << "OperandMatchResultTy " << Target.getName() << ClassName << "::\n"
2936      << "MatchOperandParserImpl(OperandVector"
2937      << " &Operands,\n                       StringRef Mnemonic,\n"
2938      << "                       bool ParseForAllFeatures) {\n";
2939 
2940   // Emit code to get the available features.
2941   OS << "  // Get the current feature set.\n";
2942   OS << "  const FeatureBitset &AvailableFeatures = getAvailableFeatures();\n\n";
2943 
2944   OS << "  // Get the next operand index.\n";
2945   OS << "  unsigned NextOpNum = Operands.size()"
2946      << (HasMnemonicFirst ? " - 1" : "") << ";\n";
2947 
2948   // Emit code to search the table.
2949   OS << "  // Search the table.\n";
2950   if (HasMnemonicFirst) {
2951     OS << "  auto MnemonicRange =\n";
2952     OS << "    std::equal_range(std::begin(OperandMatchTable), "
2953           "std::end(OperandMatchTable),\n";
2954     OS << "                     Mnemonic, LessOpcodeOperand());\n\n";
2955   } else {
2956     OS << "  auto MnemonicRange = std::make_pair(std::begin(OperandMatchTable),"
2957           " std::end(OperandMatchTable));\n";
2958     OS << "  if (!Mnemonic.empty())\n";
2959     OS << "    MnemonicRange =\n";
2960     OS << "      std::equal_range(std::begin(OperandMatchTable), "
2961           "std::end(OperandMatchTable),\n";
2962     OS << "                       Mnemonic, LessOpcodeOperand());\n\n";
2963   }
2964 
2965   OS << "  if (MnemonicRange.first == MnemonicRange.second)\n";
2966   OS << "    return MatchOperand_NoMatch;\n\n";
2967 
2968   OS << "  for (const OperandMatchEntry *it = MnemonicRange.first,\n"
2969      << "       *ie = MnemonicRange.second; it != ie; ++it) {\n";
2970 
2971   OS << "    // equal_range guarantees that instruction mnemonic matches.\n";
2972   OS << "    assert(Mnemonic == it->getMnemonic());\n\n";
2973 
2974   // Emit check that the required features are available.
2975   OS << "    // check if the available features match\n";
2976   OS << "    const FeatureBitset &RequiredFeatures = "
2977         "FeatureBitsets[it->RequiredFeaturesIdx];\n";
2978   OS << "    if (!ParseForAllFeatures && (AvailableFeatures & "
2979         "RequiredFeatures) != RequiredFeatures)\n";
2980   OS << "        continue;\n\n";
2981 
2982   // Emit check to ensure the operand number matches.
2983   OS << "    // check if the operand in question has a custom parser.\n";
2984   OS << "    if (!(it->OperandMask & (1 << NextOpNum)))\n";
2985   OS << "      continue;\n\n";
2986 
2987   // Emit call to the custom parser method
2988   OS << "    // call custom parse method to handle the operand\n";
2989   OS << "    OperandMatchResultTy Result = ";
2990   OS << "tryCustomParseOperand(Operands, it->Class);\n";
2991   OS << "    if (Result != MatchOperand_NoMatch)\n";
2992   OS << "      return Result;\n";
2993   OS << "  }\n\n";
2994 
2995   OS << "  // Okay, we had no match.\n";
2996   OS << "  return MatchOperand_NoMatch;\n";
2997   OS << "}\n\n";
2998 }
2999 
3000 static void emitAsmTiedOperandConstraints(CodeGenTarget &Target,
3001                                           AsmMatcherInfo &Info,
3002                                           raw_ostream &OS) {
3003   std::string AsmParserName =
3004       Info.AsmParser->getValueAsString("AsmParserClassName");
3005   OS << "static bool ";
3006   OS << "checkAsmTiedOperandConstraints(const " << Target.getName()
3007      << AsmParserName << "&AsmParser,\n";
3008   OS << "                               unsigned Kind,\n";
3009   OS << "                               const OperandVector &Operands,\n";
3010   OS << "                               uint64_t &ErrorInfo) {\n";
3011   OS << "  assert(Kind < CVT_NUM_SIGNATURES && \"Invalid signature!\");\n";
3012   OS << "  const uint8_t *Converter = ConversionTable[Kind];\n";
3013   OS << "  for (const uint8_t *p = Converter; *p; p+= 2) {\n";
3014   OS << "    switch (*p) {\n";
3015   OS << "    case CVT_Tied: {\n";
3016   OS << "      unsigned OpIdx = *(p+1);\n";
3017   OS << "      assert(OpIdx < (size_t)(std::end(TiedAsmOperandTable) -\n";
3018   OS << "                              std::begin(TiedAsmOperandTable)) &&\n";
3019   OS << "             \"Tied operand not found\");\n";
3020   OS << "      unsigned OpndNum1 = TiedAsmOperandTable[OpIdx][1];\n";
3021   OS << "      unsigned OpndNum2 = TiedAsmOperandTable[OpIdx][2];\n";
3022   OS << "      if (OpndNum1 != OpndNum2) {\n";
3023   OS << "        auto &SrcOp1 = Operands[OpndNum1];\n";
3024   OS << "        auto &SrcOp2 = Operands[OpndNum2];\n";
3025   OS << "        if (SrcOp1->isReg() && SrcOp2->isReg()) {\n";
3026   OS << "          if (!AsmParser.regsEqual(*SrcOp1, *SrcOp2)) {\n";
3027   OS << "            ErrorInfo = OpndNum2;\n";
3028   OS << "            return false;\n";
3029   OS << "          }\n";
3030   OS << "        }\n";
3031   OS << "      }\n";
3032   OS << "      break;\n";
3033   OS << "    }\n";
3034   OS << "    default:\n";
3035   OS << "      break;\n";
3036   OS << "    }\n";
3037   OS << "  }\n";
3038   OS << "  return true;\n";
3039   OS << "}\n\n";
3040 }
3041 
3042 static void emitMnemonicSpellChecker(raw_ostream &OS, CodeGenTarget &Target,
3043                                      unsigned VariantCount) {
3044   OS << "static std::string " << Target.getName()
3045      << "MnemonicSpellCheck(StringRef S, const FeatureBitset &FBS,"
3046      << " unsigned VariantID) {\n";
3047   if (!VariantCount)
3048     OS <<  "  return \"\";";
3049   else {
3050     OS << "  const unsigned MaxEditDist = 2;\n";
3051     OS << "  std::vector<StringRef> Candidates;\n";
3052     OS << "  StringRef Prev = \"\";\n\n";
3053 
3054     OS << "  // Find the appropriate table for this asm variant.\n";
3055     OS << "  const MatchEntry *Start, *End;\n";
3056     OS << "  switch (VariantID) {\n";
3057     OS << "  default: llvm_unreachable(\"invalid variant!\");\n";
3058     for (unsigned VC = 0; VC != VariantCount; ++VC) {
3059       Record *AsmVariant = Target.getAsmParserVariant(VC);
3060       int AsmVariantNo = AsmVariant->getValueAsInt("Variant");
3061       OS << "  case " << AsmVariantNo << ": Start = std::begin(MatchTable" << VC
3062          << "); End = std::end(MatchTable" << VC << "); break;\n";
3063     }
3064     OS << "  }\n\n";
3065     OS << "  for (auto I = Start; I < End; I++) {\n";
3066     OS << "    // Ignore unsupported instructions.\n";
3067     OS << "    const FeatureBitset &RequiredFeatures = "
3068           "FeatureBitsets[I->RequiredFeaturesIdx];\n";
3069     OS << "    if ((FBS & RequiredFeatures) != RequiredFeatures)\n";
3070     OS << "      continue;\n";
3071     OS << "\n";
3072     OS << "    StringRef T = I->getMnemonic();\n";
3073     OS << "    // Avoid recomputing the edit distance for the same string.\n";
3074     OS << "    if (T.equals(Prev))\n";
3075     OS << "      continue;\n";
3076     OS << "\n";
3077     OS << "    Prev = T;\n";
3078     OS << "    unsigned Dist = S.edit_distance(T, false, MaxEditDist);\n";
3079     OS << "    if (Dist <= MaxEditDist)\n";
3080     OS << "      Candidates.push_back(T);\n";
3081     OS << "  }\n";
3082     OS << "\n";
3083     OS << "  if (Candidates.empty())\n";
3084     OS << "    return \"\";\n";
3085     OS << "\n";
3086     OS << "  std::string Res = \", did you mean: \";\n";
3087     OS << "  unsigned i = 0;\n";
3088     OS << "  for( ; i < Candidates.size() - 1; i++)\n";
3089     OS << "    Res += Candidates[i].str() + \", \";\n";
3090     OS << "  return Res + Candidates[i].str() + \"?\";\n";
3091   }
3092   OS << "}\n";
3093   OS << "\n";
3094 }
3095 
3096 
3097 // Emit a function mapping match classes to strings, for debugging.
3098 static void emitMatchClassKindNames(std::forward_list<ClassInfo> &Infos,
3099                                     raw_ostream &OS) {
3100   OS << "#ifndef NDEBUG\n";
3101   OS << "const char *getMatchClassName(MatchClassKind Kind) {\n";
3102   OS << "  switch (Kind) {\n";
3103 
3104   OS << "  case InvalidMatchClass: return \"InvalidMatchClass\";\n";
3105   OS << "  case OptionalMatchClass: return \"OptionalMatchClass\";\n";
3106   for (const auto &CI : Infos) {
3107     OS << "  case " << CI.Name << ": return \"" << CI.Name << "\";\n";
3108   }
3109   OS << "  case NumMatchClassKinds: return \"NumMatchClassKinds\";\n";
3110 
3111   OS << "  }\n";
3112   OS << "  llvm_unreachable(\"unhandled MatchClassKind!\");\n";
3113   OS << "}\n\n";
3114   OS << "#endif // NDEBUG\n";
3115 }
3116 
3117 static std::string
3118 getNameForFeatureBitset(const std::vector<Record *> &FeatureBitset) {
3119   std::string Name = "AMFBS";
3120   for (const auto &Feature : FeatureBitset)
3121     Name += ("_" + Feature->getName()).str();
3122   return Name;
3123 }
3124 
3125 void AsmMatcherEmitter::run(raw_ostream &OS) {
3126   CodeGenTarget Target(Records);
3127   Record *AsmParser = Target.getAsmParser();
3128   StringRef ClassName = AsmParser->getValueAsString("AsmParserClassName");
3129 
3130   // Compute the information on the instructions to match.
3131   AsmMatcherInfo Info(AsmParser, Target, Records);
3132   Info.buildInfo();
3133 
3134   // Sort the instruction table using the partial order on classes. We use
3135   // stable_sort to ensure that ambiguous instructions are still
3136   // deterministically ordered.
3137   llvm::stable_sort(
3138       Info.Matchables,
3139       [](const std::unique_ptr<MatchableInfo> &a,
3140          const std::unique_ptr<MatchableInfo> &b) { return *a < *b; });
3141 
3142 #ifdef EXPENSIVE_CHECKS
3143   // Verify that the table is sorted and operator < works transitively.
3144   for (auto I = Info.Matchables.begin(), E = Info.Matchables.end(); I != E;
3145        ++I) {
3146     for (auto J = I; J != E; ++J) {
3147       assert(!(**J < **I));
3148     }
3149   }
3150 #endif
3151 
3152   DEBUG_WITH_TYPE("instruction_info", {
3153       for (const auto &MI : Info.Matchables)
3154         MI->dump();
3155     });
3156 
3157   // Check for ambiguous matchables.
3158   DEBUG_WITH_TYPE("ambiguous_instrs", {
3159     unsigned NumAmbiguous = 0;
3160     for (auto I = Info.Matchables.begin(), E = Info.Matchables.end(); I != E;
3161          ++I) {
3162       for (auto J = std::next(I); J != E; ++J) {
3163         const MatchableInfo &A = **I;
3164         const MatchableInfo &B = **J;
3165 
3166         if (A.couldMatchAmbiguouslyWith(B)) {
3167           errs() << "warning: ambiguous matchables:\n";
3168           A.dump();
3169           errs() << "\nis incomparable with:\n";
3170           B.dump();
3171           errs() << "\n\n";
3172           ++NumAmbiguous;
3173         }
3174       }
3175     }
3176     if (NumAmbiguous)
3177       errs() << "warning: " << NumAmbiguous
3178              << " ambiguous matchables!\n";
3179   });
3180 
3181   // Compute the information on the custom operand parsing.
3182   Info.buildOperandMatchInfo();
3183 
3184   bool HasMnemonicFirst = AsmParser->getValueAsBit("HasMnemonicFirst");
3185   bool HasOptionalOperands = Info.hasOptionalOperands();
3186   bool ReportMultipleNearMisses =
3187       AsmParser->getValueAsBit("ReportMultipleNearMisses");
3188 
3189   // Write the output.
3190 
3191   // Information for the class declaration.
3192   OS << "\n#ifdef GET_ASSEMBLER_HEADER\n";
3193   OS << "#undef GET_ASSEMBLER_HEADER\n";
3194   OS << "  // This should be included into the middle of the declaration of\n";
3195   OS << "  // your subclasses implementation of MCTargetAsmParser.\n";
3196   OS << "  FeatureBitset ComputeAvailableFeatures(const FeatureBitset& FB) const;\n";
3197   if (HasOptionalOperands) {
3198     OS << "  void convertToMCInst(unsigned Kind, MCInst &Inst, "
3199        << "unsigned Opcode,\n"
3200        << "                       const OperandVector &Operands,\n"
3201        << "                       const SmallBitVector &OptionalOperandsMask);\n";
3202   } else {
3203     OS << "  void convertToMCInst(unsigned Kind, MCInst &Inst, "
3204        << "unsigned Opcode,\n"
3205        << "                       const OperandVector &Operands);\n";
3206   }
3207   OS << "  void convertToMapAndConstraints(unsigned Kind,\n                ";
3208   OS << "           const OperandVector &Operands) override;\n";
3209   OS << "  unsigned MatchInstructionImpl(const OperandVector &Operands,\n"
3210      << "                                MCInst &Inst,\n";
3211   if (ReportMultipleNearMisses)
3212     OS << "                                SmallVectorImpl<NearMissInfo> *NearMisses,\n";
3213   else
3214     OS << "                                uint64_t &ErrorInfo,\n"
3215        << "                                FeatureBitset &MissingFeatures,\n";
3216   OS << "                                bool matchingInlineAsm,\n"
3217      << "                                unsigned VariantID = 0);\n";
3218   if (!ReportMultipleNearMisses)
3219     OS << "  unsigned MatchInstructionImpl(const OperandVector &Operands,\n"
3220        << "                                MCInst &Inst,\n"
3221        << "                                uint64_t &ErrorInfo,\n"
3222        << "                                bool matchingInlineAsm,\n"
3223        << "                                unsigned VariantID = 0) {\n"
3224        << "    FeatureBitset MissingFeatures;\n"
3225        << "    return MatchInstructionImpl(Operands, Inst, ErrorInfo, MissingFeatures,\n"
3226        << "                                matchingInlineAsm, VariantID);\n"
3227        << "  }\n\n";
3228 
3229 
3230   if (!Info.OperandMatchInfo.empty()) {
3231     OS << "  OperandMatchResultTy MatchOperandParserImpl(\n";
3232     OS << "    OperandVector &Operands,\n";
3233     OS << "    StringRef Mnemonic,\n";
3234     OS << "    bool ParseForAllFeatures = false);\n";
3235 
3236     OS << "  OperandMatchResultTy tryCustomParseOperand(\n";
3237     OS << "    OperandVector &Operands,\n";
3238     OS << "    unsigned MCK);\n\n";
3239   }
3240 
3241   OS << "#endif // GET_ASSEMBLER_HEADER_INFO\n\n";
3242 
3243   // Emit the operand match diagnostic enum names.
3244   OS << "\n#ifdef GET_OPERAND_DIAGNOSTIC_TYPES\n";
3245   OS << "#undef GET_OPERAND_DIAGNOSTIC_TYPES\n\n";
3246   emitOperandDiagnosticTypes(Info, OS);
3247   OS << "#endif // GET_OPERAND_DIAGNOSTIC_TYPES\n\n";
3248 
3249   OS << "\n#ifdef GET_REGISTER_MATCHER\n";
3250   OS << "#undef GET_REGISTER_MATCHER\n\n";
3251 
3252   // Emit the subtarget feature enumeration.
3253   SubtargetFeatureInfo::emitSubtargetFeatureBitEnumeration(
3254       Info.SubtargetFeatures, OS);
3255 
3256   // Emit the function to match a register name to number.
3257   // This should be omitted for Mips target
3258   if (AsmParser->getValueAsBit("ShouldEmitMatchRegisterName"))
3259     emitMatchRegisterName(Target, AsmParser, OS);
3260 
3261   if (AsmParser->getValueAsBit("ShouldEmitMatchRegisterAltName"))
3262     emitMatchRegisterAltName(Target, AsmParser, OS);
3263 
3264   OS << "#endif // GET_REGISTER_MATCHER\n\n";
3265 
3266   OS << "\n#ifdef GET_SUBTARGET_FEATURE_NAME\n";
3267   OS << "#undef GET_SUBTARGET_FEATURE_NAME\n\n";
3268 
3269   // Generate the helper function to get the names for subtarget features.
3270   emitGetSubtargetFeatureName(Info, OS);
3271 
3272   OS << "#endif // GET_SUBTARGET_FEATURE_NAME\n\n";
3273 
3274   OS << "\n#ifdef GET_MATCHER_IMPLEMENTATION\n";
3275   OS << "#undef GET_MATCHER_IMPLEMENTATION\n\n";
3276 
3277   // Generate the function that remaps for mnemonic aliases.
3278   bool HasMnemonicAliases = emitMnemonicAliases(OS, Info, Target);
3279 
3280   // Generate the convertToMCInst function to convert operands into an MCInst.
3281   // Also, generate the convertToMapAndConstraints function for MS-style inline
3282   // assembly.  The latter doesn't actually generate a MCInst.
3283   unsigned NumConverters = emitConvertFuncs(Target, ClassName, Info.Matchables,
3284                                             HasMnemonicFirst,
3285                                             HasOptionalOperands, OS);
3286 
3287   // Emit the enumeration for classes which participate in matching.
3288   emitMatchClassEnumeration(Target, Info.Classes, OS);
3289 
3290   // Emit a function to get the user-visible string to describe an operand
3291   // match failure in diagnostics.
3292   emitOperandMatchErrorDiagStrings(Info, OS);
3293 
3294   // Emit a function to map register classes to operand match failure codes.
3295   emitRegisterMatchErrorFunc(Info, OS);
3296 
3297   // Emit the routine to match token strings to their match class.
3298   emitMatchTokenString(Target, Info.Classes, OS);
3299 
3300   // Emit the subclass predicate routine.
3301   emitIsSubclass(Target, Info.Classes, OS);
3302 
3303   // Emit the routine to validate an operand against a match class.
3304   emitValidateOperandClass(Info, OS);
3305 
3306   emitMatchClassKindNames(Info.Classes, OS);
3307 
3308   // Emit the available features compute function.
3309   SubtargetFeatureInfo::emitComputeAssemblerAvailableFeatures(
3310       Info.Target.getName(), ClassName, "ComputeAvailableFeatures",
3311       Info.SubtargetFeatures, OS);
3312 
3313   if (!ReportMultipleNearMisses)
3314     emitAsmTiedOperandConstraints(Target, Info, OS);
3315 
3316   StringToOffsetTable StringTable;
3317 
3318   size_t MaxNumOperands = 0;
3319   unsigned MaxMnemonicIndex = 0;
3320   bool HasDeprecation = false;
3321   for (const auto &MI : Info.Matchables) {
3322     MaxNumOperands = std::max(MaxNumOperands, MI->AsmOperands.size());
3323     HasDeprecation |= MI->HasDeprecation;
3324 
3325     // Store a pascal-style length byte in the mnemonic.
3326     std::string LenMnemonic = char(MI->Mnemonic.size()) + MI->Mnemonic.str();
3327     MaxMnemonicIndex = std::max(MaxMnemonicIndex,
3328                         StringTable.GetOrAddStringOffset(LenMnemonic, false));
3329   }
3330 
3331   OS << "static const char *const MnemonicTable =\n";
3332   StringTable.EmitString(OS);
3333   OS << ";\n\n";
3334 
3335   std::vector<std::vector<Record *>> FeatureBitsets;
3336   for (const auto &MI : Info.Matchables) {
3337     if (MI->RequiredFeatures.empty())
3338       continue;
3339     FeatureBitsets.emplace_back();
3340     for (unsigned I = 0, E = MI->RequiredFeatures.size(); I != E; ++I)
3341       FeatureBitsets.back().push_back(MI->RequiredFeatures[I]->TheDef);
3342   }
3343 
3344   llvm::sort(FeatureBitsets, [&](const std::vector<Record *> &A,
3345                                  const std::vector<Record *> &B) {
3346     if (A.size() < B.size())
3347       return true;
3348     if (A.size() > B.size())
3349       return false;
3350     for (const auto &Pair : zip(A, B)) {
3351       if (std::get<0>(Pair)->getName() < std::get<1>(Pair)->getName())
3352         return true;
3353       if (std::get<0>(Pair)->getName() > std::get<1>(Pair)->getName())
3354         return false;
3355     }
3356     return false;
3357   });
3358   FeatureBitsets.erase(
3359       std::unique(FeatureBitsets.begin(), FeatureBitsets.end()),
3360       FeatureBitsets.end());
3361   OS << "// Feature bitsets.\n"
3362      << "enum : " << getMinimalTypeForRange(FeatureBitsets.size()) << " {\n"
3363      << "  AMFBS_None,\n";
3364   for (const auto &FeatureBitset : FeatureBitsets) {
3365     if (FeatureBitset.empty())
3366       continue;
3367     OS << "  " << getNameForFeatureBitset(FeatureBitset) << ",\n";
3368   }
3369   OS << "};\n\n"
3370      << "static constexpr FeatureBitset FeatureBitsets[] = {\n"
3371      << "  {}, // AMFBS_None\n";
3372   for (const auto &FeatureBitset : FeatureBitsets) {
3373     if (FeatureBitset.empty())
3374       continue;
3375     OS << "  {";
3376     for (const auto &Feature : FeatureBitset) {
3377       const auto &I = Info.SubtargetFeatures.find(Feature);
3378       assert(I != Info.SubtargetFeatures.end() && "Didn't import predicate?");
3379       OS << I->second.getEnumBitName() << ", ";
3380     }
3381     OS << "},\n";
3382   }
3383   OS << "};\n\n";
3384 
3385   // Emit the static match table; unused classes get initialized to 0 which is
3386   // guaranteed to be InvalidMatchClass.
3387   //
3388   // FIXME: We can reduce the size of this table very easily. First, we change
3389   // it so that store the kinds in separate bit-fields for each index, which
3390   // only needs to be the max width used for classes at that index (we also need
3391   // to reject based on this during classification). If we then make sure to
3392   // order the match kinds appropriately (putting mnemonics last), then we
3393   // should only end up using a few bits for each class, especially the ones
3394   // following the mnemonic.
3395   OS << "namespace {\n";
3396   OS << "  struct MatchEntry {\n";
3397   OS << "    " << getMinimalTypeForRange(MaxMnemonicIndex)
3398                << " Mnemonic;\n";
3399   OS << "    uint16_t Opcode;\n";
3400   OS << "    " << getMinimalTypeForRange(NumConverters)
3401                << " ConvertFn;\n";
3402   OS << "    " << getMinimalTypeForRange(FeatureBitsets.size())
3403                << " RequiredFeaturesIdx;\n";
3404   OS << "    " << getMinimalTypeForRange(
3405                       std::distance(Info.Classes.begin(), Info.Classes.end()))
3406      << " Classes[" << MaxNumOperands << "];\n";
3407   OS << "    StringRef getMnemonic() const {\n";
3408   OS << "      return StringRef(MnemonicTable + Mnemonic + 1,\n";
3409   OS << "                       MnemonicTable[Mnemonic]);\n";
3410   OS << "    }\n";
3411   OS << "  };\n\n";
3412 
3413   OS << "  // Predicate for searching for an opcode.\n";
3414   OS << "  struct LessOpcode {\n";
3415   OS << "    bool operator()(const MatchEntry &LHS, StringRef RHS) {\n";
3416   OS << "      return LHS.getMnemonic() < RHS;\n";
3417   OS << "    }\n";
3418   OS << "    bool operator()(StringRef LHS, const MatchEntry &RHS) {\n";
3419   OS << "      return LHS < RHS.getMnemonic();\n";
3420   OS << "    }\n";
3421   OS << "    bool operator()(const MatchEntry &LHS, const MatchEntry &RHS) {\n";
3422   OS << "      return LHS.getMnemonic() < RHS.getMnemonic();\n";
3423   OS << "    }\n";
3424   OS << "  };\n";
3425 
3426   OS << "} // end anonymous namespace\n\n";
3427 
3428   unsigned VariantCount = Target.getAsmParserVariantCount();
3429   for (unsigned VC = 0; VC != VariantCount; ++VC) {
3430     Record *AsmVariant = Target.getAsmParserVariant(VC);
3431     int AsmVariantNo = AsmVariant->getValueAsInt("Variant");
3432 
3433     OS << "static const MatchEntry MatchTable" << VC << "[] = {\n";
3434 
3435     for (const auto &MI : Info.Matchables) {
3436       if (MI->AsmVariantID != AsmVariantNo)
3437         continue;
3438 
3439       // Store a pascal-style length byte in the mnemonic.
3440       std::string LenMnemonic = char(MI->Mnemonic.size()) + MI->Mnemonic.str();
3441       OS << "  { " << StringTable.GetOrAddStringOffset(LenMnemonic, false)
3442          << " /* " << MI->Mnemonic << " */, "
3443          << Target.getInstNamespace() << "::"
3444          << MI->getResultInst()->TheDef->getName() << ", "
3445          << MI->ConversionFnKind << ", ";
3446 
3447       // Write the required features mask.
3448       OS << "AMFBS";
3449       if (MI->RequiredFeatures.empty())
3450         OS << "_None";
3451       else
3452         for (unsigned i = 0, e = MI->RequiredFeatures.size(); i != e; ++i)
3453           OS << '_' << MI->RequiredFeatures[i]->TheDef->getName();
3454 
3455       OS << ", { ";
3456       for (unsigned i = 0, e = MI->AsmOperands.size(); i != e; ++i) {
3457         const MatchableInfo::AsmOperand &Op = MI->AsmOperands[i];
3458 
3459         if (i) OS << ", ";
3460         OS << Op.Class->Name;
3461       }
3462       OS << " }, },\n";
3463     }
3464 
3465     OS << "};\n\n";
3466   }
3467 
3468   OS << "#include \"llvm/Support/Debug.h\"\n";
3469   OS << "#include \"llvm/Support/Format.h\"\n\n";
3470 
3471   // Finally, build the match function.
3472   OS << "unsigned " << Target.getName() << ClassName << "::\n"
3473      << "MatchInstructionImpl(const OperandVector &Operands,\n";
3474   OS << "                     MCInst &Inst,\n";
3475   if (ReportMultipleNearMisses)
3476     OS << "                     SmallVectorImpl<NearMissInfo> *NearMisses,\n";
3477   else
3478     OS << "                     uint64_t &ErrorInfo,\n"
3479        << "                     FeatureBitset &MissingFeatures,\n";
3480   OS << "                     bool matchingInlineAsm, unsigned VariantID) {\n";
3481 
3482   if (!ReportMultipleNearMisses) {
3483     OS << "  // Eliminate obvious mismatches.\n";
3484     OS << "  if (Operands.size() > "
3485        << (MaxNumOperands + HasMnemonicFirst) << ") {\n";
3486     OS << "    ErrorInfo = "
3487        << (MaxNumOperands + HasMnemonicFirst) << ";\n";
3488     OS << "    return Match_InvalidOperand;\n";
3489     OS << "  }\n\n";
3490   }
3491 
3492   // Emit code to get the available features.
3493   OS << "  // Get the current feature set.\n";
3494   OS << "  const FeatureBitset &AvailableFeatures = getAvailableFeatures();\n\n";
3495 
3496   OS << "  // Get the instruction mnemonic, which is the first token.\n";
3497   if (HasMnemonicFirst) {
3498     OS << "  StringRef Mnemonic = ((" << Target.getName()
3499        << "Operand&)*Operands[0]).getToken();\n\n";
3500   } else {
3501     OS << "  StringRef Mnemonic;\n";
3502     OS << "  if (Operands[0]->isToken())\n";
3503     OS << "    Mnemonic = ((" << Target.getName()
3504        << "Operand&)*Operands[0]).getToken();\n\n";
3505   }
3506 
3507   if (HasMnemonicAliases) {
3508     OS << "  // Process all MnemonicAliases to remap the mnemonic.\n";
3509     OS << "  applyMnemonicAliases(Mnemonic, AvailableFeatures, VariantID);\n\n";
3510   }
3511 
3512   // Emit code to compute the class list for this operand vector.
3513   if (!ReportMultipleNearMisses) {
3514     OS << "  // Some state to try to produce better error messages.\n";
3515     OS << "  bool HadMatchOtherThanFeatures = false;\n";
3516     OS << "  bool HadMatchOtherThanPredicate = false;\n";
3517     OS << "  unsigned RetCode = Match_InvalidOperand;\n";
3518     OS << "  MissingFeatures.set();\n";
3519     OS << "  // Set ErrorInfo to the operand that mismatches if it is\n";
3520     OS << "  // wrong for all instances of the instruction.\n";
3521     OS << "  ErrorInfo = ~0ULL;\n";
3522   }
3523 
3524   if (HasOptionalOperands) {
3525     OS << "  SmallBitVector OptionalOperandsMask(" << MaxNumOperands << ");\n";
3526   }
3527 
3528   // Emit code to search the table.
3529   OS << "  // Find the appropriate table for this asm variant.\n";
3530   OS << "  const MatchEntry *Start, *End;\n";
3531   OS << "  switch (VariantID) {\n";
3532   OS << "  default: llvm_unreachable(\"invalid variant!\");\n";
3533   for (unsigned VC = 0; VC != VariantCount; ++VC) {
3534     Record *AsmVariant = Target.getAsmParserVariant(VC);
3535     int AsmVariantNo = AsmVariant->getValueAsInt("Variant");
3536     OS << "  case " << AsmVariantNo << ": Start = std::begin(MatchTable" << VC
3537        << "); End = std::end(MatchTable" << VC << "); break;\n";
3538   }
3539   OS << "  }\n";
3540 
3541   OS << "  // Search the table.\n";
3542   if (HasMnemonicFirst) {
3543     OS << "  auto MnemonicRange = "
3544           "std::equal_range(Start, End, Mnemonic, LessOpcode());\n\n";
3545   } else {
3546     OS << "  auto MnemonicRange = std::make_pair(Start, End);\n";
3547     OS << "  unsigned SIndex = Mnemonic.empty() ? 0 : 1;\n";
3548     OS << "  if (!Mnemonic.empty())\n";
3549     OS << "    MnemonicRange = "
3550           "std::equal_range(Start, End, Mnemonic.lower(), LessOpcode());\n\n";
3551   }
3552 
3553   OS << "  DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"AsmMatcher: found \" <<\n"
3554      << "  std::distance(MnemonicRange.first, MnemonicRange.second) << \n"
3555      << "  \" encodings with mnemonic '\" << Mnemonic << \"'\\n\");\n\n";
3556 
3557   OS << "  // Return a more specific error code if no mnemonics match.\n";
3558   OS << "  if (MnemonicRange.first == MnemonicRange.second)\n";
3559   OS << "    return Match_MnemonicFail;\n\n";
3560 
3561   OS << "  for (const MatchEntry *it = MnemonicRange.first, "
3562      << "*ie = MnemonicRange.second;\n";
3563   OS << "       it != ie; ++it) {\n";
3564   OS << "    const FeatureBitset &RequiredFeatures = "
3565         "FeatureBitsets[it->RequiredFeaturesIdx];\n";
3566   OS << "    bool HasRequiredFeatures =\n";
3567   OS << "      (AvailableFeatures & RequiredFeatures) == RequiredFeatures;\n";
3568   OS << "    DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"Trying to match opcode \"\n";
3569   OS << "                                          << MII.getName(it->Opcode) << \"\\n\");\n";
3570 
3571   if (ReportMultipleNearMisses) {
3572     OS << "    // Some state to record ways in which this instruction did not match.\n";
3573     OS << "    NearMissInfo OperandNearMiss = NearMissInfo::getSuccess();\n";
3574     OS << "    NearMissInfo FeaturesNearMiss = NearMissInfo::getSuccess();\n";
3575     OS << "    NearMissInfo EarlyPredicateNearMiss = NearMissInfo::getSuccess();\n";
3576     OS << "    NearMissInfo LatePredicateNearMiss = NearMissInfo::getSuccess();\n";
3577     OS << "    bool MultipleInvalidOperands = false;\n";
3578   }
3579 
3580   if (HasMnemonicFirst) {
3581     OS << "    // equal_range guarantees that instruction mnemonic matches.\n";
3582     OS << "    assert(Mnemonic == it->getMnemonic());\n";
3583   }
3584 
3585   // Emit check that the subclasses match.
3586   if (!ReportMultipleNearMisses)
3587     OS << "    bool OperandsValid = true;\n";
3588   if (HasOptionalOperands) {
3589     OS << "    OptionalOperandsMask.reset(0, " << MaxNumOperands << ");\n";
3590   }
3591   OS << "    for (unsigned FormalIdx = " << (HasMnemonicFirst ? "0" : "SIndex")
3592      << ", ActualIdx = " << (HasMnemonicFirst ? "1" : "SIndex")
3593      << "; FormalIdx != " << MaxNumOperands << "; ++FormalIdx) {\n";
3594   OS << "      auto Formal = "
3595      << "static_cast<MatchClassKind>(it->Classes[FormalIdx]);\n";
3596   OS << "      DEBUG_WITH_TYPE(\"asm-matcher\",\n";
3597   OS << "                      dbgs() << \"  Matching formal operand class \" << getMatchClassName(Formal)\n";
3598   OS << "                             << \" against actual operand at index \" << ActualIdx);\n";
3599   OS << "      if (ActualIdx < Operands.size())\n";
3600   OS << "        DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \" (\";\n";
3601   OS << "                        Operands[ActualIdx]->print(dbgs()); dbgs() << \"): \");\n";
3602   OS << "      else\n";
3603   OS << "        DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \": \");\n";
3604   OS << "      if (ActualIdx >= Operands.size()) {\n";
3605   OS << "        DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"actual operand index out of range \");\n";
3606   if (ReportMultipleNearMisses) {
3607     OS << "        bool ThisOperandValid = (Formal == " <<"InvalidMatchClass) || "
3608                                    "isSubclass(Formal, OptionalMatchClass);\n";
3609     OS << "        if (!ThisOperandValid) {\n";
3610     OS << "          if (!OperandNearMiss) {\n";
3611     OS << "            // Record info about match failure for later use.\n";
3612     OS << "            DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"recording too-few-operands near miss\\n\");\n";
3613     OS << "            OperandNearMiss =\n";
3614     OS << "                NearMissInfo::getTooFewOperands(Formal, it->Opcode);\n";
3615     OS << "          } else if (OperandNearMiss.getKind() != NearMissInfo::NearMissTooFewOperands) {\n";
3616     OS << "            // If more than one operand is invalid, give up on this match entry.\n";
3617     OS << "            DEBUG_WITH_TYPE(\n";
3618     OS << "                \"asm-matcher\",\n";
3619     OS << "                dbgs() << \"second invalid operand, giving up on this opcode\\n\");\n";
3620     OS << "            MultipleInvalidOperands = true;\n";
3621     OS << "            break;\n";
3622     OS << "          }\n";
3623     OS << "        } else {\n";
3624     OS << "          DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"but formal operand not required\\n\");\n";
3625     OS << "          break;\n";
3626     OS << "        }\n";
3627     OS << "        continue;\n";
3628   } else {
3629     OS << "        OperandsValid = (Formal == InvalidMatchClass) || isSubclass(Formal, OptionalMatchClass);\n";
3630     OS << "        if (!OperandsValid) ErrorInfo = ActualIdx;\n";
3631     if (HasOptionalOperands) {
3632       OS << "        OptionalOperandsMask.set(FormalIdx, " << MaxNumOperands
3633          << ");\n";
3634     }
3635     OS << "        break;\n";
3636   }
3637   OS << "      }\n";
3638   OS << "      MCParsedAsmOperand &Actual = *Operands[ActualIdx];\n";
3639   OS << "      unsigned Diag = validateOperandClass(Actual, Formal);\n";
3640   OS << "      if (Diag == Match_Success) {\n";
3641   OS << "        DEBUG_WITH_TYPE(\"asm-matcher\",\n";
3642   OS << "                        dbgs() << \"match success using generic matcher\\n\");\n";
3643   OS << "        ++ActualIdx;\n";
3644   OS << "        continue;\n";
3645   OS << "      }\n";
3646   OS << "      // If the generic handler indicates an invalid operand\n";
3647   OS << "      // failure, check for a special case.\n";
3648   OS << "      if (Diag != Match_Success) {\n";
3649   OS << "        unsigned TargetDiag = validateTargetOperandClass(Actual, Formal);\n";
3650   OS << "        if (TargetDiag == Match_Success) {\n";
3651   OS << "          DEBUG_WITH_TYPE(\"asm-matcher\",\n";
3652   OS << "                          dbgs() << \"match success using target matcher\\n\");\n";
3653   OS << "          ++ActualIdx;\n";
3654   OS << "          continue;\n";
3655   OS << "        }\n";
3656   OS << "        // If the target matcher returned a specific error code use\n";
3657   OS << "        // that, else use the one from the generic matcher.\n";
3658   OS << "        if (TargetDiag != Match_InvalidOperand && "
3659         "HasRequiredFeatures)\n";
3660   OS << "          Diag = TargetDiag;\n";
3661   OS << "      }\n";
3662   OS << "      // If current formal operand wasn't matched and it is optional\n"
3663      << "      // then try to match next formal operand\n";
3664   OS << "      if (Diag == Match_InvalidOperand "
3665      << "&& isSubclass(Formal, OptionalMatchClass)) {\n";
3666   if (HasOptionalOperands) {
3667     OS << "        OptionalOperandsMask.set(FormalIdx);\n";
3668   }
3669     OS << "        DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"ignoring optional operand\\n\");\n";
3670   OS << "        continue;\n";
3671   OS << "      }\n";
3672 
3673   if (ReportMultipleNearMisses) {
3674     OS << "      if (!OperandNearMiss) {\n";
3675     OS << "        // If this is the first invalid operand we have seen, record some\n";
3676     OS << "        // information about it.\n";
3677     OS << "        DEBUG_WITH_TYPE(\n";
3678     OS << "            \"asm-matcher\",\n";
3679     OS << "            dbgs()\n";
3680     OS << "                << \"operand match failed, recording near-miss with diag code \"\n";
3681     OS << "                << Diag << \"\\n\");\n";
3682     OS << "        OperandNearMiss =\n";
3683     OS << "            NearMissInfo::getMissedOperand(Diag, Formal, it->Opcode, ActualIdx);\n";
3684     OS << "        ++ActualIdx;\n";
3685     OS << "      } else {\n";
3686     OS << "        // If more than one operand is invalid, give up on this match entry.\n";
3687     OS << "        DEBUG_WITH_TYPE(\n";
3688     OS << "            \"asm-matcher\",\n";
3689     OS << "            dbgs() << \"second operand mismatch, skipping this opcode\\n\");\n";
3690     OS << "        MultipleInvalidOperands = true;\n";
3691     OS << "        break;\n";
3692     OS << "      }\n";
3693     OS << "    }\n\n";
3694   } else {
3695     OS << "      // If this operand is broken for all of the instances of this\n";
3696     OS << "      // mnemonic, keep track of it so we can report loc info.\n";
3697     OS << "      // If we already had a match that only failed due to a\n";
3698     OS << "      // target predicate, that diagnostic is preferred.\n";
3699     OS << "      if (!HadMatchOtherThanPredicate &&\n";
3700     OS << "          (it == MnemonicRange.first || ErrorInfo <= ActualIdx)) {\n";
3701     OS << "        if (HasRequiredFeatures && (ErrorInfo != ActualIdx || Diag "
3702           "!= Match_InvalidOperand))\n";
3703     OS << "          RetCode = Diag;\n";
3704     OS << "        ErrorInfo = ActualIdx;\n";
3705     OS << "      }\n";
3706     OS << "      // Otherwise, just reject this instance of the mnemonic.\n";
3707     OS << "      OperandsValid = false;\n";
3708     OS << "      break;\n";
3709     OS << "    }\n\n";
3710   }
3711 
3712   if (ReportMultipleNearMisses)
3713     OS << "    if (MultipleInvalidOperands) {\n";
3714   else
3715     OS << "    if (!OperandsValid) {\n";
3716   OS << "      DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"Opcode result: multiple \"\n";
3717   OS << "                                               \"operand mismatches, ignoring \"\n";
3718   OS << "                                               \"this opcode\\n\");\n";
3719   OS << "      continue;\n";
3720   OS << "    }\n";
3721 
3722   // Emit check that the required features are available.
3723   OS << "    if (!HasRequiredFeatures) {\n";
3724   if (!ReportMultipleNearMisses)
3725     OS << "      HadMatchOtherThanFeatures = true;\n";
3726   OS << "      FeatureBitset NewMissingFeatures = RequiredFeatures & "
3727         "~AvailableFeatures;\n";
3728   OS << "      DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"Missing target features:\";\n";
3729   OS << "                       for (unsigned I = 0, E = NewMissingFeatures.size(); I != E; ++I)\n";
3730   OS << "                         if (NewMissingFeatures[I])\n";
3731   OS << "                           dbgs() << ' ' << I;\n";
3732   OS << "                       dbgs() << \"\\n\");\n";
3733   if (ReportMultipleNearMisses) {
3734     OS << "      FeaturesNearMiss = NearMissInfo::getMissedFeature(NewMissingFeatures);\n";
3735   } else {
3736     OS << "      if (NewMissingFeatures.count() <=\n"
3737           "          MissingFeatures.count())\n";
3738     OS << "        MissingFeatures = NewMissingFeatures;\n";
3739     OS << "      continue;\n";
3740   }
3741   OS << "    }\n";
3742   OS << "\n";
3743   OS << "    Inst.clear();\n\n";
3744   OS << "    Inst.setOpcode(it->Opcode);\n";
3745   // Verify the instruction with the target-specific match predicate function.
3746   OS << "    // We have a potential match but have not rendered the operands.\n"
3747      << "    // Check the target predicate to handle any context sensitive\n"
3748         "    // constraints.\n"
3749      << "    // For example, Ties that are referenced multiple times must be\n"
3750         "    // checked here to ensure the input is the same for each match\n"
3751         "    // constraints. If we leave it any later the ties will have been\n"
3752         "    // canonicalized\n"
3753      << "    unsigned MatchResult;\n"
3754      << "    if ((MatchResult = checkEarlyTargetMatchPredicate(Inst, "
3755         "Operands)) != Match_Success) {\n"
3756      << "      Inst.clear();\n";
3757   OS << "      DEBUG_WITH_TYPE(\n";
3758   OS << "          \"asm-matcher\",\n";
3759   OS << "          dbgs() << \"Early target match predicate failed with diag code \"\n";
3760   OS << "                 << MatchResult << \"\\n\");\n";
3761   if (ReportMultipleNearMisses) {
3762     OS << "      EarlyPredicateNearMiss = NearMissInfo::getMissedPredicate(MatchResult);\n";
3763   } else {
3764     OS << "      RetCode = MatchResult;\n"
3765        << "      HadMatchOtherThanPredicate = true;\n"
3766        << "      continue;\n";
3767   }
3768   OS << "    }\n\n";
3769 
3770   if (ReportMultipleNearMisses) {
3771     OS << "    // If we did not successfully match the operands, then we can't convert to\n";
3772     OS << "    // an MCInst, so bail out on this instruction variant now.\n";
3773     OS << "    if (OperandNearMiss) {\n";
3774     OS << "      // If the operand mismatch was the only problem, reprrt it as a near-miss.\n";
3775     OS << "      if (NearMisses && !FeaturesNearMiss && !EarlyPredicateNearMiss) {\n";
3776     OS << "        DEBUG_WITH_TYPE(\n";
3777     OS << "            \"asm-matcher\",\n";
3778     OS << "            dbgs()\n";
3779     OS << "                << \"Opcode result: one mismatched operand, adding near-miss\\n\");\n";
3780     OS << "        NearMisses->push_back(OperandNearMiss);\n";
3781     OS << "      } else {\n";
3782     OS << "        DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"Opcode result: multiple \"\n";
3783     OS << "                                                 \"types of mismatch, so not \"\n";
3784     OS << "                                                 \"reporting near-miss\\n\");\n";
3785     OS << "      }\n";
3786     OS << "      continue;\n";
3787     OS << "    }\n\n";
3788   }
3789 
3790   OS << "    if (matchingInlineAsm) {\n";
3791   OS << "      convertToMapAndConstraints(it->ConvertFn, Operands);\n";
3792   if (!ReportMultipleNearMisses) {
3793     OS << "      if (!checkAsmTiedOperandConstraints(*this, it->ConvertFn, "
3794           "Operands, ErrorInfo))\n";
3795     OS << "        return Match_InvalidTiedOperand;\n";
3796     OS << "\n";
3797   }
3798   OS << "      return Match_Success;\n";
3799   OS << "    }\n\n";
3800   OS << "    // We have selected a definite instruction, convert the parsed\n"
3801      << "    // operands into the appropriate MCInst.\n";
3802   if (HasOptionalOperands) {
3803     OS << "    convertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands,\n"
3804        << "                    OptionalOperandsMask);\n";
3805   } else {
3806     OS << "    convertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands);\n";
3807   }
3808   OS << "\n";
3809 
3810   // Verify the instruction with the target-specific match predicate function.
3811   OS << "    // We have a potential match. Check the target predicate to\n"
3812      << "    // handle any context sensitive constraints.\n"
3813      << "    if ((MatchResult = checkTargetMatchPredicate(Inst)) !="
3814      << " Match_Success) {\n"
3815      << "      DEBUG_WITH_TYPE(\"asm-matcher\",\n"
3816      << "                      dbgs() << \"Target match predicate failed with diag code \"\n"
3817      << "                             << MatchResult << \"\\n\");\n"
3818      << "      Inst.clear();\n";
3819   if (ReportMultipleNearMisses) {
3820     OS << "      LatePredicateNearMiss = NearMissInfo::getMissedPredicate(MatchResult);\n";
3821   } else {
3822     OS << "      RetCode = MatchResult;\n"
3823        << "      HadMatchOtherThanPredicate = true;\n"
3824        << "      continue;\n";
3825   }
3826   OS << "    }\n\n";
3827 
3828   if (ReportMultipleNearMisses) {
3829     OS << "    int NumNearMisses = ((int)(bool)OperandNearMiss +\n";
3830     OS << "                         (int)(bool)FeaturesNearMiss +\n";
3831     OS << "                         (int)(bool)EarlyPredicateNearMiss +\n";
3832     OS << "                         (int)(bool)LatePredicateNearMiss);\n";
3833     OS << "    if (NumNearMisses == 1) {\n";
3834     OS << "      // We had exactly one type of near-miss, so add that to the list.\n";
3835     OS << "      assert(!OperandNearMiss && \"OperandNearMiss was handled earlier\");\n";
3836     OS << "      DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"Opcode result: found one type of \"\n";
3837     OS << "                                            \"mismatch, so reporting a \"\n";
3838     OS << "                                            \"near-miss\\n\");\n";
3839     OS << "      if (NearMisses && FeaturesNearMiss)\n";
3840     OS << "        NearMisses->push_back(FeaturesNearMiss);\n";
3841     OS << "      else if (NearMisses && EarlyPredicateNearMiss)\n";
3842     OS << "        NearMisses->push_back(EarlyPredicateNearMiss);\n";
3843     OS << "      else if (NearMisses && LatePredicateNearMiss)\n";
3844     OS << "        NearMisses->push_back(LatePredicateNearMiss);\n";
3845     OS << "\n";
3846     OS << "      continue;\n";
3847     OS << "    } else if (NumNearMisses > 1) {\n";
3848     OS << "      // This instruction missed in more than one way, so ignore it.\n";
3849     OS << "      DEBUG_WITH_TYPE(\"asm-matcher\", dbgs() << \"Opcode result: multiple \"\n";
3850     OS << "                                               \"types of mismatch, so not \"\n";
3851     OS << "                                               \"reporting near-miss\\n\");\n";
3852     OS << "      continue;\n";
3853     OS << "    }\n";
3854   }
3855 
3856   // Call the post-processing function, if used.
3857   StringRef InsnCleanupFn = AsmParser->getValueAsString("AsmParserInstCleanup");
3858   if (!InsnCleanupFn.empty())
3859     OS << "    " << InsnCleanupFn << "(Inst);\n";
3860 
3861   if (HasDeprecation) {
3862     OS << "    std::string Info;\n";
3863     OS << "    if (!getParser().getTargetParser().\n";
3864     OS << "        getTargetOptions().MCNoDeprecatedWarn &&\n";
3865     OS << "        MII.get(Inst.getOpcode()).getDeprecatedInfo(Inst, getSTI(), Info)) {\n";
3866     OS << "      SMLoc Loc = ((" << Target.getName()
3867        << "Operand&)*Operands[0]).getStartLoc();\n";
3868     OS << "      getParser().Warning(Loc, Info, None);\n";
3869     OS << "    }\n";
3870   }
3871 
3872   if (!ReportMultipleNearMisses) {
3873     OS << "    if (!checkAsmTiedOperandConstraints(*this, it->ConvertFn, "
3874           "Operands, ErrorInfo))\n";
3875     OS << "      return Match_InvalidTiedOperand;\n";
3876     OS << "\n";
3877   }
3878 
3879   OS << "    DEBUG_WITH_TYPE(\n";
3880   OS << "        \"asm-matcher\",\n";
3881   OS << "        dbgs() << \"Opcode result: complete match, selecting this opcode\\n\");\n";
3882   OS << "    return Match_Success;\n";
3883   OS << "  }\n\n";
3884 
3885   if (ReportMultipleNearMisses) {
3886     OS << "  // No instruction variants matched exactly.\n";
3887     OS << "  return Match_NearMisses;\n";
3888   } else {
3889     OS << "  // Okay, we had no match.  Try to return a useful error code.\n";
3890     OS << "  if (HadMatchOtherThanPredicate || !HadMatchOtherThanFeatures)\n";
3891     OS << "    return RetCode;\n\n";
3892     OS << "  ErrorInfo = 0;\n";
3893     OS << "  return Match_MissingFeature;\n";
3894   }
3895   OS << "}\n\n";
3896 
3897   if (!Info.OperandMatchInfo.empty())
3898     emitCustomOperandParsing(OS, Target, Info, ClassName, StringTable,
3899                              MaxMnemonicIndex, FeatureBitsets.size(),
3900                              HasMnemonicFirst);
3901 
3902   OS << "#endif // GET_MATCHER_IMPLEMENTATION\n\n";
3903 
3904   OS << "\n#ifdef GET_MNEMONIC_SPELL_CHECKER\n";
3905   OS << "#undef GET_MNEMONIC_SPELL_CHECKER\n\n";
3906 
3907   emitMnemonicSpellChecker(OS, Target, VariantCount);
3908 
3909   OS << "#endif // GET_MNEMONIC_SPELL_CHECKER\n\n";
3910 }
3911 
3912 namespace llvm {
3913 
3914 void EmitAsmMatcher(RecordKeeper &RK, raw_ostream &OS) {
3915   emitSourceFileHeader("Assembly Matcher Source Fragment", OS);
3916   AsmMatcherEmitter(RK).run(OS);
3917 }
3918 
3919 } // end namespace llvm
3920