1*0b57cec5SDimitry Andric //===--------------------- SchedulerStatistics.h ----------------*- C++ -*-===// 2*0b57cec5SDimitry Andric // 3*0b57cec5SDimitry Andric // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4*0b57cec5SDimitry Andric // See https://llvm.org/LICENSE.txt for license information. 5*0b57cec5SDimitry Andric // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6*0b57cec5SDimitry Andric // 7*0b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 8*0b57cec5SDimitry Andric /// \file 9*0b57cec5SDimitry Andric /// 10*0b57cec5SDimitry Andric /// This file defines class SchedulerStatistics. Class SchedulerStatistics is a 11*0b57cec5SDimitry Andric /// View that listens to instruction issue events in order to print general 12*0b57cec5SDimitry Andric /// statistics related to the hardware schedulers. 13*0b57cec5SDimitry Andric /// 14*0b57cec5SDimitry Andric /// Example: 15*0b57cec5SDimitry Andric /// ======== 16*0b57cec5SDimitry Andric /// 17*0b57cec5SDimitry Andric /// Schedulers - number of cycles where we saw N instructions issued: 18*0b57cec5SDimitry Andric /// [# issued], [# cycles] 19*0b57cec5SDimitry Andric /// 0, 6 (2.9%) 20*0b57cec5SDimitry Andric /// 1, 106 (50.7%) 21*0b57cec5SDimitry Andric /// 2, 97 (46.4%) 22*0b57cec5SDimitry Andric /// 23*0b57cec5SDimitry Andric /// Scheduler's queue usage: 24*0b57cec5SDimitry Andric /// [1] Resource name. 25*0b57cec5SDimitry Andric /// [2] Average number of used buffer entries. 26*0b57cec5SDimitry Andric /// [3] Maximum number of used buffer entries. 27*0b57cec5SDimitry Andric /// [4] Total number of buffer entries. 28*0b57cec5SDimitry Andric /// 29*0b57cec5SDimitry Andric /// [1] [2] [3] [4] 30*0b57cec5SDimitry Andric /// JALU01 0 0 20 31*0b57cec5SDimitry Andric /// JFPU01 15 18 18 32*0b57cec5SDimitry Andric /// JLSAGU 0 0 12 33*0b57cec5SDimitry Andric // 34*0b57cec5SDimitry Andric //===----------------------------------------------------------------------===// 35*0b57cec5SDimitry Andric 36*0b57cec5SDimitry Andric #ifndef LLVM_TOOLS_LLVM_MCA_SCHEDULERSTATISTICS_H 37*0b57cec5SDimitry Andric #define LLVM_TOOLS_LLVM_MCA_SCHEDULERSTATISTICS_H 38*0b57cec5SDimitry Andric 39*0b57cec5SDimitry Andric #include "Views/View.h" 40*0b57cec5SDimitry Andric #include "llvm/ADT/SmallVector.h" 41*0b57cec5SDimitry Andric #include "llvm/MC/MCSubtargetInfo.h" 42*0b57cec5SDimitry Andric #include <map> 43*0b57cec5SDimitry Andric 44*0b57cec5SDimitry Andric namespace llvm { 45*0b57cec5SDimitry Andric namespace mca { 46*0b57cec5SDimitry Andric 47*0b57cec5SDimitry Andric class SchedulerStatistics final : public View { 48*0b57cec5SDimitry Andric const llvm::MCSchedModel &SM; 49*0b57cec5SDimitry Andric unsigned LQResourceID; 50*0b57cec5SDimitry Andric unsigned SQResourceID; 51*0b57cec5SDimitry Andric 52*0b57cec5SDimitry Andric unsigned NumIssued; 53*0b57cec5SDimitry Andric unsigned NumCycles; 54*0b57cec5SDimitry Andric 55*0b57cec5SDimitry Andric unsigned MostRecentLoadDispatched; 56*0b57cec5SDimitry Andric unsigned MostRecentStoreDispatched; 57*0b57cec5SDimitry Andric 58*0b57cec5SDimitry Andric // Tracks the usage of a scheduler's queue. 59*0b57cec5SDimitry Andric struct BufferUsage { 60*0b57cec5SDimitry Andric unsigned SlotsInUse; 61*0b57cec5SDimitry Andric unsigned MaxUsedSlots; 62*0b57cec5SDimitry Andric uint64_t CumulativeNumUsedSlots; 63*0b57cec5SDimitry Andric }; 64*0b57cec5SDimitry Andric 65*0b57cec5SDimitry Andric using Histogram = std::map<unsigned, unsigned>; 66*0b57cec5SDimitry Andric Histogram IssueWidthPerCycle; 67*0b57cec5SDimitry Andric 68*0b57cec5SDimitry Andric std::vector<BufferUsage> Usage; 69*0b57cec5SDimitry Andric 70*0b57cec5SDimitry Andric void updateHistograms(); 71*0b57cec5SDimitry Andric void printSchedulerStats(llvm::raw_ostream &OS) const; 72*0b57cec5SDimitry Andric void printSchedulerUsage(llvm::raw_ostream &OS) const; 73*0b57cec5SDimitry Andric 74*0b57cec5SDimitry Andric public: 75*0b57cec5SDimitry Andric SchedulerStatistics(const llvm::MCSubtargetInfo &STI); 76*0b57cec5SDimitry Andric void onEvent(const HWInstructionEvent &Event) override; 77*0b57cec5SDimitry Andric void onCycleBegin() override { NumCycles++; } 78*0b57cec5SDimitry Andric void onCycleEnd() override { updateHistograms(); } 79*0b57cec5SDimitry Andric 80*0b57cec5SDimitry Andric // Increases the number of used scheduler queue slots of every buffered 81*0b57cec5SDimitry Andric // resource in the Buffers set. 82*0b57cec5SDimitry Andric void onReservedBuffers(const InstRef &IR, 83*0b57cec5SDimitry Andric llvm::ArrayRef<unsigned> Buffers) override; 84*0b57cec5SDimitry Andric 85*0b57cec5SDimitry Andric // Decreases by one the number of used scheduler queue slots of every 86*0b57cec5SDimitry Andric // buffered resource in the Buffers set. 87*0b57cec5SDimitry Andric void onReleasedBuffers(const InstRef &IR, 88*0b57cec5SDimitry Andric llvm::ArrayRef<unsigned> Buffers) override; 89*0b57cec5SDimitry Andric 90*0b57cec5SDimitry Andric void printView(llvm::raw_ostream &OS) const override; 91*0b57cec5SDimitry Andric }; 92*0b57cec5SDimitry Andric } // namespace mca 93*0b57cec5SDimitry Andric } // namespace llvm 94*0b57cec5SDimitry Andric 95*0b57cec5SDimitry Andric #endif 96