1 //===-- X86TargetParser - Parser for X86 features ---------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements a target parser to recognise X86 hardware features. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "llvm/TargetParser/X86TargetParser.h" 14 #include "llvm/ADT/StringSwitch.h" 15 #include <numeric> 16 17 using namespace llvm; 18 using namespace llvm::X86; 19 20 namespace { 21 22 /// Container class for CPU features. 23 /// This is a constexpr reimplementation of a subset of std::bitset. It would be 24 /// nice to use std::bitset directly, but it doesn't support constant 25 /// initialization. 26 class FeatureBitset { 27 static constexpr unsigned NUM_FEATURE_WORDS = 28 (X86::CPU_FEATURE_MAX + 31) / 32; 29 30 // This cannot be a std::array, operator[] is not constexpr until C++17. 31 uint32_t Bits[NUM_FEATURE_WORDS] = {}; 32 33 public: 34 constexpr FeatureBitset() = default; 35 constexpr FeatureBitset(std::initializer_list<unsigned> Init) { 36 for (auto I : Init) 37 set(I); 38 } 39 40 bool any() const { 41 return llvm::any_of(Bits, [](uint64_t V) { return V != 0; }); 42 } 43 44 constexpr FeatureBitset &set(unsigned I) { 45 // GCC <6.2 crashes if this is written in a single statement. 46 uint32_t NewBits = Bits[I / 32] | (uint32_t(1) << (I % 32)); 47 Bits[I / 32] = NewBits; 48 return *this; 49 } 50 51 constexpr bool operator[](unsigned I) const { 52 uint32_t Mask = uint32_t(1) << (I % 32); 53 return (Bits[I / 32] & Mask) != 0; 54 } 55 56 constexpr FeatureBitset &operator&=(const FeatureBitset &RHS) { 57 for (unsigned I = 0, E = std::size(Bits); I != E; ++I) { 58 // GCC <6.2 crashes if this is written in a single statement. 59 uint32_t NewBits = Bits[I] & RHS.Bits[I]; 60 Bits[I] = NewBits; 61 } 62 return *this; 63 } 64 65 constexpr FeatureBitset &operator|=(const FeatureBitset &RHS) { 66 for (unsigned I = 0, E = std::size(Bits); I != E; ++I) { 67 // GCC <6.2 crashes if this is written in a single statement. 68 uint32_t NewBits = Bits[I] | RHS.Bits[I]; 69 Bits[I] = NewBits; 70 } 71 return *this; 72 } 73 74 // gcc 5.3 miscompiles this if we try to write this using operator&=. 75 constexpr FeatureBitset operator&(const FeatureBitset &RHS) const { 76 FeatureBitset Result; 77 for (unsigned I = 0, E = std::size(Bits); I != E; ++I) 78 Result.Bits[I] = Bits[I] & RHS.Bits[I]; 79 return Result; 80 } 81 82 // gcc 5.3 miscompiles this if we try to write this using operator&=. 83 constexpr FeatureBitset operator|(const FeatureBitset &RHS) const { 84 FeatureBitset Result; 85 for (unsigned I = 0, E = std::size(Bits); I != E; ++I) 86 Result.Bits[I] = Bits[I] | RHS.Bits[I]; 87 return Result; 88 } 89 90 constexpr FeatureBitset operator~() const { 91 FeatureBitset Result; 92 for (unsigned I = 0, E = std::size(Bits); I != E; ++I) 93 Result.Bits[I] = ~Bits[I]; 94 return Result; 95 } 96 97 constexpr bool operator!=(const FeatureBitset &RHS) const { 98 for (unsigned I = 0, E = std::size(Bits); I != E; ++I) 99 if (Bits[I] != RHS.Bits[I]) 100 return true; 101 return false; 102 } 103 }; 104 105 struct ProcInfo { 106 StringLiteral Name; 107 X86::CPUKind Kind; 108 unsigned KeyFeature; 109 FeatureBitset Features; 110 }; 111 112 struct FeatureInfo { 113 StringLiteral Name; 114 FeatureBitset ImpliedFeatures; 115 }; 116 117 } // end anonymous namespace 118 119 #define X86_FEATURE(ENUM, STRING) \ 120 constexpr FeatureBitset Feature##ENUM = {X86::FEATURE_##ENUM}; 121 #include "llvm/TargetParser/X86TargetParser.def" 122 123 // Pentium with MMX. 124 constexpr FeatureBitset FeaturesPentiumMMX = 125 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX; 126 127 // Pentium 2 and 3. 128 constexpr FeatureBitset FeaturesPentium2 = 129 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | FeatureFXSR; 130 constexpr FeatureBitset FeaturesPentium3 = FeaturesPentium2 | FeatureSSE; 131 132 // Pentium 4 CPUs 133 constexpr FeatureBitset FeaturesPentium4 = FeaturesPentium3 | FeatureSSE2; 134 constexpr FeatureBitset FeaturesPrescott = FeaturesPentium4 | FeatureSSE3; 135 constexpr FeatureBitset FeaturesNocona = 136 FeaturesPrescott | Feature64BIT | FeatureCMPXCHG16B; 137 138 // Basic 64-bit capable CPU. 139 constexpr FeatureBitset FeaturesX86_64 = FeaturesPentium4 | Feature64BIT; 140 constexpr FeatureBitset FeaturesX86_64_V2 = FeaturesX86_64 | FeatureSAHF | 141 FeaturePOPCNT | FeatureCRC32 | 142 FeatureSSE4_2 | FeatureCMPXCHG16B; 143 constexpr FeatureBitset FeaturesX86_64_V3 = 144 FeaturesX86_64_V2 | FeatureAVX2 | FeatureBMI | FeatureBMI2 | FeatureF16C | 145 FeatureFMA | FeatureLZCNT | FeatureMOVBE | FeatureXSAVE; 146 constexpr FeatureBitset FeaturesX86_64_V4 = FeaturesX86_64_V3 | 147 FeatureAVX512BW | FeatureAVX512CD | 148 FeatureAVX512DQ | FeatureAVX512VL; 149 150 // Intel Core CPUs 151 constexpr FeatureBitset FeaturesCore2 = 152 FeaturesNocona | FeatureSAHF | FeatureSSSE3; 153 constexpr FeatureBitset FeaturesPenryn = FeaturesCore2 | FeatureSSE4_1; 154 constexpr FeatureBitset FeaturesNehalem = 155 FeaturesPenryn | FeaturePOPCNT | FeatureCRC32 | FeatureSSE4_2; 156 constexpr FeatureBitset FeaturesWestmere = FeaturesNehalem | FeaturePCLMUL; 157 constexpr FeatureBitset FeaturesSandyBridge = 158 FeaturesWestmere | FeatureAVX | FeatureXSAVE | FeatureXSAVEOPT; 159 constexpr FeatureBitset FeaturesIvyBridge = 160 FeaturesSandyBridge | FeatureF16C | FeatureFSGSBASE | FeatureRDRND; 161 constexpr FeatureBitset FeaturesHaswell = 162 FeaturesIvyBridge | FeatureAVX2 | FeatureBMI | FeatureBMI2 | FeatureFMA | 163 FeatureINVPCID | FeatureLZCNT | FeatureMOVBE; 164 constexpr FeatureBitset FeaturesBroadwell = 165 FeaturesHaswell | FeatureADX | FeaturePRFCHW | FeatureRDSEED; 166 167 // Intel Knights Landing and Knights Mill 168 // Knights Landing has feature parity with Broadwell. 169 constexpr FeatureBitset FeaturesKNL = 170 FeaturesBroadwell | FeatureAES | FeatureAVX512F | FeatureAVX512CD | 171 FeatureAVX512ER | FeatureAVX512PF | FeaturePREFETCHWT1; 172 constexpr FeatureBitset FeaturesKNM = FeaturesKNL | FeatureAVX512VPOPCNTDQ; 173 174 // Intel Skylake processors. 175 constexpr FeatureBitset FeaturesSkylakeClient = 176 FeaturesBroadwell | FeatureAES | FeatureCLFLUSHOPT | FeatureXSAVEC | 177 FeatureXSAVES | FeatureSGX; 178 // SkylakeServer inherits all SkylakeClient features except SGX. 179 // FIXME: That doesn't match gcc. 180 constexpr FeatureBitset FeaturesSkylakeServer = 181 (FeaturesSkylakeClient & ~FeatureSGX) | FeatureAVX512F | FeatureAVX512CD | 182 FeatureAVX512DQ | FeatureAVX512BW | FeatureAVX512VL | FeatureCLWB | 183 FeaturePKU; 184 constexpr FeatureBitset FeaturesCascadeLake = 185 FeaturesSkylakeServer | FeatureAVX512VNNI; 186 constexpr FeatureBitset FeaturesCooperLake = 187 FeaturesCascadeLake | FeatureAVX512BF16; 188 189 // Intel 10nm processors. 190 constexpr FeatureBitset FeaturesCannonlake = 191 FeaturesSkylakeClient | FeatureAVX512F | FeatureAVX512CD | FeatureAVX512DQ | 192 FeatureAVX512BW | FeatureAVX512VL | FeatureAVX512IFMA | FeatureAVX512VBMI | 193 FeaturePKU | FeatureSHA; 194 constexpr FeatureBitset FeaturesICLClient = 195 FeaturesCannonlake | FeatureAVX512BITALG | FeatureAVX512VBMI2 | 196 FeatureAVX512VNNI | FeatureAVX512VPOPCNTDQ | FeatureGFNI | FeatureRDPID | 197 FeatureVAES | FeatureVPCLMULQDQ; 198 constexpr FeatureBitset FeaturesRocketlake = FeaturesICLClient & ~FeatureSGX; 199 constexpr FeatureBitset FeaturesICLServer = 200 FeaturesICLClient | FeatureCLWB | FeaturePCONFIG | FeatureWBNOINVD; 201 constexpr FeatureBitset FeaturesTigerlake = 202 FeaturesICLClient | FeatureAVX512VP2INTERSECT | FeatureMOVDIR64B | 203 FeatureCLWB | FeatureMOVDIRI | FeatureSHSTK | FeatureKL | FeatureWIDEKL; 204 constexpr FeatureBitset FeaturesSapphireRapids = 205 FeaturesICLServer | FeatureAMX_BF16 | FeatureAMX_INT8 | FeatureAMX_TILE | 206 FeatureAVX512BF16 | FeatureAVX512FP16 | FeatureAVXVNNI | FeatureCLDEMOTE | 207 FeatureENQCMD | FeatureMOVDIR64B | FeatureMOVDIRI | FeaturePTWRITE | 208 FeatureSERIALIZE | FeatureSHSTK | FeatureTSXLDTRK | FeatureUINTR | 209 FeatureWAITPKG; 210 constexpr FeatureBitset FeaturesGraniteRapids = 211 FeaturesSapphireRapids | FeatureAMX_FP16 | FeaturePREFETCHI; 212 213 // Intel Atom processors. 214 // Bonnell has feature parity with Core2 and adds MOVBE. 215 constexpr FeatureBitset FeaturesBonnell = FeaturesCore2 | FeatureMOVBE; 216 // Silvermont has parity with Westmere and Bonnell plus PRFCHW and RDRND. 217 constexpr FeatureBitset FeaturesSilvermont = 218 FeaturesBonnell | FeaturesWestmere | FeaturePRFCHW | FeatureRDRND; 219 constexpr FeatureBitset FeaturesGoldmont = 220 FeaturesSilvermont | FeatureAES | FeatureCLFLUSHOPT | FeatureFSGSBASE | 221 FeatureRDSEED | FeatureSHA | FeatureXSAVE | FeatureXSAVEC | 222 FeatureXSAVEOPT | FeatureXSAVES; 223 constexpr FeatureBitset FeaturesGoldmontPlus = 224 FeaturesGoldmont | FeaturePTWRITE | FeatureRDPID | FeatureSGX; 225 constexpr FeatureBitset FeaturesTremont = 226 FeaturesGoldmontPlus | FeatureCLWB | FeatureGFNI; 227 constexpr FeatureBitset FeaturesAlderlake = 228 FeaturesTremont | FeatureADX | FeatureBMI | FeatureBMI2 | FeatureF16C | 229 FeatureFMA | FeatureINVPCID | FeatureLZCNT | FeaturePCONFIG | FeaturePKU | 230 FeatureSERIALIZE | FeatureSHSTK | FeatureVAES | FeatureVPCLMULQDQ | 231 FeatureCLDEMOTE | FeatureMOVDIR64B | FeatureMOVDIRI | FeatureWAITPKG | 232 FeatureAVXVNNI | FeatureHRESET | FeatureWIDEKL; 233 constexpr FeatureBitset FeaturesSierraforest = 234 FeaturesAlderlake | FeatureCMPCCXADD | FeatureAVXIFMA | 235 FeatureAVXNECONVERT | FeatureAVXVNNIINT8; 236 constexpr FeatureBitset FeaturesGrandridge = 237 FeaturesSierraforest | FeatureRAOINT; 238 239 // Geode Processor. 240 constexpr FeatureBitset FeaturesGeode = 241 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | Feature3DNOW | Feature3DNOWA; 242 243 // K6 processor. 244 constexpr FeatureBitset FeaturesK6 = FeatureX87 | FeatureCMPXCHG8B | FeatureMMX; 245 246 // K7 and K8 architecture processors. 247 constexpr FeatureBitset FeaturesAthlon = 248 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | Feature3DNOW | Feature3DNOWA; 249 constexpr FeatureBitset FeaturesAthlonXP = 250 FeaturesAthlon | FeatureFXSR | FeatureSSE; 251 constexpr FeatureBitset FeaturesK8 = 252 FeaturesAthlonXP | FeatureSSE2 | Feature64BIT; 253 constexpr FeatureBitset FeaturesK8SSE3 = FeaturesK8 | FeatureSSE3; 254 constexpr FeatureBitset FeaturesAMDFAM10 = 255 FeaturesK8SSE3 | FeatureCMPXCHG16B | FeatureLZCNT | FeaturePOPCNT | 256 FeaturePRFCHW | FeatureSAHF | FeatureSSE4_A; 257 258 // Bobcat architecture processors. 259 constexpr FeatureBitset FeaturesBTVER1 = 260 FeatureX87 | FeatureCMPXCHG8B | FeatureCMPXCHG16B | Feature64BIT | 261 FeatureFXSR | FeatureLZCNT | FeatureMMX | FeaturePOPCNT | FeaturePRFCHW | 262 FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_A | 263 FeatureSAHF; 264 constexpr FeatureBitset FeaturesBTVER2 = 265 FeaturesBTVER1 | FeatureAES | FeatureAVX | FeatureBMI | FeatureCRC32 | 266 FeatureF16C | FeatureMOVBE | FeaturePCLMUL | FeatureXSAVE | FeatureXSAVEOPT; 267 268 // AMD Bulldozer architecture processors. 269 constexpr FeatureBitset FeaturesBDVER1 = 270 FeatureX87 | FeatureAES | FeatureAVX | FeatureCMPXCHG8B | 271 FeatureCMPXCHG16B | FeatureCRC32 | Feature64BIT | FeatureFMA4 | 272 FeatureFXSR | FeatureLWP | FeatureLZCNT | FeatureMMX | FeaturePCLMUL | 273 FeaturePOPCNT | FeaturePRFCHW | FeatureSAHF | FeatureSSE | FeatureSSE2 | 274 FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_1 | FeatureSSE4_2 | FeatureSSE4_A | 275 FeatureXOP | FeatureXSAVE; 276 constexpr FeatureBitset FeaturesBDVER2 = 277 FeaturesBDVER1 | FeatureBMI | FeatureFMA | FeatureF16C | FeatureTBM; 278 constexpr FeatureBitset FeaturesBDVER3 = 279 FeaturesBDVER2 | FeatureFSGSBASE | FeatureXSAVEOPT; 280 constexpr FeatureBitset FeaturesBDVER4 = FeaturesBDVER3 | FeatureAVX2 | 281 FeatureBMI2 | FeatureMOVBE | 282 FeatureMWAITX | FeatureRDRND; 283 284 // AMD Zen architecture processors. 285 constexpr FeatureBitset FeaturesZNVER1 = 286 FeatureX87 | FeatureADX | FeatureAES | FeatureAVX | FeatureAVX2 | 287 FeatureBMI | FeatureBMI2 | FeatureCLFLUSHOPT | FeatureCLZERO | 288 FeatureCMPXCHG8B | FeatureCMPXCHG16B | FeatureCRC32 | Feature64BIT | 289 FeatureF16C | FeatureFMA | FeatureFSGSBASE | FeatureFXSR | FeatureLZCNT | 290 FeatureMMX | FeatureMOVBE | FeatureMWAITX | FeaturePCLMUL | FeaturePOPCNT | 291 FeaturePRFCHW | FeatureRDRND | FeatureRDSEED | FeatureSAHF | FeatureSHA | 292 FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_1 | 293 FeatureSSE4_2 | FeatureSSE4_A | FeatureXSAVE | FeatureXSAVEC | 294 FeatureXSAVEOPT | FeatureXSAVES; 295 constexpr FeatureBitset FeaturesZNVER2 = FeaturesZNVER1 | FeatureCLWB | 296 FeatureRDPID | FeatureRDPRU | 297 FeatureWBNOINVD; 298 static constexpr FeatureBitset FeaturesZNVER3 = FeaturesZNVER2 | 299 FeatureINVPCID | FeaturePKU | 300 FeatureVAES | FeatureVPCLMULQDQ; 301 static constexpr FeatureBitset FeaturesZNVER4 = 302 FeaturesZNVER3 | FeatureAVX512F | FeatureAVX512CD | FeatureAVX512DQ | 303 FeatureAVX512BW | FeatureAVX512VL | FeatureAVX512IFMA | FeatureAVX512VBMI | 304 FeatureAVX512VBMI2 | FeatureAVX512VNNI | FeatureAVX512BITALG | 305 FeatureAVX512VPOPCNTDQ | FeatureAVX512BF16 | FeatureGFNI | 306 FeatureSHSTK; 307 308 constexpr ProcInfo Processors[] = { 309 // Empty processor. Include X87 and CMPXCHG8 for backwards compatibility. 310 { {""}, CK_None, ~0U, FeatureX87 | FeatureCMPXCHG8B }, 311 // i386-generation processors. 312 { {"i386"}, CK_i386, ~0U, FeatureX87 }, 313 // i486-generation processors. 314 { {"i486"}, CK_i486, ~0U, FeatureX87 }, 315 { {"winchip-c6"}, CK_WinChipC6, ~0U, FeaturesPentiumMMX }, 316 { {"winchip2"}, CK_WinChip2, ~0U, FeaturesPentiumMMX | Feature3DNOW }, 317 { {"c3"}, CK_C3, ~0U, FeaturesPentiumMMX | Feature3DNOW }, 318 // i586-generation processors, P5 microarchitecture based. 319 { {"i586"}, CK_i586, ~0U, FeatureX87 | FeatureCMPXCHG8B }, 320 { {"pentium"}, CK_Pentium, ~0U, FeatureX87 | FeatureCMPXCHG8B }, 321 { {"pentium-mmx"}, CK_PentiumMMX, ~0U, FeaturesPentiumMMX }, 322 // i686-generation processors, P6 / Pentium M microarchitecture based. 323 { {"pentiumpro"}, CK_PentiumPro, ~0U, FeatureX87 | FeatureCMPXCHG8B }, 324 { {"i686"}, CK_i686, ~0U, FeatureX87 | FeatureCMPXCHG8B }, 325 { {"pentium2"}, CK_Pentium2, ~0U, FeaturesPentium2 }, 326 { {"pentium3"}, CK_Pentium3, ~0U, FeaturesPentium3 }, 327 { {"pentium3m"}, CK_Pentium3, ~0U, FeaturesPentium3 }, 328 { {"pentium-m"}, CK_PentiumM, ~0U, FeaturesPentium4 }, 329 { {"c3-2"}, CK_C3_2, ~0U, FeaturesPentium3 }, 330 { {"yonah"}, CK_Yonah, ~0U, FeaturesPrescott }, 331 // Netburst microarchitecture based processors. 332 { {"pentium4"}, CK_Pentium4, ~0U, FeaturesPentium4 }, 333 { {"pentium4m"}, CK_Pentium4, ~0U, FeaturesPentium4 }, 334 { {"prescott"}, CK_Prescott, ~0U, FeaturesPrescott }, 335 { {"nocona"}, CK_Nocona, ~0U, FeaturesNocona }, 336 // Core microarchitecture based processors. 337 { {"core2"}, CK_Core2, FEATURE_SSSE3, FeaturesCore2 }, 338 { {"penryn"}, CK_Penryn, ~0U, FeaturesPenryn }, 339 // Atom processors 340 { {"bonnell"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell }, 341 { {"atom"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell }, 342 { {"silvermont"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont }, 343 { {"slm"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont }, 344 { {"goldmont"}, CK_Goldmont, FEATURE_SSE4_2, FeaturesGoldmont }, 345 { {"goldmont-plus"}, CK_GoldmontPlus, FEATURE_SSE4_2, FeaturesGoldmontPlus }, 346 { {"tremont"}, CK_Tremont, FEATURE_SSE4_2, FeaturesTremont }, 347 // Nehalem microarchitecture based processors. 348 { {"nehalem"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem }, 349 { {"corei7"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem }, 350 // Westmere microarchitecture based processors. 351 { {"westmere"}, CK_Westmere, FEATURE_PCLMUL, FeaturesWestmere }, 352 // Sandy Bridge microarchitecture based processors. 353 { {"sandybridge"}, CK_SandyBridge, FEATURE_AVX, FeaturesSandyBridge }, 354 { {"corei7-avx"}, CK_SandyBridge, FEATURE_AVX, FeaturesSandyBridge }, 355 // Ivy Bridge microarchitecture based processors. 356 { {"ivybridge"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge }, 357 { {"core-avx-i"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge }, 358 // Haswell microarchitecture based processors. 359 { {"haswell"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell }, 360 { {"core-avx2"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell }, 361 // Broadwell microarchitecture based processors. 362 { {"broadwell"}, CK_Broadwell, FEATURE_AVX2, FeaturesBroadwell }, 363 // Skylake client microarchitecture based processors. 364 { {"skylake"}, CK_SkylakeClient, FEATURE_AVX2, FeaturesSkylakeClient }, 365 // Skylake server microarchitecture based processors. 366 { {"skylake-avx512"}, CK_SkylakeServer, FEATURE_AVX512F, FeaturesSkylakeServer }, 367 { {"skx"}, CK_SkylakeServer, FEATURE_AVX512F, FeaturesSkylakeServer }, 368 // Cascadelake Server microarchitecture based processors. 369 { {"cascadelake"}, CK_Cascadelake, FEATURE_AVX512VNNI, FeaturesCascadeLake }, 370 // Cooperlake Server microarchitecture based processors. 371 { {"cooperlake"}, CK_Cooperlake, FEATURE_AVX512BF16, FeaturesCooperLake }, 372 // Cannonlake client microarchitecture based processors. 373 { {"cannonlake"}, CK_Cannonlake, FEATURE_AVX512VBMI, FeaturesCannonlake }, 374 // Icelake client microarchitecture based processors. 375 { {"icelake-client"}, CK_IcelakeClient, FEATURE_AVX512VBMI2, FeaturesICLClient }, 376 // Rocketlake microarchitecture based processors. 377 { {"rocketlake"}, CK_Rocketlake, FEATURE_AVX512VBMI2, FeaturesRocketlake }, 378 // Icelake server microarchitecture based processors. 379 { {"icelake-server"}, CK_IcelakeServer, FEATURE_AVX512VBMI2, FeaturesICLServer }, 380 // Tigerlake microarchitecture based processors. 381 { {"tigerlake"}, CK_Tigerlake, FEATURE_AVX512VP2INTERSECT, FeaturesTigerlake }, 382 // Sapphire Rapids microarchitecture based processors. 383 { {"sapphirerapids"}, CK_SapphireRapids, FEATURE_AVX512BF16, FeaturesSapphireRapids }, 384 // Alderlake microarchitecture based processors. 385 { {"alderlake"}, CK_Alderlake, FEATURE_AVX2, FeaturesAlderlake }, 386 // Raptorlake microarchitecture based processors. 387 { {"raptorlake"}, CK_Raptorlake, FEATURE_AVX2, FeaturesAlderlake }, 388 // Meteorlake microarchitecture based processors. 389 { {"meteorlake"}, CK_Meteorlake, FEATURE_AVX2, FeaturesAlderlake }, 390 // Sierraforest microarchitecture based processors. 391 { {"sierraforest"}, CK_Sierraforest, FEATURE_AVX2, FeaturesSierraforest }, 392 // Grandridge microarchitecture based processors. 393 { {"grandridge"}, CK_Grandridge, FEATURE_AVX2, FeaturesGrandridge }, 394 // Granite Rapids microarchitecture based processors. 395 { {"graniterapids"}, CK_Graniterapids, FEATURE_AVX512BF16, FeaturesGraniteRapids }, 396 // Emerald Rapids microarchitecture based processors. 397 { {"emeraldrapids"}, CK_Emeraldrapids, FEATURE_AVX512BF16, FeaturesSapphireRapids }, 398 // Knights Landing processor. 399 { {"knl"}, CK_KNL, FEATURE_AVX512F, FeaturesKNL }, 400 // Knights Mill processor. 401 { {"knm"}, CK_KNM, FEATURE_AVX5124FMAPS, FeaturesKNM }, 402 // Lakemont microarchitecture based processors. 403 { {"lakemont"}, CK_Lakemont, ~0U, FeatureCMPXCHG8B }, 404 // K6 architecture processors. 405 { {"k6"}, CK_K6, ~0U, FeaturesK6 }, 406 { {"k6-2"}, CK_K6_2, ~0U, FeaturesK6 | Feature3DNOW }, 407 { {"k6-3"}, CK_K6_3, ~0U, FeaturesK6 | Feature3DNOW }, 408 // K7 architecture processors. 409 { {"athlon"}, CK_Athlon, ~0U, FeaturesAthlon }, 410 { {"athlon-tbird"}, CK_Athlon, ~0U, FeaturesAthlon }, 411 { {"athlon-xp"}, CK_AthlonXP, ~0U, FeaturesAthlonXP }, 412 { {"athlon-mp"}, CK_AthlonXP, ~0U, FeaturesAthlonXP }, 413 { {"athlon-4"}, CK_AthlonXP, ~0U, FeaturesAthlonXP }, 414 // K8 architecture processors. 415 { {"k8"}, CK_K8, ~0U, FeaturesK8 }, 416 { {"athlon64"}, CK_K8, ~0U, FeaturesK8 }, 417 { {"athlon-fx"}, CK_K8, ~0U, FeaturesK8 }, 418 { {"opteron"}, CK_K8, ~0U, FeaturesK8 }, 419 { {"k8-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3 }, 420 { {"athlon64-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3 }, 421 { {"opteron-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3 }, 422 { {"amdfam10"}, CK_AMDFAM10, FEATURE_SSE4_A, FeaturesAMDFAM10 }, 423 { {"barcelona"}, CK_AMDFAM10, FEATURE_SSE4_A, FeaturesAMDFAM10 }, 424 // Bobcat architecture processors. 425 { {"btver1"}, CK_BTVER1, FEATURE_SSE4_A, FeaturesBTVER1 }, 426 { {"btver2"}, CK_BTVER2, FEATURE_BMI, FeaturesBTVER2 }, 427 // Bulldozer architecture processors. 428 { {"bdver1"}, CK_BDVER1, FEATURE_XOP, FeaturesBDVER1 }, 429 { {"bdver2"}, CK_BDVER2, FEATURE_FMA, FeaturesBDVER2 }, 430 { {"bdver3"}, CK_BDVER3, FEATURE_FMA, FeaturesBDVER3 }, 431 { {"bdver4"}, CK_BDVER4, FEATURE_AVX2, FeaturesBDVER4 }, 432 // Zen architecture processors. 433 { {"znver1"}, CK_ZNVER1, FEATURE_AVX2, FeaturesZNVER1 }, 434 { {"znver2"}, CK_ZNVER2, FEATURE_AVX2, FeaturesZNVER2 }, 435 { {"znver3"}, CK_ZNVER3, FEATURE_AVX2, FeaturesZNVER3 }, 436 { {"znver4"}, CK_ZNVER4, FEATURE_AVX512VBMI2, FeaturesZNVER4 }, 437 // Generic 64-bit processor. 438 { {"x86-64"}, CK_x86_64, ~0U, FeaturesX86_64 }, 439 { {"x86-64-v2"}, CK_x86_64_v2, ~0U, FeaturesX86_64_V2 }, 440 { {"x86-64-v3"}, CK_x86_64_v3, ~0U, FeaturesX86_64_V3 }, 441 { {"x86-64-v4"}, CK_x86_64_v4, ~0U, FeaturesX86_64_V4 }, 442 // Geode processors. 443 { {"geode"}, CK_Geode, ~0U, FeaturesGeode }, 444 }; 445 446 constexpr const char *NoTuneList[] = {"x86-64-v2", "x86-64-v3", "x86-64-v4"}; 447 448 X86::CPUKind llvm::X86::parseArchX86(StringRef CPU, bool Only64Bit) { 449 for (const auto &P : Processors) 450 if (P.Name == CPU && (P.Features[FEATURE_64BIT] || !Only64Bit)) 451 return P.Kind; 452 453 return CK_None; 454 } 455 456 X86::CPUKind llvm::X86::parseTuneCPU(StringRef CPU, bool Only64Bit) { 457 if (llvm::is_contained(NoTuneList, CPU)) 458 return CK_None; 459 return parseArchX86(CPU, Only64Bit); 460 } 461 462 void llvm::X86::fillValidCPUArchList(SmallVectorImpl<StringRef> &Values, 463 bool Only64Bit) { 464 for (const auto &P : Processors) 465 if (!P.Name.empty() && (P.Features[FEATURE_64BIT] || !Only64Bit)) 466 Values.emplace_back(P.Name); 467 } 468 469 void llvm::X86::fillValidTuneCPUList(SmallVectorImpl<StringRef> &Values, 470 bool Only64Bit) { 471 for (const ProcInfo &P : Processors) 472 if (!P.Name.empty() && (P.Features[FEATURE_64BIT] || !Only64Bit) && 473 !llvm::is_contained(NoTuneList, P.Name)) 474 Values.emplace_back(P.Name); 475 } 476 477 ProcessorFeatures llvm::X86::getKeyFeature(X86::CPUKind Kind) { 478 // FIXME: Can we avoid a linear search here? The table might be sorted by 479 // CPUKind so we could binary search? 480 for (const auto &P : Processors) { 481 if (P.Kind == Kind) { 482 assert(P.KeyFeature != ~0U && "Processor does not have a key feature."); 483 return static_cast<ProcessorFeatures>(P.KeyFeature); 484 } 485 } 486 487 llvm_unreachable("Unable to find CPU kind!"); 488 } 489 490 // Features with no dependencies. 491 constexpr FeatureBitset ImpliedFeatures64BIT = {}; 492 constexpr FeatureBitset ImpliedFeaturesADX = {}; 493 constexpr FeatureBitset ImpliedFeaturesBMI = {}; 494 constexpr FeatureBitset ImpliedFeaturesBMI2 = {}; 495 constexpr FeatureBitset ImpliedFeaturesCLDEMOTE = {}; 496 constexpr FeatureBitset ImpliedFeaturesCLFLUSHOPT = {}; 497 constexpr FeatureBitset ImpliedFeaturesCLWB = {}; 498 constexpr FeatureBitset ImpliedFeaturesCLZERO = {}; 499 constexpr FeatureBitset ImpliedFeaturesCMOV = {}; 500 constexpr FeatureBitset ImpliedFeaturesCMPXCHG16B = {}; 501 constexpr FeatureBitset ImpliedFeaturesCMPXCHG8B = {}; 502 constexpr FeatureBitset ImpliedFeaturesCRC32 = {}; 503 constexpr FeatureBitset ImpliedFeaturesENQCMD = {}; 504 constexpr FeatureBitset ImpliedFeaturesFSGSBASE = {}; 505 constexpr FeatureBitset ImpliedFeaturesFXSR = {}; 506 constexpr FeatureBitset ImpliedFeaturesINVPCID = {}; 507 constexpr FeatureBitset ImpliedFeaturesLWP = {}; 508 constexpr FeatureBitset ImpliedFeaturesLZCNT = {}; 509 constexpr FeatureBitset ImpliedFeaturesMWAITX = {}; 510 constexpr FeatureBitset ImpliedFeaturesMOVBE = {}; 511 constexpr FeatureBitset ImpliedFeaturesMOVDIR64B = {}; 512 constexpr FeatureBitset ImpliedFeaturesMOVDIRI = {}; 513 constexpr FeatureBitset ImpliedFeaturesPCONFIG = {}; 514 constexpr FeatureBitset ImpliedFeaturesPOPCNT = {}; 515 constexpr FeatureBitset ImpliedFeaturesPKU = {}; 516 constexpr FeatureBitset ImpliedFeaturesPREFETCHWT1 = {}; 517 constexpr FeatureBitset ImpliedFeaturesPRFCHW = {}; 518 constexpr FeatureBitset ImpliedFeaturesPTWRITE = {}; 519 constexpr FeatureBitset ImpliedFeaturesRDPID = {}; 520 constexpr FeatureBitset ImpliedFeaturesRDPRU = {}; 521 constexpr FeatureBitset ImpliedFeaturesRDRND = {}; 522 constexpr FeatureBitset ImpliedFeaturesRDSEED = {}; 523 constexpr FeatureBitset ImpliedFeaturesRTM = {}; 524 constexpr FeatureBitset ImpliedFeaturesSAHF = {}; 525 constexpr FeatureBitset ImpliedFeaturesSERIALIZE = {}; 526 constexpr FeatureBitset ImpliedFeaturesSGX = {}; 527 constexpr FeatureBitset ImpliedFeaturesSHSTK = {}; 528 constexpr FeatureBitset ImpliedFeaturesTBM = {}; 529 constexpr FeatureBitset ImpliedFeaturesTSXLDTRK = {}; 530 constexpr FeatureBitset ImpliedFeaturesUINTR = {}; 531 constexpr FeatureBitset ImpliedFeaturesWAITPKG = {}; 532 constexpr FeatureBitset ImpliedFeaturesWBNOINVD = {}; 533 constexpr FeatureBitset ImpliedFeaturesVZEROUPPER = {}; 534 constexpr FeatureBitset ImpliedFeaturesX87 = {}; 535 constexpr FeatureBitset ImpliedFeaturesXSAVE = {}; 536 537 // Not really CPU features, but need to be in the table because clang uses 538 // target features to communicate them to the backend. 539 constexpr FeatureBitset ImpliedFeaturesRETPOLINE_EXTERNAL_THUNK = {}; 540 constexpr FeatureBitset ImpliedFeaturesRETPOLINE_INDIRECT_BRANCHES = {}; 541 constexpr FeatureBitset ImpliedFeaturesRETPOLINE_INDIRECT_CALLS = {}; 542 constexpr FeatureBitset ImpliedFeaturesLVI_CFI = {}; 543 constexpr FeatureBitset ImpliedFeaturesLVI_LOAD_HARDENING = {}; 544 545 // XSAVE features are dependent on basic XSAVE. 546 constexpr FeatureBitset ImpliedFeaturesXSAVEC = FeatureXSAVE; 547 constexpr FeatureBitset ImpliedFeaturesXSAVEOPT = FeatureXSAVE; 548 constexpr FeatureBitset ImpliedFeaturesXSAVES = FeatureXSAVE; 549 550 // MMX->3DNOW->3DNOWA chain. 551 constexpr FeatureBitset ImpliedFeaturesMMX = {}; 552 constexpr FeatureBitset ImpliedFeatures3DNOW = FeatureMMX; 553 constexpr FeatureBitset ImpliedFeatures3DNOWA = Feature3DNOW; 554 555 // SSE/AVX/AVX512F chain. 556 constexpr FeatureBitset ImpliedFeaturesSSE = {}; 557 constexpr FeatureBitset ImpliedFeaturesSSE2 = FeatureSSE; 558 constexpr FeatureBitset ImpliedFeaturesSSE3 = FeatureSSE2; 559 constexpr FeatureBitset ImpliedFeaturesSSSE3 = FeatureSSE3; 560 constexpr FeatureBitset ImpliedFeaturesSSE4_1 = FeatureSSSE3; 561 constexpr FeatureBitset ImpliedFeaturesSSE4_2 = FeatureSSE4_1; 562 constexpr FeatureBitset ImpliedFeaturesAVX = FeatureSSE4_2; 563 constexpr FeatureBitset ImpliedFeaturesAVX2 = FeatureAVX; 564 constexpr FeatureBitset ImpliedFeaturesAVX512F = 565 FeatureAVX2 | FeatureF16C | FeatureFMA; 566 567 // Vector extensions that build on SSE or AVX. 568 constexpr FeatureBitset ImpliedFeaturesAES = FeatureSSE2; 569 constexpr FeatureBitset ImpliedFeaturesF16C = FeatureAVX; 570 constexpr FeatureBitset ImpliedFeaturesFMA = FeatureAVX; 571 constexpr FeatureBitset ImpliedFeaturesGFNI = FeatureSSE2; 572 constexpr FeatureBitset ImpliedFeaturesPCLMUL = FeatureSSE2; 573 constexpr FeatureBitset ImpliedFeaturesSHA = FeatureSSE2; 574 constexpr FeatureBitset ImpliedFeaturesVAES = FeatureAES | FeatureAVX; 575 constexpr FeatureBitset ImpliedFeaturesVPCLMULQDQ = FeatureAVX | FeaturePCLMUL; 576 577 // AVX512 features. 578 constexpr FeatureBitset ImpliedFeaturesAVX512CD = FeatureAVX512F; 579 constexpr FeatureBitset ImpliedFeaturesAVX512BW = FeatureAVX512F; 580 constexpr FeatureBitset ImpliedFeaturesAVX512DQ = FeatureAVX512F; 581 constexpr FeatureBitset ImpliedFeaturesAVX512ER = FeatureAVX512F; 582 constexpr FeatureBitset ImpliedFeaturesAVX512PF = FeatureAVX512F; 583 constexpr FeatureBitset ImpliedFeaturesAVX512VL = FeatureAVX512F; 584 585 constexpr FeatureBitset ImpliedFeaturesAVX512BF16 = FeatureAVX512BW; 586 constexpr FeatureBitset ImpliedFeaturesAVX512BITALG = FeatureAVX512BW; 587 constexpr FeatureBitset ImpliedFeaturesAVX512IFMA = FeatureAVX512F; 588 constexpr FeatureBitset ImpliedFeaturesAVX512VNNI = FeatureAVX512F; 589 constexpr FeatureBitset ImpliedFeaturesAVX512VPOPCNTDQ = FeatureAVX512F; 590 constexpr FeatureBitset ImpliedFeaturesAVX512VBMI = FeatureAVX512BW; 591 constexpr FeatureBitset ImpliedFeaturesAVX512VBMI2 = FeatureAVX512BW; 592 constexpr FeatureBitset ImpliedFeaturesAVX512VP2INTERSECT = FeatureAVX512F; 593 594 // FIXME: These two aren't really implemented and just exist in the feature 595 // list for __builtin_cpu_supports. So omit their dependencies. 596 constexpr FeatureBitset ImpliedFeaturesAVX5124FMAPS = {}; 597 constexpr FeatureBitset ImpliedFeaturesAVX5124VNNIW = {}; 598 599 // SSE4_A->FMA4->XOP chain. 600 constexpr FeatureBitset ImpliedFeaturesSSE4_A = FeatureSSE3; 601 constexpr FeatureBitset ImpliedFeaturesFMA4 = FeatureAVX | FeatureSSE4_A; 602 constexpr FeatureBitset ImpliedFeaturesXOP = FeatureFMA4; 603 604 // AMX Features 605 constexpr FeatureBitset ImpliedFeaturesAMX_TILE = {}; 606 constexpr FeatureBitset ImpliedFeaturesAMX_BF16 = FeatureAMX_TILE; 607 constexpr FeatureBitset ImpliedFeaturesAMX_FP16 = FeatureAMX_TILE; 608 constexpr FeatureBitset ImpliedFeaturesAMX_INT8 = FeatureAMX_TILE; 609 constexpr FeatureBitset ImpliedFeaturesHRESET = {}; 610 611 constexpr FeatureBitset ImpliedFeaturesPREFETCHI = {}; 612 constexpr FeatureBitset ImpliedFeaturesCMPCCXADD = {}; 613 constexpr FeatureBitset ImpliedFeaturesRAOINT = {}; 614 constexpr FeatureBitset ImpliedFeaturesAVXVNNIINT8 = FeatureAVX2; 615 constexpr FeatureBitset ImpliedFeaturesAVXIFMA = FeatureAVX2; 616 constexpr FeatureBitset ImpliedFeaturesAVXNECONVERT = FeatureAVX2; 617 constexpr FeatureBitset ImpliedFeaturesAVX512FP16 = 618 FeatureAVX512BW | FeatureAVX512DQ | FeatureAVX512VL; 619 // Key Locker Features 620 constexpr FeatureBitset ImpliedFeaturesKL = FeatureSSE2; 621 constexpr FeatureBitset ImpliedFeaturesWIDEKL = FeatureKL; 622 623 // AVXVNNI Features 624 constexpr FeatureBitset ImpliedFeaturesAVXVNNI = FeatureAVX2; 625 626 constexpr FeatureInfo FeatureInfos[X86::CPU_FEATURE_MAX] = { 627 #define X86_FEATURE(ENUM, STR) {{STR}, ImpliedFeatures##ENUM}, 628 #include "llvm/TargetParser/X86TargetParser.def" 629 }; 630 631 void llvm::X86::getFeaturesForCPU(StringRef CPU, 632 SmallVectorImpl<StringRef> &EnabledFeatures) { 633 auto I = llvm::find_if(Processors, 634 [&](const ProcInfo &P) { return P.Name == CPU; }); 635 assert(I != std::end(Processors) && "Processor not found!"); 636 637 FeatureBitset Bits = I->Features; 638 639 // Remove the 64-bit feature which we only use to validate if a CPU can 640 // be used with 64-bit mode. 641 Bits &= ~Feature64BIT; 642 643 // Add the string version of all set bits. 644 for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i) 645 if (Bits[i] && !FeatureInfos[i].Name.empty()) 646 EnabledFeatures.push_back(FeatureInfos[i].Name); 647 } 648 649 // For each feature that is (transitively) implied by this feature, set it. 650 static void getImpliedEnabledFeatures(FeatureBitset &Bits, 651 const FeatureBitset &Implies) { 652 // Fast path: Implies is often empty. 653 if (!Implies.any()) 654 return; 655 FeatureBitset Prev; 656 Bits |= Implies; 657 do { 658 Prev = Bits; 659 for (unsigned i = CPU_FEATURE_MAX; i;) 660 if (Bits[--i]) 661 Bits |= FeatureInfos[i].ImpliedFeatures; 662 } while (Prev != Bits); 663 } 664 665 /// Create bit vector of features that are implied disabled if the feature 666 /// passed in Value is disabled. 667 static void getImpliedDisabledFeatures(FeatureBitset &Bits, unsigned Value) { 668 // Check all features looking for any dependent on this feature. If we find 669 // one, mark it and recursively find any feature that depend on it. 670 FeatureBitset Prev; 671 Bits.set(Value); 672 do { 673 Prev = Bits; 674 for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i) 675 if ((FeatureInfos[i].ImpliedFeatures & Bits).any()) 676 Bits.set(i); 677 } while (Prev != Bits); 678 } 679 680 void llvm::X86::updateImpliedFeatures( 681 StringRef Feature, bool Enabled, 682 StringMap<bool> &Features) { 683 auto I = llvm::find_if( 684 FeatureInfos, [&](const FeatureInfo &FI) { return FI.Name == Feature; }); 685 if (I == std::end(FeatureInfos)) { 686 // FIXME: This shouldn't happen, but may not have all features in the table 687 // yet. 688 return; 689 } 690 691 FeatureBitset ImpliedBits; 692 if (Enabled) 693 getImpliedEnabledFeatures(ImpliedBits, I->ImpliedFeatures); 694 else 695 getImpliedDisabledFeatures(ImpliedBits, 696 std::distance(std::begin(FeatureInfos), I)); 697 698 // Update the map entry for all implied features. 699 for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i) 700 if (ImpliedBits[i] && !FeatureInfos[i].Name.empty()) 701 Features[FeatureInfos[i].Name] = Enabled; 702 } 703 704 uint64_t llvm::X86::getCpuSupportsMask(ArrayRef<StringRef> FeatureStrs) { 705 // Processor features and mapping to processor feature value. 706 uint64_t FeaturesMask = 0; 707 for (const StringRef &FeatureStr : FeatureStrs) { 708 unsigned Feature = StringSwitch<unsigned>(FeatureStr) 709 #define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) \ 710 .Case(STR, llvm::X86::FEATURE_##ENUM) 711 #include "llvm/TargetParser/X86TargetParser.def" 712 ; 713 FeaturesMask |= (1ULL << Feature); 714 } 715 return FeaturesMask; 716 } 717 718 unsigned llvm::X86::getFeaturePriority(ProcessorFeatures Feat) { 719 #ifndef NDEBUG 720 // Check that priorities are set properly in the .def file. We expect that 721 // "compat" features are assigned non-duplicate consecutive priorities 722 // starting from zero (0, 1, ..., num_features - 1). 723 #define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) PRIORITY, 724 unsigned Priorities[] = { 725 #include "llvm/TargetParser/X86TargetParser.def" 726 std::numeric_limits<unsigned>::max() // Need to consume last comma. 727 }; 728 std::array<unsigned, std::size(Priorities) - 1> HelperList; 729 std::iota(HelperList.begin(), HelperList.end(), 0); 730 assert(std::is_permutation(HelperList.begin(), HelperList.end(), 731 std::begin(Priorities), 732 std::prev(std::end(Priorities))) && 733 "Priorities don't form consecutive range!"); 734 #endif 735 736 switch (Feat) { 737 #define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) \ 738 case X86::FEATURE_##ENUM: \ 739 return PRIORITY; 740 #include "llvm/TargetParser/X86TargetParser.def" 741 default: 742 llvm_unreachable("No Feature Priority for non-CPUSupports Features"); 743 } 744 } 745