1 //===-- X86TargetParser - Parser for X86 features ---------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements a target parser to recognise X86 hardware features. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "llvm/TargetParser/X86TargetParser.h" 14 #include "llvm/ADT/Bitset.h" 15 #include "llvm/ADT/StringSwitch.h" 16 #include <numeric> 17 18 using namespace llvm; 19 using namespace llvm::X86; 20 21 namespace { 22 23 using FeatureBitset = Bitset<X86::CPU_FEATURE_MAX>; 24 25 struct ProcInfo { 26 StringLiteral Name; 27 X86::CPUKind Kind; 28 unsigned KeyFeature; 29 FeatureBitset Features; 30 char Mangling; 31 bool OnlyForCPUDispatchSpecific; 32 }; 33 34 struct FeatureInfo { 35 StringLiteral NameWithPlus; 36 FeatureBitset ImpliedFeatures; 37 38 StringRef getName(bool WithPlus = false) const { 39 assert(NameWithPlus[0] == '+' && "Expected string to start with '+'"); 40 if (WithPlus) 41 return NameWithPlus; 42 return NameWithPlus.drop_front(); 43 } 44 }; 45 46 } // end anonymous namespace 47 48 #define X86_FEATURE(ENUM, STRING) \ 49 constexpr FeatureBitset Feature##ENUM = {X86::FEATURE_##ENUM}; 50 #include "llvm/TargetParser/X86TargetParser.def" 51 52 // Pentium with MMX. 53 constexpr FeatureBitset FeaturesPentiumMMX = 54 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX; 55 56 // Pentium 2 and 3. 57 constexpr FeatureBitset FeaturesPentium2 = 58 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | FeatureFXSR | FeatureCMOV; 59 constexpr FeatureBitset FeaturesPentium3 = FeaturesPentium2 | FeatureSSE; 60 61 // Pentium 4 CPUs 62 constexpr FeatureBitset FeaturesPentium4 = FeaturesPentium3 | FeatureSSE2; 63 constexpr FeatureBitset FeaturesPrescott = FeaturesPentium4 | FeatureSSE3; 64 constexpr FeatureBitset FeaturesNocona = 65 FeaturesPrescott | Feature64BIT | FeatureCMPXCHG16B; 66 67 // Basic 64-bit capable CPU. 68 constexpr FeatureBitset FeaturesX86_64 = FeaturesPentium4 | Feature64BIT; 69 constexpr FeatureBitset FeaturesX86_64_V2 = FeaturesX86_64 | FeatureSAHF | 70 FeaturePOPCNT | FeatureCRC32 | 71 FeatureSSE4_2 | FeatureCMPXCHG16B; 72 constexpr FeatureBitset FeaturesX86_64_V3 = 73 FeaturesX86_64_V2 | FeatureAVX2 | FeatureBMI | FeatureBMI2 | FeatureF16C | 74 FeatureFMA | FeatureLZCNT | FeatureMOVBE | FeatureXSAVE; 75 constexpr FeatureBitset FeaturesX86_64_V4 = FeaturesX86_64_V3 | FeatureEVEX512 | 76 FeatureAVX512BW | FeatureAVX512CD | 77 FeatureAVX512DQ | FeatureAVX512VL; 78 79 // Intel Core CPUs 80 constexpr FeatureBitset FeaturesCore2 = 81 FeaturesNocona | FeatureSAHF | FeatureSSSE3; 82 constexpr FeatureBitset FeaturesPenryn = FeaturesCore2 | FeatureSSE4_1; 83 constexpr FeatureBitset FeaturesNehalem = 84 FeaturesPenryn | FeaturePOPCNT | FeatureCRC32 | FeatureSSE4_2; 85 constexpr FeatureBitset FeaturesWestmere = FeaturesNehalem | FeaturePCLMUL; 86 constexpr FeatureBitset FeaturesSandyBridge = 87 FeaturesWestmere | FeatureAVX | FeatureXSAVE | FeatureXSAVEOPT; 88 constexpr FeatureBitset FeaturesIvyBridge = 89 FeaturesSandyBridge | FeatureF16C | FeatureFSGSBASE | FeatureRDRND; 90 constexpr FeatureBitset FeaturesHaswell = 91 FeaturesIvyBridge | FeatureAVX2 | FeatureBMI | FeatureBMI2 | FeatureFMA | 92 FeatureINVPCID | FeatureLZCNT | FeatureMOVBE; 93 constexpr FeatureBitset FeaturesBroadwell = 94 FeaturesHaswell | FeatureADX | FeaturePRFCHW | FeatureRDSEED; 95 96 // Intel Knights Landing and Knights Mill 97 // Knights Landing has feature parity with Broadwell. 98 constexpr FeatureBitset FeaturesKNL = 99 FeaturesBroadwell | FeatureAES | FeatureAVX512F | FeatureEVEX512 | 100 FeatureAVX512CD | FeatureAVX512ER | FeatureAVX512PF | FeaturePREFETCHWT1; 101 constexpr FeatureBitset FeaturesKNM = FeaturesKNL | FeatureAVX512VPOPCNTDQ; 102 103 // Intel Skylake processors. 104 constexpr FeatureBitset FeaturesSkylakeClient = 105 FeaturesBroadwell | FeatureAES | FeatureCLFLUSHOPT | FeatureXSAVEC | 106 FeatureXSAVES | FeatureSGX; 107 // SkylakeServer inherits all SkylakeClient features except SGX. 108 // FIXME: That doesn't match gcc. 109 constexpr FeatureBitset FeaturesSkylakeServer = 110 (FeaturesSkylakeClient & ~FeatureSGX) | FeatureAVX512F | FeatureEVEX512 | 111 FeatureAVX512CD | FeatureAVX512DQ | FeatureAVX512BW | FeatureAVX512VL | 112 FeatureCLWB | FeaturePKU; 113 constexpr FeatureBitset FeaturesCascadeLake = 114 FeaturesSkylakeServer | FeatureAVX512VNNI; 115 constexpr FeatureBitset FeaturesCooperLake = 116 FeaturesCascadeLake | FeatureAVX512BF16; 117 118 // Intel 10nm processors. 119 constexpr FeatureBitset FeaturesCannonlake = 120 FeaturesSkylakeClient | FeatureAVX512F | FeatureEVEX512 | FeatureAVX512CD | 121 FeatureAVX512DQ | FeatureAVX512BW | FeatureAVX512VL | FeatureAVX512IFMA | 122 FeatureAVX512VBMI | FeaturePKU | FeatureSHA; 123 constexpr FeatureBitset FeaturesICLClient = 124 FeaturesCannonlake | FeatureAVX512BITALG | FeatureAVX512VBMI2 | 125 FeatureAVX512VNNI | FeatureAVX512VPOPCNTDQ | FeatureGFNI | FeatureRDPID | 126 FeatureVAES | FeatureVPCLMULQDQ; 127 constexpr FeatureBitset FeaturesRocketlake = FeaturesICLClient & ~FeatureSGX; 128 constexpr FeatureBitset FeaturesICLServer = 129 FeaturesICLClient | FeatureCLWB | FeaturePCONFIG | FeatureWBNOINVD; 130 constexpr FeatureBitset FeaturesTigerlake = 131 FeaturesICLClient | FeatureAVX512VP2INTERSECT | FeatureMOVDIR64B | 132 FeatureCLWB | FeatureMOVDIRI | FeatureSHSTK | FeatureKL | FeatureWIDEKL; 133 constexpr FeatureBitset FeaturesSapphireRapids = 134 FeaturesICLServer | FeatureAMX_BF16 | FeatureAMX_INT8 | FeatureAMX_TILE | 135 FeatureAVX512BF16 | FeatureAVX512FP16 | FeatureAVXVNNI | FeatureCLDEMOTE | 136 FeatureENQCMD | FeatureMOVDIR64B | FeatureMOVDIRI | FeaturePTWRITE | 137 FeatureSERIALIZE | FeatureSHSTK | FeatureTSXLDTRK | FeatureUINTR | 138 FeatureWAITPKG; 139 constexpr FeatureBitset FeaturesGraniteRapids = 140 FeaturesSapphireRapids | FeatureAMX_FP16 | FeaturePREFETCHI; 141 142 // Intel Atom processors. 143 // Bonnell has feature parity with Core2 and adds MOVBE. 144 constexpr FeatureBitset FeaturesBonnell = FeaturesCore2 | FeatureMOVBE; 145 // Silvermont has parity with Westmere and Bonnell plus PRFCHW and RDRND. 146 constexpr FeatureBitset FeaturesSilvermont = 147 FeaturesBonnell | FeaturesWestmere | FeaturePRFCHW | FeatureRDRND; 148 constexpr FeatureBitset FeaturesGoldmont = 149 FeaturesSilvermont | FeatureAES | FeatureCLFLUSHOPT | FeatureFSGSBASE | 150 FeatureRDSEED | FeatureSHA | FeatureXSAVE | FeatureXSAVEC | 151 FeatureXSAVEOPT | FeatureXSAVES; 152 constexpr FeatureBitset FeaturesGoldmontPlus = 153 FeaturesGoldmont | FeaturePTWRITE | FeatureRDPID | FeatureSGX; 154 constexpr FeatureBitset FeaturesTremont = 155 FeaturesGoldmontPlus | FeatureCLWB | FeatureGFNI; 156 constexpr FeatureBitset FeaturesAlderlake = 157 FeaturesTremont | FeatureADX | FeatureBMI | FeatureBMI2 | FeatureF16C | 158 FeatureFMA | FeatureINVPCID | FeatureLZCNT | FeaturePCONFIG | FeaturePKU | 159 FeatureSERIALIZE | FeatureSHSTK | FeatureVAES | FeatureVPCLMULQDQ | 160 FeatureCLDEMOTE | FeatureMOVDIR64B | FeatureMOVDIRI | FeatureWAITPKG | 161 FeatureAVXVNNI | FeatureHRESET | FeatureWIDEKL; 162 constexpr FeatureBitset FeaturesSierraforest = 163 FeaturesAlderlake | FeatureCMPCCXADD | FeatureAVXIFMA | FeatureUINTR | 164 FeatureENQCMD | FeatureAVXNECONVERT | FeatureAVXVNNIINT8; 165 constexpr FeatureBitset FeaturesArrowlakeS = FeaturesSierraforest | 166 FeatureAVXVNNIINT16 | FeatureSHA512 | FeatureSM3 | FeatureSM4; 167 constexpr FeatureBitset FeaturesPantherlake = 168 FeaturesArrowlakeS | FeaturePREFETCHI; 169 constexpr FeatureBitset FeaturesClearwaterforest = 170 FeaturesArrowlakeS | FeatureUSERMSR | FeaturePREFETCHI; 171 172 // Geode Processor. 173 constexpr FeatureBitset FeaturesGeode = 174 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | Feature3DNOW | Feature3DNOWA; 175 176 // K6 processor. 177 constexpr FeatureBitset FeaturesK6 = FeatureX87 | FeatureCMPXCHG8B | FeatureMMX; 178 179 // K7 and K8 architecture processors. 180 constexpr FeatureBitset FeaturesAthlon = 181 FeatureX87 | FeatureCMPXCHG8B | FeatureMMX | Feature3DNOW | Feature3DNOWA; 182 constexpr FeatureBitset FeaturesAthlonXP = 183 FeaturesAthlon | FeatureFXSR | FeatureSSE; 184 constexpr FeatureBitset FeaturesK8 = 185 FeaturesAthlonXP | FeatureSSE2 | Feature64BIT; 186 constexpr FeatureBitset FeaturesK8SSE3 = FeaturesK8 | FeatureSSE3; 187 constexpr FeatureBitset FeaturesAMDFAM10 = 188 FeaturesK8SSE3 | FeatureCMPXCHG16B | FeatureLZCNT | FeaturePOPCNT | 189 FeaturePRFCHW | FeatureSAHF | FeatureSSE4_A; 190 191 // Bobcat architecture processors. 192 constexpr FeatureBitset FeaturesBTVER1 = 193 FeatureX87 | FeatureCMPXCHG8B | FeatureCMPXCHG16B | Feature64BIT | 194 FeatureFXSR | FeatureLZCNT | FeatureMMX | FeaturePOPCNT | FeaturePRFCHW | 195 FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_A | 196 FeatureSAHF; 197 constexpr FeatureBitset FeaturesBTVER2 = 198 FeaturesBTVER1 | FeatureAES | FeatureAVX | FeatureBMI | FeatureCRC32 | 199 FeatureF16C | FeatureMOVBE | FeaturePCLMUL | FeatureXSAVE | FeatureXSAVEOPT; 200 201 // AMD Bulldozer architecture processors. 202 constexpr FeatureBitset FeaturesBDVER1 = 203 FeatureX87 | FeatureAES | FeatureAVX | FeatureCMPXCHG8B | 204 FeatureCMPXCHG16B | FeatureCRC32 | Feature64BIT | FeatureFMA4 | 205 FeatureFXSR | FeatureLWP | FeatureLZCNT | FeatureMMX | FeaturePCLMUL | 206 FeaturePOPCNT | FeaturePRFCHW | FeatureSAHF | FeatureSSE | FeatureSSE2 | 207 FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_1 | FeatureSSE4_2 | FeatureSSE4_A | 208 FeatureXOP | FeatureXSAVE; 209 constexpr FeatureBitset FeaturesBDVER2 = 210 FeaturesBDVER1 | FeatureBMI | FeatureFMA | FeatureF16C | FeatureTBM; 211 constexpr FeatureBitset FeaturesBDVER3 = 212 FeaturesBDVER2 | FeatureFSGSBASE | FeatureXSAVEOPT; 213 constexpr FeatureBitset FeaturesBDVER4 = FeaturesBDVER3 | FeatureAVX2 | 214 FeatureBMI2 | FeatureMOVBE | 215 FeatureMWAITX | FeatureRDRND; 216 217 // AMD Zen architecture processors. 218 constexpr FeatureBitset FeaturesZNVER1 = 219 FeatureX87 | FeatureADX | FeatureAES | FeatureAVX | FeatureAVX2 | 220 FeatureBMI | FeatureBMI2 | FeatureCLFLUSHOPT | FeatureCLZERO | 221 FeatureCMPXCHG8B | FeatureCMPXCHG16B | FeatureCRC32 | Feature64BIT | 222 FeatureF16C | FeatureFMA | FeatureFSGSBASE | FeatureFXSR | FeatureLZCNT | 223 FeatureMMX | FeatureMOVBE | FeatureMWAITX | FeaturePCLMUL | FeaturePOPCNT | 224 FeaturePRFCHW | FeatureRDRND | FeatureRDSEED | FeatureSAHF | FeatureSHA | 225 FeatureSSE | FeatureSSE2 | FeatureSSE3 | FeatureSSSE3 | FeatureSSE4_1 | 226 FeatureSSE4_2 | FeatureSSE4_A | FeatureXSAVE | FeatureXSAVEC | 227 FeatureXSAVEOPT | FeatureXSAVES; 228 constexpr FeatureBitset FeaturesZNVER2 = FeaturesZNVER1 | FeatureCLWB | 229 FeatureRDPID | FeatureRDPRU | 230 FeatureWBNOINVD; 231 static constexpr FeatureBitset FeaturesZNVER3 = FeaturesZNVER2 | 232 FeatureINVPCID | FeaturePKU | 233 FeatureVAES | FeatureVPCLMULQDQ; 234 static constexpr FeatureBitset FeaturesZNVER4 = 235 FeaturesZNVER3 | FeatureAVX512F | FeatureEVEX512 | FeatureAVX512CD | 236 FeatureAVX512DQ | FeatureAVX512BW | FeatureAVX512VL | FeatureAVX512IFMA | 237 FeatureAVX512VBMI | FeatureAVX512VBMI2 | FeatureAVX512VNNI | 238 FeatureAVX512BITALG | FeatureAVX512VPOPCNTDQ | FeatureAVX512BF16 | 239 FeatureGFNI | FeatureSHSTK; 240 241 // D151696 tranplanted Mangling and OnlyForCPUDispatchSpecific from 242 // X86TargetParser.def to here. They are assigned by following ways: 243 // 1. Copy the mangling from the original CPU_SPEICIFC MACROs. If no, assign 244 // to '\0' by default, which means not support cpu_specific/dispatch feature. 245 // 2. set OnlyForCPUDispatchSpecific as true if this cpu name was not 246 // listed here before, which means it doesn't support -march, -mtune and so on. 247 // FIXME: Remove OnlyForCPUDispatchSpecific after all CPUs here support both 248 // cpu_dispatch/specific() feature and -march, -mtune, and so on. 249 // clang-format off 250 constexpr ProcInfo Processors[] = { 251 // Empty processor. Include X87 and CMPXCHG8 for backwards compatibility. 252 { {""}, CK_None, ~0U, FeatureX87 | FeatureCMPXCHG8B, '\0', false }, 253 { {"generic"}, CK_None, ~0U, FeatureX87 | FeatureCMPXCHG8B | Feature64BIT, 'A', true }, 254 // i386-generation processors. 255 { {"i386"}, CK_i386, ~0U, FeatureX87, '\0', false }, 256 // i486-generation processors. 257 { {"i486"}, CK_i486, ~0U, FeatureX87, '\0', false }, 258 { {"winchip-c6"}, CK_WinChipC6, ~0U, FeaturesPentiumMMX, '\0', false }, 259 { {"winchip2"}, CK_WinChip2, ~0U, FeaturesPentiumMMX | Feature3DNOW, '\0', false }, 260 { {"c3"}, CK_C3, ~0U, FeaturesPentiumMMX | Feature3DNOW, '\0', false }, 261 // i586-generation processors, P5 microarchitecture based. 262 { {"i586"}, CK_i586, ~0U, FeatureX87 | FeatureCMPXCHG8B, '\0', false }, 263 { {"pentium"}, CK_Pentium, ~0U, FeatureX87 | FeatureCMPXCHG8B, 'B', false }, 264 { {"pentium-mmx"}, CK_PentiumMMX, ~0U, FeaturesPentiumMMX, '\0', false }, 265 { {"pentium_mmx"}, CK_PentiumMMX, ~0U, FeaturesPentiumMMX, 'D', true }, 266 // i686-generation processors, P6 / Pentium M microarchitecture based. 267 { {"pentiumpro"}, CK_PentiumPro, ~0U, FeatureCMOV | FeatureX87 | FeatureCMPXCHG8B, 'C', false }, 268 { {"pentium_pro"}, CK_PentiumPro, ~0U, FeatureCMOV | FeatureX87 | FeatureCMPXCHG8B, 'C', true }, 269 { {"i686"}, CK_i686, ~0U, FeatureCMOV | FeatureX87 | FeatureCMPXCHG8B, '\0', false }, 270 { {"pentium2"}, CK_Pentium2, ~0U, FeaturesPentium2, 'E', false }, 271 { {"pentium_ii"}, CK_Pentium2, ~0U, FeaturesPentium2, 'E', true }, 272 { {"pentium3"}, CK_Pentium3, ~0U, FeaturesPentium3, 'H', false }, 273 { {"pentium3m"}, CK_Pentium3, ~0U, FeaturesPentium3, 'H', false }, 274 { {"pentium_iii"}, CK_Pentium3, ~0U, FeaturesPentium3, 'H', true }, 275 { {"pentium_iii_no_xmm_regs"}, CK_Pentium3, ~0U, FeaturesPentium3, 'H', true }, 276 { {"pentium-m"}, CK_PentiumM, ~0U, FeaturesPentium4, '\0', false }, 277 { {"pentium_m"}, CK_PentiumM, ~0U, FeaturesPentium4, 'K', true }, 278 { {"c3-2"}, CK_C3_2, ~0U, FeaturesPentium3, '\0', false }, 279 { {"yonah"}, CK_Yonah, ~0U, FeaturesPrescott, 'L', false }, 280 // Netburst microarchitecture based processors. 281 { {"pentium4"}, CK_Pentium4, ~0U, FeaturesPentium4, 'J', false }, 282 { {"pentium4m"}, CK_Pentium4, ~0U, FeaturesPentium4, 'J', false }, 283 { {"pentium_4"}, CK_Pentium4, ~0U, FeaturesPentium4, 'J', true }, 284 { {"pentium_4_sse3"}, CK_Prescott, ~0U, FeaturesPrescott, 'L', true }, 285 { {"prescott"}, CK_Prescott, ~0U, FeaturesPrescott, 'L', false }, 286 { {"nocona"}, CK_Nocona, ~0U, FeaturesNocona, 'L', false }, 287 // Core microarchitecture based processors. 288 { {"core2"}, CK_Core2, FEATURE_SSSE3, FeaturesCore2, 'M', false }, 289 { {"core_2_duo_ssse3"}, CK_Core2, ~0U, FeaturesCore2, 'M', true }, 290 { {"penryn"}, CK_Penryn, ~0U, FeaturesPenryn, 'N', false }, 291 { {"core_2_duo_sse4_1"}, CK_Penryn, ~0U, FeaturesPenryn, 'N', true }, 292 // Atom processors 293 { {"bonnell"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell, 'O', false }, 294 { {"atom"}, CK_Bonnell, FEATURE_SSSE3, FeaturesBonnell, 'O', false }, 295 { {"silvermont"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont, 'c', false }, 296 { {"slm"}, CK_Silvermont, FEATURE_SSE4_2, FeaturesSilvermont, 'c', false }, 297 { {"atom_sse4_2"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem, 'c', true }, 298 { {"atom_sse4_2_movbe"}, CK_Goldmont, FEATURE_SSE4_2, FeaturesGoldmont, 'd', true }, 299 { {"goldmont"}, CK_Goldmont, FEATURE_SSE4_2, FeaturesGoldmont, 'i', false }, 300 { {"goldmont-plus"}, CK_GoldmontPlus, FEATURE_SSE4_2, FeaturesGoldmontPlus, '\0', false }, 301 { {"goldmont_plus"}, CK_GoldmontPlus, FEATURE_SSE4_2, FeaturesGoldmontPlus, 'd', true }, 302 { {"tremont"}, CK_Tremont, FEATURE_SSE4_2, FeaturesTremont, 'd', false }, 303 // Nehalem microarchitecture based processors. 304 { {"nehalem"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem, 'P', false }, 305 { {"core_i7_sse4_2"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem, 'P', true }, 306 { {"corei7"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem, 'P', false }, 307 // Westmere microarchitecture based processors. 308 { {"westmere"}, CK_Westmere, FEATURE_PCLMUL, FeaturesWestmere, 'Q', false }, 309 { {"core_aes_pclmulqdq"}, CK_Nehalem, FEATURE_SSE4_2, FeaturesNehalem, 'Q', true }, 310 // Sandy Bridge microarchitecture based processors. 311 { {"sandybridge"}, CK_SandyBridge, FEATURE_AVX, FeaturesSandyBridge, 'R', false }, 312 { {"core_2nd_gen_avx"}, CK_SandyBridge, FEATURE_AVX, FeaturesSandyBridge, 'R', true }, 313 { {"corei7-avx"}, CK_SandyBridge, FEATURE_AVX, FeaturesSandyBridge, '\0', false }, 314 // Ivy Bridge microarchitecture based processors. 315 { {"ivybridge"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge, 'S', false }, 316 { {"core_3rd_gen_avx"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge, 'S', true }, 317 { {"core-avx-i"}, CK_IvyBridge, FEATURE_AVX, FeaturesIvyBridge, '\0', false }, 318 // Haswell microarchitecture based processors. 319 { {"haswell"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell, 'V', false }, 320 { {"core-avx2"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell, '\0', false }, 321 { {"core_4th_gen_avx"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell, 'V', true }, 322 { {"core_4th_gen_avx_tsx"}, CK_Haswell, FEATURE_AVX2, FeaturesHaswell, 'W', true }, 323 // Broadwell microarchitecture based processors. 324 { {"broadwell"}, CK_Broadwell, FEATURE_AVX2, FeaturesBroadwell, 'X', false }, 325 { {"core_5th_gen_avx"}, CK_Broadwell, FEATURE_AVX2, FeaturesBroadwell, 'X', true }, 326 { {"core_5th_gen_avx_tsx"}, CK_Broadwell, FEATURE_AVX2, FeaturesBroadwell, 'Y', true }, 327 // Skylake client microarchitecture based processors. 328 { {"skylake"}, CK_SkylakeClient, FEATURE_AVX2, FeaturesSkylakeClient, 'b', false }, 329 // Skylake server microarchitecture based processors. 330 { {"skylake-avx512"}, CK_SkylakeServer, FEATURE_AVX512F, FeaturesSkylakeServer, '\0', false }, 331 { {"skx"}, CK_SkylakeServer, FEATURE_AVX512F, FeaturesSkylakeServer, 'a', false }, 332 { {"skylake_avx512"}, CK_SkylakeServer, FEATURE_AVX512F, FeaturesSkylakeServer, 'a', true }, 333 // Cascadelake Server microarchitecture based processors. 334 { {"cascadelake"}, CK_Cascadelake, FEATURE_AVX512VNNI, FeaturesCascadeLake, 'o', false }, 335 // Cooperlake Server microarchitecture based processors. 336 { {"cooperlake"}, CK_Cooperlake, FEATURE_AVX512BF16, FeaturesCooperLake, 'f', false }, 337 // Cannonlake client microarchitecture based processors. 338 { {"cannonlake"}, CK_Cannonlake, FEATURE_AVX512VBMI, FeaturesCannonlake, 'e', false }, 339 // Icelake client microarchitecture based processors. 340 { {"icelake-client"}, CK_IcelakeClient, FEATURE_AVX512VBMI2, FeaturesICLClient, '\0', false }, 341 { {"icelake_client"}, CK_IcelakeClient, FEATURE_AVX512VBMI2, FeaturesICLClient, 'k', true }, 342 // Rocketlake microarchitecture based processors. 343 { {"rocketlake"}, CK_Rocketlake, FEATURE_AVX512VBMI2, FeaturesRocketlake, 'k', false }, 344 // Icelake server microarchitecture based processors. 345 { {"icelake-server"}, CK_IcelakeServer, FEATURE_AVX512VBMI2, FeaturesICLServer, '\0', false }, 346 { {"icelake_server"}, CK_IcelakeServer, FEATURE_AVX512VBMI2, FeaturesICLServer, 'k', true }, 347 // Tigerlake microarchitecture based processors. 348 { {"tigerlake"}, CK_Tigerlake, FEATURE_AVX512VP2INTERSECT, FeaturesTigerlake, 'l', false }, 349 // Sapphire Rapids microarchitecture based processors. 350 { {"sapphirerapids"}, CK_SapphireRapids, FEATURE_AVX512FP16, FeaturesSapphireRapids, 'n', false }, 351 // Alderlake microarchitecture based processors. 352 { {"alderlake"}, CK_Alderlake, FEATURE_AVX2, FeaturesAlderlake, 'p', false }, 353 // Raptorlake microarchitecture based processors. 354 { {"raptorlake"}, CK_Raptorlake, FEATURE_AVX2, FeaturesAlderlake, 'p', false }, 355 // Meteorlake microarchitecture based processors. 356 { {"meteorlake"}, CK_Meteorlake, FEATURE_AVX2, FeaturesAlderlake, 'p', false }, 357 // Arrowlake microarchitecture based processors. 358 { {"arrowlake"}, CK_Arrowlake, FEATURE_AVX2, FeaturesSierraforest, 'p', false }, 359 { {"arrowlake-s"}, CK_ArrowlakeS, FEATURE_AVX2, FeaturesArrowlakeS, '\0', false }, 360 { {"arrowlake_s"}, CK_ArrowlakeS, FEATURE_AVX2, FeaturesArrowlakeS, 'p', true }, 361 // Lunarlake microarchitecture based processors. 362 { {"lunarlake"}, CK_Lunarlake, FEATURE_AVX2, FeaturesArrowlakeS, 'p', false }, 363 // Gracemont microarchitecture based processors. 364 { {"gracemont"}, CK_Gracemont, FEATURE_AVX2, FeaturesAlderlake, 'p', false }, 365 // Pantherlake microarchitecture based processors. 366 { {"pantherlake"}, CK_Lunarlake, FEATURE_AVX2, FeaturesPantherlake, 'p', false }, 367 // Sierraforest microarchitecture based processors. 368 { {"sierraforest"}, CK_Sierraforest, FEATURE_AVX2, FeaturesSierraforest, 'p', false }, 369 // Grandridge microarchitecture based processors. 370 { {"grandridge"}, CK_Grandridge, FEATURE_AVX2, FeaturesSierraforest, 'p', false }, 371 // Granite Rapids microarchitecture based processors. 372 { {"graniterapids"}, CK_Graniterapids, FEATURE_AVX512FP16, FeaturesGraniteRapids, 'n', false }, 373 // Granite Rapids D microarchitecture based processors. 374 { {"graniterapids-d"}, CK_GraniterapidsD, FEATURE_AVX512FP16, FeaturesGraniteRapids | FeatureAMX_COMPLEX, '\0', false }, 375 { {"graniterapids_d"}, CK_GraniterapidsD, FEATURE_AVX512FP16, FeaturesGraniteRapids | FeatureAMX_COMPLEX, 'n', true }, 376 // Emerald Rapids microarchitecture based processors. 377 { {"emeraldrapids"}, CK_Emeraldrapids, FEATURE_AVX512FP16, FeaturesSapphireRapids, 'n', false }, 378 // Clearwaterforest microarchitecture based processors. 379 { {"clearwaterforest"}, CK_Lunarlake, FEATURE_AVX2, FeaturesClearwaterforest, 'p', false }, 380 // Knights Landing processor. 381 { {"knl"}, CK_KNL, FEATURE_AVX512F, FeaturesKNL, 'Z', false }, 382 { {"mic_avx512"}, CK_KNL, FEATURE_AVX512F, FeaturesKNL, 'Z', true }, 383 // Knights Mill processor. 384 { {"knm"}, CK_KNM, FEATURE_AVX5124FMAPS, FeaturesKNM, 'j', false }, 385 // Lakemont microarchitecture based processors. 386 { {"lakemont"}, CK_Lakemont, ~0U, FeatureCMPXCHG8B, '\0', false }, 387 // K6 architecture processors. 388 { {"k6"}, CK_K6, ~0U, FeaturesK6, '\0', false }, 389 { {"k6-2"}, CK_K6_2, ~0U, FeaturesK6 | Feature3DNOW, '\0', false }, 390 { {"k6-3"}, CK_K6_3, ~0U, FeaturesK6 | Feature3DNOW, '\0', false }, 391 // K7 architecture processors. 392 { {"athlon"}, CK_Athlon, ~0U, FeaturesAthlon, '\0', false }, 393 { {"athlon-tbird"}, CK_Athlon, ~0U, FeaturesAthlon, '\0', false }, 394 { {"athlon-xp"}, CK_AthlonXP, ~0U, FeaturesAthlonXP, '\0', false }, 395 { {"athlon-mp"}, CK_AthlonXP, ~0U, FeaturesAthlonXP, '\0', false }, 396 { {"athlon-4"}, CK_AthlonXP, ~0U, FeaturesAthlonXP, '\0', false }, 397 // K8 architecture processors. 398 { {"k8"}, CK_K8, ~0U, FeaturesK8, '\0', false }, 399 { {"athlon64"}, CK_K8, ~0U, FeaturesK8, '\0', false }, 400 { {"athlon-fx"}, CK_K8, ~0U, FeaturesK8, '\0', false }, 401 { {"opteron"}, CK_K8, ~0U, FeaturesK8, '\0', false }, 402 { {"k8-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3, '\0', false }, 403 { {"athlon64-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3, '\0', false }, 404 { {"opteron-sse3"}, CK_K8SSE3, ~0U, FeaturesK8SSE3, '\0', false }, 405 { {"amdfam10"}, CK_AMDFAM10, FEATURE_SSE4_A, FeaturesAMDFAM10, '\0', false }, 406 { {"barcelona"}, CK_AMDFAM10, FEATURE_SSE4_A, FeaturesAMDFAM10, '\0', false }, 407 // Bobcat architecture processors. 408 { {"btver1"}, CK_BTVER1, FEATURE_SSE4_A, FeaturesBTVER1, '\0', false }, 409 { {"btver2"}, CK_BTVER2, FEATURE_BMI, FeaturesBTVER2, '\0', false }, 410 // Bulldozer architecture processors. 411 { {"bdver1"}, CK_BDVER1, FEATURE_XOP, FeaturesBDVER1, '\0', false }, 412 { {"bdver2"}, CK_BDVER2, FEATURE_FMA, FeaturesBDVER2, '\0', false }, 413 { {"bdver3"}, CK_BDVER3, FEATURE_FMA, FeaturesBDVER3, '\0', false }, 414 { {"bdver4"}, CK_BDVER4, FEATURE_AVX2, FeaturesBDVER4, '\0', false }, 415 // Zen architecture processors. 416 { {"znver1"}, CK_ZNVER1, FEATURE_AVX2, FeaturesZNVER1, '\0', false }, 417 { {"znver2"}, CK_ZNVER2, FEATURE_AVX2, FeaturesZNVER2, '\0', false }, 418 { {"znver3"}, CK_ZNVER3, FEATURE_AVX2, FeaturesZNVER3, '\0', false }, 419 { {"znver4"}, CK_ZNVER4, FEATURE_AVX512VBMI2, FeaturesZNVER4, '\0', false }, 420 // Generic 64-bit processor. 421 { {"x86-64"}, CK_x86_64, FEATURE_SSE2 , FeaturesX86_64, '\0', false }, 422 { {"x86-64-v2"}, CK_x86_64_v2, FEATURE_SSE4_2 , FeaturesX86_64_V2, '\0', false }, 423 { {"x86-64-v3"}, CK_x86_64_v3, FEATURE_AVX2, FeaturesX86_64_V3, '\0', false }, 424 { {"x86-64-v4"}, CK_x86_64_v4, FEATURE_AVX512VL, FeaturesX86_64_V4, '\0', false }, 425 // Geode processors. 426 { {"geode"}, CK_Geode, ~0U, FeaturesGeode, '\0', false }, 427 }; 428 // clang-format on 429 430 constexpr const char *NoTuneList[] = {"x86-64-v2", "x86-64-v3", "x86-64-v4"}; 431 432 X86::CPUKind llvm::X86::parseArchX86(StringRef CPU, bool Only64Bit) { 433 for (const auto &P : Processors) 434 if (!P.OnlyForCPUDispatchSpecific && P.Name == CPU && 435 (P.Features[FEATURE_64BIT] || !Only64Bit)) 436 return P.Kind; 437 438 return CK_None; 439 } 440 441 X86::CPUKind llvm::X86::parseTuneCPU(StringRef CPU, bool Only64Bit) { 442 if (llvm::is_contained(NoTuneList, CPU)) 443 return CK_None; 444 return parseArchX86(CPU, Only64Bit); 445 } 446 447 void llvm::X86::fillValidCPUArchList(SmallVectorImpl<StringRef> &Values, 448 bool Only64Bit) { 449 for (const auto &P : Processors) 450 if (!P.OnlyForCPUDispatchSpecific && !P.Name.empty() && 451 (P.Features[FEATURE_64BIT] || !Only64Bit)) 452 Values.emplace_back(P.Name); 453 } 454 455 void llvm::X86::fillValidTuneCPUList(SmallVectorImpl<StringRef> &Values, 456 bool Only64Bit) { 457 for (const ProcInfo &P : Processors) 458 if (!P.OnlyForCPUDispatchSpecific && !P.Name.empty() && 459 (P.Features[FEATURE_64BIT] || !Only64Bit) && 460 !llvm::is_contained(NoTuneList, P.Name)) 461 Values.emplace_back(P.Name); 462 } 463 464 ProcessorFeatures llvm::X86::getKeyFeature(X86::CPUKind Kind) { 465 // FIXME: Can we avoid a linear search here? The table might be sorted by 466 // CPUKind so we could binary search? 467 for (const auto &P : Processors) { 468 if (P.Kind == Kind) { 469 assert(P.KeyFeature != ~0U && "Processor does not have a key feature."); 470 return static_cast<ProcessorFeatures>(P.KeyFeature); 471 } 472 } 473 474 llvm_unreachable("Unable to find CPU kind!"); 475 } 476 477 // Features with no dependencies. 478 constexpr FeatureBitset ImpliedFeatures64BIT = {}; 479 constexpr FeatureBitset ImpliedFeaturesADX = {}; 480 constexpr FeatureBitset ImpliedFeaturesBMI = {}; 481 constexpr FeatureBitset ImpliedFeaturesBMI2 = {}; 482 constexpr FeatureBitset ImpliedFeaturesCLDEMOTE = {}; 483 constexpr FeatureBitset ImpliedFeaturesCLFLUSHOPT = {}; 484 constexpr FeatureBitset ImpliedFeaturesCLWB = {}; 485 constexpr FeatureBitset ImpliedFeaturesCLZERO = {}; 486 constexpr FeatureBitset ImpliedFeaturesCMOV = {}; 487 constexpr FeatureBitset ImpliedFeaturesCMPXCHG16B = {}; 488 constexpr FeatureBitset ImpliedFeaturesCMPXCHG8B = {}; 489 constexpr FeatureBitset ImpliedFeaturesCRC32 = {}; 490 constexpr FeatureBitset ImpliedFeaturesENQCMD = {}; 491 constexpr FeatureBitset ImpliedFeaturesFSGSBASE = {}; 492 constexpr FeatureBitset ImpliedFeaturesFXSR = {}; 493 constexpr FeatureBitset ImpliedFeaturesINVPCID = {}; 494 constexpr FeatureBitset ImpliedFeaturesLWP = {}; 495 constexpr FeatureBitset ImpliedFeaturesLZCNT = {}; 496 constexpr FeatureBitset ImpliedFeaturesMWAITX = {}; 497 constexpr FeatureBitset ImpliedFeaturesMOVBE = {}; 498 constexpr FeatureBitset ImpliedFeaturesMOVDIR64B = {}; 499 constexpr FeatureBitset ImpliedFeaturesMOVDIRI = {}; 500 constexpr FeatureBitset ImpliedFeaturesPCONFIG = {}; 501 constexpr FeatureBitset ImpliedFeaturesPOPCNT = {}; 502 constexpr FeatureBitset ImpliedFeaturesPKU = {}; 503 constexpr FeatureBitset ImpliedFeaturesPREFETCHWT1 = {}; 504 constexpr FeatureBitset ImpliedFeaturesPRFCHW = {}; 505 constexpr FeatureBitset ImpliedFeaturesPTWRITE = {}; 506 constexpr FeatureBitset ImpliedFeaturesRDPID = {}; 507 constexpr FeatureBitset ImpliedFeaturesRDPRU = {}; 508 constexpr FeatureBitset ImpliedFeaturesRDRND = {}; 509 constexpr FeatureBitset ImpliedFeaturesRDSEED = {}; 510 constexpr FeatureBitset ImpliedFeaturesRTM = {}; 511 constexpr FeatureBitset ImpliedFeaturesSAHF = {}; 512 constexpr FeatureBitset ImpliedFeaturesSERIALIZE = {}; 513 constexpr FeatureBitset ImpliedFeaturesSGX = {}; 514 constexpr FeatureBitset ImpliedFeaturesSHSTK = {}; 515 constexpr FeatureBitset ImpliedFeaturesTBM = {}; 516 constexpr FeatureBitset ImpliedFeaturesTSXLDTRK = {}; 517 constexpr FeatureBitset ImpliedFeaturesUINTR = {}; 518 constexpr FeatureBitset ImpliedFeaturesUSERMSR = {}; 519 constexpr FeatureBitset ImpliedFeaturesWAITPKG = {}; 520 constexpr FeatureBitset ImpliedFeaturesWBNOINVD = {}; 521 constexpr FeatureBitset ImpliedFeaturesVZEROUPPER = {}; 522 constexpr FeatureBitset ImpliedFeaturesX87 = {}; 523 constexpr FeatureBitset ImpliedFeaturesXSAVE = {}; 524 525 // Not really CPU features, but need to be in the table because clang uses 526 // target features to communicate them to the backend. 527 constexpr FeatureBitset ImpliedFeaturesRETPOLINE_EXTERNAL_THUNK = {}; 528 constexpr FeatureBitset ImpliedFeaturesRETPOLINE_INDIRECT_BRANCHES = {}; 529 constexpr FeatureBitset ImpliedFeaturesRETPOLINE_INDIRECT_CALLS = {}; 530 constexpr FeatureBitset ImpliedFeaturesLVI_CFI = {}; 531 constexpr FeatureBitset ImpliedFeaturesLVI_LOAD_HARDENING = {}; 532 533 // XSAVE features are dependent on basic XSAVE. 534 constexpr FeatureBitset ImpliedFeaturesXSAVEC = FeatureXSAVE; 535 constexpr FeatureBitset ImpliedFeaturesXSAVEOPT = FeatureXSAVE; 536 constexpr FeatureBitset ImpliedFeaturesXSAVES = FeatureXSAVE; 537 538 // MMX->3DNOW->3DNOWA chain. 539 constexpr FeatureBitset ImpliedFeaturesMMX = {}; 540 constexpr FeatureBitset ImpliedFeatures3DNOW = FeatureMMX; 541 constexpr FeatureBitset ImpliedFeatures3DNOWA = Feature3DNOW; 542 543 // SSE/AVX/AVX512F chain. 544 constexpr FeatureBitset ImpliedFeaturesSSE = {}; 545 constexpr FeatureBitset ImpliedFeaturesSSE2 = FeatureSSE; 546 constexpr FeatureBitset ImpliedFeaturesSSE3 = FeatureSSE2; 547 constexpr FeatureBitset ImpliedFeaturesSSSE3 = FeatureSSE3; 548 constexpr FeatureBitset ImpliedFeaturesSSE4_1 = FeatureSSSE3; 549 constexpr FeatureBitset ImpliedFeaturesSSE4_2 = FeatureSSE4_1; 550 constexpr FeatureBitset ImpliedFeaturesAVX = FeatureSSE4_2; 551 constexpr FeatureBitset ImpliedFeaturesAVX2 = FeatureAVX; 552 constexpr FeatureBitset ImpliedFeaturesEVEX512 = {}; 553 constexpr FeatureBitset ImpliedFeaturesAVX512F = 554 FeatureAVX2 | FeatureF16C | FeatureFMA; 555 556 // Vector extensions that build on SSE or AVX. 557 constexpr FeatureBitset ImpliedFeaturesAES = FeatureSSE2; 558 constexpr FeatureBitset ImpliedFeaturesF16C = FeatureAVX; 559 constexpr FeatureBitset ImpliedFeaturesFMA = FeatureAVX; 560 constexpr FeatureBitset ImpliedFeaturesGFNI = FeatureSSE2; 561 constexpr FeatureBitset ImpliedFeaturesPCLMUL = FeatureSSE2; 562 constexpr FeatureBitset ImpliedFeaturesSHA = FeatureSSE2; 563 constexpr FeatureBitset ImpliedFeaturesVAES = FeatureAES | FeatureAVX2; 564 constexpr FeatureBitset ImpliedFeaturesVPCLMULQDQ = FeatureAVX | FeaturePCLMUL; 565 constexpr FeatureBitset ImpliedFeaturesSM3 = FeatureAVX; 566 constexpr FeatureBitset ImpliedFeaturesSM4 = FeatureAVX2; 567 568 // AVX512 features. 569 constexpr FeatureBitset ImpliedFeaturesAVX512CD = FeatureAVX512F; 570 constexpr FeatureBitset ImpliedFeaturesAVX512BW = FeatureAVX512F; 571 constexpr FeatureBitset ImpliedFeaturesAVX512DQ = FeatureAVX512F; 572 constexpr FeatureBitset ImpliedFeaturesAVX512ER = FeatureAVX512F; 573 constexpr FeatureBitset ImpliedFeaturesAVX512PF = FeatureAVX512F; 574 constexpr FeatureBitset ImpliedFeaturesAVX512VL = FeatureAVX512F; 575 576 constexpr FeatureBitset ImpliedFeaturesAVX512BF16 = FeatureAVX512BW; 577 constexpr FeatureBitset ImpliedFeaturesAVX512BITALG = FeatureAVX512BW; 578 constexpr FeatureBitset ImpliedFeaturesAVX512IFMA = FeatureAVX512F; 579 constexpr FeatureBitset ImpliedFeaturesAVX512VNNI = FeatureAVX512F; 580 constexpr FeatureBitset ImpliedFeaturesAVX512VPOPCNTDQ = FeatureAVX512F; 581 constexpr FeatureBitset ImpliedFeaturesAVX512VBMI = FeatureAVX512BW; 582 constexpr FeatureBitset ImpliedFeaturesAVX512VBMI2 = FeatureAVX512BW; 583 constexpr FeatureBitset ImpliedFeaturesAVX512VP2INTERSECT = FeatureAVX512F; 584 585 // FIXME: These two aren't really implemented and just exist in the feature 586 // list for __builtin_cpu_supports. So omit their dependencies. 587 constexpr FeatureBitset ImpliedFeaturesAVX5124FMAPS = {}; 588 constexpr FeatureBitset ImpliedFeaturesAVX5124VNNIW = {}; 589 590 // SSE4_A->FMA4->XOP chain. 591 constexpr FeatureBitset ImpliedFeaturesSSE4_A = FeatureSSE3; 592 constexpr FeatureBitset ImpliedFeaturesFMA4 = FeatureAVX | FeatureSSE4_A; 593 constexpr FeatureBitset ImpliedFeaturesXOP = FeatureFMA4; 594 595 // AMX Features 596 constexpr FeatureBitset ImpliedFeaturesAMX_TILE = {}; 597 constexpr FeatureBitset ImpliedFeaturesAMX_BF16 = FeatureAMX_TILE; 598 constexpr FeatureBitset ImpliedFeaturesAMX_FP16 = FeatureAMX_TILE; 599 constexpr FeatureBitset ImpliedFeaturesAMX_INT8 = FeatureAMX_TILE; 600 constexpr FeatureBitset ImpliedFeaturesAMX_COMPLEX = FeatureAMX_TILE; 601 constexpr FeatureBitset ImpliedFeaturesHRESET = {}; 602 603 constexpr FeatureBitset ImpliedFeaturesPREFETCHI = {}; 604 constexpr FeatureBitset ImpliedFeaturesCMPCCXADD = {}; 605 constexpr FeatureBitset ImpliedFeaturesRAOINT = {}; 606 constexpr FeatureBitset ImpliedFeaturesAVXVNNIINT16 = FeatureAVX2; 607 constexpr FeatureBitset ImpliedFeaturesAVXVNNIINT8 = FeatureAVX2; 608 constexpr FeatureBitset ImpliedFeaturesAVXIFMA = FeatureAVX2; 609 constexpr FeatureBitset ImpliedFeaturesAVXNECONVERT = FeatureAVX2; 610 constexpr FeatureBitset ImpliedFeaturesSHA512 = FeatureAVX2; 611 constexpr FeatureBitset ImpliedFeaturesAVX512FP16 = 612 FeatureAVX512BW | FeatureAVX512DQ | FeatureAVX512VL; 613 // Key Locker Features 614 constexpr FeatureBitset ImpliedFeaturesKL = FeatureSSE2; 615 constexpr FeatureBitset ImpliedFeaturesWIDEKL = FeatureKL; 616 617 // AVXVNNI Features 618 constexpr FeatureBitset ImpliedFeaturesAVXVNNI = FeatureAVX2; 619 620 // AVX10 Features 621 constexpr FeatureBitset ImpliedFeaturesAVX10_1 = 622 FeatureAVX512CD | FeatureAVX512VBMI | FeatureAVX512IFMA | 623 FeatureAVX512VNNI | FeatureAVX512BF16 | FeatureAVX512VPOPCNTDQ | 624 FeatureAVX512VBMI2 | FeatureAVX512BITALG | FeatureVAES | FeatureVPCLMULQDQ | 625 FeatureAVX512FP16; 626 constexpr FeatureBitset ImpliedFeaturesAVX10_1_512 = 627 FeatureAVX10_1 | FeatureEVEX512; 628 629 // APX Features 630 constexpr FeatureBitset ImpliedFeaturesEGPR = {}; 631 constexpr FeatureBitset ImpliedFeaturesPush2Pop2 = {}; 632 constexpr FeatureBitset ImpliedFeaturesPPX = {}; 633 constexpr FeatureBitset ImpliedFeaturesNDD = {}; 634 constexpr FeatureBitset ImpliedFeaturesCCMP = {}; 635 constexpr FeatureBitset ImpliedFeaturesCF = {}; 636 637 constexpr FeatureInfo FeatureInfos[X86::CPU_FEATURE_MAX] = { 638 #define X86_FEATURE(ENUM, STR) {{"+" STR}, ImpliedFeatures##ENUM}, 639 #include "llvm/TargetParser/X86TargetParser.def" 640 }; 641 642 void llvm::X86::getFeaturesForCPU(StringRef CPU, 643 SmallVectorImpl<StringRef> &EnabledFeatures, 644 bool NeedPlus) { 645 auto I = llvm::find_if(Processors, 646 [&](const ProcInfo &P) { return P.Name == CPU; }); 647 assert(I != std::end(Processors) && "Processor not found!"); 648 649 FeatureBitset Bits = I->Features; 650 651 // Remove the 64-bit feature which we only use to validate if a CPU can 652 // be used with 64-bit mode. 653 Bits &= ~Feature64BIT; 654 655 // Add the string version of all set bits. 656 for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i) 657 if (Bits[i] && !FeatureInfos[i].getName(NeedPlus).empty()) 658 EnabledFeatures.push_back(FeatureInfos[i].getName(NeedPlus)); 659 } 660 661 // For each feature that is (transitively) implied by this feature, set it. 662 static void getImpliedEnabledFeatures(FeatureBitset &Bits, 663 const FeatureBitset &Implies) { 664 // Fast path: Implies is often empty. 665 if (!Implies.any()) 666 return; 667 FeatureBitset Prev; 668 Bits |= Implies; 669 do { 670 Prev = Bits; 671 for (unsigned i = CPU_FEATURE_MAX; i;) 672 if (Bits[--i]) 673 Bits |= FeatureInfos[i].ImpliedFeatures; 674 } while (Prev != Bits); 675 } 676 677 /// Create bit vector of features that are implied disabled if the feature 678 /// passed in Value is disabled. 679 static void getImpliedDisabledFeatures(FeatureBitset &Bits, unsigned Value) { 680 // Check all features looking for any dependent on this feature. If we find 681 // one, mark it and recursively find any feature that depend on it. 682 FeatureBitset Prev; 683 Bits.set(Value); 684 do { 685 Prev = Bits; 686 for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i) 687 if ((FeatureInfos[i].ImpliedFeatures & Bits).any()) 688 Bits.set(i); 689 } while (Prev != Bits); 690 } 691 692 void llvm::X86::updateImpliedFeatures( 693 StringRef Feature, bool Enabled, 694 StringMap<bool> &Features) { 695 auto I = llvm::find_if(FeatureInfos, [&](const FeatureInfo &FI) { 696 return FI.getName() == Feature; 697 }); 698 if (I == std::end(FeatureInfos)) { 699 // FIXME: This shouldn't happen, but may not have all features in the table 700 // yet. 701 return; 702 } 703 704 FeatureBitset ImpliedBits; 705 if (Enabled) 706 getImpliedEnabledFeatures(ImpliedBits, I->ImpliedFeatures); 707 else 708 getImpliedDisabledFeatures(ImpliedBits, 709 std::distance(std::begin(FeatureInfos), I)); 710 711 // Update the map entry for all implied features. 712 for (unsigned i = 0; i != CPU_FEATURE_MAX; ++i) 713 if (ImpliedBits[i] && !FeatureInfos[i].getName().empty()) 714 Features[FeatureInfos[i].getName()] = Enabled; 715 } 716 717 char llvm::X86::getCPUDispatchMangling(StringRef CPU) { 718 auto I = llvm::find_if(Processors, 719 [&](const ProcInfo &P) { return P.Name == CPU; }); 720 assert(I != std::end(Processors) && "Processor not found!"); 721 assert(I->Mangling != '\0' && "Processor dooesn't support function multiversion!"); 722 return I->Mangling; 723 } 724 725 bool llvm::X86::validateCPUSpecificCPUDispatch(StringRef Name) { 726 auto I = llvm::find_if(Processors, 727 [&](const ProcInfo &P) { return P.Name == Name; }); 728 return I != std::end(Processors); 729 } 730 731 std::array<uint32_t, 4> 732 llvm::X86::getCpuSupportsMask(ArrayRef<StringRef> FeatureStrs) { 733 // Processor features and mapping to processor feature value. 734 std::array<uint32_t, 4> FeatureMask{}; 735 for (StringRef FeatureStr : FeatureStrs) { 736 unsigned Feature = StringSwitch<unsigned>(FeatureStr) 737 #define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) \ 738 .Case(STR, llvm::X86::FEATURE_##ENUM) 739 #define X86_MICROARCH_LEVEL(ENUM, STR, PRIORITY) \ 740 .Case(STR, llvm::X86::FEATURE_##ENUM) 741 #include "llvm/TargetParser/X86TargetParser.def" 742 ; 743 assert(Feature / 32 < FeatureMask.size()); 744 FeatureMask[Feature / 32] |= 1U << (Feature % 32); 745 } 746 return FeatureMask; 747 } 748 749 unsigned llvm::X86::getFeaturePriority(ProcessorFeatures Feat) { 750 #ifndef NDEBUG 751 // Check that priorities are set properly in the .def file. We expect that 752 // "compat" features are assigned non-duplicate consecutive priorities 753 // starting from zero (0, 1, ..., num_features - 1). 754 #define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) PRIORITY, 755 unsigned Priorities[] = { 756 #include "llvm/TargetParser/X86TargetParser.def" 757 }; 758 std::array<unsigned, std::size(Priorities)> HelperList; 759 std::iota(HelperList.begin(), HelperList.end(), 0); 760 assert(std::is_permutation(HelperList.begin(), HelperList.end(), 761 std::begin(Priorities), std::end(Priorities)) && 762 "Priorities don't form consecutive range!"); 763 #endif 764 765 switch (Feat) { 766 #define X86_FEATURE_COMPAT(ENUM, STR, PRIORITY) \ 767 case X86::FEATURE_##ENUM: \ 768 return PRIORITY; 769 #include "llvm/TargetParser/X86TargetParser.def" 770 default: 771 llvm_unreachable("No Feature Priority for non-CPUSupports Features"); 772 } 773 } 774