1//===- XtensaRegisterInfo.td - Xtensa Register defs --------*- tablegen -*-===// 2// 3// The LLVM Compiler Infrastructure 4// 5// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 6// See https://llvm.org/LICENSE.txt for license information. 7// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 8// 9//===----------------------------------------------------------------------===// 10 11//===----------------------------------------------------------------------===// 12// Class definitions. 13//===----------------------------------------------------------------------===// 14 15class XtensaReg<string n> : Register<n> { 16 let Namespace = "Xtensa"; 17} 18 19class XtensaRegWithSubRegs<string n, list<Register> subregs> 20 : RegisterWithSubRegs<n, subregs> { 21 let Namespace = "Xtensa"; 22} 23 24//===----------------------------------------------------------------------===// 25// General-purpose registers 26//===----------------------------------------------------------------------===// 27 28// Xtensa general purpose regs 29class ARReg<bits<4> num, string n, list<string> alt = []> : XtensaReg<n> { 30 let HWEncoding{3-0} = num; 31 let AltNames = alt; 32} 33 34// Return Address 35def A0 : ARReg<0, "a0">, DwarfRegNum<[0]>; 36 37// Stack Pointer (callee-saved) 38def SP : ARReg<1, "a1", ["sp"]>, DwarfRegNum<[1]>; 39 40// Function Arguments 41def A2 : ARReg<2, "a2">, DwarfRegNum<[2]>; 42def A3 : ARReg<3, "a3">, DwarfRegNum<[3]>; 43def A4 : ARReg<4, "a4">, DwarfRegNum<[4]>; 44def A5 : ARReg<5, "a5">, DwarfRegNum<[5]>; 45def A6 : ARReg<6, "a6">, DwarfRegNum<[6]>; 46def A7 : ARReg<7, "a7">, DwarfRegNum<[7]>; 47 48// Static Chain 49def A8 : ARReg<8, "a8">, DwarfRegNum<[8]>; 50 51def A9 : ARReg<9, "a9">, DwarfRegNum<[9]>; 52def A10 : ARReg<10, "a10">, DwarfRegNum<[10]>; 53def A11 : ARReg<11, "a11">, DwarfRegNum<[11]>; 54 55// Callee-saved 56def A12 : ARReg<12, "a12">, DwarfRegNum<[12]>; 57def A13 : ARReg<13, "a13">, DwarfRegNum<[13]>; 58def A14 : ARReg<14, "a14">, DwarfRegNum<[14]>; 59 60// Stack-Frame Pointer (optional) - Callee-Saved 61def A15 : ARReg<15, "a15">, DwarfRegNum<[15]>; 62 63// Register class with allocation order 64def AR : RegisterClass<"Xtensa", [i32], 32, (add 65 A8, A9, A10, A11, A12, A13, A14, A15, 66 A7, A6, A5, A4, A3, A2, A0, SP)>; 67//===----------------------------------------------------------------------===// 68// Special-purpose registers 69//===----------------------------------------------------------------------===// 70class SRReg<bits<8> num, string n, list<string> alt = []> : XtensaReg<n> { 71 let HWEncoding{7-0} = num; 72 let AltNames = alt; 73} 74 75// Shift Amount Register 76def SAR : SRReg<3, "sar", ["SAR","3"]>; 77 78def SR : RegisterClass<"Xtensa", [i32], 32, (add SAR)>; 79