1 //===-- XtensaInstrInfo.h - Xtensa Instruction Information ------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 6 // See https://llvm.org/LICENSE.txt for license information. 7 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 8 // 9 //===----------------------------------------------------------------------===// 10 // 11 // This file contains the Xtensa implementation of the TargetInstrInfo class. 12 // 13 //===----------------------------------------------------------------------===// 14 15 #ifndef LLVM_LIB_TARGET_XTENSA_XTENSAINSTRINFO_H 16 #define LLVM_LIB_TARGET_XTENSA_XTENSAINSTRINFO_H 17 18 #include "Xtensa.h" 19 #include "XtensaRegisterInfo.h" 20 #include "llvm/CodeGen/TargetInstrInfo.h" 21 #include "llvm/CodeGen/TargetRegisterInfo.h" 22 23 #define GET_INSTRINFO_HEADER 24 25 #include "XtensaGenInstrInfo.inc" 26 27 namespace llvm { 28 29 class XtensaTargetMachine; 30 class XtensaSubtarget; 31 class XtensaInstrInfo : public XtensaGenInstrInfo { 32 const XtensaRegisterInfo RI; 33 const XtensaSubtarget &STI; 34 35 public: 36 XtensaInstrInfo(const XtensaSubtarget &STI); 37 38 void adjustStackPtr(unsigned SP, int64_t Amount, MachineBasicBlock &MBB, 39 MachineBasicBlock::iterator I) const; 40 41 // Return the XtensaRegisterInfo, which this class owns. 42 const XtensaRegisterInfo &getRegisterInfo() const { return RI; } 43 44 Register isLoadFromStackSlot(const MachineInstr &MI, 45 int &FrameIndex) const override; 46 47 Register isStoreToStackSlot(const MachineInstr &MI, 48 int &FrameIndex) const override; 49 50 void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, 51 const DebugLoc &DL, MCRegister DestReg, MCRegister SrcReg, 52 bool KillSrc) const override; 53 54 void storeRegToStackSlot(MachineBasicBlock &MBB, 55 MachineBasicBlock::iterator MBBI, Register SrcReg, 56 bool isKill, int FrameIndex, 57 const TargetRegisterClass *RC, 58 const TargetRegisterInfo *TRI, 59 Register VReg) const override; 60 61 void loadRegFromStackSlot(MachineBasicBlock &MBB, 62 MachineBasicBlock::iterator MBBI, Register DestReg, 63 int FrameIdx, const TargetRegisterClass *RC, 64 const TargetRegisterInfo *TRI, 65 Register VReg) const override; 66 67 // Get the load and store opcodes for a given register class and offset. 68 void getLoadStoreOpcodes(const TargetRegisterClass *RC, unsigned &LoadOpcode, 69 unsigned &StoreOpcode, int64_t offset) const; 70 71 // Emit code before MBBI in MI to move immediate value Value into 72 // physical register Reg. 73 void loadImmediate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, 74 unsigned *Reg, int64_t Value) const; 75 76 const XtensaSubtarget &getSubtarget() const { return STI; } 77 }; 78 } // end namespace llvm 79 80 #endif /* LLVM_LIB_TARGET_XTENSA_XTENSAINSTRINFO_H */ 81