1 //===-- X86TargetTransformInfo.h - X86 specific TTI -------------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 /// \file 9 /// This file a TargetTransformInfo::Concept conforming object specific to the 10 /// X86 target machine. It uses the target's detailed information to 11 /// provide more precise answers to certain TTI queries, while letting the 12 /// target independent and default TTI implementations handle the rest. 13 /// 14 //===----------------------------------------------------------------------===// 15 16 #ifndef LLVM_LIB_TARGET_X86_X86TARGETTRANSFORMINFO_H 17 #define LLVM_LIB_TARGET_X86_X86TARGETTRANSFORMINFO_H 18 19 #include "X86TargetMachine.h" 20 #include "llvm/Analysis/TargetTransformInfo.h" 21 #include "llvm/CodeGen/BasicTTIImpl.h" 22 23 namespace llvm { 24 25 class X86TTIImpl : public BasicTTIImplBase<X86TTIImpl> { 26 typedef BasicTTIImplBase<X86TTIImpl> BaseT; 27 typedef TargetTransformInfo TTI; 28 friend BaseT; 29 30 const X86Subtarget *ST; 31 const X86TargetLowering *TLI; 32 33 const X86Subtarget *getST() const { return ST; } 34 const X86TargetLowering *getTLI() const { return TLI; } 35 36 const FeatureBitset InlineFeatureIgnoreList = { 37 // This indicates the CPU is 64 bit capable not that we are in 64-bit 38 // mode. 39 X86::Feature64Bit, 40 41 // These features don't have any intrinsics or ABI effect. 42 X86::FeatureNOPL, 43 X86::FeatureCMPXCHG16B, 44 X86::FeatureLAHFSAHF, 45 46 // Codegen control options. 47 X86::FeatureFast11ByteNOP, 48 X86::FeatureFast15ByteNOP, 49 X86::FeatureFastBEXTR, 50 X86::FeatureFastHorizontalOps, 51 X86::FeatureFastLZCNT, 52 X86::FeatureFastScalarFSQRT, 53 X86::FeatureFastSHLDRotate, 54 X86::FeatureFastScalarShiftMasks, 55 X86::FeatureFastVectorShiftMasks, 56 X86::FeatureFastVariableShuffle, 57 X86::FeatureFastVectorFSQRT, 58 X86::FeatureLEAForSP, 59 X86::FeatureLEAUsesAG, 60 X86::FeatureLZCNTFalseDeps, 61 X86::FeatureBranchFusion, 62 X86::FeatureMacroFusion, 63 X86::FeatureMergeToThreeWayBranch, 64 X86::FeaturePadShortFunctions, 65 X86::FeaturePOPCNTFalseDeps, 66 X86::FeatureSSEUnalignedMem, 67 X86::FeatureSlow3OpsLEA, 68 X86::FeatureSlowDivide32, 69 X86::FeatureSlowDivide64, 70 X86::FeatureSlowIncDec, 71 X86::FeatureSlowLEA, 72 X86::FeatureSlowPMADDWD, 73 X86::FeatureSlowPMULLD, 74 X86::FeatureSlowSHLD, 75 X86::FeatureSlowTwoMemOps, 76 X86::FeatureSlowUAMem16, 77 X86::FeaturePreferMaskRegisters, 78 X86::FeatureInsertVZEROUPPER, 79 X86::FeatureUseGLMDivSqrtCosts, 80 81 // Perf-tuning flags. 82 X86::FeatureHasFastGather, 83 X86::FeatureSlowUAMem32, 84 85 // Based on whether user set the -mprefer-vector-width command line. 86 X86::FeaturePrefer128Bit, 87 X86::FeaturePrefer256Bit, 88 89 // CPU name enums. These just follow CPU string. 90 X86::ProcIntelAtom, 91 X86::ProcIntelSLM, 92 }; 93 94 public: 95 explicit X86TTIImpl(const X86TargetMachine *TM, const Function &F) 96 : BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)), 97 TLI(ST->getTargetLowering()) {} 98 99 /// \name Scalar TTI Implementations 100 /// @{ 101 TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth); 102 103 /// @} 104 105 /// \name Cache TTI Implementation 106 /// @{ 107 llvm::Optional<unsigned> getCacheSize( 108 TargetTransformInfo::CacheLevel Level) const override; 109 llvm::Optional<unsigned> getCacheAssociativity( 110 TargetTransformInfo::CacheLevel Level) const override; 111 /// @} 112 113 /// \name Vector TTI Implementations 114 /// @{ 115 116 unsigned getNumberOfRegisters(unsigned ClassID) const; 117 unsigned getRegisterBitWidth(bool Vector) const; 118 unsigned getLoadStoreVecRegBitWidth(unsigned AS) const; 119 unsigned getMaxInterleaveFactor(unsigned VF); 120 int getArithmeticInstrCost( 121 unsigned Opcode, Type *Ty, 122 TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput, 123 TTI::OperandValueKind Opd1Info = TTI::OK_AnyValue, 124 TTI::OperandValueKind Opd2Info = TTI::OK_AnyValue, 125 TTI::OperandValueProperties Opd1PropInfo = TTI::OP_None, 126 TTI::OperandValueProperties Opd2PropInfo = TTI::OP_None, 127 ArrayRef<const Value *> Args = ArrayRef<const Value *>(), 128 const Instruction *CxtI = nullptr); 129 int getShuffleCost(TTI::ShuffleKind Kind, VectorType *Tp, int Index, 130 VectorType *SubTp); 131 int getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src, 132 TTI::TargetCostKind CostKind, 133 const Instruction *I = nullptr); 134 int getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy, 135 TTI::TargetCostKind CostKind, 136 const Instruction *I = nullptr); 137 int getVectorInstrCost(unsigned Opcode, Type *Val, unsigned Index); 138 unsigned getScalarizationOverhead(VectorType *Ty, const APInt &DemandedElts, 139 bool Insert, bool Extract); 140 int getMemoryOpCost(unsigned Opcode, Type *Src, MaybeAlign Alignment, 141 unsigned AddressSpace, 142 TTI::TargetCostKind CostKind, 143 const Instruction *I = nullptr); 144 int getMaskedMemoryOpCost( 145 unsigned Opcode, Type *Src, Align Alignment, unsigned AddressSpace, 146 TTI::TargetCostKind CostKind = TTI::TCK_SizeAndLatency); 147 int getGatherScatterOpCost(unsigned Opcode, Type *DataTy, const Value *Ptr, 148 bool VariableMask, Align Alignment, 149 TTI::TargetCostKind CostKind, 150 const Instruction *I); 151 int getAddressComputationCost(Type *PtrTy, ScalarEvolution *SE, 152 const SCEV *Ptr); 153 154 unsigned getAtomicMemIntrinsicMaxElementSize() const; 155 156 int getTypeBasedIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, 157 TTI::TargetCostKind CostKind); 158 int getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA, 159 TTI::TargetCostKind CostKind); 160 161 int getArithmeticReductionCost(unsigned Opcode, VectorType *Ty, 162 bool IsPairwiseForm, 163 TTI::TargetCostKind CostKind = TTI::TCK_SizeAndLatency); 164 165 int getMinMaxCost(Type *Ty, Type *CondTy, bool IsUnsigned); 166 167 int getMinMaxReductionCost(VectorType *Ty, VectorType *CondTy, 168 bool IsPairwiseForm, bool IsUnsigned, 169 TTI::TargetCostKind CostKind); 170 171 int getInterleavedMemoryOpCost( 172 unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices, 173 Align Alignment, unsigned AddressSpace, 174 TTI::TargetCostKind CostKind = TTI::TCK_SizeAndLatency, 175 bool UseMaskForCond = false, bool UseMaskForGaps = false); 176 int getInterleavedMemoryOpCostAVX512( 177 unsigned Opcode, FixedVectorType *VecTy, unsigned Factor, 178 ArrayRef<unsigned> Indices, Align Alignment, unsigned AddressSpace, 179 TTI::TargetCostKind CostKind = TTI::TCK_SizeAndLatency, 180 bool UseMaskForCond = false, bool UseMaskForGaps = false); 181 int getInterleavedMemoryOpCostAVX2( 182 unsigned Opcode, FixedVectorType *VecTy, unsigned Factor, 183 ArrayRef<unsigned> Indices, Align Alignment, unsigned AddressSpace, 184 TTI::TargetCostKind CostKind = TTI::TCK_SizeAndLatency, 185 bool UseMaskForCond = false, bool UseMaskForGaps = false); 186 187 int getIntImmCost(int64_t); 188 189 int getIntImmCost(const APInt &Imm, Type *Ty, TTI::TargetCostKind CostKind); 190 191 unsigned getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind); 192 193 int getIntImmCostInst(unsigned Opcode, unsigned Idx, const APInt &Imm, Type *Ty, 194 TTI::TargetCostKind CostKind); 195 int getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx, const APInt &Imm, 196 Type *Ty, TTI::TargetCostKind CostKind); 197 bool isLSRCostLess(TargetTransformInfo::LSRCost &C1, 198 TargetTransformInfo::LSRCost &C2); 199 bool canMacroFuseCmp(); 200 bool isLegalMaskedLoad(Type *DataType, Align Alignment); 201 bool isLegalMaskedStore(Type *DataType, Align Alignment); 202 bool isLegalNTLoad(Type *DataType, Align Alignment); 203 bool isLegalNTStore(Type *DataType, Align Alignment); 204 bool isLegalMaskedGather(Type *DataType, Align Alignment); 205 bool isLegalMaskedScatter(Type *DataType, Align Alignment); 206 bool isLegalMaskedExpandLoad(Type *DataType); 207 bool isLegalMaskedCompressStore(Type *DataType); 208 bool hasDivRemOp(Type *DataType, bool IsSigned); 209 bool isFCmpOrdCheaperThanFCmpZero(Type *Ty); 210 bool areInlineCompatible(const Function *Caller, 211 const Function *Callee) const; 212 bool areFunctionArgsABICompatible(const Function *Caller, 213 const Function *Callee, 214 SmallPtrSetImpl<Argument *> &Args) const; 215 TTI::MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize, 216 bool IsZeroCmp) const; 217 bool enableInterleavedAccessVectorization(); 218 219 /// Allow vectorizers to form reduction intrinsics in IR. The IR is expanded 220 /// into shuffles and vector math/logic by the backend 221 /// (see TTI::shouldExpandReduction) 222 bool useReductionIntrinsic(unsigned Opcode, Type *Ty, 223 TTI::ReductionFlags Flags) const { 224 return true; 225 } 226 227 private: 228 int getGSScalarCost(unsigned Opcode, Type *DataTy, bool VariableMask, 229 Align Alignment, unsigned AddressSpace); 230 int getGSVectorCost(unsigned Opcode, Type *DataTy, const Value *Ptr, 231 Align Alignment, unsigned AddressSpace); 232 233 /// @} 234 }; 235 236 } // end namespace llvm 237 238 #endif 239