xref: /freebsd/contrib/llvm-project/llvm/lib/Target/X86/X86TargetTransformInfo.h (revision 401ab69cff8fa2320a9f8ea4baa114a6da6c952b)
1 //===-- X86TargetTransformInfo.h - X86 specific TTI -------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 /// \file
9 /// This file a TargetTransformInfo::Concept conforming object specific to the
10 /// X86 target machine. It uses the target's detailed information to
11 /// provide more precise answers to certain TTI queries, while letting the
12 /// target independent and default TTI implementations handle the rest.
13 ///
14 //===----------------------------------------------------------------------===//
15 
16 #ifndef LLVM_LIB_TARGET_X86_X86TARGETTRANSFORMINFO_H
17 #define LLVM_LIB_TARGET_X86_X86TARGETTRANSFORMINFO_H
18 
19 #include "X86TargetMachine.h"
20 #include "llvm/Analysis/TargetTransformInfo.h"
21 #include "llvm/CodeGen/BasicTTIImpl.h"
22 #include <optional>
23 
24 namespace llvm {
25 
26 class InstCombiner;
27 
28 class X86TTIImpl : public BasicTTIImplBase<X86TTIImpl> {
29   typedef BasicTTIImplBase<X86TTIImpl> BaseT;
30   typedef TargetTransformInfo TTI;
31   friend BaseT;
32 
33   const X86Subtarget *ST;
34   const X86TargetLowering *TLI;
35 
36   const X86Subtarget *getST() const { return ST; }
37   const X86TargetLowering *getTLI() const { return TLI; }
38 
39   const FeatureBitset InlineFeatureIgnoreList = {
40       // This indicates the CPU is 64 bit capable not that we are in 64-bit
41       // mode.
42       X86::FeatureX86_64,
43 
44       // These features don't have any intrinsics or ABI effect.
45       X86::FeatureNOPL,
46       X86::FeatureCX16,
47       X86::FeatureLAHFSAHF64,
48 
49       // Some older targets can be setup to fold unaligned loads.
50       X86::FeatureSSEUnalignedMem,
51 
52       // Codegen control options.
53       X86::TuningFast11ByteNOP,
54       X86::TuningFast15ByteNOP,
55       X86::TuningFastBEXTR,
56       X86::TuningFastHorizontalOps,
57       X86::TuningFastLZCNT,
58       X86::TuningFastScalarFSQRT,
59       X86::TuningFastSHLDRotate,
60       X86::TuningFastScalarShiftMasks,
61       X86::TuningFastVectorShiftMasks,
62       X86::TuningFastVariableCrossLaneShuffle,
63       X86::TuningFastVariablePerLaneShuffle,
64       X86::TuningFastVectorFSQRT,
65       X86::TuningLEAForSP,
66       X86::TuningLEAUsesAG,
67       X86::TuningLZCNTFalseDeps,
68       X86::TuningBranchFusion,
69       X86::TuningMacroFusion,
70       X86::TuningPadShortFunctions,
71       X86::TuningPOPCNTFalseDeps,
72       X86::TuningMULCFalseDeps,
73       X86::TuningPERMFalseDeps,
74       X86::TuningRANGEFalseDeps,
75       X86::TuningGETMANTFalseDeps,
76       X86::TuningMULLQFalseDeps,
77       X86::TuningSlow3OpsLEA,
78       X86::TuningSlowDivide32,
79       X86::TuningSlowDivide64,
80       X86::TuningSlowIncDec,
81       X86::TuningSlowLEA,
82       X86::TuningSlowPMADDWD,
83       X86::TuningSlowPMULLD,
84       X86::TuningSlowSHLD,
85       X86::TuningSlowTwoMemOps,
86       X86::TuningSlowUAMem16,
87       X86::TuningPreferMaskRegisters,
88       X86::TuningInsertVZEROUPPER,
89       X86::TuningUseSLMArithCosts,
90       X86::TuningUseGLMDivSqrtCosts,
91 
92       // Perf-tuning flags.
93       X86::TuningFastGather,
94       X86::TuningSlowUAMem32,
95       X86::TuningAllowLight256Bit,
96 
97       // Based on whether user set the -mprefer-vector-width command line.
98       X86::TuningPrefer128Bit,
99       X86::TuningPrefer256Bit,
100 
101       // CPU name enums. These just follow CPU string.
102       X86::ProcIntelAtom
103   };
104 
105 public:
106   explicit X86TTIImpl(const X86TargetMachine *TM, const Function &F)
107       : BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)),
108         TLI(ST->getTargetLowering()) {}
109 
110   /// \name Scalar TTI Implementations
111   /// @{
112   TTI::PopcntSupportKind getPopcntSupport(unsigned TyWidth);
113 
114   /// @}
115 
116   /// \name Cache TTI Implementation
117   /// @{
118   std::optional<unsigned> getCacheSize(
119     TargetTransformInfo::CacheLevel Level) const override;
120   std::optional<unsigned> getCacheAssociativity(
121     TargetTransformInfo::CacheLevel Level) const override;
122   /// @}
123 
124   /// \name Vector TTI Implementations
125   /// @{
126 
127   unsigned getNumberOfRegisters(unsigned ClassID) const;
128   TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const;
129   unsigned getLoadStoreVecRegBitWidth(unsigned AS) const;
130   unsigned getMaxInterleaveFactor(unsigned VF);
131   InstructionCost getArithmeticInstrCost(
132       unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
133       TTI::OperandValueInfo Op1Info = {TTI::OK_AnyValue, TTI::OP_None},
134       TTI::OperandValueInfo Op2Info = {TTI::OK_AnyValue, TTI::OP_None},
135       ArrayRef<const Value *> Args = ArrayRef<const Value *>(),
136       const Instruction *CxtI = nullptr);
137   InstructionCost getShuffleCost(TTI::ShuffleKind Kind, VectorType *Tp,
138                                  ArrayRef<int> Mask,
139                                  TTI::TargetCostKind CostKind, int Index,
140                                  VectorType *SubTp,
141                                  ArrayRef<const Value *> Args = std::nullopt);
142   InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
143                                    TTI::CastContextHint CCH,
144                                    TTI::TargetCostKind CostKind,
145                                    const Instruction *I = nullptr);
146   InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy,
147                                      CmpInst::Predicate VecPred,
148                                      TTI::TargetCostKind CostKind,
149                                      const Instruction *I = nullptr);
150   using BaseT::getVectorInstrCost;
151   InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val,
152                                      TTI::TargetCostKind CostKind,
153                                      unsigned Index, Value *Op0, Value *Op1);
154   InstructionCost getScalarizationOverhead(VectorType *Ty,
155                                            const APInt &DemandedElts,
156                                            bool Insert, bool Extract,
157                                            TTI::TargetCostKind CostKind);
158   InstructionCost getReplicationShuffleCost(Type *EltTy, int ReplicationFactor,
159                                             int VF,
160                                             const APInt &DemandedDstElts,
161                                             TTI::TargetCostKind CostKind);
162   InstructionCost
163   getMemoryOpCost(unsigned Opcode, Type *Src, MaybeAlign Alignment,
164                   unsigned AddressSpace, TTI::TargetCostKind CostKind,
165                   TTI::OperandValueInfo OpInfo = {TTI::OK_AnyValue, TTI::OP_None},
166                   const Instruction *I = nullptr);
167   InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *Src,
168                                         Align Alignment, unsigned AddressSpace,
169                                         TTI::TargetCostKind CostKind);
170   InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy,
171                                          const Value *Ptr, bool VariableMask,
172                                          Align Alignment,
173                                          TTI::TargetCostKind CostKind,
174                                          const Instruction *I);
175   InstructionCost getAddressComputationCost(Type *PtrTy, ScalarEvolution *SE,
176                                             const SCEV *Ptr);
177 
178   std::optional<Instruction *> instCombineIntrinsic(InstCombiner &IC,
179                                                     IntrinsicInst &II) const;
180   std::optional<Value *>
181   simplifyDemandedUseBitsIntrinsic(InstCombiner &IC, IntrinsicInst &II,
182                                    APInt DemandedMask, KnownBits &Known,
183                                    bool &KnownBitsComputed) const;
184   std::optional<Value *> simplifyDemandedVectorEltsIntrinsic(
185       InstCombiner &IC, IntrinsicInst &II, APInt DemandedElts, APInt &UndefElts,
186       APInt &UndefElts2, APInt &UndefElts3,
187       std::function<void(Instruction *, unsigned, APInt, APInt &)>
188           SimplifyAndSetOp) const;
189 
190   unsigned getAtomicMemIntrinsicMaxElementSize() const;
191 
192   InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
193                                         TTI::TargetCostKind CostKind);
194 
195   InstructionCost getArithmeticReductionCost(unsigned Opcode, VectorType *Ty,
196                                              std::optional<FastMathFlags> FMF,
197                                              TTI::TargetCostKind CostKind);
198 
199   InstructionCost getMinMaxCost(Type *Ty, Type *CondTy, bool IsUnsigned);
200 
201   InstructionCost getMinMaxReductionCost(VectorType *Ty, VectorType *CondTy,
202                                          bool IsUnsigned,
203                                          TTI::TargetCostKind CostKind);
204 
205   InstructionCost getInterleavedMemoryOpCost(
206       unsigned Opcode, Type *VecTy, unsigned Factor, ArrayRef<unsigned> Indices,
207       Align Alignment, unsigned AddressSpace, TTI::TargetCostKind CostKind,
208       bool UseMaskForCond = false, bool UseMaskForGaps = false);
209   InstructionCost getInterleavedMemoryOpCostAVX512(
210       unsigned Opcode, FixedVectorType *VecTy, unsigned Factor,
211       ArrayRef<unsigned> Indices, Align Alignment, unsigned AddressSpace,
212       TTI::TargetCostKind CostKind, bool UseMaskForCond = false,
213       bool UseMaskForGaps = false);
214 
215   InstructionCost getIntImmCost(int64_t);
216 
217   InstructionCost getIntImmCost(const APInt &Imm, Type *Ty,
218                                 TTI::TargetCostKind CostKind);
219 
220   InstructionCost getCFInstrCost(unsigned Opcode, TTI::TargetCostKind CostKind,
221                                  const Instruction *I = nullptr);
222 
223   InstructionCost getIntImmCostInst(unsigned Opcode, unsigned Idx,
224                                     const APInt &Imm, Type *Ty,
225                                     TTI::TargetCostKind CostKind,
226                                     Instruction *Inst = nullptr);
227   InstructionCost getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx,
228                                       const APInt &Imm, Type *Ty,
229                                       TTI::TargetCostKind CostKind);
230   /// Return the cost of the scaling factor used in the addressing
231   /// mode represented by AM for this target, for a load/store
232   /// of the specified type.
233   /// If the AM is supported, the return value must be >= 0.
234   /// If the AM is not supported, it returns a negative value.
235   InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV,
236                                        int64_t BaseOffset, bool HasBaseReg,
237                                        int64_t Scale, unsigned AddrSpace) const;
238 
239   bool isLSRCostLess(const TargetTransformInfo::LSRCost &C1,
240                      const TargetTransformInfo::LSRCost &C2);
241   bool canMacroFuseCmp();
242   bool isLegalMaskedLoad(Type *DataType, Align Alignment);
243   bool isLegalMaskedStore(Type *DataType, Align Alignment);
244   bool isLegalNTLoad(Type *DataType, Align Alignment);
245   bool isLegalNTStore(Type *DataType, Align Alignment);
246   bool isLegalBroadcastLoad(Type *ElementTy, ElementCount NumElements) const;
247   bool forceScalarizeMaskedGather(VectorType *VTy, Align Alignment);
248   bool forceScalarizeMaskedScatter(VectorType *VTy, Align Alignment) {
249     return forceScalarizeMaskedGather(VTy, Alignment);
250   }
251   bool isLegalMaskedGather(Type *DataType, Align Alignment);
252   bool isLegalMaskedScatter(Type *DataType, Align Alignment);
253   bool isLegalMaskedExpandLoad(Type *DataType);
254   bool isLegalMaskedCompressStore(Type *DataType);
255   bool isLegalAltInstr(VectorType *VecTy, unsigned Opcode0, unsigned Opcode1,
256                        const SmallBitVector &OpcodeMask) const;
257   bool hasDivRemOp(Type *DataType, bool IsSigned);
258   bool isExpensiveToSpeculativelyExecute(const Instruction *I);
259   bool isFCmpOrdCheaperThanFCmpZero(Type *Ty);
260   bool areInlineCompatible(const Function *Caller,
261                            const Function *Callee) const;
262   bool areTypesABICompatible(const Function *Caller, const Function *Callee,
263                              const ArrayRef<Type *> &Type) const;
264   TTI::MemCmpExpansionOptions enableMemCmpExpansion(bool OptSize,
265                                                     bool IsZeroCmp) const;
266   bool prefersVectorizedAddressing() const;
267   bool supportsEfficientVectorElementLoadStore() const;
268   bool enableInterleavedAccessVectorization();
269 
270 private:
271   bool supportsGather() const;
272   InstructionCost getGSScalarCost(unsigned Opcode, Type *DataTy,
273                                   bool VariableMask, Align Alignment,
274                                   unsigned AddressSpace);
275   InstructionCost getGSVectorCost(unsigned Opcode, Type *DataTy,
276                                   const Value *Ptr, Align Alignment,
277                                   unsigned AddressSpace);
278 
279   int getGatherOverhead() const;
280   int getScatterOverhead() const;
281 
282   /// @}
283 };
284 
285 } // end namespace llvm
286 
287 #endif
288