xref: /freebsd/contrib/llvm-project/llvm/lib/Target/X86/X86TargetMachine.cpp (revision ae7e8a02e6e93455e026036132c4d053b2c12ad9)
1 //===-- X86TargetMachine.cpp - Define TargetMachine for the X86 -----------===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the X86 specific subclass of TargetMachine.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #include "X86TargetMachine.h"
14 #include "MCTargetDesc/X86MCTargetDesc.h"
15 #include "TargetInfo/X86TargetInfo.h"
16 #include "X86.h"
17 #include "X86CallLowering.h"
18 #include "X86LegalizerInfo.h"
19 #include "X86MacroFusion.h"
20 #include "X86Subtarget.h"
21 #include "X86TargetObjectFile.h"
22 #include "X86TargetTransformInfo.h"
23 #include "llvm/ADT/Optional.h"
24 #include "llvm/ADT/STLExtras.h"
25 #include "llvm/ADT/SmallString.h"
26 #include "llvm/ADT/StringRef.h"
27 #include "llvm/ADT/Triple.h"
28 #include "llvm/Analysis/TargetTransformInfo.h"
29 #include "llvm/CodeGen/ExecutionDomainFix.h"
30 #include "llvm/CodeGen/GlobalISel/CallLowering.h"
31 #include "llvm/CodeGen/GlobalISel/IRTranslator.h"
32 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h"
33 #include "llvm/CodeGen/GlobalISel/Legalizer.h"
34 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h"
35 #include "llvm/CodeGen/MachineScheduler.h"
36 #include "llvm/CodeGen/Passes.h"
37 #include "llvm/CodeGen/TargetPassConfig.h"
38 #include "llvm/IR/Attributes.h"
39 #include "llvm/IR/DataLayout.h"
40 #include "llvm/IR/Function.h"
41 #include "llvm/MC/MCAsmInfo.h"
42 #include "llvm/Pass.h"
43 #include "llvm/Support/CodeGen.h"
44 #include "llvm/Support/CommandLine.h"
45 #include "llvm/Support/ErrorHandling.h"
46 #include "llvm/Support/TargetRegistry.h"
47 #include "llvm/Target/TargetLoweringObjectFile.h"
48 #include "llvm/Target/TargetOptions.h"
49 #include "llvm/Transforms/CFGuard.h"
50 #include <memory>
51 #include <string>
52 
53 using namespace llvm;
54 
55 static cl::opt<bool> EnableMachineCombinerPass("x86-machine-combiner",
56                                cl::desc("Enable the machine combiner pass"),
57                                cl::init(true), cl::Hidden);
58 
59 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeX86Target() {
60   // Register the target.
61   RegisterTargetMachine<X86TargetMachine> X(getTheX86_32Target());
62   RegisterTargetMachine<X86TargetMachine> Y(getTheX86_64Target());
63 
64   PassRegistry &PR = *PassRegistry::getPassRegistry();
65   initializeX86LowerAMXTypeLegacyPassPass(PR);
66   initializeGlobalISel(PR);
67   initializeWinEHStatePassPass(PR);
68   initializeFixupBWInstPassPass(PR);
69   initializeEvexToVexInstPassPass(PR);
70   initializeFixupLEAPassPass(PR);
71   initializeFPSPass(PR);
72   initializeX86FixupSetCCPassPass(PR);
73   initializeX86CallFrameOptimizationPass(PR);
74   initializeX86CmovConverterPassPass(PR);
75   initializeX86TileConfigPass(PR);
76   initializeX86ExpandPseudoPass(PR);
77   initializeX86ExecutionDomainFixPass(PR);
78   initializeX86DomainReassignmentPass(PR);
79   initializeX86AvoidSFBPassPass(PR);
80   initializeX86AvoidTrailingCallPassPass(PR);
81   initializeX86SpeculativeLoadHardeningPassPass(PR);
82   initializeX86SpeculativeExecutionSideEffectSuppressionPass(PR);
83   initializeX86FlagsCopyLoweringPassPass(PR);
84   initializeX86LoadValueInjectionLoadHardeningPassPass(PR);
85   initializeX86LoadValueInjectionRetHardeningPassPass(PR);
86   initializeX86OptimizeLEAPassPass(PR);
87   initializeX86PartialReductionPass(PR);
88   initializePseudoProbeInserterPass(PR);
89 }
90 
91 static std::unique_ptr<TargetLoweringObjectFile> createTLOF(const Triple &TT) {
92   if (TT.isOSBinFormatMachO()) {
93     if (TT.getArch() == Triple::x86_64)
94       return std::make_unique<X86_64MachoTargetObjectFile>();
95     return std::make_unique<TargetLoweringObjectFileMachO>();
96   }
97 
98   if (TT.isOSBinFormatCOFF())
99     return std::make_unique<TargetLoweringObjectFileCOFF>();
100   return std::make_unique<X86ELFTargetObjectFile>();
101 }
102 
103 static std::string computeDataLayout(const Triple &TT) {
104   // X86 is little endian
105   std::string Ret = "e";
106 
107   Ret += DataLayout::getManglingComponent(TT);
108   // X86 and x32 have 32 bit pointers.
109   if ((TT.isArch64Bit() &&
110        (TT.getEnvironment() == Triple::GNUX32 || TT.isOSNaCl())) ||
111       !TT.isArch64Bit())
112     Ret += "-p:32:32";
113 
114   // Address spaces for 32 bit signed, 32 bit unsigned, and 64 bit pointers.
115   Ret += "-p270:32:32-p271:32:32-p272:64:64";
116 
117   // Some ABIs align 64 bit integers and doubles to 64 bits, others to 32.
118   if (TT.isArch64Bit() || TT.isOSWindows() || TT.isOSNaCl())
119     Ret += "-i64:64";
120   else if (TT.isOSIAMCU())
121     Ret += "-i64:32-f64:32";
122   else
123     Ret += "-f64:32:64";
124 
125   // Some ABIs align long double to 128 bits, others to 32.
126   if (TT.isOSNaCl() || TT.isOSIAMCU())
127     ; // No f80
128   else if (TT.isArch64Bit() || TT.isOSDarwin())
129     Ret += "-f80:128";
130   else
131     Ret += "-f80:32";
132 
133   if (TT.isOSIAMCU())
134     Ret += "-f128:32";
135 
136   // The registers can hold 8, 16, 32 or, in x86-64, 64 bits.
137   if (TT.isArch64Bit())
138     Ret += "-n8:16:32:64";
139   else
140     Ret += "-n8:16:32";
141 
142   // The stack is aligned to 32 bits on some ABIs and 128 bits on others.
143   if ((!TT.isArch64Bit() && TT.isOSWindows()) || TT.isOSIAMCU())
144     Ret += "-a:0:32-S32";
145   else
146     Ret += "-S128";
147 
148   return Ret;
149 }
150 
151 static Reloc::Model getEffectiveRelocModel(const Triple &TT,
152                                            bool JIT,
153                                            Optional<Reloc::Model> RM) {
154   bool is64Bit = TT.getArch() == Triple::x86_64;
155   if (!RM.hasValue()) {
156     // JIT codegen should use static relocations by default, since it's
157     // typically executed in process and not relocatable.
158     if (JIT)
159       return Reloc::Static;
160 
161     // Darwin defaults to PIC in 64 bit mode and dynamic-no-pic in 32 bit mode.
162     // Win64 requires rip-rel addressing, thus we force it to PIC. Otherwise we
163     // use static relocation model by default.
164     if (TT.isOSDarwin()) {
165       if (is64Bit)
166         return Reloc::PIC_;
167       return Reloc::DynamicNoPIC;
168     }
169     if (TT.isOSWindows() && is64Bit)
170       return Reloc::PIC_;
171     return Reloc::Static;
172   }
173 
174   // ELF and X86-64 don't have a distinct DynamicNoPIC model.  DynamicNoPIC
175   // is defined as a model for code which may be used in static or dynamic
176   // executables but not necessarily a shared library. On X86-32 we just
177   // compile in -static mode, in x86-64 we use PIC.
178   if (*RM == Reloc::DynamicNoPIC) {
179     if (is64Bit)
180       return Reloc::PIC_;
181     if (!TT.isOSDarwin())
182       return Reloc::Static;
183   }
184 
185   // If we are on Darwin, disallow static relocation model in X86-64 mode, since
186   // the Mach-O file format doesn't support it.
187   if (*RM == Reloc::Static && TT.isOSDarwin() && is64Bit)
188     return Reloc::PIC_;
189 
190   return *RM;
191 }
192 
193 static CodeModel::Model getEffectiveX86CodeModel(Optional<CodeModel::Model> CM,
194                                                  bool JIT, bool Is64Bit) {
195   if (CM) {
196     if (*CM == CodeModel::Tiny)
197       report_fatal_error("Target does not support the tiny CodeModel", false);
198     return *CM;
199   }
200   if (JIT)
201     return Is64Bit ? CodeModel::Large : CodeModel::Small;
202   return CodeModel::Small;
203 }
204 
205 /// Create an X86 target.
206 ///
207 X86TargetMachine::X86TargetMachine(const Target &T, const Triple &TT,
208                                    StringRef CPU, StringRef FS,
209                                    const TargetOptions &Options,
210                                    Optional<Reloc::Model> RM,
211                                    Optional<CodeModel::Model> CM,
212                                    CodeGenOpt::Level OL, bool JIT)
213     : LLVMTargetMachine(
214           T, computeDataLayout(TT), TT, CPU, FS, Options,
215           getEffectiveRelocModel(TT, JIT, RM),
216           getEffectiveX86CodeModel(CM, JIT, TT.getArch() == Triple::x86_64),
217           OL),
218       TLOF(createTLOF(getTargetTriple())), IsJIT(JIT) {
219   // On PS4, the "return address" of a 'noreturn' call must still be within
220   // the calling function, and TrapUnreachable is an easy way to get that.
221   if (TT.isPS4() || TT.isOSBinFormatMachO()) {
222     this->Options.TrapUnreachable = true;
223     this->Options.NoTrapAfterNoreturn = TT.isOSBinFormatMachO();
224   }
225 
226   setMachineOutliner(true);
227 
228   // x86 supports the debug entry values.
229   setSupportsDebugEntryValues(true);
230 
231   initAsmInfo();
232 }
233 
234 X86TargetMachine::~X86TargetMachine() = default;
235 
236 const X86Subtarget *
237 X86TargetMachine::getSubtargetImpl(const Function &F) const {
238   Attribute CPUAttr = F.getFnAttribute("target-cpu");
239   Attribute TuneAttr = F.getFnAttribute("tune-cpu");
240   Attribute FSAttr = F.getFnAttribute("target-features");
241 
242   StringRef CPU =
243       CPUAttr.isValid() ? CPUAttr.getValueAsString() : (StringRef)TargetCPU;
244   StringRef TuneCPU =
245       TuneAttr.isValid() ? TuneAttr.getValueAsString() : (StringRef)CPU;
246   StringRef FS =
247       FSAttr.isValid() ? FSAttr.getValueAsString() : (StringRef)TargetFS;
248 
249   SmallString<512> Key;
250   // The additions here are ordered so that the definitely short strings are
251   // added first so we won't exceed the small size. We append the
252   // much longer FS string at the end so that we only heap allocate at most
253   // one time.
254 
255   // Extract prefer-vector-width attribute.
256   unsigned PreferVectorWidthOverride = 0;
257   Attribute PreferVecWidthAttr = F.getFnAttribute("prefer-vector-width");
258   if (PreferVecWidthAttr.isValid()) {
259     StringRef Val = PreferVecWidthAttr.getValueAsString();
260     unsigned Width;
261     if (!Val.getAsInteger(0, Width)) {
262       Key += "prefer-vector-width=";
263       Key += Val;
264       PreferVectorWidthOverride = Width;
265     }
266   }
267 
268   // Extract min-legal-vector-width attribute.
269   unsigned RequiredVectorWidth = UINT32_MAX;
270   Attribute MinLegalVecWidthAttr = F.getFnAttribute("min-legal-vector-width");
271   if (MinLegalVecWidthAttr.isValid()) {
272     StringRef Val = MinLegalVecWidthAttr.getValueAsString();
273     unsigned Width;
274     if (!Val.getAsInteger(0, Width)) {
275       Key += "min-legal-vector-width=";
276       Key += Val;
277       RequiredVectorWidth = Width;
278     }
279   }
280 
281   // Add CPU to the Key.
282   Key += CPU;
283 
284   // Add tune CPU to the Key.
285   Key += "tune=";
286   Key += TuneCPU;
287 
288   // Keep track of the start of the feature portion of the string.
289   unsigned FSStart = Key.size();
290 
291   // FIXME: This is related to the code below to reset the target options,
292   // we need to know whether or not the soft float flag is set on the
293   // function before we can generate a subtarget. We also need to use
294   // it as a key for the subtarget since that can be the only difference
295   // between two functions.
296   bool SoftFloat =
297       F.getFnAttribute("use-soft-float").getValueAsString() == "true";
298   // If the soft float attribute is set on the function turn on the soft float
299   // subtarget feature.
300   if (SoftFloat)
301     Key += FS.empty() ? "+soft-float" : "+soft-float,";
302 
303   Key += FS;
304 
305   // We may have added +soft-float to the features so move the StringRef to
306   // point to the full string in the Key.
307   FS = Key.substr(FSStart);
308 
309   auto &I = SubtargetMap[Key];
310   if (!I) {
311     // This needs to be done before we create a new subtarget since any
312     // creation will depend on the TM and the code generation flags on the
313     // function that reside in TargetOptions.
314     resetTargetOptions(F);
315     I = std::make_unique<X86Subtarget>(
316         TargetTriple, CPU, TuneCPU, FS, *this,
317         MaybeAlign(Options.StackAlignmentOverride), PreferVectorWidthOverride,
318         RequiredVectorWidth);
319   }
320   return I.get();
321 }
322 
323 bool X86TargetMachine::isNoopAddrSpaceCast(unsigned SrcAS,
324                                            unsigned DestAS) const {
325   assert(SrcAS != DestAS && "Expected different address spaces!");
326   if (getPointerSize(SrcAS) != getPointerSize(DestAS))
327     return false;
328   return SrcAS < 256 && DestAS < 256;
329 }
330 
331 //===----------------------------------------------------------------------===//
332 // X86 TTI query.
333 //===----------------------------------------------------------------------===//
334 
335 TargetTransformInfo
336 X86TargetMachine::getTargetTransformInfo(const Function &F) {
337   return TargetTransformInfo(X86TTIImpl(this, F));
338 }
339 
340 //===----------------------------------------------------------------------===//
341 // Pass Pipeline Configuration
342 //===----------------------------------------------------------------------===//
343 
344 namespace {
345 
346 /// X86 Code Generator Pass Configuration Options.
347 class X86PassConfig : public TargetPassConfig {
348 public:
349   X86PassConfig(X86TargetMachine &TM, PassManagerBase &PM)
350     : TargetPassConfig(TM, PM) {}
351 
352   X86TargetMachine &getX86TargetMachine() const {
353     return getTM<X86TargetMachine>();
354   }
355 
356   ScheduleDAGInstrs *
357   createMachineScheduler(MachineSchedContext *C) const override {
358     ScheduleDAGMILive *DAG = createGenericSchedLive(C);
359     DAG->addMutation(createX86MacroFusionDAGMutation());
360     return DAG;
361   }
362 
363   ScheduleDAGInstrs *
364   createPostMachineScheduler(MachineSchedContext *C) const override {
365     ScheduleDAGMI *DAG = createGenericSchedPostRA(C);
366     DAG->addMutation(createX86MacroFusionDAGMutation());
367     return DAG;
368   }
369 
370   void addIRPasses() override;
371   bool addInstSelector() override;
372   bool addIRTranslator() override;
373   bool addLegalizeMachineIR() override;
374   bool addRegBankSelect() override;
375   bool addGlobalInstructionSelect() override;
376   bool addILPOpts() override;
377   bool addPreISel() override;
378   void addMachineSSAOptimization() override;
379   void addPreRegAlloc() override;
380   void addPostRegAlloc() override;
381   void addPreEmitPass() override;
382   void addPreEmitPass2() override;
383   void addPreSched2() override;
384   bool addPreRewrite() override;
385 
386   std::unique_ptr<CSEConfigBase> getCSEConfig() const override;
387 };
388 
389 class X86ExecutionDomainFix : public ExecutionDomainFix {
390 public:
391   static char ID;
392   X86ExecutionDomainFix() : ExecutionDomainFix(ID, X86::VR128XRegClass) {}
393   StringRef getPassName() const override {
394     return "X86 Execution Dependency Fix";
395   }
396 };
397 char X86ExecutionDomainFix::ID;
398 
399 } // end anonymous namespace
400 
401 INITIALIZE_PASS_BEGIN(X86ExecutionDomainFix, "x86-execution-domain-fix",
402   "X86 Execution Domain Fix", false, false)
403 INITIALIZE_PASS_DEPENDENCY(ReachingDefAnalysis)
404 INITIALIZE_PASS_END(X86ExecutionDomainFix, "x86-execution-domain-fix",
405   "X86 Execution Domain Fix", false, false)
406 
407 TargetPassConfig *X86TargetMachine::createPassConfig(PassManagerBase &PM) {
408   return new X86PassConfig(*this, PM);
409 }
410 
411 void X86PassConfig::addIRPasses() {
412   addPass(createAtomicExpandPass());
413   addPass(createX86LowerAMXTypePass());
414 
415   TargetPassConfig::addIRPasses();
416 
417   if (TM->getOptLevel() != CodeGenOpt::None) {
418     addPass(createInterleavedAccessPass());
419     addPass(createX86PartialReductionPass());
420   }
421 
422   // Add passes that handle indirect branch removal and insertion of a retpoline
423   // thunk. These will be a no-op unless a function subtarget has the retpoline
424   // feature enabled.
425   addPass(createIndirectBrExpandPass());
426 
427   // Add Control Flow Guard checks.
428   const Triple &TT = TM->getTargetTriple();
429   if (TT.isOSWindows()) {
430     if (TT.getArch() == Triple::x86_64) {
431       addPass(createCFGuardDispatchPass());
432     } else {
433       addPass(createCFGuardCheckPass());
434     }
435   }
436 }
437 
438 bool X86PassConfig::addInstSelector() {
439   // Install an instruction selector.
440   addPass(createX86ISelDag(getX86TargetMachine(), getOptLevel()));
441 
442   // For ELF, cleanup any local-dynamic TLS accesses.
443   if (TM->getTargetTriple().isOSBinFormatELF() &&
444       getOptLevel() != CodeGenOpt::None)
445     addPass(createCleanupLocalDynamicTLSPass());
446 
447   addPass(createX86GlobalBaseRegPass());
448   return false;
449 }
450 
451 bool X86PassConfig::addIRTranslator() {
452   addPass(new IRTranslator(getOptLevel()));
453   return false;
454 }
455 
456 bool X86PassConfig::addLegalizeMachineIR() {
457   addPass(new Legalizer());
458   return false;
459 }
460 
461 bool X86PassConfig::addRegBankSelect() {
462   addPass(new RegBankSelect());
463   return false;
464 }
465 
466 bool X86PassConfig::addGlobalInstructionSelect() {
467   addPass(new InstructionSelect());
468   return false;
469 }
470 
471 bool X86PassConfig::addILPOpts() {
472   addPass(&EarlyIfConverterID);
473   if (EnableMachineCombinerPass)
474     addPass(&MachineCombinerID);
475   addPass(createX86CmovConverterPass());
476   return true;
477 }
478 
479 bool X86PassConfig::addPreISel() {
480   // Only add this pass for 32-bit x86 Windows.
481   const Triple &TT = TM->getTargetTriple();
482   if (TT.isOSWindows() && TT.getArch() == Triple::x86)
483     addPass(createX86WinEHStatePass());
484   return true;
485 }
486 
487 void X86PassConfig::addPreRegAlloc() {
488   if (getOptLevel() != CodeGenOpt::None) {
489     addPass(&LiveRangeShrinkID);
490     addPass(createX86FixupSetCC());
491     addPass(createX86OptimizeLEAs());
492     addPass(createX86CallFrameOptimization());
493     addPass(createX86AvoidStoreForwardingBlocks());
494   }
495 
496   addPass(createX86SpeculativeLoadHardeningPass());
497   addPass(createX86FlagsCopyLoweringPass());
498   addPass(createX86WinAllocaExpander());
499 
500   if (getOptLevel() != CodeGenOpt::None) {
501     addPass(createX86PreTileConfigPass());
502   }
503 }
504 
505 void X86PassConfig::addMachineSSAOptimization() {
506   addPass(createX86DomainReassignmentPass());
507   TargetPassConfig::addMachineSSAOptimization();
508 }
509 
510 void X86PassConfig::addPostRegAlloc() {
511   addPass(createX86FloatingPointStackifierPass());
512   // When -O0 is enabled, the Load Value Injection Hardening pass will fall back
513   // to using the Speculative Execution Side Effect Suppression pass for
514   // mitigation. This is to prevent slow downs due to
515   // analyses needed by the LVIHardening pass when compiling at -O0.
516   if (getOptLevel() != CodeGenOpt::None)
517     addPass(createX86LoadValueInjectionLoadHardeningPass());
518 }
519 
520 void X86PassConfig::addPreSched2() { addPass(createX86ExpandPseudoPass()); }
521 
522 void X86PassConfig::addPreEmitPass() {
523   if (getOptLevel() != CodeGenOpt::None) {
524     addPass(new X86ExecutionDomainFix());
525     addPass(createBreakFalseDeps());
526   }
527 
528   addPass(createX86IndirectBranchTrackingPass());
529 
530   addPass(createX86IssueVZeroUpperPass());
531 
532   if (getOptLevel() != CodeGenOpt::None) {
533     addPass(createX86FixupBWInsts());
534     addPass(createX86PadShortFunctions());
535     addPass(createX86FixupLEAs());
536   }
537   addPass(createX86EvexToVexInsts());
538   addPass(createX86DiscriminateMemOpsPass());
539   addPass(createX86InsertPrefetchPass());
540   addPass(createX86InsertX87waitPass());
541 }
542 
543 void X86PassConfig::addPreEmitPass2() {
544   const Triple &TT = TM->getTargetTriple();
545   const MCAsmInfo *MAI = TM->getMCAsmInfo();
546 
547   // The X86 Speculative Execution Pass must run after all control
548   // flow graph modifying passes. As a result it was listed to run right before
549   // the X86 Retpoline Thunks pass. The reason it must run after control flow
550   // graph modifications is that the model of LFENCE in LLVM has to be updated
551   // (FIXME: https://bugs.llvm.org/show_bug.cgi?id=45167). Currently the
552   // placement of this pass was hand checked to ensure that the subsequent
553   // passes don't move the code around the LFENCEs in a way that will hurt the
554   // correctness of this pass. This placement has been shown to work based on
555   // hand inspection of the codegen output.
556   addPass(createX86SpeculativeExecutionSideEffectSuppression());
557   addPass(createX86IndirectThunksPass());
558 
559   // Insert extra int3 instructions after trailing call instructions to avoid
560   // issues in the unwinder.
561   if (TT.isOSWindows() && TT.getArch() == Triple::x86_64)
562     addPass(createX86AvoidTrailingCallPass());
563 
564   // Verify basic block incoming and outgoing cfa offset and register values and
565   // correct CFA calculation rule where needed by inserting appropriate CFI
566   // instructions.
567   if (!TT.isOSDarwin() &&
568       (!TT.isOSWindows() ||
569        MAI->getExceptionHandlingType() == ExceptionHandling::DwarfCFI))
570     addPass(createCFIInstrInserter());
571   // Identify valid longjmp targets for Windows Control Flow Guard.
572   if (TT.isOSWindows())
573     addPass(createCFGuardLongjmpPass());
574   addPass(createX86LoadValueInjectionRetHardeningPass());
575 }
576 
577 bool X86PassConfig::addPreRewrite() {
578   addPass(createX86TileConfigPass());
579   return true;
580 }
581 
582 std::unique_ptr<CSEConfigBase> X86PassConfig::getCSEConfig() const {
583   return getStandardCSEConfigForOpt(TM->getOptLevel());
584 }
585