xref: /freebsd/contrib/llvm-project/llvm/lib/Target/X86/X86Subtarget.h (revision ec0ea6efa1ad229d75c394c1a9b9cac33af2b1d3)
1 //===-- X86Subtarget.h - Define Subtarget for the X86 ----------*- C++ -*--===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file declares the X86 specific subclass of TargetSubtargetInfo.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef LLVM_LIB_TARGET_X86_X86SUBTARGET_H
14 #define LLVM_LIB_TARGET_X86_X86SUBTARGET_H
15 
16 #include "X86FrameLowering.h"
17 #include "X86ISelLowering.h"
18 #include "X86InstrInfo.h"
19 #include "X86SelectionDAGInfo.h"
20 #include "llvm/ADT/Triple.h"
21 #include "llvm/CodeGen/TargetSubtargetInfo.h"
22 #include "llvm/IR/CallingConv.h"
23 #include <climits>
24 #include <memory>
25 
26 #define GET_SUBTARGETINFO_HEADER
27 #include "X86GenSubtargetInfo.inc"
28 
29 namespace llvm {
30 
31 class CallLowering;
32 class GlobalValue;
33 class InstructionSelector;
34 class LegalizerInfo;
35 class RegisterBankInfo;
36 class StringRef;
37 class TargetMachine;
38 
39 /// The X86 backend supports a number of different styles of PIC.
40 ///
41 namespace PICStyles {
42 
43 enum class Style {
44   StubPIC,          // Used on i386-darwin in pic mode.
45   GOT,              // Used on 32 bit elf on when in pic mode.
46   RIPRel,           // Used on X86-64 when in pic mode.
47   None              // Set when not in pic mode.
48 };
49 
50 } // end namespace PICStyles
51 
52 class X86Subtarget final : public X86GenSubtargetInfo {
53   // NOTE: Do not add anything new to this list. Coarse, CPU name based flags
54   // are not a good idea. We should be migrating away from these.
55   enum X86ProcFamilyEnum {
56     Others,
57     IntelAtom,
58     IntelSLM
59   };
60 
61   enum X86SSEEnum {
62     NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F
63   };
64 
65   enum X863DNowEnum {
66     NoThreeDNow, MMX, ThreeDNow, ThreeDNowA
67   };
68 
69   /// X86 processor family: Intel Atom, and others
70   X86ProcFamilyEnum X86ProcFamily = Others;
71 
72   /// Which PIC style to use
73   PICStyles::Style PICStyle;
74 
75   const TargetMachine &TM;
76 
77   /// SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or none supported.
78   X86SSEEnum X86SSELevel = NoSSE;
79 
80   /// MMX, 3DNow, 3DNow Athlon, or none supported.
81   X863DNowEnum X863DNowLevel = NoThreeDNow;
82 
83   /// True if the processor supports X87 instructions.
84   bool HasX87 = false;
85 
86   /// True if the processor supports CMPXCHG8B.
87   bool HasCmpxchg8b = false;
88 
89   /// True if this processor has NOPL instruction
90   /// (generally pentium pro+).
91   bool HasNOPL = false;
92 
93   /// True if this processor has conditional move instructions
94   /// (generally pentium pro+).
95   bool HasCMov = false;
96 
97   /// True if the processor supports X86-64 instructions.
98   bool HasX86_64 = false;
99 
100   /// True if the processor supports POPCNT.
101   bool HasPOPCNT = false;
102 
103   /// True if the processor supports SSE4A instructions.
104   bool HasSSE4A = false;
105 
106   /// Target has AES instructions
107   bool HasAES = false;
108   bool HasVAES = false;
109 
110   /// Target has FXSAVE/FXRESTOR instructions
111   bool HasFXSR = false;
112 
113   /// Target has XSAVE instructions
114   bool HasXSAVE = false;
115 
116   /// Target has XSAVEOPT instructions
117   bool HasXSAVEOPT = false;
118 
119   /// Target has XSAVEC instructions
120   bool HasXSAVEC = false;
121 
122   /// Target has XSAVES instructions
123   bool HasXSAVES = false;
124 
125   /// Target has carry-less multiplication
126   bool HasPCLMUL = false;
127   bool HasVPCLMULQDQ = false;
128 
129   /// Target has Galois Field Arithmetic instructions
130   bool HasGFNI = false;
131 
132   /// Target has 3-operand fused multiply-add
133   bool HasFMA = false;
134 
135   /// Target has 4-operand fused multiply-add
136   bool HasFMA4 = false;
137 
138   /// Target has XOP instructions
139   bool HasXOP = false;
140 
141   /// Target has TBM instructions.
142   bool HasTBM = false;
143 
144   /// Target has LWP instructions
145   bool HasLWP = false;
146 
147   /// True if the processor has the MOVBE instruction.
148   bool HasMOVBE = false;
149 
150   /// True if the processor has the RDRAND instruction.
151   bool HasRDRAND = false;
152 
153   /// Processor has 16-bit floating point conversion instructions.
154   bool HasF16C = false;
155 
156   /// Processor has FS/GS base insturctions.
157   bool HasFSGSBase = false;
158 
159   /// Processor has LZCNT instruction.
160   bool HasLZCNT = false;
161 
162   /// Processor has BMI1 instructions.
163   bool HasBMI = false;
164 
165   /// Processor has BMI2 instructions.
166   bool HasBMI2 = false;
167 
168   /// Processor has VBMI instructions.
169   bool HasVBMI = false;
170 
171   /// Processor has VBMI2 instructions.
172   bool HasVBMI2 = false;
173 
174   /// Processor has Integer Fused Multiply Add
175   bool HasIFMA = false;
176 
177   /// Processor has RTM instructions.
178   bool HasRTM = false;
179 
180   /// Processor has ADX instructions.
181   bool HasADX = false;
182 
183   /// Processor has SHA instructions.
184   bool HasSHA = false;
185 
186   /// Processor has PRFCHW instructions.
187   bool HasPRFCHW = false;
188 
189   /// Processor has RDSEED instructions.
190   bool HasRDSEED = false;
191 
192   /// Processor has LAHF/SAHF instructions in 64-bit mode.
193   bool HasLAHFSAHF64 = false;
194 
195   /// Processor has MONITORX/MWAITX instructions.
196   bool HasMWAITX = false;
197 
198   /// Processor has Cache Line Zero instruction
199   bool HasCLZERO = false;
200 
201   /// Processor has Cache Line Demote instruction
202   bool HasCLDEMOTE = false;
203 
204   /// Processor has MOVDIRI instruction (direct store integer).
205   bool HasMOVDIRI = false;
206 
207   /// Processor has MOVDIR64B instruction (direct store 64 bytes).
208   bool HasMOVDIR64B = false;
209 
210   /// Processor has ptwrite instruction.
211   bool HasPTWRITE = false;
212 
213   /// Processor has Prefetch with intent to Write instruction
214   bool HasPREFETCHWT1 = false;
215 
216   /// True if SHLD instructions are slow.
217   bool IsSHLDSlow = false;
218 
219   /// True if the PMULLD instruction is slow compared to PMULLW/PMULHW and
220   //  PMULUDQ.
221   bool IsPMULLDSlow = false;
222 
223   /// True if the PMADDWD instruction is slow compared to PMULLD.
224   bool IsPMADDWDSlow = false;
225 
226   /// True if unaligned memory accesses of 16-bytes are slow.
227   bool IsUAMem16Slow = false;
228 
229   /// True if unaligned memory accesses of 32-bytes are slow.
230   bool IsUAMem32Slow = false;
231 
232   /// True if SSE operations can have unaligned memory operands.
233   /// This may require setting a configuration bit in the processor.
234   bool HasSSEUnalignedMem = false;
235 
236   /// True if this processor has the CMPXCHG16B instruction;
237   /// this is true for most x86-64 chips, but not the first AMD chips.
238   bool HasCmpxchg16b = false;
239 
240   /// True if the LEA instruction should be used for adjusting
241   /// the stack pointer. This is an optimization for Intel Atom processors.
242   bool UseLeaForSP = false;
243 
244   /// True if POPCNT instruction has a false dependency on the destination register.
245   bool HasPOPCNTFalseDeps = false;
246 
247   /// True if LZCNT/TZCNT instructions have a false dependency on the destination register.
248   bool HasLZCNTFalseDeps = false;
249 
250   /// True if its preferable to combine to a single cross-lane shuffle
251   /// using a variable mask over multiple fixed shuffles.
252   bool HasFastVariableCrossLaneShuffle = false;
253 
254   /// True if its preferable to combine to a single per-lane shuffle
255   /// using a variable mask over multiple fixed shuffles.
256   bool HasFastVariablePerLaneShuffle = false;
257 
258   /// True if vzeroupper instructions should be inserted after code that uses
259   /// ymm or zmm registers.
260   bool InsertVZEROUPPER = false;
261 
262   /// True if there is no performance penalty for writing NOPs with up to
263   /// 7 bytes.
264   bool HasFast7ByteNOP = false;
265 
266   /// True if there is no performance penalty for writing NOPs with up to
267   /// 11 bytes.
268   bool HasFast11ByteNOP = false;
269 
270   /// True if there is no performance penalty for writing NOPs with up to
271   /// 15 bytes.
272   bool HasFast15ByteNOP = false;
273 
274   /// True if gather is reasonably fast. This is true for Skylake client and
275   /// all AVX-512 CPUs.
276   bool HasFastGather = false;
277 
278   /// True if hardware SQRTSS instruction is at least as fast (latency) as
279   /// RSQRTSS followed by a Newton-Raphson iteration.
280   bool HasFastScalarFSQRT = false;
281 
282   /// True if hardware SQRTPS/VSQRTPS instructions are at least as fast
283   /// (throughput) as RSQRTPS/VRSQRTPS followed by a Newton-Raphson iteration.
284   bool HasFastVectorFSQRT = false;
285 
286   /// True if 8-bit divisions are significantly faster than
287   /// 32-bit divisions and should be used when possible.
288   bool HasSlowDivide32 = false;
289 
290   /// True if 32-bit divides are significantly faster than
291   /// 64-bit divisions and should be used when possible.
292   bool HasSlowDivide64 = false;
293 
294   /// True if LZCNT instruction is fast.
295   bool HasFastLZCNT = false;
296 
297   /// True if SHLD based rotate is fast.
298   bool HasFastSHLDRotate = false;
299 
300   /// True if the processor supports macrofusion.
301   bool HasMacroFusion = false;
302 
303   /// True if the processor supports branch fusion.
304   bool HasBranchFusion = false;
305 
306   /// True if the processor has enhanced REP MOVSB/STOSB.
307   bool HasERMSB = false;
308 
309   /// True if the processor has fast short REP MOV.
310   bool HasFSRM = false;
311 
312   /// True if the short functions should be padded to prevent
313   /// a stall when returning too early.
314   bool PadShortFunctions = false;
315 
316   /// True if two memory operand instructions should use a temporary register
317   /// instead.
318   bool SlowTwoMemOps = false;
319 
320   /// True if the LEA instruction inputs have to be ready at address generation
321   /// (AG) time.
322   bool LEAUsesAG = false;
323 
324   /// True if the LEA instruction with certain arguments is slow
325   bool SlowLEA = false;
326 
327   /// True if the LEA instruction has all three source operands: base, index,
328   /// and offset or if the LEA instruction uses base and index registers where
329   /// the base is EBP, RBP,or R13
330   bool Slow3OpsLEA = false;
331 
332   /// True if INC and DEC instructions are slow when writing to flags
333   bool SlowIncDec = false;
334 
335   /// Processor has AVX-512 PreFetch Instructions
336   bool HasPFI = false;
337 
338   /// Processor has AVX-512 Exponential and Reciprocal Instructions
339   bool HasERI = false;
340 
341   /// Processor has AVX-512 Conflict Detection Instructions
342   bool HasCDI = false;
343 
344   /// Processor has AVX-512 population count Instructions
345   bool HasVPOPCNTDQ = false;
346 
347   /// Processor has AVX-512 Doubleword and Quadword instructions
348   bool HasDQI = false;
349 
350   /// Processor has AVX-512 Byte and Word instructions
351   bool HasBWI = false;
352 
353   /// Processor has AVX-512 Vector Length eXtenstions
354   bool HasVLX = false;
355 
356   /// Processor has PKU extenstions
357   bool HasPKU = false;
358 
359   /// Processor has AVX-512 Vector Neural Network Instructions
360   bool HasVNNI = false;
361 
362   /// Processor has AVX Vector Neural Network Instructions
363   bool HasAVXVNNI = false;
364 
365   /// Processor has AVX-512 bfloat16 floating-point extensions
366   bool HasBF16 = false;
367 
368   /// Processor supports ENQCMD instructions
369   bool HasENQCMD = false;
370 
371   /// Processor has AVX-512 Bit Algorithms instructions
372   bool HasBITALG = false;
373 
374   /// Processor has AVX-512 vp2intersect instructions
375   bool HasVP2INTERSECT = false;
376 
377   /// Processor supports CET SHSTK - Control-Flow Enforcement Technology
378   /// using Shadow Stack
379   bool HasSHSTK = false;
380 
381   /// Processor supports Invalidate Process-Context Identifier
382   bool HasINVPCID = false;
383 
384   /// Processor has Software Guard Extensions
385   bool HasSGX = false;
386 
387   /// Processor supports Flush Cache Line instruction
388   bool HasCLFLUSHOPT = false;
389 
390   /// Processor supports Cache Line Write Back instruction
391   bool HasCLWB = false;
392 
393   /// Processor supports Write Back No Invalidate instruction
394   bool HasWBNOINVD = false;
395 
396   /// Processor support RDPID instruction
397   bool HasRDPID = false;
398 
399   /// Processor supports WaitPKG instructions
400   bool HasWAITPKG = false;
401 
402   /// Processor supports PCONFIG instruction
403   bool HasPCONFIG = false;
404 
405   /// Processor support key locker instructions
406   bool HasKL = false;
407 
408   /// Processor support key locker wide instructions
409   bool HasWIDEKL = false;
410 
411   /// Processor supports HRESET instruction
412   bool HasHRESET = false;
413 
414   /// Processor supports SERIALIZE instruction
415   bool HasSERIALIZE = false;
416 
417   /// Processor supports TSXLDTRK instruction
418   bool HasTSXLDTRK = false;
419 
420   /// Processor has AMX support
421   bool HasAMXTILE = false;
422   bool HasAMXBF16 = false;
423   bool HasAMXINT8 = false;
424 
425   /// Processor supports User Level Interrupt instructions
426   bool HasUINTR = false;
427 
428   /// Processor has a single uop BEXTR implementation.
429   bool HasFastBEXTR = false;
430 
431   /// Try harder to combine to horizontal vector ops if they are fast.
432   bool HasFastHorizontalOps = false;
433 
434   /// Prefer a left/right scalar logical shifts pair over a shift+and pair.
435   bool HasFastScalarShiftMasks = false;
436 
437   /// Prefer a left/right vector logical shifts pair over a shift+and pair.
438   bool HasFastVectorShiftMasks = false;
439 
440   /// Prefer a movbe over a single-use load + bswap / single-use bswap + store.
441   bool HasFastMOVBE = false;
442 
443   /// Use a retpoline thunk rather than indirect calls to block speculative
444   /// execution.
445   bool UseRetpolineIndirectCalls = false;
446 
447   /// Use a retpoline thunk or remove any indirect branch to block speculative
448   /// execution.
449   bool UseRetpolineIndirectBranches = false;
450 
451   /// Deprecated flag, query `UseRetpolineIndirectCalls` and
452   /// `UseRetpolineIndirectBranches` instead.
453   bool DeprecatedUseRetpoline = false;
454 
455   /// When using a retpoline thunk, call an externally provided thunk rather
456   /// than emitting one inside the compiler.
457   bool UseRetpolineExternalThunk = false;
458 
459   /// Prevent generation of indirect call/branch instructions from memory,
460   /// and force all indirect call/branch instructions from a register to be
461   /// preceded by an LFENCE. Also decompose RET instructions into a
462   /// POP+LFENCE+JMP sequence.
463   bool UseLVIControlFlowIntegrity = false;
464 
465   /// Enable Speculative Execution Side Effect Suppression
466   bool UseSpeculativeExecutionSideEffectSuppression = false;
467 
468   /// Insert LFENCE instructions to prevent data speculatively injected into
469   /// loads from being used maliciously.
470   bool UseLVILoadHardening = false;
471 
472   /// Use software floating point for code generation.
473   bool UseSoftFloat = false;
474 
475   /// Use alias analysis during code generation.
476   bool UseAA = false;
477 
478   /// The minimum alignment known to hold of the stack frame on
479   /// entry to the function and which must be maintained by every function.
480   Align stackAlignment = Align(4);
481 
482   Align TileConfigAlignment = Align(4);
483 
484   /// Max. memset / memcpy size that is turned into rep/movs, rep/stos ops.
485   ///
486   // FIXME: this is a known good value for Yonah. How about others?
487   unsigned MaxInlineSizeThreshold = 128;
488 
489   /// Indicates target prefers 128 bit instructions.
490   bool Prefer128Bit = false;
491 
492   /// Indicates target prefers 256 bit instructions.
493   bool Prefer256Bit = false;
494 
495   /// Indicates target prefers AVX512 mask registers.
496   bool PreferMaskRegisters = false;
497 
498   /// Use Goldmont specific floating point div/sqrt costs.
499   bool UseGLMDivSqrtCosts = false;
500 
501   /// What processor and OS we're targeting.
502   Triple TargetTriple;
503 
504   /// GlobalISel related APIs.
505   std::unique_ptr<CallLowering> CallLoweringInfo;
506   std::unique_ptr<LegalizerInfo> Legalizer;
507   std::unique_ptr<RegisterBankInfo> RegBankInfo;
508   std::unique_ptr<InstructionSelector> InstSelector;
509 
510 private:
511   /// Override the stack alignment.
512   MaybeAlign StackAlignOverride;
513 
514   /// Preferred vector width from function attribute.
515   unsigned PreferVectorWidthOverride;
516 
517   /// Resolved preferred vector width from function attribute and subtarget
518   /// features.
519   unsigned PreferVectorWidth = UINT32_MAX;
520 
521   /// Required vector width from function attribute.
522   unsigned RequiredVectorWidth;
523 
524   /// True if compiling for 64-bit, false for 16-bit or 32-bit.
525   bool In64BitMode = false;
526 
527   /// True if compiling for 32-bit, false for 16-bit or 64-bit.
528   bool In32BitMode = false;
529 
530   /// True if compiling for 16-bit, false for 32-bit or 64-bit.
531   bool In16BitMode = false;
532 
533   X86SelectionDAGInfo TSInfo;
534   // Ordering here is important. X86InstrInfo initializes X86RegisterInfo which
535   // X86TargetLowering needs.
536   X86InstrInfo InstrInfo;
537   X86TargetLowering TLInfo;
538   X86FrameLowering FrameLowering;
539 
540 public:
541   /// This constructor initializes the data members to match that
542   /// of the specified triple.
543   ///
544   X86Subtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS,
545                const X86TargetMachine &TM, MaybeAlign StackAlignOverride,
546                unsigned PreferVectorWidthOverride,
547                unsigned RequiredVectorWidth);
548 
549   const X86TargetLowering *getTargetLowering() const override {
550     return &TLInfo;
551   }
552 
553   const X86InstrInfo *getInstrInfo() const override { return &InstrInfo; }
554 
555   const X86FrameLowering *getFrameLowering() const override {
556     return &FrameLowering;
557   }
558 
559   const X86SelectionDAGInfo *getSelectionDAGInfo() const override {
560     return &TSInfo;
561   }
562 
563   const X86RegisterInfo *getRegisterInfo() const override {
564     return &getInstrInfo()->getRegisterInfo();
565   }
566 
567   unsigned getTileConfigSize() const { return 64; }
568   Align getTileConfigAlignment() const { return TileConfigAlignment; }
569 
570   /// Returns the minimum alignment known to hold of the
571   /// stack frame on entry to the function and which must be maintained by every
572   /// function for this subtarget.
573   Align getStackAlignment() const { return stackAlignment; }
574 
575   /// Returns the maximum memset / memcpy size
576   /// that still makes it profitable to inline the call.
577   unsigned getMaxInlineSizeThreshold() const { return MaxInlineSizeThreshold; }
578 
579   /// ParseSubtargetFeatures - Parses features string setting specified
580   /// subtarget options.  Definition of function is auto generated by tblgen.
581   void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
582 
583   /// Methods used by Global ISel
584   const CallLowering *getCallLowering() const override;
585   InstructionSelector *getInstructionSelector() const override;
586   const LegalizerInfo *getLegalizerInfo() const override;
587   const RegisterBankInfo *getRegBankInfo() const override;
588 
589 private:
590   /// Initialize the full set of dependencies so we can use an initializer
591   /// list for X86Subtarget.
592   X86Subtarget &initializeSubtargetDependencies(StringRef CPU,
593                                                 StringRef TuneCPU,
594                                                 StringRef FS);
595   void initSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
596 
597 public:
598   /// Is this x86_64? (disregarding specific ABI / programming model)
599   bool is64Bit() const {
600     return In64BitMode;
601   }
602 
603   bool is32Bit() const {
604     return In32BitMode;
605   }
606 
607   bool is16Bit() const {
608     return In16BitMode;
609   }
610 
611   /// Is this x86_64 with the ILP32 programming model (x32 ABI)?
612   bool isTarget64BitILP32() const {
613     return In64BitMode && (TargetTriple.isX32() || TargetTriple.isOSNaCl());
614   }
615 
616   /// Is this x86_64 with the LP64 programming model (standard AMD64, no x32)?
617   bool isTarget64BitLP64() const {
618     return In64BitMode && (!TargetTriple.isX32() && !TargetTriple.isOSNaCl());
619   }
620 
621   PICStyles::Style getPICStyle() const { return PICStyle; }
622   void setPICStyle(PICStyles::Style Style)  { PICStyle = Style; }
623 
624   bool hasX87() const { return HasX87; }
625   bool hasCmpxchg8b() const { return HasCmpxchg8b; }
626   bool hasNOPL() const { return HasNOPL; }
627   // SSE codegen depends on cmovs, and all SSE1+ processors support them.
628   // All 64-bit processors support cmov.
629   bool hasCMov() const { return HasCMov || X86SSELevel >= SSE1 || is64Bit(); }
630   bool hasSSE1() const { return X86SSELevel >= SSE1; }
631   bool hasSSE2() const { return X86SSELevel >= SSE2; }
632   bool hasSSE3() const { return X86SSELevel >= SSE3; }
633   bool hasSSSE3() const { return X86SSELevel >= SSSE3; }
634   bool hasSSE41() const { return X86SSELevel >= SSE41; }
635   bool hasSSE42() const { return X86SSELevel >= SSE42; }
636   bool hasAVX() const { return X86SSELevel >= AVX; }
637   bool hasAVX2() const { return X86SSELevel >= AVX2; }
638   bool hasAVX512() const { return X86SSELevel >= AVX512F; }
639   bool hasInt256() const { return hasAVX2(); }
640   bool hasSSE4A() const { return HasSSE4A; }
641   bool hasMMX() const { return X863DNowLevel >= MMX; }
642   bool has3DNow() const { return X863DNowLevel >= ThreeDNow; }
643   bool has3DNowA() const { return X863DNowLevel >= ThreeDNowA; }
644   bool hasPOPCNT() const { return HasPOPCNT; }
645   bool hasAES() const { return HasAES; }
646   bool hasVAES() const { return HasVAES; }
647   bool hasFXSR() const { return HasFXSR; }
648   bool hasXSAVE() const { return HasXSAVE; }
649   bool hasXSAVEOPT() const { return HasXSAVEOPT; }
650   bool hasXSAVEC() const { return HasXSAVEC; }
651   bool hasXSAVES() const { return HasXSAVES; }
652   bool hasPCLMUL() const { return HasPCLMUL; }
653   bool hasVPCLMULQDQ() const { return HasVPCLMULQDQ; }
654   bool hasGFNI() const { return HasGFNI; }
655   // Prefer FMA4 to FMA - its better for commutation/memory folding and
656   // has equal or better performance on all supported targets.
657   bool hasFMA() const { return HasFMA; }
658   bool hasFMA4() const { return HasFMA4; }
659   bool hasAnyFMA() const { return hasFMA() || hasFMA4(); }
660   bool hasXOP() const { return HasXOP; }
661   bool hasTBM() const { return HasTBM; }
662   bool hasLWP() const { return HasLWP; }
663   bool hasMOVBE() const { return HasMOVBE; }
664   bool hasRDRAND() const { return HasRDRAND; }
665   bool hasF16C() const { return HasF16C; }
666   bool hasFSGSBase() const { return HasFSGSBase; }
667   bool hasLZCNT() const { return HasLZCNT; }
668   bool hasBMI() const { return HasBMI; }
669   bool hasBMI2() const { return HasBMI2; }
670   bool hasVBMI() const { return HasVBMI; }
671   bool hasVBMI2() const { return HasVBMI2; }
672   bool hasIFMA() const { return HasIFMA; }
673   bool hasRTM() const { return HasRTM; }
674   bool hasADX() const { return HasADX; }
675   bool hasSHA() const { return HasSHA; }
676   bool hasPRFCHW() const { return HasPRFCHW; }
677   bool hasPREFETCHWT1() const { return HasPREFETCHWT1; }
678   bool hasPrefetchW() const {
679     // The PREFETCHW instruction was added with 3DNow but later CPUs gave it
680     // its own CPUID bit as part of deprecating 3DNow. Intel eventually added
681     // it and KNL has another that prefetches to L2 cache. We assume the
682     // L1 version exists if the L2 version does.
683     return has3DNow() || hasPRFCHW() || hasPREFETCHWT1();
684   }
685   bool hasSSEPrefetch() const {
686     // We implicitly enable these when we have a write prefix supporting cache
687     // level OR if we have prfchw, but don't already have a read prefetch from
688     // 3dnow.
689     return hasSSE1() || (hasPRFCHW() && !has3DNow()) || hasPREFETCHWT1();
690   }
691   bool hasRDSEED() const { return HasRDSEED; }
692   bool hasLAHFSAHF() const { return HasLAHFSAHF64 || !is64Bit(); }
693   bool hasMWAITX() const { return HasMWAITX; }
694   bool hasCLZERO() const { return HasCLZERO; }
695   bool hasCLDEMOTE() const { return HasCLDEMOTE; }
696   bool hasMOVDIRI() const { return HasMOVDIRI; }
697   bool hasMOVDIR64B() const { return HasMOVDIR64B; }
698   bool hasPTWRITE() const { return HasPTWRITE; }
699   bool isSHLDSlow() const { return IsSHLDSlow; }
700   bool isPMULLDSlow() const { return IsPMULLDSlow; }
701   bool isPMADDWDSlow() const { return IsPMADDWDSlow; }
702   bool isUnalignedMem16Slow() const { return IsUAMem16Slow; }
703   bool isUnalignedMem32Slow() const { return IsUAMem32Slow; }
704   bool hasSSEUnalignedMem() const { return HasSSEUnalignedMem; }
705   bool hasCmpxchg16b() const { return HasCmpxchg16b && is64Bit(); }
706   bool useLeaForSP() const { return UseLeaForSP; }
707   bool hasPOPCNTFalseDeps() const { return HasPOPCNTFalseDeps; }
708   bool hasLZCNTFalseDeps() const { return HasLZCNTFalseDeps; }
709   bool hasFastVariableCrossLaneShuffle() const {
710     return HasFastVariableCrossLaneShuffle;
711   }
712   bool hasFastVariablePerLaneShuffle() const {
713     return HasFastVariablePerLaneShuffle;
714   }
715   bool insertVZEROUPPER() const { return InsertVZEROUPPER; }
716   bool hasFastGather() const { return HasFastGather; }
717   bool hasFastScalarFSQRT() const { return HasFastScalarFSQRT; }
718   bool hasFastVectorFSQRT() const { return HasFastVectorFSQRT; }
719   bool hasFastLZCNT() const { return HasFastLZCNT; }
720   bool hasFastSHLDRotate() const { return HasFastSHLDRotate; }
721   bool hasFastBEXTR() const { return HasFastBEXTR; }
722   bool hasFastHorizontalOps() const { return HasFastHorizontalOps; }
723   bool hasFastScalarShiftMasks() const { return HasFastScalarShiftMasks; }
724   bool hasFastVectorShiftMasks() const { return HasFastVectorShiftMasks; }
725   bool hasFastMOVBE() const { return HasFastMOVBE; }
726   bool hasMacroFusion() const { return HasMacroFusion; }
727   bool hasBranchFusion() const { return HasBranchFusion; }
728   bool hasERMSB() const { return HasERMSB; }
729   bool hasFSRM() const { return HasFSRM; }
730   bool hasSlowDivide32() const { return HasSlowDivide32; }
731   bool hasSlowDivide64() const { return HasSlowDivide64; }
732   bool padShortFunctions() const { return PadShortFunctions; }
733   bool slowTwoMemOps() const { return SlowTwoMemOps; }
734   bool LEAusesAG() const { return LEAUsesAG; }
735   bool slowLEA() const { return SlowLEA; }
736   bool slow3OpsLEA() const { return Slow3OpsLEA; }
737   bool slowIncDec() const { return SlowIncDec; }
738   bool hasCDI() const { return HasCDI; }
739   bool hasVPOPCNTDQ() const { return HasVPOPCNTDQ; }
740   bool hasPFI() const { return HasPFI; }
741   bool hasERI() const { return HasERI; }
742   bool hasDQI() const { return HasDQI; }
743   bool hasBWI() const { return HasBWI; }
744   bool hasVLX() const { return HasVLX; }
745   bool hasPKU() const { return HasPKU; }
746   bool hasVNNI() const { return HasVNNI; }
747   bool hasBF16() const { return HasBF16; }
748   bool hasVP2INTERSECT() const { return HasVP2INTERSECT; }
749   bool hasBITALG() const { return HasBITALG; }
750   bool hasSHSTK() const { return HasSHSTK; }
751   bool hasCLFLUSHOPT() const { return HasCLFLUSHOPT; }
752   bool hasCLWB() const { return HasCLWB; }
753   bool hasWBNOINVD() const { return HasWBNOINVD; }
754   bool hasRDPID() const { return HasRDPID; }
755   bool hasWAITPKG() const { return HasWAITPKG; }
756   bool hasPCONFIG() const { return HasPCONFIG; }
757   bool hasSGX() const { return HasSGX; }
758   bool hasINVPCID() const { return HasINVPCID; }
759   bool hasENQCMD() const { return HasENQCMD; }
760   bool hasKL() const { return HasKL; }
761   bool hasWIDEKL() const { return HasWIDEKL; }
762   bool hasHRESET() const { return HasHRESET; }
763   bool hasSERIALIZE() const { return HasSERIALIZE; }
764   bool hasTSXLDTRK() const { return HasTSXLDTRK; }
765   bool hasUINTR() const { return HasUINTR; }
766   bool useRetpolineIndirectCalls() const { return UseRetpolineIndirectCalls; }
767   bool useRetpolineIndirectBranches() const {
768     return UseRetpolineIndirectBranches;
769   }
770   bool hasAVXVNNI() const { return HasAVXVNNI; }
771   bool hasAMXTILE() const { return HasAMXTILE; }
772   bool hasAMXBF16() const { return HasAMXBF16; }
773   bool hasAMXINT8() const { return HasAMXINT8; }
774   bool useRetpolineExternalThunk() const { return UseRetpolineExternalThunk; }
775 
776   // These are generic getters that OR together all of the thunk types
777   // supported by the subtarget. Therefore useIndirectThunk*() will return true
778   // if any respective thunk feature is enabled.
779   bool useIndirectThunkCalls() const {
780     return useRetpolineIndirectCalls() || useLVIControlFlowIntegrity();
781   }
782   bool useIndirectThunkBranches() const {
783     return useRetpolineIndirectBranches() || useLVIControlFlowIntegrity();
784   }
785 
786   bool preferMaskRegisters() const { return PreferMaskRegisters; }
787   bool useGLMDivSqrtCosts() const { return UseGLMDivSqrtCosts; }
788   bool useLVIControlFlowIntegrity() const { return UseLVIControlFlowIntegrity; }
789   bool useLVILoadHardening() const { return UseLVILoadHardening; }
790   bool useSpeculativeExecutionSideEffectSuppression() const {
791     return UseSpeculativeExecutionSideEffectSuppression;
792   }
793 
794   unsigned getPreferVectorWidth() const { return PreferVectorWidth; }
795   unsigned getRequiredVectorWidth() const { return RequiredVectorWidth; }
796 
797   // Helper functions to determine when we should allow widening to 512-bit
798   // during codegen.
799   // TODO: Currently we're always allowing widening on CPUs without VLX,
800   // because for many cases we don't have a better option.
801   bool canExtendTo512DQ() const {
802     return hasAVX512() && (!hasVLX() || getPreferVectorWidth() >= 512);
803   }
804   bool canExtendTo512BW() const  {
805     return hasBWI() && canExtendTo512DQ();
806   }
807 
808   // If there are no 512-bit vectors and we prefer not to use 512-bit registers,
809   // disable them in the legalizer.
810   bool useAVX512Regs() const {
811     return hasAVX512() && (canExtendTo512DQ() || RequiredVectorWidth > 256);
812   }
813 
814   bool useBWIRegs() const {
815     return hasBWI() && useAVX512Regs();
816   }
817 
818   bool isXRaySupported() const override { return is64Bit(); }
819 
820   /// TODO: to be removed later and replaced with suitable properties
821   bool isAtom() const { return X86ProcFamily == IntelAtom; }
822   bool isSLM() const { return X86ProcFamily == IntelSLM; }
823   bool useSoftFloat() const { return UseSoftFloat; }
824   bool useAA() const override { return UseAA; }
825 
826   /// Use mfence if we have SSE2 or we're on x86-64 (even if we asked for
827   /// no-sse2). There isn't any reason to disable it if the target processor
828   /// supports it.
829   bool hasMFence() const { return hasSSE2() || is64Bit(); }
830 
831   const Triple &getTargetTriple() const { return TargetTriple; }
832 
833   bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); }
834   bool isTargetFreeBSD() const { return TargetTriple.isOSFreeBSD(); }
835   bool isTargetDragonFly() const { return TargetTriple.isOSDragonFly(); }
836   bool isTargetSolaris() const { return TargetTriple.isOSSolaris(); }
837   bool isTargetPS4() const { return TargetTriple.isPS4CPU(); }
838 
839   bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
840   bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); }
841   bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); }
842 
843   bool isTargetLinux() const { return TargetTriple.isOSLinux(); }
844   bool isTargetKFreeBSD() const { return TargetTriple.isOSKFreeBSD(); }
845   bool isTargetGlibc() const { return TargetTriple.isOSGlibc(); }
846   bool isTargetAndroid() const { return TargetTriple.isAndroid(); }
847   bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
848   bool isTargetNaCl32() const { return isTargetNaCl() && !is64Bit(); }
849   bool isTargetNaCl64() const { return isTargetNaCl() && is64Bit(); }
850   bool isTargetMCU() const { return TargetTriple.isOSIAMCU(); }
851   bool isTargetFuchsia() const { return TargetTriple.isOSFuchsia(); }
852 
853   bool isTargetWindowsMSVC() const {
854     return TargetTriple.isWindowsMSVCEnvironment();
855   }
856 
857   bool isTargetWindowsCoreCLR() const {
858     return TargetTriple.isWindowsCoreCLREnvironment();
859   }
860 
861   bool isTargetWindowsCygwin() const {
862     return TargetTriple.isWindowsCygwinEnvironment();
863   }
864 
865   bool isTargetWindowsGNU() const {
866     return TargetTriple.isWindowsGNUEnvironment();
867   }
868 
869   bool isTargetWindowsItanium() const {
870     return TargetTriple.isWindowsItaniumEnvironment();
871   }
872 
873   bool isTargetCygMing() const { return TargetTriple.isOSCygMing(); }
874 
875   bool isOSWindows() const { return TargetTriple.isOSWindows(); }
876 
877   bool isTargetWin64() const { return In64BitMode && isOSWindows(); }
878 
879   bool isTargetWin32() const { return !In64BitMode && isOSWindows(); }
880 
881   bool isPICStyleGOT() const { return PICStyle == PICStyles::Style::GOT; }
882   bool isPICStyleRIPRel() const { return PICStyle == PICStyles::Style::RIPRel; }
883 
884   bool isPICStyleStubPIC() const {
885     return PICStyle == PICStyles::Style::StubPIC;
886   }
887 
888   bool isPositionIndependent() const;
889 
890   bool isCallingConvWin64(CallingConv::ID CC) const {
891     switch (CC) {
892     // On Win64, all these conventions just use the default convention.
893     case CallingConv::C:
894     case CallingConv::Fast:
895     case CallingConv::Tail:
896     case CallingConv::Swift:
897     case CallingConv::SwiftTail:
898     case CallingConv::X86_FastCall:
899     case CallingConv::X86_StdCall:
900     case CallingConv::X86_ThisCall:
901     case CallingConv::X86_VectorCall:
902     case CallingConv::Intel_OCL_BI:
903       return isTargetWin64();
904     // This convention allows using the Win64 convention on other targets.
905     case CallingConv::Win64:
906       return true;
907     // This convention allows using the SysV convention on Windows targets.
908     case CallingConv::X86_64_SysV:
909       return false;
910     // Otherwise, who knows what this is.
911     default:
912       return false;
913     }
914   }
915 
916   /// Classify a global variable reference for the current subtarget according
917   /// to how we should reference it in a non-pcrel context.
918   unsigned char classifyLocalReference(const GlobalValue *GV) const;
919 
920   unsigned char classifyGlobalReference(const GlobalValue *GV,
921                                         const Module &M) const;
922   unsigned char classifyGlobalReference(const GlobalValue *GV) const;
923 
924   /// Classify a global function reference for the current subtarget.
925   unsigned char classifyGlobalFunctionReference(const GlobalValue *GV,
926                                                 const Module &M) const;
927   unsigned char classifyGlobalFunctionReference(const GlobalValue *GV) const;
928 
929   /// Classify a blockaddress reference for the current subtarget according to
930   /// how we should reference it in a non-pcrel context.
931   unsigned char classifyBlockAddressReference() const;
932 
933   /// Return true if the subtarget allows calls to immediate address.
934   bool isLegalToCallImmediateAddr() const;
935 
936   /// If we are using indirect thunks, we need to expand indirectbr to avoid it
937   /// lowering to an actual indirect jump.
938   bool enableIndirectBrExpand() const override {
939     return useIndirectThunkBranches();
940   }
941 
942   /// Enable the MachineScheduler pass for all X86 subtargets.
943   bool enableMachineScheduler() const override { return true; }
944 
945   bool enableEarlyIfConversion() const override;
946 
947   void getPostRAMutations(std::vector<std::unique_ptr<ScheduleDAGMutation>>
948                               &Mutations) const override;
949 
950   AntiDepBreakMode getAntiDepBreakMode() const override {
951     return TargetSubtargetInfo::ANTIDEP_CRITICAL;
952   }
953 
954   bool enableAdvancedRASplitCost() const override { return false; }
955 };
956 
957 } // end namespace llvm
958 
959 #endif // LLVM_LIB_TARGET_X86_X86SUBTARGET_H
960