1 //===-- X86Subtarget.h - Define Subtarget for the X86 ----------*- C++ -*--===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file declares the X86 specific subclass of TargetSubtargetInfo. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_X86_X86SUBTARGET_H 14 #define LLVM_LIB_TARGET_X86_X86SUBTARGET_H 15 16 #include "X86FrameLowering.h" 17 #include "X86ISelLowering.h" 18 #include "X86InstrInfo.h" 19 #include "X86SelectionDAGInfo.h" 20 #include "llvm/ADT/Triple.h" 21 #include "llvm/CodeGen/TargetSubtargetInfo.h" 22 #include "llvm/IR/CallingConv.h" 23 #include <climits> 24 #include <memory> 25 26 #define GET_SUBTARGETINFO_HEADER 27 #include "X86GenSubtargetInfo.inc" 28 29 namespace llvm { 30 31 class CallLowering; 32 class GlobalValue; 33 class InstructionSelector; 34 class LegalizerInfo; 35 class RegisterBankInfo; 36 class StringRef; 37 class TargetMachine; 38 39 /// The X86 backend supports a number of different styles of PIC. 40 /// 41 namespace PICStyles { 42 43 enum class Style { 44 StubPIC, // Used on i386-darwin in pic mode. 45 GOT, // Used on 32 bit elf on when in pic mode. 46 RIPRel, // Used on X86-64 when in pic mode. 47 None // Set when not in pic mode. 48 }; 49 50 } // end namespace PICStyles 51 52 class X86Subtarget final : public X86GenSubtargetInfo { 53 enum X86SSEEnum { 54 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512 55 }; 56 57 enum X863DNowEnum { 58 NoThreeDNow, MMX, ThreeDNow, ThreeDNowA 59 }; 60 61 /// Which PIC style to use 62 PICStyles::Style PICStyle; 63 64 const TargetMachine &TM; 65 66 /// SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or none supported. 67 X86SSEEnum X86SSELevel = NoSSE; 68 69 /// MMX, 3DNow, 3DNow Athlon, or none supported. 70 X863DNowEnum X863DNowLevel = NoThreeDNow; 71 72 #define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \ 73 bool ATTRIBUTE = DEFAULT; 74 #include "X86GenSubtargetInfo.inc" 75 /// The minimum alignment known to hold of the stack frame on 76 /// entry to the function and which must be maintained by every function. 77 Align stackAlignment = Align(4); 78 79 Align TileConfigAlignment = Align(4); 80 81 /// Max. memset / memcpy size that is turned into rep/movs, rep/stos ops. 82 /// 83 // FIXME: this is a known good value for Yonah. How about others? 84 unsigned MaxInlineSizeThreshold = 128; 85 86 /// What processor and OS we're targeting. 87 Triple TargetTriple; 88 89 /// GlobalISel related APIs. 90 std::unique_ptr<CallLowering> CallLoweringInfo; 91 std::unique_ptr<LegalizerInfo> Legalizer; 92 std::unique_ptr<RegisterBankInfo> RegBankInfo; 93 std::unique_ptr<InstructionSelector> InstSelector; 94 95 /// Override the stack alignment. 96 MaybeAlign StackAlignOverride; 97 98 /// Preferred vector width from function attribute. 99 unsigned PreferVectorWidthOverride; 100 101 /// Resolved preferred vector width from function attribute and subtarget 102 /// features. 103 unsigned PreferVectorWidth = UINT32_MAX; 104 105 /// Required vector width from function attribute. 106 unsigned RequiredVectorWidth; 107 108 X86SelectionDAGInfo TSInfo; 109 // Ordering here is important. X86InstrInfo initializes X86RegisterInfo which 110 // X86TargetLowering needs. 111 X86InstrInfo InstrInfo; 112 X86TargetLowering TLInfo; 113 X86FrameLowering FrameLowering; 114 115 public: 116 /// This constructor initializes the data members to match that 117 /// of the specified triple. 118 /// 119 X86Subtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS, 120 const X86TargetMachine &TM, MaybeAlign StackAlignOverride, 121 unsigned PreferVectorWidthOverride, 122 unsigned RequiredVectorWidth); 123 124 const X86TargetLowering *getTargetLowering() const override { 125 return &TLInfo; 126 } 127 128 const X86InstrInfo *getInstrInfo() const override { return &InstrInfo; } 129 130 const X86FrameLowering *getFrameLowering() const override { 131 return &FrameLowering; 132 } 133 134 const X86SelectionDAGInfo *getSelectionDAGInfo() const override { 135 return &TSInfo; 136 } 137 138 const X86RegisterInfo *getRegisterInfo() const override { 139 return &getInstrInfo()->getRegisterInfo(); 140 } 141 142 unsigned getTileConfigSize() const { return 64; } 143 Align getTileConfigAlignment() const { return TileConfigAlignment; } 144 145 /// Returns the minimum alignment known to hold of the 146 /// stack frame on entry to the function and which must be maintained by every 147 /// function for this subtarget. 148 Align getStackAlignment() const { return stackAlignment; } 149 150 /// Returns the maximum memset / memcpy size 151 /// that still makes it profitable to inline the call. 152 unsigned getMaxInlineSizeThreshold() const { return MaxInlineSizeThreshold; } 153 154 /// ParseSubtargetFeatures - Parses features string setting specified 155 /// subtarget options. Definition of function is auto generated by tblgen. 156 void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS); 157 158 /// Methods used by Global ISel 159 const CallLowering *getCallLowering() const override; 160 InstructionSelector *getInstructionSelector() const override; 161 const LegalizerInfo *getLegalizerInfo() const override; 162 const RegisterBankInfo *getRegBankInfo() const override; 163 164 private: 165 /// Initialize the full set of dependencies so we can use an initializer 166 /// list for X86Subtarget. 167 X86Subtarget &initializeSubtargetDependencies(StringRef CPU, 168 StringRef TuneCPU, 169 StringRef FS); 170 void initSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS); 171 172 public: 173 174 #define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \ 175 bool GETTER() const { return ATTRIBUTE; } 176 #include "X86GenSubtargetInfo.inc" 177 178 /// Is this x86_64 with the ILP32 programming model (x32 ABI)? 179 bool isTarget64BitILP32() const { 180 return Is64Bit && (TargetTriple.isX32() || TargetTriple.isOSNaCl()); 181 } 182 183 /// Is this x86_64 with the LP64 programming model (standard AMD64, no x32)? 184 bool isTarget64BitLP64() const { 185 return Is64Bit && (!TargetTriple.isX32() && !TargetTriple.isOSNaCl()); 186 } 187 188 PICStyles::Style getPICStyle() const { return PICStyle; } 189 void setPICStyle(PICStyles::Style Style) { PICStyle = Style; } 190 191 bool canUseCMPXCHG8B() const { return hasCX8(); } 192 bool canUseCMPXCHG16B() const { 193 // CX16 is just the CPUID bit, instruction requires 64-bit mode too. 194 return hasCX16() && is64Bit(); 195 } 196 // SSE codegen depends on cmovs, and all SSE1+ processors support them. 197 // All 64-bit processors support cmov. 198 bool canUseCMOV() const { return hasCMOV() || hasSSE1() || is64Bit(); } 199 bool hasSSE1() const { return X86SSELevel >= SSE1; } 200 bool hasSSE2() const { return X86SSELevel >= SSE2; } 201 bool hasSSE3() const { return X86SSELevel >= SSE3; } 202 bool hasSSSE3() const { return X86SSELevel >= SSSE3; } 203 bool hasSSE41() const { return X86SSELevel >= SSE41; } 204 bool hasSSE42() const { return X86SSELevel >= SSE42; } 205 bool hasAVX() const { return X86SSELevel >= AVX; } 206 bool hasAVX2() const { return X86SSELevel >= AVX2; } 207 bool hasAVX512() const { return X86SSELevel >= AVX512; } 208 bool hasInt256() const { return hasAVX2(); } 209 bool hasMMX() const { return X863DNowLevel >= MMX; } 210 bool hasThreeDNow() const { return X863DNowLevel >= ThreeDNow; } 211 bool hasThreeDNowA() const { return X863DNowLevel >= ThreeDNowA; } 212 bool hasAnyFMA() const { return hasFMA() || hasFMA4(); } 213 bool hasPrefetchW() const { 214 // The PREFETCHW instruction was added with 3DNow but later CPUs gave it 215 // its own CPUID bit as part of deprecating 3DNow. Intel eventually added 216 // it and KNL has another that prefetches to L2 cache. We assume the 217 // L1 version exists if the L2 version does. 218 return hasThreeDNow() || hasPRFCHW() || hasPREFETCHWT1(); 219 } 220 bool hasSSEPrefetch() const { 221 // We implicitly enable these when we have a write prefix supporting cache 222 // level OR if we have prfchw, but don't already have a read prefetch from 223 // 3dnow. 224 return hasSSE1() || (hasPRFCHW() && !hasThreeDNow()) || hasPREFETCHWT1(); 225 } 226 bool canUseLAHFSAHF() const { return hasLAHFSAHF64() || !is64Bit(); } 227 // These are generic getters that OR together all of the thunk types 228 // supported by the subtarget. Therefore useIndirectThunk*() will return true 229 // if any respective thunk feature is enabled. 230 bool useIndirectThunkCalls() const { 231 return useRetpolineIndirectCalls() || useLVIControlFlowIntegrity(); 232 } 233 bool useIndirectThunkBranches() const { 234 return useRetpolineIndirectBranches() || useLVIControlFlowIntegrity(); 235 } 236 237 unsigned getPreferVectorWidth() const { return PreferVectorWidth; } 238 unsigned getRequiredVectorWidth() const { return RequiredVectorWidth; } 239 240 // Helper functions to determine when we should allow widening to 512-bit 241 // during codegen. 242 // TODO: Currently we're always allowing widening on CPUs without VLX, 243 // because for many cases we don't have a better option. 244 bool canExtendTo512DQ() const { 245 return hasAVX512() && (!hasVLX() || getPreferVectorWidth() >= 512); 246 } 247 bool canExtendTo512BW() const { 248 return hasBWI() && canExtendTo512DQ(); 249 } 250 251 // If there are no 512-bit vectors and we prefer not to use 512-bit registers, 252 // disable them in the legalizer. 253 bool useAVX512Regs() const { 254 return hasAVX512() && (canExtendTo512DQ() || RequiredVectorWidth > 256); 255 } 256 257 bool useBWIRegs() const { 258 return hasBWI() && useAVX512Regs(); 259 } 260 261 bool isXRaySupported() const override { return is64Bit(); } 262 263 /// Use mfence if we have SSE2 or we're on x86-64 (even if we asked for 264 /// no-sse2). There isn't any reason to disable it if the target processor 265 /// supports it. 266 bool hasMFence() const { return hasSSE2() || is64Bit(); } 267 268 const Triple &getTargetTriple() const { return TargetTriple; } 269 270 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); } 271 bool isTargetFreeBSD() const { return TargetTriple.isOSFreeBSD(); } 272 bool isTargetDragonFly() const { return TargetTriple.isOSDragonFly(); } 273 bool isTargetSolaris() const { return TargetTriple.isOSSolaris(); } 274 bool isTargetPS() const { return TargetTriple.isPS(); } 275 276 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); } 277 bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); } 278 bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); } 279 280 bool isTargetLinux() const { return TargetTriple.isOSLinux(); } 281 bool isTargetKFreeBSD() const { return TargetTriple.isOSKFreeBSD(); } 282 bool isTargetGlibc() const { return TargetTriple.isOSGlibc(); } 283 bool isTargetAndroid() const { return TargetTriple.isAndroid(); } 284 bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); } 285 bool isTargetNaCl32() const { return isTargetNaCl() && !is64Bit(); } 286 bool isTargetNaCl64() const { return isTargetNaCl() && is64Bit(); } 287 bool isTargetMCU() const { return TargetTriple.isOSIAMCU(); } 288 bool isTargetFuchsia() const { return TargetTriple.isOSFuchsia(); } 289 290 bool isTargetWindowsMSVC() const { 291 return TargetTriple.isWindowsMSVCEnvironment(); 292 } 293 294 bool isTargetWindowsCoreCLR() const { 295 return TargetTriple.isWindowsCoreCLREnvironment(); 296 } 297 298 bool isTargetWindowsCygwin() const { 299 return TargetTriple.isWindowsCygwinEnvironment(); 300 } 301 302 bool isTargetWindowsGNU() const { 303 return TargetTriple.isWindowsGNUEnvironment(); 304 } 305 306 bool isTargetWindowsItanium() const { 307 return TargetTriple.isWindowsItaniumEnvironment(); 308 } 309 310 bool isTargetCygMing() const { return TargetTriple.isOSCygMing(); } 311 312 bool isOSWindows() const { return TargetTriple.isOSWindows(); } 313 314 bool isTargetWin64() const { return Is64Bit && isOSWindows(); } 315 316 bool isTargetWin32() const { return !Is64Bit && isOSWindows(); } 317 318 bool isPICStyleGOT() const { return PICStyle == PICStyles::Style::GOT; } 319 bool isPICStyleRIPRel() const { return PICStyle == PICStyles::Style::RIPRel; } 320 321 bool isPICStyleStubPIC() const { 322 return PICStyle == PICStyles::Style::StubPIC; 323 } 324 325 bool isPositionIndependent() const; 326 327 bool isCallingConvWin64(CallingConv::ID CC) const { 328 switch (CC) { 329 // On Win64, all these conventions just use the default convention. 330 case CallingConv::C: 331 case CallingConv::Fast: 332 case CallingConv::Tail: 333 case CallingConv::Swift: 334 case CallingConv::SwiftTail: 335 case CallingConv::X86_FastCall: 336 case CallingConv::X86_StdCall: 337 case CallingConv::X86_ThisCall: 338 case CallingConv::X86_VectorCall: 339 case CallingConv::Intel_OCL_BI: 340 return isTargetWin64(); 341 // This convention allows using the Win64 convention on other targets. 342 case CallingConv::Win64: 343 return true; 344 // This convention allows using the SysV convention on Windows targets. 345 case CallingConv::X86_64_SysV: 346 return false; 347 // Otherwise, who knows what this is. 348 default: 349 return false; 350 } 351 } 352 353 /// Classify a global variable reference for the current subtarget according 354 /// to how we should reference it in a non-pcrel context. 355 unsigned char classifyLocalReference(const GlobalValue *GV) const; 356 357 unsigned char classifyGlobalReference(const GlobalValue *GV, 358 const Module &M) const; 359 unsigned char classifyGlobalReference(const GlobalValue *GV) const; 360 361 /// Classify a global function reference for the current subtarget. 362 unsigned char classifyGlobalFunctionReference(const GlobalValue *GV, 363 const Module &M) const; 364 unsigned char classifyGlobalFunctionReference(const GlobalValue *GV) const; 365 366 /// Classify a blockaddress reference for the current subtarget according to 367 /// how we should reference it in a non-pcrel context. 368 unsigned char classifyBlockAddressReference() const; 369 370 /// Return true if the subtarget allows calls to immediate address. 371 bool isLegalToCallImmediateAddr() const; 372 373 /// Return whether FrameLowering should always set the "extended frame 374 /// present" bit in FP, or set it based on a symbol in the runtime. 375 bool swiftAsyncContextIsDynamicallySet() const { 376 // Older OS versions (particularly system unwinders) are confused by the 377 // Swift extended frame, so when building code that might be run on them we 378 // must dynamically query the concurrency library to determine whether 379 // extended frames should be flagged as present. 380 const Triple &TT = getTargetTriple(); 381 382 unsigned Major = TT.getOSVersion().getMajor(); 383 switch(TT.getOS()) { 384 default: 385 return false; 386 case Triple::IOS: 387 case Triple::TvOS: 388 return Major < 15; 389 case Triple::WatchOS: 390 return Major < 8; 391 case Triple::MacOSX: 392 case Triple::Darwin: 393 return Major < 12; 394 } 395 } 396 397 /// If we are using indirect thunks, we need to expand indirectbr to avoid it 398 /// lowering to an actual indirect jump. 399 bool enableIndirectBrExpand() const override { 400 return useIndirectThunkBranches(); 401 } 402 403 /// Enable the MachineScheduler pass for all X86 subtargets. 404 bool enableMachineScheduler() const override { return true; } 405 406 bool enableEarlyIfConversion() const override; 407 408 void getPostRAMutations(std::vector<std::unique_ptr<ScheduleDAGMutation>> 409 &Mutations) const override; 410 411 AntiDepBreakMode getAntiDepBreakMode() const override { 412 return TargetSubtargetInfo::ANTIDEP_CRITICAL; 413 } 414 }; 415 416 } // end namespace llvm 417 418 #endif // LLVM_LIB_TARGET_X86_X86SUBTARGET_H 419