1 //===-- X86Subtarget.h - Define Subtarget for the X86 ----------*- C++ -*--===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file declares the X86 specific subclass of TargetSubtargetInfo. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #ifndef LLVM_LIB_TARGET_X86_X86SUBTARGET_H 14 #define LLVM_LIB_TARGET_X86_X86SUBTARGET_H 15 16 #include "X86FrameLowering.h" 17 #include "X86ISelLowering.h" 18 #include "X86InstrInfo.h" 19 #include "X86SelectionDAGInfo.h" 20 #include "llvm/ADT/Triple.h" 21 #include "llvm/CodeGen/TargetSubtargetInfo.h" 22 #include "llvm/IR/CallingConv.h" 23 #include <climits> 24 #include <memory> 25 26 #define GET_SUBTARGETINFO_HEADER 27 #include "X86GenSubtargetInfo.inc" 28 29 namespace llvm { 30 31 class CallLowering; 32 class GlobalValue; 33 class InstructionSelector; 34 class LegalizerInfo; 35 class RegisterBankInfo; 36 class StringRef; 37 class TargetMachine; 38 39 /// The X86 backend supports a number of different styles of PIC. 40 /// 41 namespace PICStyles { 42 43 enum class Style { 44 StubPIC, // Used on i386-darwin in pic mode. 45 GOT, // Used on 32 bit elf on when in pic mode. 46 RIPRel, // Used on X86-64 when in pic mode. 47 None // Set when not in pic mode. 48 }; 49 50 } // end namespace PICStyles 51 52 class X86Subtarget final : public X86GenSubtargetInfo { 53 // NOTE: Do not add anything new to this list. Coarse, CPU name based flags 54 // are not a good idea. We should be migrating away from these. 55 enum X86ProcFamilyEnum { 56 Others, 57 IntelAtom 58 }; 59 60 enum X86SSEEnum { 61 NoSSE, SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, AVX, AVX2, AVX512F 62 }; 63 64 enum X863DNowEnum { 65 NoThreeDNow, MMX, ThreeDNow, ThreeDNowA 66 }; 67 68 /// X86 processor family: Intel Atom, and others 69 X86ProcFamilyEnum X86ProcFamily = Others; 70 71 /// Which PIC style to use 72 PICStyles::Style PICStyle; 73 74 const TargetMachine &TM; 75 76 /// SSE1, SSE2, SSE3, SSSE3, SSE41, SSE42, or none supported. 77 X86SSEEnum X86SSELevel = NoSSE; 78 79 /// MMX, 3DNow, 3DNow Athlon, or none supported. 80 X863DNowEnum X863DNowLevel = NoThreeDNow; 81 82 /// True if the processor supports X87 instructions. 83 bool HasX87 = false; 84 85 /// True if the processor supports CMPXCHG8B. 86 bool HasCmpxchg8b = false; 87 88 /// True if this processor has NOPL instruction 89 /// (generally pentium pro+). 90 bool HasNOPL = false; 91 92 /// True if this processor has conditional move instructions 93 /// (generally pentium pro+). 94 bool HasCMov = false; 95 96 /// True if the processor supports X86-64 instructions. 97 bool HasX86_64 = false; 98 99 /// True if the processor supports POPCNT. 100 bool HasPOPCNT = false; 101 102 /// True if the processor supports SSE4A instructions. 103 bool HasSSE4A = false; 104 105 /// Target has AES instructions 106 bool HasAES = false; 107 bool HasVAES = false; 108 109 /// Target has FXSAVE/FXRESTOR instructions 110 bool HasFXSR = false; 111 112 /// Target has XSAVE instructions 113 bool HasXSAVE = false; 114 115 /// Target has XSAVEOPT instructions 116 bool HasXSAVEOPT = false; 117 118 /// Target has XSAVEC instructions 119 bool HasXSAVEC = false; 120 121 /// Target has XSAVES instructions 122 bool HasXSAVES = false; 123 124 /// Target has carry-less multiplication 125 bool HasPCLMUL = false; 126 bool HasVPCLMULQDQ = false; 127 128 /// Target has Galois Field Arithmetic instructions 129 bool HasGFNI = false; 130 131 /// Target has 3-operand fused multiply-add 132 bool HasFMA = false; 133 134 /// Target has 4-operand fused multiply-add 135 bool HasFMA4 = false; 136 137 /// Target has XOP instructions 138 bool HasXOP = false; 139 140 /// Target has TBM instructions. 141 bool HasTBM = false; 142 143 /// Target has LWP instructions 144 bool HasLWP = false; 145 146 /// True if the processor has the MOVBE instruction. 147 bool HasMOVBE = false; 148 149 /// True if the processor has the RDRAND instruction. 150 bool HasRDRAND = false; 151 152 /// Processor has 16-bit floating point conversion instructions. 153 bool HasF16C = false; 154 155 /// Processor has FS/GS base insturctions. 156 bool HasFSGSBase = false; 157 158 /// Processor has LZCNT instruction. 159 bool HasLZCNT = false; 160 161 /// Processor has BMI1 instructions. 162 bool HasBMI = false; 163 164 /// Processor has BMI2 instructions. 165 bool HasBMI2 = false; 166 167 /// Processor has VBMI instructions. 168 bool HasVBMI = false; 169 170 /// Processor has VBMI2 instructions. 171 bool HasVBMI2 = false; 172 173 /// Processor has Integer Fused Multiply Add 174 bool HasIFMA = false; 175 176 /// Processor has RTM instructions. 177 bool HasRTM = false; 178 179 /// Processor has ADX instructions. 180 bool HasADX = false; 181 182 /// Processor has SHA instructions. 183 bool HasSHA = false; 184 185 /// Processor has PRFCHW instructions. 186 bool HasPRFCHW = false; 187 188 /// Processor has RDSEED instructions. 189 bool HasRDSEED = false; 190 191 /// Processor has LAHF/SAHF instructions in 64-bit mode. 192 bool HasLAHFSAHF64 = false; 193 194 /// Processor has MONITORX/MWAITX instructions. 195 bool HasMWAITX = false; 196 197 /// Processor has Cache Line Zero instruction 198 bool HasCLZERO = false; 199 200 /// Processor has Cache Line Demote instruction 201 bool HasCLDEMOTE = false; 202 203 /// Processor has MOVDIRI instruction (direct store integer). 204 bool HasMOVDIRI = false; 205 206 /// Processor has MOVDIR64B instruction (direct store 64 bytes). 207 bool HasMOVDIR64B = false; 208 209 /// Processor has ptwrite instruction. 210 bool HasPTWRITE = false; 211 212 /// Processor has Prefetch with intent to Write instruction 213 bool HasPREFETCHWT1 = false; 214 215 /// True if SHLD instructions are slow. 216 bool IsSHLDSlow = false; 217 218 /// True if the PMULLD instruction is slow compared to PMULLW/PMULHW and 219 // PMULUDQ. 220 bool IsPMULLDSlow = false; 221 222 /// True if the PMADDWD instruction is slow compared to PMULLD. 223 bool IsPMADDWDSlow = false; 224 225 /// True if unaligned memory accesses of 16-bytes are slow. 226 bool IsUAMem16Slow = false; 227 228 /// True if unaligned memory accesses of 32-bytes are slow. 229 bool IsUAMem32Slow = false; 230 231 /// True if SSE operations can have unaligned memory operands. 232 /// This may require setting a configuration bit in the processor. 233 bool HasSSEUnalignedMem = false; 234 235 /// True if this processor has the CMPXCHG16B instruction; 236 /// this is true for most x86-64 chips, but not the first AMD chips. 237 bool HasCmpxchg16b = false; 238 239 /// True if the LEA instruction should be used for adjusting 240 /// the stack pointer. This is an optimization for Intel Atom processors. 241 bool UseLeaForSP = false; 242 243 /// True if POPCNT instruction has a false dependency on the destination register. 244 bool HasPOPCNTFalseDeps = false; 245 246 /// True if LZCNT/TZCNT instructions have a false dependency on the destination register. 247 bool HasLZCNTFalseDeps = false; 248 249 /// True if its preferable to combine to a single cross-lane shuffle 250 /// using a variable mask over multiple fixed shuffles. 251 bool HasFastVariableCrossLaneShuffle = false; 252 253 /// True if its preferable to combine to a single per-lane shuffle 254 /// using a variable mask over multiple fixed shuffles. 255 bool HasFastVariablePerLaneShuffle = false; 256 257 /// True if vzeroupper instructions should be inserted after code that uses 258 /// ymm or zmm registers. 259 bool InsertVZEROUPPER = false; 260 261 /// True if there is no performance penalty for writing NOPs with up to 262 /// 7 bytes. 263 bool HasFast7ByteNOP = false; 264 265 /// True if there is no performance penalty for writing NOPs with up to 266 /// 11 bytes. 267 bool HasFast11ByteNOP = false; 268 269 /// True if there is no performance penalty for writing NOPs with up to 270 /// 15 bytes. 271 bool HasFast15ByteNOP = false; 272 273 /// True if gather is reasonably fast. This is true for Skylake client and 274 /// all AVX-512 CPUs. 275 bool HasFastGather = false; 276 277 /// True if hardware SQRTSS instruction is at least as fast (latency) as 278 /// RSQRTSS followed by a Newton-Raphson iteration. 279 bool HasFastScalarFSQRT = false; 280 281 /// True if hardware SQRTPS/VSQRTPS instructions are at least as fast 282 /// (throughput) as RSQRTPS/VRSQRTPS followed by a Newton-Raphson iteration. 283 bool HasFastVectorFSQRT = false; 284 285 /// True if 8-bit divisions are significantly faster than 286 /// 32-bit divisions and should be used when possible. 287 bool HasSlowDivide32 = false; 288 289 /// True if 32-bit divides are significantly faster than 290 /// 64-bit divisions and should be used when possible. 291 bool HasSlowDivide64 = false; 292 293 /// True if LZCNT instruction is fast. 294 bool HasFastLZCNT = false; 295 296 /// True if SHLD based rotate is fast. 297 bool HasFastSHLDRotate = false; 298 299 /// True if the processor supports macrofusion. 300 bool HasMacroFusion = false; 301 302 /// True if the processor supports branch fusion. 303 bool HasBranchFusion = false; 304 305 /// True if the processor has enhanced REP MOVSB/STOSB. 306 bool HasERMSB = false; 307 308 /// True if the processor has fast short REP MOV. 309 bool HasFSRM = false; 310 311 /// True if the short functions should be padded to prevent 312 /// a stall when returning too early. 313 bool PadShortFunctions = false; 314 315 /// True if two memory operand instructions should use a temporary register 316 /// instead. 317 bool SlowTwoMemOps = false; 318 319 /// True if the LEA instruction inputs have to be ready at address generation 320 /// (AG) time. 321 bool LEAUsesAG = false; 322 323 /// True if the LEA instruction with certain arguments is slow 324 bool SlowLEA = false; 325 326 /// True if the LEA instruction has all three source operands: base, index, 327 /// and offset or if the LEA instruction uses base and index registers where 328 /// the base is EBP, RBP,or R13 329 bool Slow3OpsLEA = false; 330 331 /// True if INC and DEC instructions are slow when writing to flags 332 bool SlowIncDec = false; 333 334 /// Processor has AVX-512 PreFetch Instructions 335 bool HasPFI = false; 336 337 /// Processor has AVX-512 Exponential and Reciprocal Instructions 338 bool HasERI = false; 339 340 /// Processor has AVX-512 Conflict Detection Instructions 341 bool HasCDI = false; 342 343 /// Processor has AVX-512 population count Instructions 344 bool HasVPOPCNTDQ = false; 345 346 /// Processor has AVX-512 Doubleword and Quadword instructions 347 bool HasDQI = false; 348 349 /// Processor has AVX-512 Byte and Word instructions 350 bool HasBWI = false; 351 352 /// Processor has AVX-512 Vector Length eXtenstions 353 bool HasVLX = false; 354 355 /// Processor has AVX-512 16 bit floating-point extenstions 356 bool HasFP16 = false; 357 358 /// Processor has PKU extenstions 359 bool HasPKU = false; 360 361 /// Processor has AVX-512 Vector Neural Network Instructions 362 bool HasVNNI = false; 363 364 /// Processor has AVX Vector Neural Network Instructions 365 bool HasAVXVNNI = false; 366 367 /// Processor has AVX-512 bfloat16 floating-point extensions 368 bool HasBF16 = false; 369 370 /// Processor supports ENQCMD instructions 371 bool HasENQCMD = false; 372 373 /// Processor has AVX-512 Bit Algorithms instructions 374 bool HasBITALG = false; 375 376 /// Processor has AVX-512 vp2intersect instructions 377 bool HasVP2INTERSECT = false; 378 379 /// Processor supports CET SHSTK - Control-Flow Enforcement Technology 380 /// using Shadow Stack 381 bool HasSHSTK = false; 382 383 /// Processor supports Invalidate Process-Context Identifier 384 bool HasINVPCID = false; 385 386 /// Processor has Software Guard Extensions 387 bool HasSGX = false; 388 389 /// Processor supports Flush Cache Line instruction 390 bool HasCLFLUSHOPT = false; 391 392 /// Processor supports Cache Line Write Back instruction 393 bool HasCLWB = false; 394 395 /// Processor supports Write Back No Invalidate instruction 396 bool HasWBNOINVD = false; 397 398 /// Processor support RDPID instruction 399 bool HasRDPID = false; 400 401 /// Processor supports WaitPKG instructions 402 bool HasWAITPKG = false; 403 404 /// Processor supports PCONFIG instruction 405 bool HasPCONFIG = false; 406 407 /// Processor support key locker instructions 408 bool HasKL = false; 409 410 /// Processor support key locker wide instructions 411 bool HasWIDEKL = false; 412 413 /// Processor supports HRESET instruction 414 bool HasHRESET = false; 415 416 /// Processor supports SERIALIZE instruction 417 bool HasSERIALIZE = false; 418 419 /// Processor supports TSXLDTRK instruction 420 bool HasTSXLDTRK = false; 421 422 /// Processor has AMX support 423 bool HasAMXTILE = false; 424 bool HasAMXBF16 = false; 425 bool HasAMXINT8 = false; 426 427 /// Processor supports User Level Interrupt instructions 428 bool HasUINTR = false; 429 430 /// Enable SSE4.2 CRC32 instruction (Used when SSE4.2 is supported but 431 /// function is GPR only) 432 bool HasCRC32 = false; 433 434 /// Processor has a single uop BEXTR implementation. 435 bool HasFastBEXTR = false; 436 437 /// Try harder to combine to horizontal vector ops if they are fast. 438 bool HasFastHorizontalOps = false; 439 440 /// Prefer a left/right scalar logical shifts pair over a shift+and pair. 441 bool HasFastScalarShiftMasks = false; 442 443 /// Prefer a left/right vector logical shifts pair over a shift+and pair. 444 bool HasFastVectorShiftMasks = false; 445 446 /// Prefer a movbe over a single-use load + bswap / single-use bswap + store. 447 bool HasFastMOVBE = false; 448 449 /// Use a retpoline thunk rather than indirect calls to block speculative 450 /// execution. 451 bool UseRetpolineIndirectCalls = false; 452 453 /// Use a retpoline thunk or remove any indirect branch to block speculative 454 /// execution. 455 bool UseRetpolineIndirectBranches = false; 456 457 /// Deprecated flag, query `UseRetpolineIndirectCalls` and 458 /// `UseRetpolineIndirectBranches` instead. 459 bool DeprecatedUseRetpoline = false; 460 461 /// When using a retpoline thunk, call an externally provided thunk rather 462 /// than emitting one inside the compiler. 463 bool UseRetpolineExternalThunk = false; 464 465 /// Prevent generation of indirect call/branch instructions from memory, 466 /// and force all indirect call/branch instructions from a register to be 467 /// preceded by an LFENCE. Also decompose RET instructions into a 468 /// POP+LFENCE+JMP sequence. 469 bool UseLVIControlFlowIntegrity = false; 470 471 /// Enable Speculative Execution Side Effect Suppression 472 bool UseSpeculativeExecutionSideEffectSuppression = false; 473 474 /// Insert LFENCE instructions to prevent data speculatively injected into 475 /// loads from being used maliciously. 476 bool UseLVILoadHardening = false; 477 478 /// Use an instruction sequence for taking the address of a global that allows 479 /// a memory tag in the upper address bits. 480 bool AllowTaggedGlobals = false; 481 482 /// Use software floating point for code generation. 483 bool UseSoftFloat = false; 484 485 /// Use alias analysis during code generation. 486 bool UseAA = false; 487 488 /// The minimum alignment known to hold of the stack frame on 489 /// entry to the function and which must be maintained by every function. 490 Align stackAlignment = Align(4); 491 492 Align TileConfigAlignment = Align(4); 493 494 /// Max. memset / memcpy size that is turned into rep/movs, rep/stos ops. 495 /// 496 // FIXME: this is a known good value for Yonah. How about others? 497 unsigned MaxInlineSizeThreshold = 128; 498 499 /// Indicates target prefers 128 bit instructions. 500 bool Prefer128Bit = false; 501 502 /// Indicates target prefers 256 bit instructions. 503 bool Prefer256Bit = false; 504 505 /// Indicates target prefers AVX512 mask registers. 506 bool PreferMaskRegisters = false; 507 508 /// Use Silvermont specific arithmetic costs. 509 bool UseSLMArithCosts = false; 510 511 /// Use Goldmont specific floating point div/sqrt costs. 512 bool UseGLMDivSqrtCosts = false; 513 514 /// What processor and OS we're targeting. 515 Triple TargetTriple; 516 517 /// GlobalISel related APIs. 518 std::unique_ptr<CallLowering> CallLoweringInfo; 519 std::unique_ptr<LegalizerInfo> Legalizer; 520 std::unique_ptr<RegisterBankInfo> RegBankInfo; 521 std::unique_ptr<InstructionSelector> InstSelector; 522 523 private: 524 /// Override the stack alignment. 525 MaybeAlign StackAlignOverride; 526 527 /// Preferred vector width from function attribute. 528 unsigned PreferVectorWidthOverride; 529 530 /// Resolved preferred vector width from function attribute and subtarget 531 /// features. 532 unsigned PreferVectorWidth = UINT32_MAX; 533 534 /// Required vector width from function attribute. 535 unsigned RequiredVectorWidth; 536 537 /// True if compiling for 64-bit, false for 16-bit or 32-bit. 538 bool In64BitMode = false; 539 540 /// True if compiling for 32-bit, false for 16-bit or 64-bit. 541 bool In32BitMode = false; 542 543 /// True if compiling for 16-bit, false for 32-bit or 64-bit. 544 bool In16BitMode = false; 545 546 X86SelectionDAGInfo TSInfo; 547 // Ordering here is important. X86InstrInfo initializes X86RegisterInfo which 548 // X86TargetLowering needs. 549 X86InstrInfo InstrInfo; 550 X86TargetLowering TLInfo; 551 X86FrameLowering FrameLowering; 552 553 public: 554 /// This constructor initializes the data members to match that 555 /// of the specified triple. 556 /// 557 X86Subtarget(const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS, 558 const X86TargetMachine &TM, MaybeAlign StackAlignOverride, 559 unsigned PreferVectorWidthOverride, 560 unsigned RequiredVectorWidth); 561 562 const X86TargetLowering *getTargetLowering() const override { 563 return &TLInfo; 564 } 565 566 const X86InstrInfo *getInstrInfo() const override { return &InstrInfo; } 567 568 const X86FrameLowering *getFrameLowering() const override { 569 return &FrameLowering; 570 } 571 572 const X86SelectionDAGInfo *getSelectionDAGInfo() const override { 573 return &TSInfo; 574 } 575 576 const X86RegisterInfo *getRegisterInfo() const override { 577 return &getInstrInfo()->getRegisterInfo(); 578 } 579 580 unsigned getTileConfigSize() const { return 64; } 581 Align getTileConfigAlignment() const { return TileConfigAlignment; } 582 583 /// Returns the minimum alignment known to hold of the 584 /// stack frame on entry to the function and which must be maintained by every 585 /// function for this subtarget. 586 Align getStackAlignment() const { return stackAlignment; } 587 588 /// Returns the maximum memset / memcpy size 589 /// that still makes it profitable to inline the call. 590 unsigned getMaxInlineSizeThreshold() const { return MaxInlineSizeThreshold; } 591 592 /// ParseSubtargetFeatures - Parses features string setting specified 593 /// subtarget options. Definition of function is auto generated by tblgen. 594 void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS); 595 596 /// Methods used by Global ISel 597 const CallLowering *getCallLowering() const override; 598 InstructionSelector *getInstructionSelector() const override; 599 const LegalizerInfo *getLegalizerInfo() const override; 600 const RegisterBankInfo *getRegBankInfo() const override; 601 602 private: 603 /// Initialize the full set of dependencies so we can use an initializer 604 /// list for X86Subtarget. 605 X86Subtarget &initializeSubtargetDependencies(StringRef CPU, 606 StringRef TuneCPU, 607 StringRef FS); 608 void initSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS); 609 610 public: 611 /// Is this x86_64? (disregarding specific ABI / programming model) 612 bool is64Bit() const { 613 return In64BitMode; 614 } 615 616 bool is32Bit() const { 617 return In32BitMode; 618 } 619 620 bool is16Bit() const { 621 return In16BitMode; 622 } 623 624 /// Is this x86_64 with the ILP32 programming model (x32 ABI)? 625 bool isTarget64BitILP32() const { 626 return In64BitMode && (TargetTriple.isX32() || TargetTriple.isOSNaCl()); 627 } 628 629 /// Is this x86_64 with the LP64 programming model (standard AMD64, no x32)? 630 bool isTarget64BitLP64() const { 631 return In64BitMode && (!TargetTriple.isX32() && !TargetTriple.isOSNaCl()); 632 } 633 634 PICStyles::Style getPICStyle() const { return PICStyle; } 635 void setPICStyle(PICStyles::Style Style) { PICStyle = Style; } 636 637 bool hasX87() const { return HasX87; } 638 bool hasCmpxchg8b() const { return HasCmpxchg8b; } 639 bool hasNOPL() const { return HasNOPL; } 640 // SSE codegen depends on cmovs, and all SSE1+ processors support them. 641 // All 64-bit processors support cmov. 642 bool hasCMov() const { return HasCMov || X86SSELevel >= SSE1 || is64Bit(); } 643 bool hasSSE1() const { return X86SSELevel >= SSE1; } 644 bool hasSSE2() const { return X86SSELevel >= SSE2; } 645 bool hasSSE3() const { return X86SSELevel >= SSE3; } 646 bool hasSSSE3() const { return X86SSELevel >= SSSE3; } 647 bool hasSSE41() const { return X86SSELevel >= SSE41; } 648 bool hasSSE42() const { return X86SSELevel >= SSE42; } 649 bool hasAVX() const { return X86SSELevel >= AVX; } 650 bool hasAVX2() const { return X86SSELevel >= AVX2; } 651 bool hasAVX512() const { return X86SSELevel >= AVX512F; } 652 bool hasInt256() const { return hasAVX2(); } 653 bool hasSSE4A() const { return HasSSE4A; } 654 bool hasMMX() const { return X863DNowLevel >= MMX; } 655 bool has3DNow() const { return X863DNowLevel >= ThreeDNow; } 656 bool has3DNowA() const { return X863DNowLevel >= ThreeDNowA; } 657 bool hasPOPCNT() const { return HasPOPCNT; } 658 bool hasAES() const { return HasAES; } 659 bool hasVAES() const { return HasVAES; } 660 bool hasFXSR() const { return HasFXSR; } 661 bool hasXSAVE() const { return HasXSAVE; } 662 bool hasXSAVEOPT() const { return HasXSAVEOPT; } 663 bool hasXSAVEC() const { return HasXSAVEC; } 664 bool hasXSAVES() const { return HasXSAVES; } 665 bool hasPCLMUL() const { return HasPCLMUL; } 666 bool hasVPCLMULQDQ() const { return HasVPCLMULQDQ; } 667 bool hasGFNI() const { return HasGFNI; } 668 // Prefer FMA4 to FMA - its better for commutation/memory folding and 669 // has equal or better performance on all supported targets. 670 bool hasFMA() const { return HasFMA; } 671 bool hasFMA4() const { return HasFMA4; } 672 bool hasAnyFMA() const { return hasFMA() || hasFMA4(); } 673 bool hasXOP() const { return HasXOP; } 674 bool hasTBM() const { return HasTBM; } 675 bool hasLWP() const { return HasLWP; } 676 bool hasMOVBE() const { return HasMOVBE; } 677 bool hasRDRAND() const { return HasRDRAND; } 678 bool hasF16C() const { return HasF16C; } 679 bool hasFSGSBase() const { return HasFSGSBase; } 680 bool hasLZCNT() const { return HasLZCNT; } 681 bool hasBMI() const { return HasBMI; } 682 bool hasBMI2() const { return HasBMI2; } 683 bool hasVBMI() const { return HasVBMI; } 684 bool hasVBMI2() const { return HasVBMI2; } 685 bool hasIFMA() const { return HasIFMA; } 686 bool hasRTM() const { return HasRTM; } 687 bool hasADX() const { return HasADX; } 688 bool hasSHA() const { return HasSHA; } 689 bool hasPRFCHW() const { return HasPRFCHW; } 690 bool hasPREFETCHWT1() const { return HasPREFETCHWT1; } 691 bool hasPrefetchW() const { 692 // The PREFETCHW instruction was added with 3DNow but later CPUs gave it 693 // its own CPUID bit as part of deprecating 3DNow. Intel eventually added 694 // it and KNL has another that prefetches to L2 cache. We assume the 695 // L1 version exists if the L2 version does. 696 return has3DNow() || hasPRFCHW() || hasPREFETCHWT1(); 697 } 698 bool hasSSEPrefetch() const { 699 // We implicitly enable these when we have a write prefix supporting cache 700 // level OR if we have prfchw, but don't already have a read prefetch from 701 // 3dnow. 702 return hasSSE1() || (hasPRFCHW() && !has3DNow()) || hasPREFETCHWT1(); 703 } 704 bool hasRDSEED() const { return HasRDSEED; } 705 bool hasLAHFSAHF() const { return HasLAHFSAHF64 || !is64Bit(); } 706 bool hasMWAITX() const { return HasMWAITX; } 707 bool hasCLZERO() const { return HasCLZERO; } 708 bool hasCLDEMOTE() const { return HasCLDEMOTE; } 709 bool hasMOVDIRI() const { return HasMOVDIRI; } 710 bool hasMOVDIR64B() const { return HasMOVDIR64B; } 711 bool hasPTWRITE() const { return HasPTWRITE; } 712 bool isSHLDSlow() const { return IsSHLDSlow; } 713 bool isPMULLDSlow() const { return IsPMULLDSlow; } 714 bool isPMADDWDSlow() const { return IsPMADDWDSlow; } 715 bool isUnalignedMem16Slow() const { return IsUAMem16Slow; } 716 bool isUnalignedMem32Slow() const { return IsUAMem32Slow; } 717 bool hasSSEUnalignedMem() const { return HasSSEUnalignedMem; } 718 bool hasCmpxchg16b() const { return HasCmpxchg16b && is64Bit(); } 719 bool useLeaForSP() const { return UseLeaForSP; } 720 bool hasPOPCNTFalseDeps() const { return HasPOPCNTFalseDeps; } 721 bool hasLZCNTFalseDeps() const { return HasLZCNTFalseDeps; } 722 bool hasFastVariableCrossLaneShuffle() const { 723 return HasFastVariableCrossLaneShuffle; 724 } 725 bool hasFastVariablePerLaneShuffle() const { 726 return HasFastVariablePerLaneShuffle; 727 } 728 bool insertVZEROUPPER() const { return InsertVZEROUPPER; } 729 bool hasFastGather() const { return HasFastGather; } 730 bool hasFastScalarFSQRT() const { return HasFastScalarFSQRT; } 731 bool hasFastVectorFSQRT() const { return HasFastVectorFSQRT; } 732 bool hasFastLZCNT() const { return HasFastLZCNT; } 733 bool hasFastSHLDRotate() const { return HasFastSHLDRotate; } 734 bool hasFastBEXTR() const { return HasFastBEXTR; } 735 bool hasFastHorizontalOps() const { return HasFastHorizontalOps; } 736 bool hasFastScalarShiftMasks() const { return HasFastScalarShiftMasks; } 737 bool hasFastVectorShiftMasks() const { return HasFastVectorShiftMasks; } 738 bool hasFastMOVBE() const { return HasFastMOVBE; } 739 bool hasMacroFusion() const { return HasMacroFusion; } 740 bool hasBranchFusion() const { return HasBranchFusion; } 741 bool hasERMSB() const { return HasERMSB; } 742 bool hasFSRM() const { return HasFSRM; } 743 bool hasSlowDivide32() const { return HasSlowDivide32; } 744 bool hasSlowDivide64() const { return HasSlowDivide64; } 745 bool padShortFunctions() const { return PadShortFunctions; } 746 bool slowTwoMemOps() const { return SlowTwoMemOps; } 747 bool LEAusesAG() const { return LEAUsesAG; } 748 bool slowLEA() const { return SlowLEA; } 749 bool slow3OpsLEA() const { return Slow3OpsLEA; } 750 bool slowIncDec() const { return SlowIncDec; } 751 bool hasCDI() const { return HasCDI; } 752 bool hasVPOPCNTDQ() const { return HasVPOPCNTDQ; } 753 bool hasPFI() const { return HasPFI; } 754 bool hasERI() const { return HasERI; } 755 bool hasDQI() const { return HasDQI; } 756 bool hasBWI() const { return HasBWI; } 757 bool hasVLX() const { return HasVLX; } 758 bool hasFP16() const { return HasFP16; } 759 bool hasPKU() const { return HasPKU; } 760 bool hasVNNI() const { return HasVNNI; } 761 bool hasBF16() const { return HasBF16; } 762 bool hasVP2INTERSECT() const { return HasVP2INTERSECT; } 763 bool hasBITALG() const { return HasBITALG; } 764 bool hasSHSTK() const { return HasSHSTK; } 765 bool hasCLFLUSHOPT() const { return HasCLFLUSHOPT; } 766 bool hasCLWB() const { return HasCLWB; } 767 bool hasWBNOINVD() const { return HasWBNOINVD; } 768 bool hasRDPID() const { return HasRDPID; } 769 bool hasWAITPKG() const { return HasWAITPKG; } 770 bool hasPCONFIG() const { return HasPCONFIG; } 771 bool hasSGX() const { return HasSGX; } 772 bool hasINVPCID() const { return HasINVPCID; } 773 bool hasENQCMD() const { return HasENQCMD; } 774 bool hasKL() const { return HasKL; } 775 bool hasWIDEKL() const { return HasWIDEKL; } 776 bool hasHRESET() const { return HasHRESET; } 777 bool hasSERIALIZE() const { return HasSERIALIZE; } 778 bool hasTSXLDTRK() const { return HasTSXLDTRK; } 779 bool hasUINTR() const { return HasUINTR; } 780 bool hasCRC32() const { return HasCRC32; } 781 bool useRetpolineIndirectCalls() const { return UseRetpolineIndirectCalls; } 782 bool useRetpolineIndirectBranches() const { 783 return UseRetpolineIndirectBranches; 784 } 785 bool hasAVXVNNI() const { return HasAVXVNNI; } 786 bool hasAMXTILE() const { return HasAMXTILE; } 787 bool hasAMXBF16() const { return HasAMXBF16; } 788 bool hasAMXINT8() const { return HasAMXINT8; } 789 bool useRetpolineExternalThunk() const { return UseRetpolineExternalThunk; } 790 791 // These are generic getters that OR together all of the thunk types 792 // supported by the subtarget. Therefore useIndirectThunk*() will return true 793 // if any respective thunk feature is enabled. 794 bool useIndirectThunkCalls() const { 795 return useRetpolineIndirectCalls() || useLVIControlFlowIntegrity(); 796 } 797 bool useIndirectThunkBranches() const { 798 return useRetpolineIndirectBranches() || useLVIControlFlowIntegrity(); 799 } 800 801 bool preferMaskRegisters() const { return PreferMaskRegisters; } 802 bool useSLMArithCosts() const { return UseSLMArithCosts; } 803 bool useGLMDivSqrtCosts() const { return UseGLMDivSqrtCosts; } 804 bool useLVIControlFlowIntegrity() const { return UseLVIControlFlowIntegrity; } 805 bool allowTaggedGlobals() const { return AllowTaggedGlobals; } 806 bool useLVILoadHardening() const { return UseLVILoadHardening; } 807 bool useSpeculativeExecutionSideEffectSuppression() const { 808 return UseSpeculativeExecutionSideEffectSuppression; 809 } 810 811 unsigned getPreferVectorWidth() const { return PreferVectorWidth; } 812 unsigned getRequiredVectorWidth() const { return RequiredVectorWidth; } 813 814 // Helper functions to determine when we should allow widening to 512-bit 815 // during codegen. 816 // TODO: Currently we're always allowing widening on CPUs without VLX, 817 // because for many cases we don't have a better option. 818 bool canExtendTo512DQ() const { 819 return hasAVX512() && (!hasVLX() || getPreferVectorWidth() >= 512); 820 } 821 bool canExtendTo512BW() const { 822 return hasBWI() && canExtendTo512DQ(); 823 } 824 825 // If there are no 512-bit vectors and we prefer not to use 512-bit registers, 826 // disable them in the legalizer. 827 bool useAVX512Regs() const { 828 return hasAVX512() && (canExtendTo512DQ() || RequiredVectorWidth > 256); 829 } 830 831 bool useBWIRegs() const { 832 return hasBWI() && useAVX512Regs(); 833 } 834 835 bool isXRaySupported() const override { return is64Bit(); } 836 837 /// TODO: to be removed later and replaced with suitable properties 838 bool isAtom() const { return X86ProcFamily == IntelAtom; } 839 bool useSoftFloat() const { return UseSoftFloat; } 840 bool useAA() const override { return UseAA; } 841 842 /// Use mfence if we have SSE2 or we're on x86-64 (even if we asked for 843 /// no-sse2). There isn't any reason to disable it if the target processor 844 /// supports it. 845 bool hasMFence() const { return hasSSE2() || is64Bit(); } 846 847 const Triple &getTargetTriple() const { return TargetTriple; } 848 849 bool isTargetDarwin() const { return TargetTriple.isOSDarwin(); } 850 bool isTargetFreeBSD() const { return TargetTriple.isOSFreeBSD(); } 851 bool isTargetDragonFly() const { return TargetTriple.isOSDragonFly(); } 852 bool isTargetSolaris() const { return TargetTriple.isOSSolaris(); } 853 bool isTargetPS4() const { return TargetTriple.isPS4CPU(); } 854 855 bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); } 856 bool isTargetCOFF() const { return TargetTriple.isOSBinFormatCOFF(); } 857 bool isTargetMachO() const { return TargetTriple.isOSBinFormatMachO(); } 858 859 bool isTargetLinux() const { return TargetTriple.isOSLinux(); } 860 bool isTargetKFreeBSD() const { return TargetTriple.isOSKFreeBSD(); } 861 bool isTargetGlibc() const { return TargetTriple.isOSGlibc(); } 862 bool isTargetAndroid() const { return TargetTriple.isAndroid(); } 863 bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); } 864 bool isTargetNaCl32() const { return isTargetNaCl() && !is64Bit(); } 865 bool isTargetNaCl64() const { return isTargetNaCl() && is64Bit(); } 866 bool isTargetMCU() const { return TargetTriple.isOSIAMCU(); } 867 bool isTargetFuchsia() const { return TargetTriple.isOSFuchsia(); } 868 869 bool isTargetWindowsMSVC() const { 870 return TargetTriple.isWindowsMSVCEnvironment(); 871 } 872 873 bool isTargetWindowsCoreCLR() const { 874 return TargetTriple.isWindowsCoreCLREnvironment(); 875 } 876 877 bool isTargetWindowsCygwin() const { 878 return TargetTriple.isWindowsCygwinEnvironment(); 879 } 880 881 bool isTargetWindowsGNU() const { 882 return TargetTriple.isWindowsGNUEnvironment(); 883 } 884 885 bool isTargetWindowsItanium() const { 886 return TargetTriple.isWindowsItaniumEnvironment(); 887 } 888 889 bool isTargetCygMing() const { return TargetTriple.isOSCygMing(); } 890 891 bool isOSWindows() const { return TargetTriple.isOSWindows(); } 892 893 bool isTargetWin64() const { return In64BitMode && isOSWindows(); } 894 895 bool isTargetWin32() const { return !In64BitMode && isOSWindows(); } 896 897 bool isPICStyleGOT() const { return PICStyle == PICStyles::Style::GOT; } 898 bool isPICStyleRIPRel() const { return PICStyle == PICStyles::Style::RIPRel; } 899 900 bool isPICStyleStubPIC() const { 901 return PICStyle == PICStyles::Style::StubPIC; 902 } 903 904 bool isPositionIndependent() const; 905 906 bool isCallingConvWin64(CallingConv::ID CC) const { 907 switch (CC) { 908 // On Win64, all these conventions just use the default convention. 909 case CallingConv::C: 910 case CallingConv::Fast: 911 case CallingConv::Tail: 912 case CallingConv::Swift: 913 case CallingConv::SwiftTail: 914 case CallingConv::X86_FastCall: 915 case CallingConv::X86_StdCall: 916 case CallingConv::X86_ThisCall: 917 case CallingConv::X86_VectorCall: 918 case CallingConv::Intel_OCL_BI: 919 return isTargetWin64(); 920 // This convention allows using the Win64 convention on other targets. 921 case CallingConv::Win64: 922 return true; 923 // This convention allows using the SysV convention on Windows targets. 924 case CallingConv::X86_64_SysV: 925 return false; 926 // Otherwise, who knows what this is. 927 default: 928 return false; 929 } 930 } 931 932 /// Classify a global variable reference for the current subtarget according 933 /// to how we should reference it in a non-pcrel context. 934 unsigned char classifyLocalReference(const GlobalValue *GV) const; 935 936 unsigned char classifyGlobalReference(const GlobalValue *GV, 937 const Module &M) const; 938 unsigned char classifyGlobalReference(const GlobalValue *GV) const; 939 940 /// Classify a global function reference for the current subtarget. 941 unsigned char classifyGlobalFunctionReference(const GlobalValue *GV, 942 const Module &M) const; 943 unsigned char classifyGlobalFunctionReference(const GlobalValue *GV) const; 944 945 /// Classify a blockaddress reference for the current subtarget according to 946 /// how we should reference it in a non-pcrel context. 947 unsigned char classifyBlockAddressReference() const; 948 949 /// Return true if the subtarget allows calls to immediate address. 950 bool isLegalToCallImmediateAddr() const; 951 952 /// Return whether FrameLowering should always set the "extended frame 953 /// present" bit in FP, or set it based on a symbol in the runtime. 954 bool swiftAsyncContextIsDynamicallySet() const { 955 // Older OS versions (particularly system unwinders) are confused by the 956 // Swift extended frame, so when building code that might be run on them we 957 // must dynamically query the concurrency library to determine whether 958 // extended frames should be flagged as present. 959 const Triple &TT = getTargetTriple(); 960 961 unsigned Major = TT.getOSVersion().getMajor(); 962 switch(TT.getOS()) { 963 default: 964 return false; 965 case Triple::IOS: 966 case Triple::TvOS: 967 return Major < 15; 968 case Triple::WatchOS: 969 return Major < 8; 970 case Triple::MacOSX: 971 case Triple::Darwin: 972 return Major < 12; 973 } 974 } 975 976 /// If we are using indirect thunks, we need to expand indirectbr to avoid it 977 /// lowering to an actual indirect jump. 978 bool enableIndirectBrExpand() const override { 979 return useIndirectThunkBranches(); 980 } 981 982 /// Enable the MachineScheduler pass for all X86 subtargets. 983 bool enableMachineScheduler() const override { return true; } 984 985 bool enableEarlyIfConversion() const override; 986 987 void getPostRAMutations(std::vector<std::unique_ptr<ScheduleDAGMutation>> 988 &Mutations) const override; 989 990 AntiDepBreakMode getAntiDepBreakMode() const override { 991 return TargetSubtargetInfo::ANTIDEP_CRITICAL; 992 } 993 994 bool enableAdvancedRASplitCost() const override { return false; } 995 }; 996 997 } // end namespace llvm 998 999 #endif // LLVM_LIB_TARGET_X86_X86SUBTARGET_H 1000