1 //===-- X86Subtarget.cpp - X86 Subtarget Information ----------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file implements the X86 specific subclass of TargetSubtargetInfo. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "X86.h" 14 15 #include "X86CallLowering.h" 16 #include "X86LegalizerInfo.h" 17 #include "X86MacroFusion.h" 18 #include "X86RegisterBankInfo.h" 19 #include "X86Subtarget.h" 20 #include "MCTargetDesc/X86BaseInfo.h" 21 #include "X86TargetMachine.h" 22 #include "llvm/ADT/Triple.h" 23 #include "llvm/CodeGen/GlobalISel/CallLowering.h" 24 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h" 25 #include "llvm/IR/Attributes.h" 26 #include "llvm/IR/ConstantRange.h" 27 #include "llvm/IR/Function.h" 28 #include "llvm/IR/GlobalValue.h" 29 #include "llvm/Support/Casting.h" 30 #include "llvm/Support/CodeGen.h" 31 #include "llvm/Support/CommandLine.h" 32 #include "llvm/Support/Debug.h" 33 #include "llvm/Support/ErrorHandling.h" 34 #include "llvm/Support/raw_ostream.h" 35 #include "llvm/Target/TargetMachine.h" 36 37 #if defined(_MSC_VER) 38 #include <intrin.h> 39 #endif 40 41 using namespace llvm; 42 43 #define DEBUG_TYPE "subtarget" 44 45 #define GET_SUBTARGETINFO_TARGET_DESC 46 #define GET_SUBTARGETINFO_CTOR 47 #include "X86GenSubtargetInfo.inc" 48 49 // Temporary option to control early if-conversion for x86 while adding machine 50 // models. 51 static cl::opt<bool> 52 X86EarlyIfConv("x86-early-ifcvt", cl::Hidden, 53 cl::desc("Enable early if-conversion on X86")); 54 55 56 /// Classify a blockaddress reference for the current subtarget according to how 57 /// we should reference it in a non-pcrel context. 58 unsigned char X86Subtarget::classifyBlockAddressReference() const { 59 return classifyLocalReference(nullptr); 60 } 61 62 /// Classify a global variable reference for the current subtarget according to 63 /// how we should reference it in a non-pcrel context. 64 unsigned char 65 X86Subtarget::classifyGlobalReference(const GlobalValue *GV) const { 66 return classifyGlobalReference(GV, *GV->getParent()); 67 } 68 69 unsigned char 70 X86Subtarget::classifyLocalReference(const GlobalValue *GV) const { 71 // If we're not PIC, it's not very interesting. 72 if (!isPositionIndependent()) 73 return X86II::MO_NO_FLAG; 74 75 if (is64Bit()) { 76 // 64-bit ELF PIC local references may use GOTOFF relocations. 77 if (isTargetELF()) { 78 switch (TM.getCodeModel()) { 79 // 64-bit small code model is simple: All rip-relative. 80 case CodeModel::Tiny: 81 llvm_unreachable("Tiny codesize model not supported on X86"); 82 case CodeModel::Small: 83 case CodeModel::Kernel: 84 return X86II::MO_NO_FLAG; 85 86 // The large PIC code model uses GOTOFF. 87 case CodeModel::Large: 88 return X86II::MO_GOTOFF; 89 90 // Medium is a hybrid: RIP-rel for code, GOTOFF for DSO local data. 91 case CodeModel::Medium: 92 if (isa<Function>(GV)) 93 return X86II::MO_NO_FLAG; // All code is RIP-relative 94 return X86II::MO_GOTOFF; // Local symbols use GOTOFF. 95 } 96 llvm_unreachable("invalid code model"); 97 } 98 99 // Otherwise, this is either a RIP-relative reference or a 64-bit movabsq, 100 // both of which use MO_NO_FLAG. 101 return X86II::MO_NO_FLAG; 102 } 103 104 // The COFF dynamic linker just patches the executable sections. 105 if (isTargetCOFF()) 106 return X86II::MO_NO_FLAG; 107 108 if (isTargetDarwin()) { 109 // 32 bit macho has no relocation for a-b if a is undefined, even if 110 // b is in the section that is being relocated. 111 // This means we have to use o load even for GVs that are known to be 112 // local to the dso. 113 if (GV && (GV->isDeclarationForLinker() || GV->hasCommonLinkage())) 114 return X86II::MO_DARWIN_NONLAZY_PIC_BASE; 115 116 return X86II::MO_PIC_BASE_OFFSET; 117 } 118 119 return X86II::MO_GOTOFF; 120 } 121 122 unsigned char X86Subtarget::classifyGlobalReference(const GlobalValue *GV, 123 const Module &M) const { 124 // The static large model never uses stubs. 125 if (TM.getCodeModel() == CodeModel::Large && !isPositionIndependent()) 126 return X86II::MO_NO_FLAG; 127 128 // Absolute symbols can be referenced directly. 129 if (GV) { 130 if (Optional<ConstantRange> CR = GV->getAbsoluteSymbolRange()) { 131 // See if we can use the 8-bit immediate form. Note that some instructions 132 // will sign extend the immediate operand, so to be conservative we only 133 // accept the range [0,128). 134 if (CR->getUnsignedMax().ult(128)) 135 return X86II::MO_ABS8; 136 else 137 return X86II::MO_NO_FLAG; 138 } 139 } 140 141 if (TM.shouldAssumeDSOLocal(M, GV)) 142 return classifyLocalReference(GV); 143 144 if (isTargetCOFF()) { 145 if (GV->hasDLLImportStorageClass()) 146 return X86II::MO_DLLIMPORT; 147 return X86II::MO_COFFSTUB; 148 } 149 // Some JIT users use *-win32-elf triples; these shouldn't use GOT tables. 150 if (isOSWindows()) 151 return X86II::MO_NO_FLAG; 152 153 if (is64Bit()) { 154 // ELF supports a large, truly PIC code model with non-PC relative GOT 155 // references. Other object file formats do not. Use the no-flag, 64-bit 156 // reference for them. 157 if (TM.getCodeModel() == CodeModel::Large) 158 return isTargetELF() ? X86II::MO_GOT : X86II::MO_NO_FLAG; 159 return X86II::MO_GOTPCREL; 160 } 161 162 if (isTargetDarwin()) { 163 if (!isPositionIndependent()) 164 return X86II::MO_DARWIN_NONLAZY; 165 return X86II::MO_DARWIN_NONLAZY_PIC_BASE; 166 } 167 168 return X86II::MO_GOT; 169 } 170 171 unsigned char 172 X86Subtarget::classifyGlobalFunctionReference(const GlobalValue *GV) const { 173 return classifyGlobalFunctionReference(GV, *GV->getParent()); 174 } 175 176 unsigned char 177 X86Subtarget::classifyGlobalFunctionReference(const GlobalValue *GV, 178 const Module &M) const { 179 if (TM.shouldAssumeDSOLocal(M, GV)) 180 return X86II::MO_NO_FLAG; 181 182 // Functions on COFF can be non-DSO local for two reasons: 183 // - They are marked dllimport 184 // - They are extern_weak, and a stub is needed 185 if (isTargetCOFF()) { 186 if (GV->hasDLLImportStorageClass()) 187 return X86II::MO_DLLIMPORT; 188 return X86II::MO_COFFSTUB; 189 } 190 191 const Function *F = dyn_cast_or_null<Function>(GV); 192 193 if (isTargetELF()) { 194 if (is64Bit() && F && (CallingConv::X86_RegCall == F->getCallingConv())) 195 // According to psABI, PLT stub clobbers XMM8-XMM15. 196 // In Regcall calling convention those registers are used for passing 197 // parameters. Thus we need to prevent lazy binding in Regcall. 198 return X86II::MO_GOTPCREL; 199 // If PLT must be avoided then the call should be via GOTPCREL. 200 if (((F && F->hasFnAttribute(Attribute::NonLazyBind)) || 201 (!F && M.getRtLibUseGOT())) && 202 is64Bit()) 203 return X86II::MO_GOTPCREL; 204 return X86II::MO_PLT; 205 } 206 207 if (is64Bit()) { 208 if (F && F->hasFnAttribute(Attribute::NonLazyBind)) 209 // If the function is marked as non-lazy, generate an indirect call 210 // which loads from the GOT directly. This avoids runtime overhead 211 // at the cost of eager binding (and one extra byte of encoding). 212 return X86II::MO_GOTPCREL; 213 return X86II::MO_NO_FLAG; 214 } 215 216 return X86II::MO_NO_FLAG; 217 } 218 219 /// Return true if the subtarget allows calls to immediate address. 220 bool X86Subtarget::isLegalToCallImmediateAddr() const { 221 // FIXME: I386 PE/COFF supports PC relative calls using IMAGE_REL_I386_REL32 222 // but WinCOFFObjectWriter::RecordRelocation cannot emit them. Once it does, 223 // the following check for Win32 should be removed. 224 if (In64BitMode || isTargetWin32()) 225 return false; 226 return isTargetELF() || TM.getRelocationModel() == Reloc::Static; 227 } 228 229 void X86Subtarget::initSubtargetFeatures(StringRef CPU, StringRef FS) { 230 std::string CPUName = CPU; 231 if (CPUName.empty()) 232 CPUName = "generic"; 233 234 std::string FullFS = FS; 235 if (In64BitMode) { 236 // SSE2 should default to enabled in 64-bit mode, but can be turned off 237 // explicitly. 238 if (!FullFS.empty()) 239 FullFS = "+sse2," + FullFS; 240 else 241 FullFS = "+sse2"; 242 243 // If no CPU was specified, enable 64bit feature to satisy later check. 244 if (CPUName == "generic") { 245 if (!FullFS.empty()) 246 FullFS = "+64bit," + FullFS; 247 else 248 FullFS = "+64bit"; 249 } 250 } 251 252 // LAHF/SAHF are always supported in non-64-bit mode. 253 if (!In64BitMode) { 254 if (!FullFS.empty()) 255 FullFS = "+sahf," + FullFS; 256 else 257 FullFS = "+sahf"; 258 } 259 260 // Parse features string and set the CPU. 261 ParseSubtargetFeatures(CPUName, FullFS); 262 263 // All CPUs that implement SSE4.2 or SSE4A support unaligned accesses of 264 // 16-bytes and under that are reasonably fast. These features were 265 // introduced with Intel's Nehalem/Silvermont and AMD's Family10h 266 // micro-architectures respectively. 267 if (hasSSE42() || hasSSE4A()) 268 IsUAMem16Slow = false; 269 270 // It's important to keep the MCSubtargetInfo feature bits in sync with 271 // target data structure which is shared with MC code emitter, etc. 272 if (In64BitMode) 273 ToggleFeature(X86::Mode64Bit); 274 else if (In32BitMode) 275 ToggleFeature(X86::Mode32Bit); 276 else if (In16BitMode) 277 ToggleFeature(X86::Mode16Bit); 278 else 279 llvm_unreachable("Not 16-bit, 32-bit or 64-bit mode!"); 280 281 LLVM_DEBUG(dbgs() << "Subtarget features: SSELevel " << X86SSELevel 282 << ", 3DNowLevel " << X863DNowLevel << ", 64bit " 283 << HasX86_64 << "\n"); 284 if (In64BitMode && !HasX86_64) 285 report_fatal_error("64-bit code requested on a subtarget that doesn't " 286 "support it!"); 287 288 // Stack alignment is 16 bytes on Darwin, Linux, kFreeBSD and Solaris (both 289 // 32 and 64 bit) and for all 64-bit targets. 290 if (StackAlignOverride) 291 stackAlignment = StackAlignOverride; 292 else if (isTargetDarwin() || isTargetLinux() || isTargetSolaris() || 293 isTargetKFreeBSD() || In64BitMode) 294 stackAlignment = 16; 295 296 // Some CPUs have more overhead for gather. The specified overhead is relative 297 // to the Load operation. "2" is the number provided by Intel architects. This 298 // parameter is used for cost estimation of Gather Op and comparison with 299 // other alternatives. 300 // TODO: Remove the explicit hasAVX512()?, That would mean we would only 301 // enable gather with a -march. 302 if (hasAVX512() || (hasAVX2() && hasFastGather())) 303 GatherOverhead = 2; 304 if (hasAVX512()) 305 ScatterOverhead = 2; 306 307 // Consume the vector width attribute or apply any target specific limit. 308 if (PreferVectorWidthOverride) 309 PreferVectorWidth = PreferVectorWidthOverride; 310 else if (Prefer256Bit) 311 PreferVectorWidth = 256; 312 } 313 314 X86Subtarget &X86Subtarget::initializeSubtargetDependencies(StringRef CPU, 315 StringRef FS) { 316 initSubtargetFeatures(CPU, FS); 317 return *this; 318 } 319 320 X86Subtarget::X86Subtarget(const Triple &TT, StringRef CPU, StringRef FS, 321 const X86TargetMachine &TM, 322 unsigned StackAlignOverride, 323 unsigned PreferVectorWidthOverride, 324 unsigned RequiredVectorWidth) 325 : X86GenSubtargetInfo(TT, CPU, FS), 326 PICStyle(PICStyles::None), TM(TM), TargetTriple(TT), 327 StackAlignOverride(StackAlignOverride), 328 PreferVectorWidthOverride(PreferVectorWidthOverride), 329 RequiredVectorWidth(RequiredVectorWidth), 330 In64BitMode(TargetTriple.getArch() == Triple::x86_64), 331 In32BitMode(TargetTriple.getArch() == Triple::x86 && 332 TargetTriple.getEnvironment() != Triple::CODE16), 333 In16BitMode(TargetTriple.getArch() == Triple::x86 && 334 TargetTriple.getEnvironment() == Triple::CODE16), 335 InstrInfo(initializeSubtargetDependencies(CPU, FS)), TLInfo(TM, *this), 336 FrameLowering(*this, getStackAlignment()) { 337 // Determine the PICStyle based on the target selected. 338 if (!isPositionIndependent()) 339 setPICStyle(PICStyles::None); 340 else if (is64Bit()) 341 setPICStyle(PICStyles::RIPRel); 342 else if (isTargetCOFF()) 343 setPICStyle(PICStyles::None); 344 else if (isTargetDarwin()) 345 setPICStyle(PICStyles::StubPIC); 346 else if (isTargetELF()) 347 setPICStyle(PICStyles::GOT); 348 349 CallLoweringInfo.reset(new X86CallLowering(*getTargetLowering())); 350 Legalizer.reset(new X86LegalizerInfo(*this, TM)); 351 352 auto *RBI = new X86RegisterBankInfo(*getRegisterInfo()); 353 RegBankInfo.reset(RBI); 354 InstSelector.reset(createX86InstructionSelector(TM, *this, *RBI)); 355 } 356 357 const CallLowering *X86Subtarget::getCallLowering() const { 358 return CallLoweringInfo.get(); 359 } 360 361 const InstructionSelector *X86Subtarget::getInstructionSelector() const { 362 return InstSelector.get(); 363 } 364 365 const LegalizerInfo *X86Subtarget::getLegalizerInfo() const { 366 return Legalizer.get(); 367 } 368 369 const RegisterBankInfo *X86Subtarget::getRegBankInfo() const { 370 return RegBankInfo.get(); 371 } 372 373 bool X86Subtarget::enableEarlyIfConversion() const { 374 return hasCMov() && X86EarlyIfConv; 375 } 376 377 void X86Subtarget::getPostRAMutations( 378 std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations) const { 379 Mutations.push_back(createX86MacroFusionDAGMutation()); 380 } 381