1//=- X86ScheduleZnver1.td - X86 Znver1 Scheduling -------------*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the machine model for Znver1 to support instruction 10// scheduling and other instruction cost heuristics. 11// 12//===----------------------------------------------------------------------===// 13 14def Znver1Model : SchedMachineModel { 15 // Zen can decode 4 instructions per cycle. 16 let IssueWidth = 4; 17 // Based on the reorder buffer we define MicroOpBufferSize 18 let MicroOpBufferSize = 192; 19 let LoadLatency = 4; 20 let MispredictPenalty = 17; 21 let HighLatency = 25; 22 let PostRAScheduler = 1; 23 24 // FIXME: This variable is required for incomplete model. 25 // We haven't catered all instructions. 26 // So, we reset the value of this variable so as to 27 // say that the model is incomplete. 28 let CompleteModel = 0; 29} 30 31let SchedModel = Znver1Model in { 32 33// Zen can issue micro-ops to 10 different units in one cycle. 34// These are 35// * Four integer ALU units (ZALU0, ZALU1, ZALU2, ZALU3) 36// * Two AGU units (ZAGU0, ZAGU1) 37// * Four FPU units (ZFPU0, ZFPU1, ZFPU2, ZFPU3) 38// AGUs feed load store queues @two loads and 1 store per cycle. 39 40// Four ALU units are defined below 41def ZnALU0 : ProcResource<1>; 42def ZnALU1 : ProcResource<1>; 43def ZnALU2 : ProcResource<1>; 44def ZnALU3 : ProcResource<1>; 45 46// Two AGU units are defined below 47def ZnAGU0 : ProcResource<1>; 48def ZnAGU1 : ProcResource<1>; 49 50// Four FPU units are defined below 51def ZnFPU0 : ProcResource<1>; 52def ZnFPU1 : ProcResource<1>; 53def ZnFPU2 : ProcResource<1>; 54def ZnFPU3 : ProcResource<1>; 55 56// FPU grouping 57def ZnFPU013 : ProcResGroup<[ZnFPU0, ZnFPU1, ZnFPU3]>; 58def ZnFPU01 : ProcResGroup<[ZnFPU0, ZnFPU1]>; 59def ZnFPU12 : ProcResGroup<[ZnFPU1, ZnFPU2]>; 60def ZnFPU13 : ProcResGroup<[ZnFPU1, ZnFPU3]>; 61def ZnFPU23 : ProcResGroup<[ZnFPU2, ZnFPU3]>; 62def ZnFPU02 : ProcResGroup<[ZnFPU0, ZnFPU2]>; 63def ZnFPU03 : ProcResGroup<[ZnFPU0, ZnFPU3]>; 64 65// Below are the grouping of the units. 66// Micro-ops to be issued to multiple units are tackled this way. 67 68// ALU grouping 69// ZnALU03 - 0,3 grouping 70def ZnALU03: ProcResGroup<[ZnALU0, ZnALU3]>; 71 72// 56 Entry (14x4 entries) Int Scheduler 73def ZnALU : ProcResGroup<[ZnALU0, ZnALU1, ZnALU2, ZnALU3]> { 74 let BufferSize=56; 75} 76 77// 28 Entry (14x2) AGU group. AGUs can't be used for all ALU operations 78// but are relevant for some instructions 79def ZnAGU : ProcResGroup<[ZnAGU0, ZnAGU1]> { 80 let BufferSize=28; 81} 82 83// Integer Multiplication issued on ALU1. 84def ZnMultiplier : ProcResource<1>; 85 86// Integer division issued on ALU2. 87def ZnDivider : ProcResource<1>; 88 89// 4 Cycles integer load-to use Latency is captured 90def : ReadAdvance<ReadAfterLd, 4>; 91 92// 8 Cycles vector load-to use Latency is captured 93def : ReadAdvance<ReadAfterVecLd, 8>; 94def : ReadAdvance<ReadAfterVecXLd, 8>; 95def : ReadAdvance<ReadAfterVecYLd, 8>; 96 97def : ReadAdvance<ReadInt2Fpu, 0>; 98 99// The Integer PRF for Zen is 168 entries, and it holds the architectural and 100// speculative version of the 64-bit integer registers. 101// Reference: "Software Optimization Guide for AMD Family 17h Processors" 102def ZnIntegerPRF : RegisterFile<168, [GR64, CCR]>; 103 104// 36 Entry (9x4 entries) floating-point Scheduler 105def ZnFPU : ProcResGroup<[ZnFPU0, ZnFPU1, ZnFPU2, ZnFPU3]> { 106let BufferSize=36; 107} 108 109// The Zen FP Retire Queue renames SIMD and FP uOps onto a pool of 160 128-bit 110// registers. Operations on 256-bit data types are cracked into two COPs. 111// Reference: "Software Optimization Guide for AMD Family 17h Processors" 112def ZnFpuPRF: RegisterFile<160, [VR64, VR128, VR256], [1, 1, 2]>; 113 114// The unit can track up to 192 macro ops in-flight. 115// The retire unit handles in-order commit of up to 8 macro ops per cycle. 116// Reference: "Software Optimization Guide for AMD Family 17h Processors" 117// To be noted, the retire unit is shared between integer and FP ops. 118// In SMT mode it is 96 entry per thread. But, we do not use the conservative 119// value here because there is currently no way to fully mode the SMT mode, 120// so there is no point in trying. 121def ZnRCU : RetireControlUnit<192, 8>; 122 123// FIXME: there are 72 read buffers and 44 write buffers. 124 125// (a folded load is an instruction that loads and does some operation) 126// Ex: ADDPD xmm,[mem]-> This instruction has two micro-ops 127// Instructions with folded loads are usually micro-fused, so they only appear 128// as two micro-ops. 129// a. load and 130// b. addpd 131// This multiclass is for folded loads for integer units. 132multiclass ZnWriteResPair<X86FoldableSchedWrite SchedRW, 133 list<ProcResourceKind> ExePorts, 134 int Lat, list<int> Res = [], int UOps = 1, 135 int LoadLat = 4, int LoadUOps = 1> { 136 // Register variant takes 1-cycle on Execution Port. 137 def : WriteRes<SchedRW, ExePorts> { 138 let Latency = Lat; 139 let ResourceCycles = Res; 140 let NumMicroOps = UOps; 141 } 142 143 // Memory variant also uses a cycle on ZnAGU 144 // adds LoadLat cycles to the latency (default = 4). 145 def : WriteRes<SchedRW.Folded, !listconcat([ZnAGU], ExePorts)> { 146 let Latency = !add(Lat, LoadLat); 147 let ResourceCycles = !if(!empty(Res), [], !listconcat([1], Res)); 148 let NumMicroOps = !add(UOps, LoadUOps); 149 } 150} 151 152// This multiclass is for folded loads for floating point units. 153multiclass ZnWriteResFpuPair<X86FoldableSchedWrite SchedRW, 154 list<ProcResourceKind> ExePorts, 155 int Lat, list<int> Res = [], int UOps = 1, 156 int LoadLat = 7, int LoadUOps = 0> { 157 // Register variant takes 1-cycle on Execution Port. 158 def : WriteRes<SchedRW, ExePorts> { 159 let Latency = Lat; 160 let ResourceCycles = Res; 161 let NumMicroOps = UOps; 162 } 163 164 // Memory variant also uses a cycle on ZnAGU 165 // adds LoadLat cycles to the latency (default = 7). 166 def : WriteRes<SchedRW.Folded, !listconcat([ZnAGU], ExePorts)> { 167 let Latency = !add(Lat, LoadLat); 168 let ResourceCycles = !if(!empty(Res), [], !listconcat([1], Res)); 169 let NumMicroOps = !add(UOps, LoadUOps); 170 } 171} 172 173// WriteRMW is set for instructions with Memory write 174// operation in codegen 175def : WriteRes<WriteRMW, [ZnAGU]>; 176 177def : WriteRes<WriteStore, [ZnAGU]>; 178def : WriteRes<WriteStoreNT, [ZnAGU]>; 179def : WriteRes<WriteMove, [ZnALU]>; 180def : WriteRes<WriteLoad, [ZnAGU]> { let Latency = 8; } 181 182def : WriteRes<WriteZero, []>; 183def : WriteRes<WriteLEA, [ZnALU]>; 184defm : ZnWriteResPair<WriteALU, [ZnALU], 1>; 185defm : ZnWriteResPair<WriteADC, [ZnALU], 1>; 186 187defm : ZnWriteResPair<WriteIMul8, [ZnALU1, ZnMultiplier], 4>; 188//defm : ZnWriteResPair<WriteIMul16, [ZnALU1, ZnMultiplier], 4>; 189//defm : ZnWriteResPair<WriteIMul16Imm, [ZnALU1, ZnMultiplier], 4>; 190//defm : ZnWriteResPair<WriteIMul16Reg, [ZnALU1, ZnMultiplier], 4>; 191//defm : ZnWriteResPair<WriteIMul32, [ZnALU1, ZnMultiplier], 4>; 192//defm : ZnWriteResPair<WriteIMul32Imm, [ZnALU1, ZnMultiplier], 4>; 193//defm : ZnWriteResPair<WriteIMul32Reg, [ZnALU1, ZnMultiplier], 4>; 194//defm : ZnWriteResPair<WriteIMul64, [ZnALU1, ZnMultiplier], 4, [1,1], 2>; 195//defm : ZnWriteResPair<WriteIMul64Imm, [ZnALU1, ZnMultiplier], 4, [1,1], 2>; 196//defm : ZnWriteResPair<WriteIMul64Reg, [ZnALU1, ZnMultiplier], 4, [1,1], 2>; 197 198defm : X86WriteRes<WriteBSWAP32, [ZnALU], 1, [4], 1>; 199defm : X86WriteRes<WriteBSWAP64, [ZnALU], 1, [4], 1>; 200defm : X86WriteRes<WriteCMPXCHG, [ZnALU], 1, [1], 1>; 201defm : X86WriteRes<WriteCMPXCHGRMW,[ZnALU,ZnAGU], 8, [1,1], 5>; 202defm : X86WriteRes<WriteXCHG, [ZnALU], 1, [2], 2>; 203 204defm : ZnWriteResPair<WriteShift, [ZnALU], 1>; 205defm : ZnWriteResPair<WriteShiftCL, [ZnALU], 1>; 206defm : ZnWriteResPair<WriteRotate, [ZnALU], 1>; 207defm : ZnWriteResPair<WriteRotateCL, [ZnALU], 1>; 208 209defm : X86WriteRes<WriteSHDrri, [ZnALU], 1, [1], 1>; 210defm : X86WriteResUnsupported<WriteSHDrrcl>; 211defm : X86WriteResUnsupported<WriteSHDmri>; 212defm : X86WriteResUnsupported<WriteSHDmrcl>; 213 214defm : ZnWriteResPair<WriteJump, [ZnALU], 1>; 215defm : ZnWriteResFpuPair<WriteCRC32, [ZnFPU0], 3>; 216 217defm : ZnWriteResPair<WriteCMOV, [ZnALU], 1>; 218def : WriteRes<WriteSETCC, [ZnALU]>; 219def : WriteRes<WriteSETCCStore, [ZnALU, ZnAGU]>; 220defm : X86WriteRes<WriteLAHFSAHF, [ZnALU], 2, [1], 2>; 221 222defm : X86WriteRes<WriteBitTest, [ZnALU], 1, [1], 1>; 223defm : X86WriteRes<WriteBitTestImmLd, [ZnALU,ZnAGU], 5, [1,1], 2>; 224defm : X86WriteRes<WriteBitTestRegLd, [ZnALU,ZnAGU], 5, [1,1], 2>; 225defm : X86WriteRes<WriteBitTestSet, [ZnALU], 2, [1], 2>; 226//defm : X86WriteRes<WriteBitTestSetImmLd, [ZnALU,ZnAGU], 5, [1,1], 2>; 227//defm : X86WriteRes<WriteBitTestSetRegLd, [ZnALU,ZnAGU], 5, [1,1], 2>; 228 229// Bit counts. 230defm : ZnWriteResPair<WriteBSF, [ZnALU], 3>; 231defm : ZnWriteResPair<WriteBSR, [ZnALU], 3>; 232defm : ZnWriteResPair<WriteLZCNT, [ZnALU], 2>; 233defm : ZnWriteResPair<WriteTZCNT, [ZnALU], 2>; 234defm : ZnWriteResPair<WritePOPCNT, [ZnALU], 1>; 235 236// Treat misc copies as a move. 237def : InstRW<[WriteMove], (instrs COPY)>; 238 239// BMI1 BEXTR/BLS, BMI2 BZHI 240defm : ZnWriteResPair<WriteBEXTR, [ZnALU], 1>; 241//defm : ZnWriteResPair<WriteBLS, [ZnALU], 2>; 242defm : ZnWriteResPair<WriteBZHI, [ZnALU], 1>; 243 244// IDIV 245defm : ZnWriteResPair<WriteDiv8, [ZnALU2, ZnDivider], 15, [1,15], 1>; 246defm : ZnWriteResPair<WriteDiv16, [ZnALU2, ZnDivider], 17, [1,17], 2>; 247defm : ZnWriteResPair<WriteDiv32, [ZnALU2, ZnDivider], 25, [1,25], 2>; 248defm : ZnWriteResPair<WriteDiv64, [ZnALU2, ZnDivider], 41, [1,41], 2>; 249defm : ZnWriteResPair<WriteIDiv8, [ZnALU2, ZnDivider], 15, [1,15], 1>; 250defm : ZnWriteResPair<WriteIDiv16, [ZnALU2, ZnDivider], 17, [1,17], 2>; 251defm : ZnWriteResPair<WriteIDiv32, [ZnALU2, ZnDivider], 25, [1,25], 2>; 252defm : ZnWriteResPair<WriteIDiv64, [ZnALU2, ZnDivider], 41, [1,41], 2>; 253 254// IMULH 255def : WriteRes<WriteIMulH, [ZnALU1, ZnMultiplier]>{ 256 let Latency = 4; 257} 258 259// Floating point operations 260defm : X86WriteRes<WriteFLoad, [ZnAGU], 8, [1], 1>; 261defm : X86WriteRes<WriteFLoadX, [ZnAGU], 8, [1], 1>; 262defm : X86WriteRes<WriteFLoadY, [ZnAGU], 8, [1], 1>; 263defm : X86WriteRes<WriteFMaskedLoad, [ZnAGU,ZnFPU01], 8, [1,1], 1>; 264defm : X86WriteRes<WriteFMaskedLoadY, [ZnAGU,ZnFPU01], 8, [1,2], 2>; 265defm : X86WriteRes<WriteFStore, [ZnAGU], 1, [1], 1>; 266defm : X86WriteRes<WriteFStoreX, [ZnAGU], 1, [1], 1>; 267defm : X86WriteRes<WriteFStoreY, [ZnAGU], 1, [1], 1>; 268defm : X86WriteRes<WriteFStoreNT, [ZnAGU,ZnFPU2], 8, [1,1], 1>; 269defm : X86WriteRes<WriteFStoreNTX, [ZnAGU], 1, [1], 1>; 270defm : X86WriteRes<WriteFStoreNTY, [ZnAGU], 1, [1], 1>; 271 272defm : X86WriteRes<WriteFMaskedStore32, [ZnAGU,ZnFPU01], 4, [1,1], 1>; 273defm : X86WriteRes<WriteFMaskedStore32Y, [ZnAGU,ZnFPU01], 5, [1,2], 2>; 274defm : X86WriteRes<WriteFMaskedStore64, [ZnAGU,ZnFPU01], 4, [1,1], 1>; 275defm : X86WriteRes<WriteFMaskedStore64Y, [ZnAGU,ZnFPU01], 5, [1,2], 2>; 276 277defm : X86WriteRes<WriteFMove, [ZnFPU], 1, [1], 1>; 278defm : X86WriteRes<WriteFMoveX, [ZnFPU], 1, [1], 1>; 279defm : X86WriteRes<WriteFMoveY, [ZnFPU], 1, [1], 1>; 280 281defm : ZnWriteResFpuPair<WriteFAdd, [ZnFPU0], 3>; 282defm : ZnWriteResFpuPair<WriteFAddX, [ZnFPU0], 3>; 283defm : ZnWriteResFpuPair<WriteFAddY, [ZnFPU0], 3>; 284defm : X86WriteResPairUnsupported<WriteFAddZ>; 285defm : ZnWriteResFpuPair<WriteFAdd64, [ZnFPU0], 3>; 286defm : ZnWriteResFpuPair<WriteFAdd64X, [ZnFPU0], 3>; 287defm : ZnWriteResFpuPair<WriteFAdd64Y, [ZnFPU0], 3>; 288defm : X86WriteResPairUnsupported<WriteFAdd64Z>; 289defm : ZnWriteResFpuPair<WriteFCmp, [ZnFPU0], 3>; 290defm : ZnWriteResFpuPair<WriteFCmpX, [ZnFPU0], 3>; 291defm : ZnWriteResFpuPair<WriteFCmpY, [ZnFPU0], 3>; 292defm : X86WriteResPairUnsupported<WriteFCmpZ>; 293defm : ZnWriteResFpuPair<WriteFCmp64, [ZnFPU0], 3>; 294defm : ZnWriteResFpuPair<WriteFCmp64X, [ZnFPU0], 3>; 295defm : ZnWriteResFpuPair<WriteFCmp64Y, [ZnFPU0], 3>; 296defm : X86WriteResPairUnsupported<WriteFCmp64Z>; 297defm : ZnWriteResFpuPair<WriteFCom, [ZnFPU0], 3>; 298defm : ZnWriteResFpuPair<WriteFComX, [ZnFPU0], 3>; 299defm : ZnWriteResFpuPair<WriteFBlend, [ZnFPU01], 1>; 300defm : ZnWriteResFpuPair<WriteFBlendY, [ZnFPU01], 1>; 301defm : X86WriteResPairUnsupported<WriteFBlendZ>; 302defm : ZnWriteResFpuPair<WriteFVarBlend, [ZnFPU01], 1>; 303defm : ZnWriteResFpuPair<WriteFVarBlendY,[ZnFPU01], 1>; 304defm : X86WriteResPairUnsupported<WriteFVarBlendZ>; 305defm : ZnWriteResFpuPair<WriteVarBlend, [ZnFPU0], 1>; 306defm : ZnWriteResFpuPair<WriteVarBlendY, [ZnFPU0], 1>; 307defm : X86WriteResPairUnsupported<WriteVarBlendZ>; 308defm : ZnWriteResFpuPair<WriteCvtSS2I, [ZnFPU3], 5>; 309defm : ZnWriteResFpuPair<WriteCvtPS2I, [ZnFPU3], 5>; 310defm : ZnWriteResFpuPair<WriteCvtPS2IY, [ZnFPU3], 5>; 311defm : X86WriteResPairUnsupported<WriteCvtPS2IZ>; 312defm : ZnWriteResFpuPair<WriteCvtSD2I, [ZnFPU3], 5>; 313defm : ZnWriteResFpuPair<WriteCvtPD2I, [ZnFPU3], 5>; 314defm : ZnWriteResFpuPair<WriteCvtPD2IY, [ZnFPU3], 5>; 315defm : X86WriteResPairUnsupported<WriteCvtPD2IZ>; 316defm : ZnWriteResFpuPair<WriteCvtI2SS, [ZnFPU3], 5>; 317defm : ZnWriteResFpuPair<WriteCvtI2PS, [ZnFPU3], 5>; 318defm : ZnWriteResFpuPair<WriteCvtI2PSY, [ZnFPU3], 5>; 319defm : X86WriteResPairUnsupported<WriteCvtI2PSZ>; 320defm : ZnWriteResFpuPair<WriteCvtI2SD, [ZnFPU3], 5>; 321defm : ZnWriteResFpuPair<WriteCvtI2PD, [ZnFPU3], 5>; 322defm : ZnWriteResFpuPair<WriteCvtI2PDY, [ZnFPU3], 5>; 323defm : X86WriteResPairUnsupported<WriteCvtI2PDZ>; 324defm : ZnWriteResFpuPair<WriteFDiv, [ZnFPU3], 15>; 325defm : ZnWriteResFpuPair<WriteFDivX, [ZnFPU3], 15>; 326//defm : ZnWriteResFpuPair<WriteFDivY, [ZnFPU3], 15>; 327defm : X86WriteResPairUnsupported<WriteFDivZ>; 328defm : ZnWriteResFpuPair<WriteFDiv64, [ZnFPU3], 15>; 329defm : ZnWriteResFpuPair<WriteFDiv64X, [ZnFPU3], 15>; 330//defm : ZnWriteResFpuPair<WriteFDiv64Y, [ZnFPU3], 15>; 331defm : X86WriteResPairUnsupported<WriteFDiv64Z>; 332defm : ZnWriteResFpuPair<WriteFSign, [ZnFPU3], 2>; 333defm : ZnWriteResFpuPair<WriteFRnd, [ZnFPU3], 4, [1], 1, 7, 1>; // FIXME: Should folds require 1 extra uops? 334defm : ZnWriteResFpuPair<WriteFRndY, [ZnFPU3], 4, [1], 1, 7, 1>; // FIXME: Should folds require 1 extra uops? 335defm : X86WriteResPairUnsupported<WriteFRndZ>; 336defm : ZnWriteResFpuPair<WriteFLogic, [ZnFPU], 1>; 337defm : ZnWriteResFpuPair<WriteFLogicY, [ZnFPU], 1>; 338defm : X86WriteResPairUnsupported<WriteFLogicZ>; 339defm : ZnWriteResFpuPair<WriteFTest, [ZnFPU], 1>; 340defm : ZnWriteResFpuPair<WriteFTestY, [ZnFPU], 1>; 341defm : X86WriteResPairUnsupported<WriteFTestZ>; 342defm : ZnWriteResFpuPair<WriteFShuffle, [ZnFPU12], 1>; 343defm : ZnWriteResFpuPair<WriteFShuffleY, [ZnFPU12], 1>; 344defm : X86WriteResPairUnsupported<WriteFShuffleZ>; 345defm : ZnWriteResFpuPair<WriteFVarShuffle, [ZnFPU12], 1>; 346defm : ZnWriteResFpuPair<WriteFVarShuffleY,[ZnFPU12], 1>; 347defm : X86WriteResPairUnsupported<WriteFVarShuffleZ>; 348defm : ZnWriteResFpuPair<WriteFMul, [ZnFPU01], 3, [1], 1, 7, 1>; 349defm : ZnWriteResFpuPair<WriteFMulX, [ZnFPU01], 3, [1], 1, 7, 1>; 350defm : ZnWriteResFpuPair<WriteFMulY, [ZnFPU01], 4, [1], 1, 7, 1>; 351defm : X86WriteResPairUnsupported<WriteFMulZ>; 352defm : ZnWriteResFpuPair<WriteFMul64, [ZnFPU01], 3, [1], 1, 7, 1>; 353defm : ZnWriteResFpuPair<WriteFMul64X, [ZnFPU01], 3, [1], 1, 7, 1>; 354defm : ZnWriteResFpuPair<WriteFMul64Y, [ZnFPU01], 4, [1], 1, 7, 1>; 355defm : X86WriteResPairUnsupported<WriteFMul64Z>; 356defm : ZnWriteResFpuPair<WriteFMA, [ZnFPU03], 5>; 357defm : ZnWriteResFpuPair<WriteFMAX, [ZnFPU03], 5>; 358defm : ZnWriteResFpuPair<WriteFMAY, [ZnFPU03], 5>; 359defm : X86WriteResPairUnsupported<WriteFMAZ>; 360defm : ZnWriteResFpuPair<WriteFRcp, [ZnFPU01], 5>; 361defm : ZnWriteResFpuPair<WriteFRcpX, [ZnFPU01], 5>; 362defm : ZnWriteResFpuPair<WriteFRcpY, [ZnFPU01], 5, [1], 1, 7, 2>; 363defm : X86WriteResPairUnsupported<WriteFRcpZ>; 364//defm : ZnWriteResFpuPair<WriteFRsqrt, [ZnFPU02], 5>; 365defm : ZnWriteResFpuPair<WriteFRsqrtX, [ZnFPU01], 5, [1], 1, 7, 1>; 366//defm : ZnWriteResFpuPair<WriteFRsqrtY, [ZnFPU01], 5, [2], 2>; 367defm : X86WriteResPairUnsupported<WriteFRsqrtZ>; 368defm : ZnWriteResFpuPair<WriteFSqrt, [ZnFPU3], 20, [20]>; 369defm : ZnWriteResFpuPair<WriteFSqrtX, [ZnFPU3], 20, [20]>; 370defm : ZnWriteResFpuPair<WriteFSqrtY, [ZnFPU3], 28, [28], 1, 7, 1>; 371defm : X86WriteResPairUnsupported<WriteFSqrtZ>; 372defm : ZnWriteResFpuPair<WriteFSqrt64, [ZnFPU3], 20, [20]>; 373defm : ZnWriteResFpuPair<WriteFSqrt64X, [ZnFPU3], 20, [20]>; 374defm : ZnWriteResFpuPair<WriteFSqrt64Y, [ZnFPU3], 40, [40], 1, 7, 1>; 375defm : X86WriteResPairUnsupported<WriteFSqrt64Z>; 376defm : ZnWriteResFpuPair<WriteFSqrt80, [ZnFPU3], 20, [20]>; 377 378// Vector integer operations which uses FPU units 379defm : X86WriteRes<WriteVecLoad, [ZnAGU], 8, [1], 1>; 380defm : X86WriteRes<WriteVecLoadX, [ZnAGU], 8, [1], 1>; 381defm : X86WriteRes<WriteVecLoadY, [ZnAGU], 8, [1], 1>; 382defm : X86WriteRes<WriteVecLoadNT, [ZnAGU], 8, [1], 1>; 383defm : X86WriteRes<WriteVecLoadNTY, [ZnAGU], 8, [1], 1>; 384defm : X86WriteRes<WriteVecMaskedLoad, [ZnAGU,ZnFPU01], 8, [1,2], 2>; 385defm : X86WriteRes<WriteVecMaskedLoadY, [ZnAGU,ZnFPU01], 9, [1,3], 2>; 386defm : X86WriteRes<WriteVecStore, [ZnAGU], 1, [1], 1>; 387defm : X86WriteRes<WriteVecStoreX, [ZnAGU], 1, [1], 1>; 388defm : X86WriteRes<WriteVecStoreY, [ZnAGU], 1, [1], 1>; 389defm : X86WriteRes<WriteVecStoreNT, [ZnAGU], 1, [1], 1>; 390defm : X86WriteRes<WriteVecStoreNTY, [ZnAGU], 1, [1], 1>; 391defm : X86WriteRes<WriteVecMaskedStore32, [ZnAGU,ZnFPU01], 4, [1,1], 1>; 392defm : X86WriteRes<WriteVecMaskedStore32Y, [ZnAGU,ZnFPU01], 5, [1,2], 2>; 393defm : X86WriteRes<WriteVecMaskedStore64, [ZnAGU,ZnFPU01], 4, [1,1], 1>; 394defm : X86WriteRes<WriteVecMaskedStore64Y, [ZnAGU,ZnFPU01], 5, [1,2], 2>; 395defm : X86WriteRes<WriteVecMove, [ZnFPU], 1, [1], 1>; 396defm : X86WriteRes<WriteVecMoveX, [ZnFPU], 1, [1], 1>; 397defm : X86WriteRes<WriteVecMoveY, [ZnFPU], 2, [1], 2>; 398defm : X86WriteRes<WriteVecMoveToGpr, [ZnFPU2], 2, [1], 1>; 399defm : X86WriteRes<WriteVecMoveFromGpr, [ZnFPU2], 3, [1], 1>; 400defm : X86WriteRes<WriteEMMS, [ZnFPU], 2, [1], 1>; 401 402defm : ZnWriteResFpuPair<WriteVecShift, [ZnFPU], 1>; 403defm : ZnWriteResFpuPair<WriteVecShiftX, [ZnFPU2], 1>; 404defm : ZnWriteResFpuPair<WriteVecShiftY, [ZnFPU2], 2>; 405defm : X86WriteResPairUnsupported<WriteVecShiftZ>; 406defm : ZnWriteResFpuPair<WriteVecShiftImm, [ZnFPU], 1>; 407defm : ZnWriteResFpuPair<WriteVecShiftImmX, [ZnFPU], 1>; 408defm : ZnWriteResFpuPair<WriteVecShiftImmY, [ZnFPU], 1>; 409defm : X86WriteResPairUnsupported<WriteVecShiftImmZ>; 410defm : ZnWriteResFpuPair<WriteVecLogic, [ZnFPU], 1>; 411defm : ZnWriteResFpuPair<WriteVecLogicX, [ZnFPU], 1>; 412defm : ZnWriteResFpuPair<WriteVecLogicY, [ZnFPU], 1>; 413defm : X86WriteResPairUnsupported<WriteVecLogicZ>; 414defm : ZnWriteResFpuPair<WriteVecTest, [ZnFPU12], 1, [2], 1, 7, 1>; 415defm : ZnWriteResFpuPair<WriteVecTestY, [ZnFPU12], 1, [2], 1, 7, 1>; 416defm : X86WriteResPairUnsupported<WriteVecTestZ>; 417defm : ZnWriteResFpuPair<WriteVecALU, [ZnFPU], 1>; 418defm : ZnWriteResFpuPair<WriteVecALUX, [ZnFPU], 1>; 419defm : ZnWriteResFpuPair<WriteVecALUY, [ZnFPU], 1>; 420defm : X86WriteResPairUnsupported<WriteVecALUZ>; 421defm : ZnWriteResFpuPair<WriteVecIMul, [ZnFPU0], 4>; 422defm : ZnWriteResFpuPair<WriteVecIMulX, [ZnFPU0], 4>; 423defm : ZnWriteResFpuPair<WriteVecIMulY, [ZnFPU0], 4>; 424defm : X86WriteResPairUnsupported<WriteVecIMulZ>; 425defm : ZnWriteResFpuPair<WritePMULLD, [ZnFPU0], 4, [1], 1, 7, 1>; // FIXME 426defm : ZnWriteResFpuPair<WritePMULLDY, [ZnFPU0], 5, [2], 1, 7, 1>; // FIXME 427defm : X86WriteResPairUnsupported<WritePMULLDZ>; 428defm : ZnWriteResFpuPair<WriteShuffle, [ZnFPU], 1>; 429defm : ZnWriteResFpuPair<WriteShuffleX, [ZnFPU], 1>; 430defm : ZnWriteResFpuPair<WriteShuffleY, [ZnFPU], 1>; 431defm : X86WriteResPairUnsupported<WriteShuffleZ>; 432defm : ZnWriteResFpuPair<WriteVarShuffle, [ZnFPU], 1>; 433defm : ZnWriteResFpuPair<WriteVarShuffleX,[ZnFPU], 1>; 434defm : ZnWriteResFpuPair<WriteVarShuffleY,[ZnFPU], 1>; 435defm : X86WriteResPairUnsupported<WriteVarShuffleZ>; 436defm : ZnWriteResFpuPair<WriteBlend, [ZnFPU01], 1>; 437defm : ZnWriteResFpuPair<WriteBlendY, [ZnFPU01], 1>; 438defm : X86WriteResPairUnsupported<WriteBlendZ>; 439defm : ZnWriteResFpuPair<WriteShuffle256, [ZnFPU], 2>; 440defm : ZnWriteResFpuPair<WriteVarShuffle256, [ZnFPU], 2>; 441defm : ZnWriteResFpuPair<WritePSADBW, [ZnFPU0], 3>; 442defm : ZnWriteResFpuPair<WritePSADBWX, [ZnFPU0], 3>; 443defm : ZnWriteResFpuPair<WritePSADBWY, [ZnFPU0], 3>; 444defm : X86WriteResPairUnsupported<WritePSADBWZ>; 445defm : ZnWriteResFpuPair<WritePHMINPOS, [ZnFPU0], 4>; 446 447// Vector Shift Operations 448defm : ZnWriteResFpuPair<WriteVarVecShift, [ZnFPU12], 1>; 449defm : ZnWriteResFpuPair<WriteVarVecShiftY, [ZnFPU12], 1>; 450defm : X86WriteResPairUnsupported<WriteVarVecShiftZ>; 451 452// Vector insert/extract operations. 453defm : ZnWriteResFpuPair<WriteVecInsert, [ZnFPU], 1>; 454 455def : WriteRes<WriteVecExtract, [ZnFPU12, ZnFPU2]> { 456 let Latency = 2; 457 let ResourceCycles = [1, 2]; 458} 459def : WriteRes<WriteVecExtractSt, [ZnAGU, ZnFPU12, ZnFPU2]> { 460 let Latency = 5; 461 let NumMicroOps = 2; 462 let ResourceCycles = [1, 2, 3]; 463} 464 465// MOVMSK Instructions. 466def : WriteRes<WriteFMOVMSK, [ZnFPU2]>; 467def : WriteRes<WriteMMXMOVMSK, [ZnFPU2]>; 468def : WriteRes<WriteVecMOVMSK, [ZnFPU2]>; 469 470def : WriteRes<WriteVecMOVMSKY, [ZnFPU2]> { 471 let NumMicroOps = 2; 472 let Latency = 2; 473 let ResourceCycles = [2]; 474} 475 476// AES Instructions. 477defm : ZnWriteResFpuPair<WriteAESDecEnc, [ZnFPU01], 4>; 478defm : ZnWriteResFpuPair<WriteAESIMC, [ZnFPU01], 4>; 479defm : ZnWriteResFpuPair<WriteAESKeyGen, [ZnFPU01], 4>; 480 481def : WriteRes<WriteFence, [ZnAGU]>; 482def : WriteRes<WriteNop, []>; 483 484// Following instructions with latency=100 are microcoded. 485// We set long latency so as to block the entire pipeline. 486defm : ZnWriteResFpuPair<WriteFShuffle256, [ZnFPU], 100>; 487defm : ZnWriteResFpuPair<WriteFVarShuffle256, [ZnFPU], 100>; 488 489// Microcoded Instructions 490def ZnWriteMicrocoded : SchedWriteRes<[]> { 491 let Latency = 100; 492} 493 494def : SchedAlias<WriteMicrocoded, ZnWriteMicrocoded>; 495def : SchedAlias<WriteFCMOV, ZnWriteMicrocoded>; 496def : SchedAlias<WriteSystem, ZnWriteMicrocoded>; 497def : SchedAlias<WriteMPSAD, ZnWriteMicrocoded>; 498def : SchedAlias<WriteMPSADY, ZnWriteMicrocoded>; 499def : SchedAlias<WriteMPSADLd, ZnWriteMicrocoded>; 500def : SchedAlias<WriteMPSADYLd, ZnWriteMicrocoded>; 501def : SchedAlias<WriteCLMul, ZnWriteMicrocoded>; 502def : SchedAlias<WriteCLMulLd, ZnWriteMicrocoded>; 503def : SchedAlias<WritePCmpIStrM, ZnWriteMicrocoded>; 504def : SchedAlias<WritePCmpIStrMLd, ZnWriteMicrocoded>; 505def : SchedAlias<WritePCmpEStrI, ZnWriteMicrocoded>; 506def : SchedAlias<WritePCmpEStrILd, ZnWriteMicrocoded>; 507def : SchedAlias<WritePCmpEStrM, ZnWriteMicrocoded>; 508def : SchedAlias<WritePCmpEStrMLd, ZnWriteMicrocoded>; 509def : SchedAlias<WritePCmpIStrI, ZnWriteMicrocoded>; 510def : SchedAlias<WritePCmpIStrILd, ZnWriteMicrocoded>; 511def : SchedAlias<WriteLDMXCSR, ZnWriteMicrocoded>; 512def : SchedAlias<WriteSTMXCSR, ZnWriteMicrocoded>; 513 514//=== Regex based InstRW ===// 515// Notation: 516// - r: register. 517// - m = memory. 518// - i = immediate 519// - mm: 64 bit mmx register. 520// - x = 128 bit xmm register. 521// - (x)mm = mmx or xmm register. 522// - y = 256 bit ymm register. 523// - v = any vector register. 524 525//=== Integer Instructions ===// 526//-- Move instructions --// 527// MOV. 528// r16,m. 529def : InstRW<[WriteALULd, ReadAfterLd], (instrs MOV16rm)>; 530 531// MOVSX, MOVZX. 532// r,m. 533def : InstRW<[WriteLoad], (instregex "MOV(S|Z)X32rm(8|16)")>; 534 535// XCHG. 536// r,m. 537def ZnWriteXCHGrm : SchedWriteRes<[ZnAGU, ZnALU]> { 538 let Latency = 5; 539 let NumMicroOps = 2; 540} 541def : InstRW<[ZnWriteXCHGrm, ReadAfterLd], (instregex "XCHG(8|16|32|64)rm")>; 542 543def : InstRW<[WriteMicrocoded], (instrs XLAT)>; 544 545// POP16. 546// r. 547def ZnWritePop16r : SchedWriteRes<[ZnAGU]>{ 548 let Latency = 5; 549 let NumMicroOps = 2; 550} 551def : InstRW<[ZnWritePop16r], (instrs POP16rmm)>; 552def : InstRW<[WriteMicrocoded], (instregex "POPF(16|32)")>; 553def : InstRW<[WriteMicrocoded], (instregex "POPA(16|32)")>; 554 555 556// PUSH. 557// r. Has default values. 558// m. 559def ZnWritePUSH : SchedWriteRes<[ZnAGU]>{ 560 let Latency = 4; 561} 562def : InstRW<[ZnWritePUSH], (instregex "PUSH(16|32)rmm")>; 563 564//PUSHF 565def : InstRW<[WriteMicrocoded], (instregex "PUSHF(16|32)")>; 566 567// PUSHA. 568def ZnWritePushA : SchedWriteRes<[ZnAGU]> { 569 let Latency = 8; 570} 571def : InstRW<[ZnWritePushA], (instregex "PUSHA(16|32)")>; 572 573//LAHF 574def : InstRW<[WriteMicrocoded], (instrs LAHF)>; 575 576// MOVBE. 577// r,m. 578def ZnWriteMOVBE : SchedWriteRes<[ZnAGU, ZnALU]> { 579 let Latency = 5; 580} 581def : InstRW<[ZnWriteMOVBE, ReadAfterLd], (instregex "MOVBE(16|32|64)rm")>; 582 583// m16,r16. 584def : InstRW<[ZnWriteMOVBE], (instregex "MOVBE(16|32|64)mr")>; 585 586//-- Arithmetic instructions --// 587 588// ADD SUB. 589// m,r/i. 590def : InstRW<[WriteALULd], (instregex "(ADD|SUB)(8|16|32|64)m(r|i)", 591 "(ADD|SUB)(8|16|32|64)mi8", 592 "(ADD|SUB)64mi32")>; 593 594// ADC SBB. 595// m,r/i. 596def : InstRW<[WriteALULd], 597 (instregex "(ADC|SBB)(8|16|32|64)m(r|i)", 598 "(ADC|SBB)(16|32|64)mi8", 599 "(ADC|SBB)64mi32")>; 600 601// INC DEC NOT NEG. 602// m. 603def : InstRW<[WriteALULd], 604 (instregex "(INC|DEC|NOT|NEG)(8|16|32|64)m")>; 605 606// MUL IMUL. 607// r16. 608def ZnWriteMul16 : SchedWriteRes<[ZnALU1, ZnMultiplier]> { 609 let Latency = 3; 610} 611def : SchedAlias<WriteIMul16, ZnWriteMul16>; 612def : SchedAlias<WriteIMul16Imm, ZnWriteMul16>; // TODO: is this right? 613def : SchedAlias<WriteIMul16Reg, ZnWriteMul16>; // TODO: is this right? 614def : SchedAlias<WriteIMul16ImmLd, ZnWriteMul16>; // TODO: this is definitely wrong but matches what the instregex did. 615def : SchedAlias<WriteIMul16RegLd, ZnWriteMul16>; // TODO: this is definitely wrong but matches what the instregex did. 616 617// m16. 618def ZnWriteMul16Ld : SchedWriteRes<[ZnAGU, ZnALU1, ZnMultiplier]> { 619 let Latency = 8; 620} 621def : SchedAlias<WriteIMul16Ld, ZnWriteMul16Ld>; 622 623// r32. 624def ZnWriteMul32 : SchedWriteRes<[ZnALU1, ZnMultiplier]> { 625 let Latency = 3; 626} 627def : SchedAlias<WriteIMul32, ZnWriteMul32>; 628def : SchedAlias<WriteIMul32Imm, ZnWriteMul32>; // TODO: is this right? 629def : SchedAlias<WriteIMul32Reg, ZnWriteMul32>; // TODO: is this right? 630def : SchedAlias<WriteIMul32ImmLd, ZnWriteMul32>; // TODO: this is definitely wrong but matches what the instregex did. 631def : SchedAlias<WriteIMul32RegLd, ZnWriteMul32>; // TODO: this is definitely wrong but matches what the instregex did. 632 633// m32. 634def ZnWriteMul32Ld : SchedWriteRes<[ZnAGU, ZnALU1, ZnMultiplier]> { 635 let Latency = 8; 636} 637def : SchedAlias<WriteIMul32Ld, ZnWriteMul32Ld>; 638 639// r64. 640def ZnWriteMul64 : SchedWriteRes<[ZnALU1, ZnMultiplier]> { 641 let Latency = 4; 642 let NumMicroOps = 2; 643} 644def : SchedAlias<WriteIMul64, ZnWriteMul64>; 645def : SchedAlias<WriteIMul64Imm, ZnWriteMul64>; // TODO: is this right? 646def : SchedAlias<WriteIMul64Reg, ZnWriteMul64>; // TODO: is this right? 647def : SchedAlias<WriteIMul64ImmLd, ZnWriteMul64>; // TODO: this is definitely wrong but matches what the instregex did. 648def : SchedAlias<WriteIMul64RegLd, ZnWriteMul64>; // TODO: this is definitely wrong but matches what the instregex did. 649 650// m64. 651def ZnWriteMul64Ld : SchedWriteRes<[ZnAGU, ZnALU1, ZnMultiplier]> { 652 let Latency = 9; 653 let NumMicroOps = 2; 654} 655def : SchedAlias<WriteIMul64Ld, ZnWriteMul64Ld>; 656 657// MULX. 658// r32,r32,r32. 659def ZnWriteMulX32 : SchedWriteRes<[ZnALU1, ZnMultiplier]> { 660 let Latency = 3; 661 let ResourceCycles = [1, 2]; 662} 663def : InstRW<[ZnWriteMulX32], (instrs MULX32rr)>; 664 665// r32,r32,m32. 666def ZnWriteMulX32Ld : SchedWriteRes<[ZnAGU, ZnALU1, ZnMultiplier]> { 667 let Latency = 8; 668 let ResourceCycles = [1, 2, 2]; 669} 670def : InstRW<[ZnWriteMulX32Ld, ReadAfterLd], (instrs MULX32rm)>; 671 672// r64,r64,r64. 673def ZnWriteMulX64 : SchedWriteRes<[ZnALU1]> { 674 let Latency = 3; 675} 676def : InstRW<[ZnWriteMulX64], (instrs MULX64rr)>; 677 678// r64,r64,m64. 679def ZnWriteMulX64Ld : SchedWriteRes<[ZnAGU, ZnALU1, ZnMultiplier]> { 680 let Latency = 8; 681} 682def : InstRW<[ZnWriteMulX64Ld, ReadAfterLd], (instrs MULX64rm)>; 683 684//-- Control transfer instructions --// 685 686// J(E|R)CXZ. 687def ZnWriteJCXZ : SchedWriteRes<[ZnALU03]>; 688def : InstRW<[ZnWriteJCXZ], (instrs JCXZ, JECXZ, JRCXZ)>; 689 690// INTO 691def : InstRW<[WriteMicrocoded], (instrs INTO)>; 692 693// LOOP. 694def ZnWriteLOOP : SchedWriteRes<[ZnALU03]>; 695def : InstRW<[ZnWriteLOOP], (instrs LOOP)>; 696 697// LOOP(N)E, LOOP(N)Z 698def ZnWriteLOOPE : SchedWriteRes<[ZnALU03]>; 699def : InstRW<[ZnWriteLOOPE], (instrs LOOPE, LOOPNE)>; 700 701// CALL. 702// r. 703def ZnWriteCALLr : SchedWriteRes<[ZnAGU, ZnALU03]>; 704def : InstRW<[ZnWriteCALLr], (instregex "CALL(16|32)r")>; 705 706def : InstRW<[WriteMicrocoded], (instregex "CALL(16|32)m")>; 707 708// RET. 709def ZnWriteRET : SchedWriteRes<[ZnALU03]> { 710 let NumMicroOps = 2; 711} 712def : InstRW<[ZnWriteRET], (instregex "RET(L|Q|W)", "LRET(L|Q|W)", 713 "IRET(16|32|64)")>; 714 715//-- Logic instructions --// 716 717// AND OR XOR. 718// m,r/i. 719def : InstRW<[WriteALULd], 720 (instregex "(AND|OR|XOR)(8|16|32|64)m(r|i)", 721 "(AND|OR|XOR)(8|16|32|64)mi8", "(AND|OR|XOR)64mi32")>; 722 723// Define ALU latency variants 724def ZnWriteALULat2 : SchedWriteRes<[ZnALU]> { 725 let Latency = 2; 726} 727def ZnWriteALULat2Ld : SchedWriteRes<[ZnAGU, ZnALU]> { 728 let Latency = 6; 729} 730 731// BTR BTS BTC. 732// m,r,i. 733def ZnWriteBTRSCm : SchedWriteRes<[ZnAGU, ZnALU]> { 734 let Latency = 6; 735 let NumMicroOps = 2; 736} 737// m,r,i. 738def : SchedAlias<WriteBitTestSetImmRMW, ZnWriteBTRSCm>; 739def : SchedAlias<WriteBitTestSetRegRMW, ZnWriteBTRSCm>; 740 741// BLSI BLSMSK BLSR. 742// r,r. 743def : SchedAlias<WriteBLS, ZnWriteALULat2>; 744// r,m. 745def : SchedAlias<WriteBLSLd, ZnWriteALULat2Ld>; 746 747// CLD STD. 748def : InstRW<[WriteALU], (instrs STD, CLD)>; 749 750// PDEP PEXT. 751// r,r,r. 752def : InstRW<[WriteMicrocoded], (instregex "PDEP(32|64)rr", "PEXT(32|64)rr")>; 753// r,r,m. 754def : InstRW<[WriteMicrocoded], (instregex "PDEP(32|64)rm", "PEXT(32|64)rm")>; 755 756// RCR RCL. 757// m,i. 758def : InstRW<[WriteMicrocoded], (instregex "RC(R|L)(8|16|32|64)m(1|i|CL)")>; 759 760// SHR SHL SAR. 761// m,i. 762def : InstRW<[WriteShiftLd], (instregex "S(A|H)(R|L)(8|16|32|64)m(i|1)")>; 763 764// SHRD SHLD. 765// m,r 766def : InstRW<[WriteShiftLd], (instregex "SH(R|L)D(16|32|64)mri8")>; 767 768// r,r,cl. 769def : InstRW<[WriteMicrocoded], (instregex "SH(R|L)D(16|32|64)rrCL")>; 770 771// m,r,cl. 772def : InstRW<[WriteMicrocoded], (instregex "SH(R|L)D(16|32|64)mrCL")>; 773 774//-- Misc instructions --// 775// CMPXCHG8B. 776def ZnWriteCMPXCHG8B : SchedWriteRes<[ZnAGU, ZnALU]> { 777 let NumMicroOps = 18; 778} 779def : InstRW<[ZnWriteCMPXCHG8B], (instrs CMPXCHG8B)>; 780 781def : InstRW<[WriteMicrocoded], (instrs CMPXCHG16B)>; 782 783// LEAVE 784def ZnWriteLEAVE : SchedWriteRes<[ZnALU, ZnAGU]> { 785 let Latency = 8; 786 let NumMicroOps = 2; 787} 788def : InstRW<[ZnWriteLEAVE], (instregex "LEAVE")>; 789 790// PAUSE. 791def : InstRW<[WriteMicrocoded], (instrs PAUSE)>; 792 793// RDTSC. 794def : InstRW<[WriteMicrocoded], (instregex "RDTSC")>; 795 796// RDPMC. 797def : InstRW<[WriteMicrocoded], (instrs RDPMC)>; 798 799// RDRAND. 800def : InstRW<[WriteMicrocoded], (instrs RDRAND16r, RDRAND32r, RDRAND64r)>; 801 802// XGETBV. 803def : InstRW<[WriteMicrocoded], (instrs XGETBV)>; 804 805//-- String instructions --// 806// CMPS. 807def : InstRW<[WriteMicrocoded], (instregex "CMPS(B|L|Q|W)")>; 808 809// LODSB/W. 810def : InstRW<[WriteMicrocoded], (instregex "LODS(B|W)")>; 811 812// LODSD/Q. 813def : InstRW<[WriteMicrocoded], (instregex "LODS(L|Q)")>; 814 815// MOVS. 816def : InstRW<[WriteMicrocoded], (instregex "MOVS(B|L|Q|W)")>; 817 818// SCAS. 819def : InstRW<[WriteMicrocoded], (instregex "SCAS(B|W|L|Q)")>; 820 821// STOS 822def : InstRW<[WriteMicrocoded], (instregex "STOS(B|L|Q|W)")>; 823 824// XADD. 825def ZnXADD : SchedWriteRes<[ZnALU]>; 826def : InstRW<[ZnXADD], (instregex "XADD(8|16|32|64)rr")>; 827def : InstRW<[WriteMicrocoded], (instregex "XADD(8|16|32|64)rm")>; 828 829//=== Floating Point x87 Instructions ===// 830//-- Move instructions --// 831 832def ZnWriteFLDr : SchedWriteRes<[ZnFPU13]> ; 833 834def ZnWriteSTr: SchedWriteRes<[ZnFPU23]> { 835 let Latency = 5; 836 let NumMicroOps = 2; 837} 838 839// LD_F. 840// r. 841def : InstRW<[ZnWriteFLDr], (instrs LD_Frr)>; 842 843// m. 844def ZnWriteLD_F80m : SchedWriteRes<[ZnAGU, ZnFPU13]> { 845 let NumMicroOps = 2; 846} 847def : InstRW<[ZnWriteLD_F80m], (instrs LD_F80m)>; 848 849// FBLD. 850def : InstRW<[WriteMicrocoded], (instrs FBLDm)>; 851 852// FST(P). 853// r. 854def : InstRW<[ZnWriteSTr], (instregex "ST_(F|FP)rr")>; 855 856// m80. 857def ZnWriteST_FP80m : SchedWriteRes<[ZnAGU, ZnFPU23]> { 858 let Latency = 5; 859} 860def : InstRW<[ZnWriteST_FP80m], (instrs ST_FP80m)>; 861 862// FBSTP. 863// m80. 864def : InstRW<[WriteMicrocoded], (instrs FBSTPm)>; 865 866def ZnWriteFXCH : SchedWriteRes<[ZnFPU]>; 867 868// FXCHG. 869def : InstRW<[ZnWriteFXCH], (instrs XCH_F)>; 870 871// FILD. 872def ZnWriteFILD : SchedWriteRes<[ZnAGU, ZnFPU3]> { 873 let Latency = 11; 874 let NumMicroOps = 2; 875} 876def : InstRW<[ZnWriteFILD], (instregex "ILD_F(16|32|64)m")>; 877 878// FIST(P) FISTTP. 879def ZnWriteFIST : SchedWriteRes<[ZnAGU, ZnFPU23]> { 880 let Latency = 12; 881} 882def : InstRW<[ZnWriteFIST], (instregex "IS(T|TT)_(F|FP)(16|32|64)m")>; 883 884def ZnWriteFPU13 : SchedWriteRes<[ZnAGU, ZnFPU13]> { 885 let Latency = 8; 886} 887 888def ZnWriteFPU3 : SchedWriteRes<[ZnAGU, ZnFPU3]> { 889 let Latency = 11; 890} 891 892// FLDZ. 893def : SchedAlias<WriteFLD0, ZnWriteFPU13>; 894 895// FLD1. 896def : SchedAlias<WriteFLD1, ZnWriteFPU3>; 897 898// FLDPI FLDL2E etc. 899def : SchedAlias<WriteFLDC, ZnWriteFPU3>; 900 901// FNSTSW. 902// AX. 903def : InstRW<[WriteMicrocoded], (instrs FNSTSW16r)>; 904 905// m16. 906def : InstRW<[WriteMicrocoded], (instrs FNSTSWm)>; 907 908// FLDCW. 909def : InstRW<[WriteMicrocoded], (instrs FLDCW16m)>; 910 911// FNSTCW. 912def : InstRW<[WriteMicrocoded], (instrs FNSTCW16m)>; 913 914// FINCSTP FDECSTP. 915def : InstRW<[ZnWriteFPU3], (instrs FINCSTP, FDECSTP)>; 916 917// FFREE. 918def : InstRW<[ZnWriteFPU3], (instregex "FFREE")>; 919 920// FNSAVE. 921def : InstRW<[WriteMicrocoded], (instrs FSAVEm)>; 922 923// FRSTOR. 924def : InstRW<[WriteMicrocoded], (instrs FRSTORm)>; 925 926//-- Arithmetic instructions --// 927 928def ZnWriteFPU3Lat1 : SchedWriteRes<[ZnFPU3]> ; 929 930def ZnWriteFPU0Lat1 : SchedWriteRes<[ZnFPU0]> ; 931 932def ZnWriteFPU0Lat1Ld : SchedWriteRes<[ZnAGU, ZnFPU0]> { 933 let Latency = 8; 934} 935 936// FCHS. 937def : InstRW<[ZnWriteFPU3Lat1], (instregex "CHS_F")>; 938 939// FCOM(P) FUCOM(P). 940// r. 941def : InstRW<[ZnWriteFPU0Lat1], (instregex "COM(P?)_FST0r", "UCOM_F(P?)r")>; 942// m. 943def : InstRW<[ZnWriteFPU0Lat1Ld], (instregex "FCOM(P?)(32|64)m")>; 944 945// FCOMPP FUCOMPP. 946// r. 947def : InstRW<[ZnWriteFPU0Lat1], (instrs FCOMPP, UCOM_FPPr)>; 948 949def ZnWriteFPU02 : SchedWriteRes<[ZnAGU, ZnFPU02]> 950{ 951 let Latency = 9; 952} 953 954// FCOMI(P) FUCOMI(P). 955// m. 956def : InstRW<[ZnWriteFPU02], (instrs COM_FIPr, COM_FIr, UCOM_FIPr, UCOM_FIr)>; 957 958def ZnWriteFPU03 : SchedWriteRes<[ZnAGU, ZnFPU03]> 959{ 960 let Latency = 12; 961 let NumMicroOps = 2; 962 let ResourceCycles = [1,3]; 963} 964 965// FICOM(P). 966def : InstRW<[ZnWriteFPU03], (instregex "FICOM(P?)(16|32)m")>; 967 968// FTST. 969def : InstRW<[ZnWriteFPU0Lat1], (instregex "TST_F")>; 970 971// FXAM. 972def : InstRW<[ZnWriteFPU3Lat1], (instrs FXAM)>; 973 974// FPREM. 975def : InstRW<[WriteMicrocoded], (instrs FPREM)>; 976 977// FPREM1. 978def : InstRW<[WriteMicrocoded], (instrs FPREM1)>; 979 980// FRNDINT. 981def : InstRW<[WriteMicrocoded], (instrs FRNDINT)>; 982 983// FSCALE. 984def : InstRW<[WriteMicrocoded], (instrs FSCALE)>; 985 986// FXTRACT. 987def : InstRW<[WriteMicrocoded], (instrs FXTRACT)>; 988 989// FNOP. 990def : InstRW<[ZnWriteFPU0Lat1], (instrs FNOP)>; 991 992// WAIT. 993def : InstRW<[ZnWriteFPU0Lat1], (instrs WAIT)>; 994 995// FNCLEX. 996def : InstRW<[WriteMicrocoded], (instrs FNCLEX)>; 997 998// FNINIT. 999def : InstRW<[WriteMicrocoded], (instrs FNINIT)>; 1000 1001//=== Integer MMX and XMM Instructions ===// 1002 1003// PACKSSWB/DW. 1004// mm <- mm. 1005def ZnWriteFPU12 : SchedWriteRes<[ZnFPU12]> ; 1006def ZnWriteFPU12Y : SchedWriteRes<[ZnFPU12]> { 1007 let NumMicroOps = 2; 1008} 1009def ZnWriteFPU12m : SchedWriteRes<[ZnAGU, ZnFPU12]> ; 1010def ZnWriteFPU12Ym : SchedWriteRes<[ZnAGU, ZnFPU12]> { 1011 let Latency = 8; 1012 let NumMicroOps = 2; 1013} 1014 1015def : InstRW<[ZnWriteFPU12], (instrs MMX_PACKSSDWirr, 1016 MMX_PACKSSWBirr, 1017 MMX_PACKUSWBirr)>; 1018def : InstRW<[ZnWriteFPU12m], (instrs MMX_PACKSSDWirm, 1019 MMX_PACKSSWBirm, 1020 MMX_PACKUSWBirm)>; 1021 1022// VPMOVSX/ZX BW BD BQ WD WQ DQ. 1023// y <- x. 1024def : InstRW<[ZnWriteFPU12Y], (instregex "VPMOV(SX|ZX)(BW|BD|BQ|WD|WQ|DQ)Yrr")>; 1025def : InstRW<[ZnWriteFPU12Ym], (instregex "VPMOV(SX|ZX)(BW|BD|BQ|WD|WQ|DQ)Yrm")>; 1026 1027def ZnWriteFPU013 : SchedWriteRes<[ZnFPU013]> ; 1028def ZnWriteFPU013Y : SchedWriteRes<[ZnFPU013]> { 1029 let Latency = 2; 1030} 1031def ZnWriteFPU013m : SchedWriteRes<[ZnAGU, ZnFPU013]> { 1032 let Latency = 8; 1033 let NumMicroOps = 2; 1034} 1035def ZnWriteFPU013Ld : SchedWriteRes<[ZnAGU, ZnFPU013]> { 1036 let Latency = 8; 1037 let NumMicroOps = 2; 1038} 1039def ZnWriteFPU013LdY : SchedWriteRes<[ZnAGU, ZnFPU013]> { 1040 let Latency = 9; 1041 let NumMicroOps = 2; 1042} 1043 1044// PBLENDW. 1045// x,x,i / v,v,v,i 1046def : InstRW<[ZnWriteFPU013], (instregex "(V?)PBLENDWrri")>; 1047// ymm 1048def : InstRW<[ZnWriteFPU013Y], (instrs VPBLENDWYrri)>; 1049 1050// x,m,i / v,v,m,i 1051def : InstRW<[ZnWriteFPU013Ld], (instregex "(V?)PBLENDWrmi")>; 1052// y,m,i 1053def : InstRW<[ZnWriteFPU013LdY], (instrs VPBLENDWYrmi)>; 1054 1055def ZnWriteFPU01 : SchedWriteRes<[ZnFPU01]> ; 1056def ZnWriteFPU01Y : SchedWriteRes<[ZnFPU01]> { 1057 let NumMicroOps = 2; 1058} 1059 1060// VPBLENDD. 1061// v,v,v,i. 1062def : InstRW<[ZnWriteFPU01], (instrs VPBLENDDrri)>; 1063// ymm 1064def : InstRW<[ZnWriteFPU01Y], (instrs VPBLENDDYrri)>; 1065 1066// v,v,m,i 1067def ZnWriteFPU01Op2 : SchedWriteRes<[ZnAGU, ZnFPU01]> { 1068 let NumMicroOps = 2; 1069 let Latency = 8; 1070 let ResourceCycles = [1, 2]; 1071} 1072def ZnWriteFPU01Op2Y : SchedWriteRes<[ZnAGU, ZnFPU01]> { 1073 let NumMicroOps = 2; 1074 let Latency = 9; 1075 let ResourceCycles = [1, 3]; 1076} 1077def : InstRW<[ZnWriteFPU01Op2], (instrs VPBLENDDrmi)>; 1078def : InstRW<[ZnWriteFPU01Op2Y], (instrs VPBLENDDYrmi)>; 1079 1080// MASKMOVQ. 1081def : InstRW<[WriteMicrocoded], (instregex "MMX_MASKMOVQ(64)?")>; 1082 1083// MASKMOVDQU. 1084def : InstRW<[WriteMicrocoded], (instregex "(V?)MASKMOVDQU(64)?")>; 1085 1086// VPMASKMOVD. 1087// ymm 1088def : InstRW<[WriteMicrocoded], 1089 (instregex "VPMASKMOVD(Y?)rm")>; 1090// m, v,v. 1091def : InstRW<[WriteMicrocoded], (instregex "VPMASKMOV(D|Q)(Y?)mr")>; 1092 1093// VPBROADCAST B/W. 1094// x, m8/16. 1095def ZnWriteVPBROADCAST128Ld : SchedWriteRes<[ZnAGU, ZnFPU12]> { 1096 let Latency = 8; 1097 let NumMicroOps = 2; 1098 let ResourceCycles = [1, 2]; 1099} 1100def : InstRW<[ZnWriteVPBROADCAST128Ld], 1101 (instregex "VPBROADCAST(B|W)rm")>; 1102 1103// y, m8/16 1104def ZnWriteVPBROADCAST256Ld : SchedWriteRes<[ZnAGU, ZnFPU1]> { 1105 let Latency = 8; 1106 let NumMicroOps = 2; 1107 let ResourceCycles = [1, 2]; 1108} 1109def : InstRW<[ZnWriteVPBROADCAST256Ld], 1110 (instregex "VPBROADCAST(B|W)Yrm")>; 1111 1112// VPGATHER. 1113def : InstRW<[WriteMicrocoded], (instregex "VPGATHER(Q|D)(Q|D)(Y?)rm")>; 1114 1115//-- Arithmetic instructions --// 1116 1117// HADD, HSUB PS/PD 1118// PHADD|PHSUB (S) W/D. 1119def : SchedAlias<WritePHAdd, ZnWriteMicrocoded>; 1120def : SchedAlias<WritePHAddLd, ZnWriteMicrocoded>; 1121def : SchedAlias<WritePHAddX, ZnWriteMicrocoded>; 1122def : SchedAlias<WritePHAddXLd, ZnWriteMicrocoded>; 1123def : SchedAlias<WritePHAddY, ZnWriteMicrocoded>; 1124def : SchedAlias<WritePHAddYLd, ZnWriteMicrocoded>; 1125 1126// PCMPGTQ. 1127def ZnWritePCMPGTQr : SchedWriteRes<[ZnFPU03]>; 1128def : InstRW<[ZnWritePCMPGTQr], (instregex "(V?)PCMPGTQ(Y?)rr")>; 1129 1130// x <- x,m. 1131def ZnWritePCMPGTQm : SchedWriteRes<[ZnAGU, ZnFPU03]> { 1132 let Latency = 8; 1133} 1134// ymm. 1135def ZnWritePCMPGTQYm : SchedWriteRes<[ZnAGU, ZnFPU03]> { 1136 let Latency = 8; 1137 let NumMicroOps = 2; 1138 let ResourceCycles = [1,2]; 1139} 1140def : InstRW<[ZnWritePCMPGTQm], (instregex "(V?)PCMPGTQrm")>; 1141def : InstRW<[ZnWritePCMPGTQYm], (instrs VPCMPGTQYrm)>; 1142 1143//-- Logic instructions --// 1144 1145// PSLL,PSRL,PSRA W/D/Q. 1146// x,x / v,v,x. 1147def ZnWritePShift : SchedWriteRes<[ZnFPU2]> ; 1148def ZnWritePShiftY : SchedWriteRes<[ZnFPU2]> { 1149 let Latency = 2; 1150} 1151 1152// PSLL,PSRL DQ. 1153def : InstRW<[ZnWritePShift], (instregex "(V?)PS(R|L)LDQri")>; 1154def : InstRW<[ZnWritePShiftY], (instregex "(V?)PS(R|L)LDQYri")>; 1155 1156//=== Floating Point XMM and YMM Instructions ===// 1157//-- Move instructions --// 1158 1159// VPERM2F128. 1160def : InstRW<[WriteMicrocoded], (instrs VPERM2F128rr)>; 1161def : InstRW<[WriteMicrocoded], (instrs VPERM2F128rm)>; 1162 1163def ZnWriteBROADCAST : SchedWriteRes<[ZnAGU, ZnFPU13]> { 1164 let NumMicroOps = 2; 1165 let Latency = 8; 1166} 1167// VBROADCASTF128. 1168def : InstRW<[ZnWriteBROADCAST], (instrs VBROADCASTF128)>; 1169 1170// EXTRACTPS. 1171// r32,x,i. 1172def ZnWriteEXTRACTPSr : SchedWriteRes<[ZnFPU12, ZnFPU2]> { 1173 let Latency = 2; 1174 let NumMicroOps = 2; 1175 let ResourceCycles = [1, 2]; 1176} 1177def : InstRW<[ZnWriteEXTRACTPSr], (instregex "(V?)EXTRACTPSrr")>; 1178 1179def ZnWriteEXTRACTPSm : SchedWriteRes<[ZnAGU,ZnFPU12, ZnFPU2]> { 1180 let Latency = 5; 1181 let NumMicroOps = 2; 1182 let ResourceCycles = [5, 1, 2]; 1183} 1184// m32,x,i. 1185def : InstRW<[ZnWriteEXTRACTPSm], (instregex "(V?)EXTRACTPSmr")>; 1186 1187// VEXTRACTF128. 1188// x,y,i. 1189def : InstRW<[ZnWriteFPU013], (instrs VEXTRACTF128rr)>; 1190 1191// m128,y,i. 1192def : InstRW<[ZnWriteFPU013m], (instrs VEXTRACTF128mr)>; 1193 1194def ZnWriteVINSERT128r: SchedWriteRes<[ZnFPU013]> { 1195 let Latency = 2; 1196 let ResourceCycles = [2]; 1197} 1198def ZnWriteVINSERT128Ld: SchedWriteRes<[ZnAGU,ZnFPU013]> { 1199 let Latency = 9; 1200 let NumMicroOps = 2; 1201 let ResourceCycles = [1, 2]; 1202} 1203// VINSERTF128. 1204// y,y,x,i. 1205def : InstRW<[ZnWriteVINSERT128r], (instrs VINSERTF128rr)>; 1206def : InstRW<[ZnWriteVINSERT128Ld], (instrs VINSERTF128rm)>; 1207 1208// VGATHER. 1209def : InstRW<[WriteMicrocoded], (instregex "VGATHER(Q|D)(PD|PS)(Y?)rm")>; 1210 1211//-- Conversion instructions --// 1212def ZnWriteCVTPD2PSr: SchedWriteRes<[ZnFPU3]> { 1213 let Latency = 4; 1214} 1215def ZnWriteCVTPD2PSYr: SchedWriteRes<[ZnFPU3]> { 1216 let Latency = 5; 1217} 1218 1219// CVTPD2PS. 1220// x,x. 1221def : SchedAlias<WriteCvtPD2PS, ZnWriteCVTPD2PSr>; 1222// y,y. 1223def : SchedAlias<WriteCvtPD2PSY, ZnWriteCVTPD2PSYr>; 1224// z,z. 1225defm : X86WriteResUnsupported<WriteCvtPD2PSZ>; 1226 1227def ZnWriteCVTPD2PSLd: SchedWriteRes<[ZnAGU,ZnFPU03]> { 1228 let Latency = 11; 1229 let NumMicroOps = 2; 1230 let ResourceCycles = [1,2]; 1231} 1232// x,m128. 1233def : SchedAlias<WriteCvtPD2PSLd, ZnWriteCVTPD2PSLd>; 1234 1235// x,m256. 1236def ZnWriteCVTPD2PSYLd : SchedWriteRes<[ZnAGU, ZnFPU3]> { 1237 let Latency = 11; 1238} 1239def : SchedAlias<WriteCvtPD2PSYLd, ZnWriteCVTPD2PSYLd>; 1240// z,m512 1241defm : X86WriteResUnsupported<WriteCvtPD2PSZLd>; 1242 1243// CVTSD2SS. 1244// x,x. 1245// Same as WriteCVTPD2PSr 1246def : SchedAlias<WriteCvtSD2SS, ZnWriteCVTPD2PSr>; 1247 1248// x,m64. 1249def : SchedAlias<WriteCvtSD2SSLd, ZnWriteCVTPD2PSLd>; 1250 1251// CVTPS2PD. 1252// x,x. 1253def ZnWriteCVTPS2PDr : SchedWriteRes<[ZnFPU3]> { 1254 let Latency = 3; 1255} 1256def : SchedAlias<WriteCvtPS2PD, ZnWriteCVTPS2PDr>; 1257 1258// x,m64. 1259// y,m128. 1260def ZnWriteCVTPS2PDLd : SchedWriteRes<[ZnAGU, ZnFPU3]> { 1261 let Latency = 10; 1262 let NumMicroOps = 2; 1263} 1264def : SchedAlias<WriteCvtPS2PDLd, ZnWriteCVTPS2PDLd>; 1265def : SchedAlias<WriteCvtPS2PDYLd, ZnWriteCVTPS2PDLd>; 1266defm : X86WriteResUnsupported<WriteCvtPS2PDZLd>; 1267 1268// y,x. 1269def ZnWriteVCVTPS2PDY : SchedWriteRes<[ZnFPU3]> { 1270 let Latency = 3; 1271} 1272def : SchedAlias<WriteCvtPS2PDY, ZnWriteVCVTPS2PDY>; 1273defm : X86WriteResUnsupported<WriteCvtPS2PDZ>; 1274 1275// CVTSS2SD. 1276// x,x. 1277def ZnWriteCVTSS2SDr : SchedWriteRes<[ZnFPU3]> { 1278 let Latency = 4; 1279} 1280def : SchedAlias<WriteCvtSS2SD, ZnWriteCVTSS2SDr>; 1281 1282// x,m32. 1283def ZnWriteCVTSS2SDLd : SchedWriteRes<[ZnAGU, ZnFPU3]> { 1284 let Latency = 11; 1285 let NumMicroOps = 2; 1286 let ResourceCycles = [1, 2]; 1287} 1288def : SchedAlias<WriteCvtSS2SDLd, ZnWriteCVTSS2SDLd>; 1289 1290def ZnWriteCVTDQ2PDr: SchedWriteRes<[ZnFPU12,ZnFPU3]> { 1291 let Latency = 5; 1292} 1293// CVTDQ2PD. 1294// x,x. 1295def : InstRW<[ZnWriteCVTDQ2PDr], (instregex "(V)?CVTDQ2PDrr")>; 1296 1297// Same as xmm 1298// y,x. 1299def : InstRW<[ZnWriteCVTDQ2PDr], (instrs VCVTDQ2PDYrr)>; 1300 1301def ZnWriteCVTPD2DQr: SchedWriteRes<[ZnFPU12, ZnFPU3]> { 1302 let Latency = 5; 1303} 1304// CVT(T)PD2DQ. 1305// x,x. 1306def : InstRW<[ZnWriteCVTDQ2PDr], (instregex "(V?)CVT(T?)PD2DQrr")>; 1307 1308def ZnWriteCVTPD2DQLd: SchedWriteRes<[ZnAGU,ZnFPU12,ZnFPU3]> { 1309 let Latency = 12; 1310 let NumMicroOps = 2; 1311} 1312// x,m128. 1313def : InstRW<[ZnWriteCVTPD2DQLd], (instregex "(V?)CVT(T?)PD2DQrm")>; 1314// same as xmm handling 1315// x,y. 1316def : InstRW<[ZnWriteCVTPD2DQr], (instregex "VCVT(T?)PD2DQYrr")>; 1317// x,m256. 1318def : InstRW<[ZnWriteCVTPD2DQLd], (instregex "VCVT(T?)PD2DQYrm")>; 1319 1320def ZnWriteCVTPS2PIr: SchedWriteRes<[ZnFPU3]> { 1321 let Latency = 4; 1322} 1323// CVT(T)PS2PI. 1324// mm,x. 1325def : InstRW<[ZnWriteCVTPS2PIr], (instregex "MMX_CVT(T?)PS2PIirr")>; 1326 1327// CVTPI2PD. 1328// x,mm. 1329def : InstRW<[ZnWriteCVTPS2PDr], (instrs MMX_CVTPI2PDirr)>; 1330 1331// CVT(T)PD2PI. 1332// mm,x. 1333def : InstRW<[ZnWriteCVTPS2PIr], (instregex "MMX_CVT(T?)PD2PIirr")>; 1334 1335def ZnWriteCVSTSI2SSr: SchedWriteRes<[ZnFPU3]> { 1336 let Latency = 5; 1337} 1338 1339// same as CVTPD2DQr 1340// CVT(T)SS2SI. 1341// r32,x. 1342def : InstRW<[ZnWriteCVTPD2DQr], (instregex "(V?)CVT(T?)SS2SI(64)?rr")>; 1343// same as CVTPD2DQm 1344// r32,m32. 1345def : InstRW<[ZnWriteCVTPD2DQLd], (instregex "(V?)CVT(T?)SS2SI(64)?rm")>; 1346 1347def ZnWriteCVSTSI2SDr: SchedWriteRes<[ZnFPU013, ZnFPU3]> { 1348 let Latency = 5; 1349} 1350// CVTSI2SD. 1351// x,r32/64. 1352def : InstRW<[ZnWriteCVSTSI2SDr], (instregex "(V?)CVTSI(64)?2SDrr")>; 1353 1354 1355def ZnWriteCVSTSI2SIr: SchedWriteRes<[ZnFPU3, ZnFPU2]> { 1356 let Latency = 5; 1357} 1358def ZnWriteCVSTSI2SILd: SchedWriteRes<[ZnAGU, ZnFPU3, ZnFPU2]> { 1359 let Latency = 12; 1360} 1361// CVTSD2SI. 1362// r32/64 1363def : InstRW<[ZnWriteCVSTSI2SIr], (instregex "(V?)CVT(T?)SD2SI(64)?rr")>; 1364// r32,m32. 1365def : InstRW<[ZnWriteCVSTSI2SILd], (instregex "(V?)CVT(T?)SD2SI(64)?rm")>; 1366 1367// VCVTPS2PH. 1368// x,v,i. 1369def : SchedAlias<WriteCvtPS2PH, ZnWriteMicrocoded>; 1370def : SchedAlias<WriteCvtPS2PHY, ZnWriteMicrocoded>; 1371defm : X86WriteResUnsupported<WriteCvtPS2PHZ>; 1372// m,v,i. 1373def : SchedAlias<WriteCvtPS2PHSt, ZnWriteMicrocoded>; 1374def : SchedAlias<WriteCvtPS2PHYSt, ZnWriteMicrocoded>; 1375defm : X86WriteResUnsupported<WriteCvtPS2PHZSt>; 1376 1377// VCVTPH2PS. 1378// v,x. 1379def : SchedAlias<WriteCvtPH2PS, ZnWriteMicrocoded>; 1380def : SchedAlias<WriteCvtPH2PSY, ZnWriteMicrocoded>; 1381defm : X86WriteResUnsupported<WriteCvtPH2PSZ>; 1382// v,m. 1383def : SchedAlias<WriteCvtPH2PSLd, ZnWriteMicrocoded>; 1384def : SchedAlias<WriteCvtPH2PSYLd, ZnWriteMicrocoded>; 1385defm : X86WriteResUnsupported<WriteCvtPH2PSZLd>; 1386 1387//-- SSE4A instructions --// 1388// EXTRQ 1389def ZnWriteEXTRQ: SchedWriteRes<[ZnFPU12, ZnFPU2]> { 1390 let Latency = 2; 1391} 1392def : InstRW<[ZnWriteEXTRQ], (instregex "EXTRQ")>; 1393 1394// INSERTQ 1395def ZnWriteINSERTQ: SchedWriteRes<[ZnFPU03,ZnFPU1]> { 1396 let Latency = 4; 1397} 1398def : InstRW<[ZnWriteINSERTQ], (instregex "INSERTQ")>; 1399 1400//-- SHA instructions --// 1401// SHA256MSG2 1402def : InstRW<[WriteMicrocoded], (instregex "SHA256MSG2(Y?)r(r|m)")>; 1403 1404// SHA1MSG1, SHA256MSG1 1405// x,x. 1406def ZnWriteSHA1MSG1r : SchedWriteRes<[ZnFPU12]> { 1407 let Latency = 2; 1408 let ResourceCycles = [2]; 1409} 1410def : InstRW<[ZnWriteSHA1MSG1r], (instregex "SHA(1|256)MSG1rr")>; 1411// x,m. 1412def ZnWriteSHA1MSG1Ld : SchedWriteRes<[ZnAGU, ZnFPU12]> { 1413 let Latency = 9; 1414 let ResourceCycles = [1,2]; 1415} 1416def : InstRW<[ZnWriteSHA1MSG1Ld], (instregex "SHA(1|256)MSG1rm")>; 1417 1418// SHA1MSG2 1419// x,x. 1420def ZnWriteSHA1MSG2r : SchedWriteRes<[ZnFPU12]> ; 1421def : InstRW<[ZnWriteSHA1MSG2r], (instrs SHA1MSG2rr)>; 1422// x,m. 1423def ZnWriteSHA1MSG2Ld : SchedWriteRes<[ZnAGU, ZnFPU12]> { 1424 let Latency = 8; 1425} 1426def : InstRW<[ZnWriteSHA1MSG2Ld], (instrs SHA1MSG2rm)>; 1427 1428// SHA1NEXTE 1429// x,x. 1430def ZnWriteSHA1NEXTEr : SchedWriteRes<[ZnFPU1]> ; 1431def : InstRW<[ZnWriteSHA1NEXTEr], (instrs SHA1NEXTErr)>; 1432// x,m. 1433def ZnWriteSHA1NEXTELd : SchedWriteRes<[ZnAGU, ZnFPU1]> { 1434 let Latency = 8; 1435} 1436def : InstRW<[ZnWriteSHA1NEXTELd], (instrs SHA1NEXTErm)>; 1437 1438// SHA1RNDS4 1439// x,x. 1440def ZnWriteSHA1RNDS4r : SchedWriteRes<[ZnFPU1]> { 1441 let Latency = 6; 1442} 1443def : InstRW<[ZnWriteSHA1RNDS4r], (instrs SHA1RNDS4rri)>; 1444// x,m. 1445def ZnWriteSHA1RNDS4Ld : SchedWriteRes<[ZnAGU, ZnFPU1]> { 1446 let Latency = 13; 1447} 1448def : InstRW<[ZnWriteSHA1RNDS4Ld], (instrs SHA1RNDS4rmi)>; 1449 1450// SHA256RNDS2 1451// x,x. 1452def ZnWriteSHA256RNDS2r : SchedWriteRes<[ZnFPU1]> { 1453 let Latency = 4; 1454} 1455def : InstRW<[ZnWriteSHA256RNDS2r], (instrs SHA256RNDS2rr)>; 1456// x,m. 1457def ZnWriteSHA256RNDS2Ld : SchedWriteRes<[ZnAGU, ZnFPU1]> { 1458 let Latency = 11; 1459} 1460def : InstRW<[ZnWriteSHA256RNDS2Ld], (instrs SHA256RNDS2rm)>; 1461 1462//-- Arithmetic instructions --// 1463 1464// HADD, HSUB PS/PD 1465def : SchedAlias<WriteFHAdd, ZnWriteMicrocoded>; 1466def : SchedAlias<WriteFHAddLd, ZnWriteMicrocoded>; 1467def : SchedAlias<WriteFHAddY, ZnWriteMicrocoded>; 1468def : SchedAlias<WriteFHAddYLd, ZnWriteMicrocoded>; 1469 1470// VDIVPS. 1471// TODO - convert to ZnWriteResFpuPair 1472// y,y,y. 1473def ZnWriteVDIVPSYr : SchedWriteRes<[ZnFPU3]> { 1474 let Latency = 12; 1475 let ResourceCycles = [12]; 1476} 1477def : SchedAlias<WriteFDivY, ZnWriteVDIVPSYr>; 1478 1479// y,y,m256. 1480def ZnWriteVDIVPSYLd : SchedWriteRes<[ZnAGU, ZnFPU3]> { 1481 let Latency = 19; 1482 let NumMicroOps = 2; 1483 let ResourceCycles = [1, 19]; 1484} 1485def : SchedAlias<WriteFDivYLd, ZnWriteVDIVPSYLd>; 1486 1487// VDIVPD. 1488// TODO - convert to ZnWriteResFpuPair 1489// y,y,y. 1490def ZnWriteVDIVPDY : SchedWriteRes<[ZnFPU3]> { 1491 let Latency = 15; 1492 let ResourceCycles = [15]; 1493} 1494def : SchedAlias<WriteFDiv64Y, ZnWriteVDIVPDY>; 1495 1496// y,y,m256. 1497def ZnWriteVDIVPDYLd : SchedWriteRes<[ZnAGU, ZnFPU3]> { 1498 let Latency = 22; 1499 let NumMicroOps = 2; 1500 let ResourceCycles = [1,22]; 1501} 1502def : SchedAlias<WriteFDiv64YLd, ZnWriteVDIVPDYLd>; 1503 1504// DPPS. 1505// x,x,i / v,v,v,i. 1506def : SchedAlias<WriteDPPS, ZnWriteMicrocoded>; 1507def : SchedAlias<WriteDPPSY, ZnWriteMicrocoded>; 1508 1509// x,m,i / v,v,m,i. 1510def : SchedAlias<WriteDPPSLd, ZnWriteMicrocoded>; 1511def : SchedAlias<WriteDPPSYLd,ZnWriteMicrocoded>; 1512 1513// DPPD. 1514// x,x,i. 1515def : SchedAlias<WriteDPPD, ZnWriteMicrocoded>; 1516 1517// x,m,i. 1518def : SchedAlias<WriteDPPDLd, ZnWriteMicrocoded>; 1519 1520// RSQRTSS 1521// TODO - convert to ZnWriteResFpuPair 1522// x,x. 1523def ZnWriteRSQRTSSr : SchedWriteRes<[ZnFPU02]> { 1524 let Latency = 5; 1525} 1526def : SchedAlias<WriteFRsqrt, ZnWriteRSQRTSSr>; 1527 1528// x,m128. 1529def ZnWriteRSQRTSSLd: SchedWriteRes<[ZnAGU, ZnFPU02]> { 1530 let Latency = 12; 1531 let NumMicroOps = 2; 1532 let ResourceCycles = [1,2]; // FIXME: Is this right? 1533} 1534def : SchedAlias<WriteFRsqrtLd, ZnWriteRSQRTSSLd>; 1535 1536// RSQRTPS 1537// TODO - convert to ZnWriteResFpuPair 1538// y,y. 1539def ZnWriteRSQRTPSYr : SchedWriteRes<[ZnFPU01]> { 1540 let Latency = 5; 1541 let NumMicroOps = 2; 1542 let ResourceCycles = [2]; 1543} 1544def : SchedAlias<WriteFRsqrtY, ZnWriteRSQRTPSYr>; 1545 1546// y,m256. 1547def ZnWriteRSQRTPSYLd : SchedWriteRes<[ZnAGU, ZnFPU01]> { 1548 let Latency = 12; 1549 let NumMicroOps = 2; 1550} 1551def : SchedAlias<WriteFRsqrtYLd, ZnWriteRSQRTPSYLd>; 1552 1553//-- Other instructions --// 1554 1555// VZEROUPPER. 1556def : InstRW<[WriteMicrocoded], (instrs VZEROUPPER)>; 1557 1558// VZEROALL. 1559def : InstRW<[WriteMicrocoded], (instrs VZEROALL)>; 1560 1561} // SchedModel 1562