1//=- X86ScheduleSLM.td - X86 Silvermont Scheduling -----------*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the machine model for Intel Silvermont to support 10// instruction scheduling and other instruction cost heuristics. 11// 12//===----------------------------------------------------------------------===// 13 14def SLMModel : SchedMachineModel { 15 // All x86 instructions are modeled as a single micro-op, and SLM can decode 2 16 // instructions per cycle. 17 let IssueWidth = 2; 18 let MicroOpBufferSize = 32; // Based on the reorder buffer. 19 let LoadLatency = 3; 20 let MispredictPenalty = 10; 21 let PostRAScheduler = 1; 22 23 // For small loops, expand by a small factor to hide the backedge cost. 24 let LoopMicroOpBufferSize = 10; 25 26 // FIXME: SSE4 is unimplemented. This flag is set to allow 27 // the scheduler to assign a default model to unrecognized opcodes. 28 let CompleteModel = 0; 29} 30 31let SchedModel = SLMModel in { 32 33// Silvermont has 5 reservation stations for micro-ops 34def SLM_IEC_RSV0 : ProcResource<1>; 35def SLM_IEC_RSV1 : ProcResource<1>; 36def SLM_FPC_RSV0 : ProcResource<1> { let BufferSize = 1; } 37def SLM_FPC_RSV1 : ProcResource<1> { let BufferSize = 1; } 38def SLM_MEC_RSV : ProcResource<1>; 39 40// Many micro-ops are capable of issuing on multiple ports. 41def SLM_IEC_RSV01 : ProcResGroup<[SLM_IEC_RSV0, SLM_IEC_RSV1]>; 42def SLM_FPC_RSV01 : ProcResGroup<[SLM_FPC_RSV0, SLM_FPC_RSV1]>; 43 44def SLMDivider : ProcResource<1>; 45def SLMFPMultiplier : ProcResource<1>; 46def SLMFPDivider : ProcResource<1>; 47 48// Loads are 3 cycles, so ReadAfterLd registers needn't be available until 3 49// cycles after the memory operand. 50def : ReadAdvance<ReadAfterLd, 3>; 51def : ReadAdvance<ReadAfterVecLd, 3>; 52def : ReadAdvance<ReadAfterVecXLd, 3>; 53def : ReadAdvance<ReadAfterVecYLd, 3>; 54 55def : ReadAdvance<ReadInt2Fpu, 0>; 56 57// Many SchedWrites are defined in pairs with and without a folded load. 58// Instructions with folded loads are usually micro-fused, so they only appear 59// as two micro-ops when queued in the reservation station. 60// This multiclass defines the resource usage for variants with and without 61// folded loads. 62multiclass SLMWriteResPair<X86FoldableSchedWrite SchedRW, 63 list<ProcResourceKind> ExePorts, 64 int Lat, list<int> Res = [1], int UOps = 1, 65 int LoadLat = 3> { 66 // Register variant is using a single cycle on ExePort. 67 def : WriteRes<SchedRW, ExePorts> { 68 let Latency = Lat; 69 let ResourceCycles = Res; 70 let NumMicroOps = UOps; 71 } 72 73 // Memory variant also uses a cycle on MEC_RSV and adds LoadLat cycles to 74 // the latency (default = 3). 75 def : WriteRes<SchedRW.Folded, !listconcat([SLM_MEC_RSV], ExePorts)> { 76 let Latency = !add(Lat, LoadLat); 77 let ResourceCycles = !listconcat([1], Res); 78 let NumMicroOps = UOps; 79 } 80} 81 82// A folded store needs a cycle on MEC_RSV for the store data, but it does not 83// need an extra port cycle to recompute the address. 84def : WriteRes<WriteRMW, [SLM_MEC_RSV]>; 85 86def : WriteRes<WriteStore, [SLM_IEC_RSV01, SLM_MEC_RSV]>; 87def : WriteRes<WriteStoreNT, [SLM_IEC_RSV01, SLM_MEC_RSV]>; 88def : WriteRes<WriteLoad, [SLM_MEC_RSV]> { let Latency = 3; } 89def : WriteRes<WriteMove, [SLM_IEC_RSV01]>; 90def : WriteRes<WriteZero, []>; 91 92// Load/store MXCSR. 93// FIXME: These are probably wrong. They are copy pasted from WriteStore/Load. 94def : WriteRes<WriteSTMXCSR, [SLM_IEC_RSV01, SLM_MEC_RSV]>; 95def : WriteRes<WriteLDMXCSR, [SLM_MEC_RSV]> { let Latency = 3; } 96 97// Treat misc copies as a move. 98def : InstRW<[WriteMove], (instrs COPY)>; 99 100defm : SLMWriteResPair<WriteALU, [SLM_IEC_RSV01], 1>; 101defm : SLMWriteResPair<WriteADC, [SLM_IEC_RSV01], 1>; 102 103defm : SLMWriteResPair<WriteIMul8, [SLM_IEC_RSV1], 3>; 104defm : SLMWriteResPair<WriteIMul16, [SLM_IEC_RSV1], 3>; 105defm : SLMWriteResPair<WriteIMul16Imm, [SLM_IEC_RSV1], 3>; 106defm : SLMWriteResPair<WriteIMul16Reg, [SLM_IEC_RSV1], 3>; 107defm : SLMWriteResPair<WriteIMul32, [SLM_IEC_RSV1], 3>; 108defm : SLMWriteResPair<WriteIMul32Imm, [SLM_IEC_RSV1], 3>; 109defm : SLMWriteResPair<WriteIMul32Reg, [SLM_IEC_RSV1], 3>; 110defm : SLMWriteResPair<WriteIMul64, [SLM_IEC_RSV1], 3>; 111defm : SLMWriteResPair<WriteIMul64Imm, [SLM_IEC_RSV1], 3>; 112defm : SLMWriteResPair<WriteIMul64Reg, [SLM_IEC_RSV1], 3>; 113 114defm : X86WriteRes<WriteBSWAP32, [SLM_IEC_RSV01], 1, [1], 1>; 115defm : X86WriteRes<WriteBSWAP64, [SLM_IEC_RSV01], 1, [1], 1>; 116defm : X86WriteRes<WriteCMPXCHG, [SLM_IEC_RSV01], 1, [1], 1>; 117defm : X86WriteRes<WriteCMPXCHGRMW, [SLM_IEC_RSV01, SLM_MEC_RSV], 4, [1, 2], 2>; 118defm : X86WriteRes<WriteXCHG, [SLM_IEC_RSV01], 1, [1], 1>; 119 120defm : SLMWriteResPair<WriteShift, [SLM_IEC_RSV0], 1>; 121defm : SLMWriteResPair<WriteShiftCL, [SLM_IEC_RSV0], 1>; 122defm : SLMWriteResPair<WriteRotate, [SLM_IEC_RSV0], 1>; 123defm : SLMWriteResPair<WriteRotateCL, [SLM_IEC_RSV0], 1>; 124 125defm : X86WriteRes<WriteSHDrri, [SLM_IEC_RSV0], 1, [1], 1>; 126defm : X86WriteRes<WriteSHDrrcl,[SLM_IEC_RSV0], 1, [1], 1>; 127defm : X86WriteRes<WriteSHDmri, [SLM_MEC_RSV, SLM_IEC_RSV0], 4, [2, 1], 2>; 128defm : X86WriteRes<WriteSHDmrcl,[SLM_MEC_RSV, SLM_IEC_RSV0], 4, [2, 1], 2>; 129 130defm : SLMWriteResPair<WriteJump, [SLM_IEC_RSV1], 1>; 131defm : SLMWriteResPair<WriteCRC32, [SLM_IEC_RSV1], 3>; 132 133defm : SLMWriteResPair<WriteCMOV, [SLM_IEC_RSV01], 2, [2]>; 134defm : X86WriteRes<WriteFCMOV, [SLM_FPC_RSV1], 3, [1], 1>; // x87 conditional move. 135def : WriteRes<WriteSETCC, [SLM_IEC_RSV01]>; 136def : WriteRes<WriteSETCCStore, [SLM_IEC_RSV01, SLM_MEC_RSV]> { 137 // FIXME Latency and NumMicrOps? 138 let ResourceCycles = [2,1]; 139} 140defm : X86WriteRes<WriteLAHFSAHF, [SLM_IEC_RSV01], 1, [1], 1>; 141defm : X86WriteRes<WriteBitTest, [SLM_IEC_RSV01], 1, [1], 1>; 142defm : X86WriteRes<WriteBitTestImmLd, [SLM_IEC_RSV01, SLM_MEC_RSV], 4, [1,1], 1>; 143defm : X86WriteRes<WriteBitTestRegLd, [SLM_IEC_RSV01, SLM_MEC_RSV], 4, [1,1], 1>; 144defm : X86WriteRes<WriteBitTestSet, [SLM_IEC_RSV01], 1, [1], 1>; 145defm : X86WriteRes<WriteBitTestSetImmLd, [SLM_IEC_RSV01, SLM_MEC_RSV], 3, [1,1], 1>; 146defm : X86WriteRes<WriteBitTestSetRegLd, [SLM_IEC_RSV01, SLM_MEC_RSV], 3, [1,1], 1>; 147 148// This is for simple LEAs with one or two input operands. 149// The complex ones can only execute on port 1, and they require two cycles on 150// the port to read all inputs. We don't model that. 151def : WriteRes<WriteLEA, [SLM_IEC_RSV1]>; 152 153// Bit counts. 154defm : SLMWriteResPair<WriteBSF, [SLM_IEC_RSV01], 10, [20], 10>; 155defm : SLMWriteResPair<WriteBSR, [SLM_IEC_RSV01], 10, [20], 10>; 156defm : SLMWriteResPair<WriteLZCNT, [SLM_IEC_RSV0], 3>; 157defm : SLMWriteResPair<WriteTZCNT, [SLM_IEC_RSV0], 3>; 158defm : SLMWriteResPair<WritePOPCNT, [SLM_IEC_RSV0], 3>; 159 160// BMI1 BEXTR/BLS, BMI2 BZHI 161defm : X86WriteResPairUnsupported<WriteBEXTR>; 162defm : X86WriteResPairUnsupported<WriteBLS>; 163defm : X86WriteResPairUnsupported<WriteBZHI>; 164 165defm : SLMWriteResPair<WriteDiv8, [SLM_IEC_RSV01, SLMDivider], 25, [1,25], 1, 4>; 166defm : SLMWriteResPair<WriteDiv16, [SLM_IEC_RSV01, SLMDivider], 25, [1,25], 1, 4>; 167defm : SLMWriteResPair<WriteDiv32, [SLM_IEC_RSV01, SLMDivider], 25, [1,25], 1, 4>; 168defm : SLMWriteResPair<WriteDiv64, [SLM_IEC_RSV01, SLMDivider], 25, [1,25], 1, 4>; 169defm : SLMWriteResPair<WriteIDiv8, [SLM_IEC_RSV01, SLMDivider], 25, [1,25], 1, 4>; 170defm : SLMWriteResPair<WriteIDiv16, [SLM_IEC_RSV01, SLMDivider], 25, [1,25], 1, 4>; 171defm : SLMWriteResPair<WriteIDiv32, [SLM_IEC_RSV01, SLMDivider], 25, [1,25], 1, 4>; 172defm : SLMWriteResPair<WriteIDiv64, [SLM_IEC_RSV01, SLMDivider], 25, [1,25], 1, 4>; 173 174// Scalar and vector floating point. 175defm : X86WriteRes<WriteFLD0, [SLM_FPC_RSV01], 1, [1], 1>; 176defm : X86WriteRes<WriteFLD1, [SLM_FPC_RSV01], 1, [1], 1>; 177defm : X86WriteRes<WriteFLDC, [SLM_FPC_RSV01], 1, [2], 2>; 178def : WriteRes<WriteFLoad, [SLM_MEC_RSV]> { let Latency = 3; } 179def : WriteRes<WriteFLoadX, [SLM_MEC_RSV]> { let Latency = 3; } 180def : WriteRes<WriteFLoadY, [SLM_MEC_RSV]> { let Latency = 3; } 181def : WriteRes<WriteFMaskedLoad, [SLM_MEC_RSV]> { let Latency = 3; } 182def : WriteRes<WriteFMaskedLoadY, [SLM_MEC_RSV]> { let Latency = 3; } 183def : WriteRes<WriteFStore, [SLM_MEC_RSV]>; 184def : WriteRes<WriteFStoreX, [SLM_MEC_RSV]>; 185def : WriteRes<WriteFStoreY, [SLM_MEC_RSV]>; 186def : WriteRes<WriteFStoreNT, [SLM_MEC_RSV]>; 187def : WriteRes<WriteFStoreNTX, [SLM_MEC_RSV]>; 188def : WriteRes<WriteFStoreNTY, [SLM_MEC_RSV]>; 189def : WriteRes<WriteFMaskedStore, [SLM_MEC_RSV]>; 190def : WriteRes<WriteFMaskedStoreY, [SLM_MEC_RSV]>; 191def : WriteRes<WriteFMove, [SLM_FPC_RSV01]>; 192def : WriteRes<WriteFMoveX, [SLM_FPC_RSV01]>; 193def : WriteRes<WriteFMoveY, [SLM_FPC_RSV01]>; 194defm : X86WriteRes<WriteEMMS, [SLM_FPC_RSV01], 10, [10], 9>; 195 196defm : SLMWriteResPair<WriteFAdd, [SLM_FPC_RSV1], 3>; 197defm : SLMWriteResPair<WriteFAddX, [SLM_FPC_RSV1], 3>; 198defm : SLMWriteResPair<WriteFAddY, [SLM_FPC_RSV1], 3>; 199defm : X86WriteResPairUnsupported<WriteFAddZ>; 200defm : SLMWriteResPair<WriteFAdd64, [SLM_FPC_RSV1], 3>; 201defm : SLMWriteResPair<WriteFAdd64X, [SLM_FPC_RSV1], 3>; 202defm : SLMWriteResPair<WriteFAdd64Y, [SLM_FPC_RSV1], 3>; 203defm : X86WriteResPairUnsupported<WriteFAdd64Z>; 204defm : SLMWriteResPair<WriteFCmp, [SLM_FPC_RSV1], 3>; 205defm : SLMWriteResPair<WriteFCmpX, [SLM_FPC_RSV1], 3>; 206defm : SLMWriteResPair<WriteFCmpY, [SLM_FPC_RSV1], 3>; 207defm : X86WriteResPairUnsupported<WriteFCmpZ>; 208defm : SLMWriteResPair<WriteFCmp64, [SLM_FPC_RSV1], 3>; 209defm : SLMWriteResPair<WriteFCmp64X, [SLM_FPC_RSV1], 3>; 210defm : SLMWriteResPair<WriteFCmp64Y, [SLM_FPC_RSV1], 3>; 211defm : X86WriteResPairUnsupported<WriteFCmp64Z>; 212defm : SLMWriteResPair<WriteFCom, [SLM_FPC_RSV1], 3>; 213defm : SLMWriteResPair<WriteFMul, [SLM_FPC_RSV0, SLMFPMultiplier], 5, [1,2]>; 214defm : SLMWriteResPair<WriteFMulX, [SLM_FPC_RSV0, SLMFPMultiplier], 5, [1,2]>; 215defm : SLMWriteResPair<WriteFMulY, [SLM_FPC_RSV0, SLMFPMultiplier], 5, [1,2]>; 216defm : X86WriteResPairUnsupported<WriteFMulZ>; 217defm : SLMWriteResPair<WriteFMul64, [SLM_FPC_RSV0, SLMFPMultiplier], 5, [1,2]>; 218defm : SLMWriteResPair<WriteFMul64X, [SLM_FPC_RSV0, SLMFPMultiplier], 5, [1,2]>; 219defm : SLMWriteResPair<WriteFMul64Y, [SLM_FPC_RSV0, SLMFPMultiplier], 5, [1,2]>; 220defm : X86WriteResPairUnsupported<WriteFMul64Z>; 221defm : SLMWriteResPair<WriteFDiv, [SLM_FPC_RSV0, SLMFPDivider], 19, [1,17]>; 222defm : SLMWriteResPair<WriteFDivX, [SLM_FPC_RSV0, SLMFPDivider], 39, [1,39]>; 223defm : SLMWriteResPair<WriteFDivY, [SLM_FPC_RSV0, SLMFPDivider], 39, [1,39]>; 224defm : X86WriteResPairUnsupported<WriteFDivZ>; 225defm : SLMWriteResPair<WriteFDiv64, [SLM_FPC_RSV0, SLMFPDivider], 34, [1,32]>; 226defm : SLMWriteResPair<WriteFDiv64X, [SLM_FPC_RSV0, SLMFPDivider], 69, [1,69]>; 227defm : SLMWriteResPair<WriteFDiv64Y, [SLM_FPC_RSV0, SLMFPDivider], 69, [1,69]>; 228defm : X86WriteResPairUnsupported<WriteFDiv64Z>; 229defm : SLMWriteResPair<WriteFRcp, [SLM_FPC_RSV0], 5>; 230defm : SLMWriteResPair<WriteFRcpX, [SLM_FPC_RSV0], 5>; 231defm : SLMWriteResPair<WriteFRcpY, [SLM_FPC_RSV0], 5>; 232defm : X86WriteResPairUnsupported<WriteFRcpZ>; 233defm : SLMWriteResPair<WriteFRsqrt, [SLM_FPC_RSV0], 5>; 234defm : SLMWriteResPair<WriteFRsqrtX, [SLM_FPC_RSV0], 5>; 235defm : SLMWriteResPair<WriteFRsqrtY, [SLM_FPC_RSV0], 5>; 236defm : X86WriteResPairUnsupported<WriteFRsqrtZ>; 237defm : SLMWriteResPair<WriteFSqrt, [SLM_FPC_RSV0,SLMFPDivider], 20, [1,20], 1, 3>; 238defm : SLMWriteResPair<WriteFSqrtX, [SLM_FPC_RSV0,SLMFPDivider], 41, [1,40], 1, 3>; 239defm : SLMWriteResPair<WriteFSqrtY, [SLM_FPC_RSV0,SLMFPDivider], 41, [1,40], 1, 3>; 240defm : X86WriteResPairUnsupported<WriteFSqrtZ>; 241defm : SLMWriteResPair<WriteFSqrt64, [SLM_FPC_RSV0,SLMFPDivider], 35, [1,35], 1, 3>; 242defm : SLMWriteResPair<WriteFSqrt64X, [SLM_FPC_RSV0,SLMFPDivider], 71, [1,70], 1, 3>; 243defm : SLMWriteResPair<WriteFSqrt64Y, [SLM_FPC_RSV0,SLMFPDivider], 71, [1,70], 1, 3>; 244defm : X86WriteResPairUnsupported<WriteFSqrt64Z>; 245defm : SLMWriteResPair<WriteFSqrt80, [SLM_FPC_RSV0,SLMFPDivider], 40, [1,40]>; 246defm : SLMWriteResPair<WriteDPPD, [SLM_FPC_RSV1], 3>; 247defm : SLMWriteResPair<WriteDPPS, [SLM_FPC_RSV1], 3>; 248defm : SLMWriteResPair<WriteDPPSY, [SLM_FPC_RSV1], 3>; 249defm : X86WriteResPairUnsupported<WriteDPPSZ>; 250defm : SLMWriteResPair<WriteFSign, [SLM_FPC_RSV01], 1>; 251defm : SLMWriteResPair<WriteFRnd, [SLM_FPC_RSV1], 3>; 252defm : SLMWriteResPair<WriteFRndY, [SLM_FPC_RSV1], 3>; 253defm : X86WriteResPairUnsupported<WriteFRndZ>; 254defm : SLMWriteResPair<WriteFLogic, [SLM_FPC_RSV01], 1>; 255defm : SLMWriteResPair<WriteFLogicY, [SLM_FPC_RSV01], 1>; 256defm : X86WriteResPairUnsupported<WriteFLogicZ>; 257defm : SLMWriteResPair<WriteFTest, [SLM_FPC_RSV01], 1>; 258defm : SLMWriteResPair<WriteFTestY, [SLM_FPC_RSV01], 1>; 259defm : X86WriteResPairUnsupported<WriteFTestZ>; 260defm : SLMWriteResPair<WriteFShuffle, [SLM_FPC_RSV0], 1>; 261defm : SLMWriteResPair<WriteFShuffleY, [SLM_FPC_RSV0], 1>; 262defm : X86WriteResPairUnsupported<WriteFShuffleZ>; 263defm : SLMWriteResPair<WriteFVarShuffle, [SLM_FPC_RSV0], 1>; 264defm : SLMWriteResPair<WriteFVarShuffleY,[SLM_FPC_RSV0], 1>; 265defm : X86WriteResPairUnsupported<WriteFVarShuffleZ>; 266defm : SLMWriteResPair<WriteFBlend, [SLM_FPC_RSV0], 1>; 267 268// Conversion between integer and float. 269defm : SLMWriteResPair<WriteCvtSS2I, [SLM_FPC_RSV01], 4>; 270defm : SLMWriteResPair<WriteCvtPS2I, [SLM_FPC_RSV01], 4>; 271defm : SLMWriteResPair<WriteCvtPS2IY, [SLM_FPC_RSV01], 4>; 272defm : X86WriteResPairUnsupported<WriteCvtPS2IZ>; 273defm : SLMWriteResPair<WriteCvtSD2I, [SLM_FPC_RSV01], 4>; 274defm : SLMWriteResPair<WriteCvtPD2I, [SLM_FPC_RSV01], 4>; 275defm : SLMWriteResPair<WriteCvtPD2IY, [SLM_FPC_RSV01], 4>; 276defm : X86WriteResPairUnsupported<WriteCvtPD2IZ>; 277 278defm : SLMWriteResPair<WriteCvtI2SS, [SLM_FPC_RSV01], 4>; 279defm : SLMWriteResPair<WriteCvtI2PS, [SLM_FPC_RSV01], 4>; 280defm : SLMWriteResPair<WriteCvtI2PSY, [SLM_FPC_RSV01], 4>; 281defm : X86WriteResPairUnsupported<WriteCvtI2PSZ>; 282defm : SLMWriteResPair<WriteCvtI2SD, [SLM_FPC_RSV01], 4>; 283defm : SLMWriteResPair<WriteCvtI2PD, [SLM_FPC_RSV01], 4>; 284defm : SLMWriteResPair<WriteCvtI2PDY, [SLM_FPC_RSV01], 4>; 285defm : X86WriteResPairUnsupported<WriteCvtI2PDZ>; 286 287defm : SLMWriteResPair<WriteCvtSS2SD, [SLM_FPC_RSV01], 4>; 288defm : SLMWriteResPair<WriteCvtPS2PD, [SLM_FPC_RSV01], 4>; 289defm : SLMWriteResPair<WriteCvtPS2PDY, [SLM_FPC_RSV01], 4>; 290defm : X86WriteResPairUnsupported<WriteCvtPS2PDZ>; 291defm : SLMWriteResPair<WriteCvtSD2SS, [SLM_FPC_RSV01], 4>; 292defm : SLMWriteResPair<WriteCvtPD2PS, [SLM_FPC_RSV01], 4>; 293defm : SLMWriteResPair<WriteCvtPD2PSY, [SLM_FPC_RSV01], 4>; 294defm : X86WriteResPairUnsupported<WriteCvtPD2PSZ>; 295 296// Vector integer operations. 297def : WriteRes<WriteVecLoad, [SLM_MEC_RSV]> { let Latency = 3; } 298def : WriteRes<WriteVecLoadX, [SLM_MEC_RSV]> { let Latency = 3; } 299def : WriteRes<WriteVecLoadY, [SLM_MEC_RSV]> { let Latency = 3; } 300def : WriteRes<WriteVecLoadNT, [SLM_MEC_RSV]> { let Latency = 3; } 301def : WriteRes<WriteVecLoadNTY, [SLM_MEC_RSV]> { let Latency = 3; } 302def : WriteRes<WriteVecMaskedLoad, [SLM_MEC_RSV]> { let Latency = 3; } 303def : WriteRes<WriteVecMaskedLoadY, [SLM_MEC_RSV]> { let Latency = 3; } 304def : WriteRes<WriteVecStore, [SLM_MEC_RSV]>; 305def : WriteRes<WriteVecStoreX, [SLM_MEC_RSV]>; 306def : WriteRes<WriteVecStoreY, [SLM_MEC_RSV]>; 307def : WriteRes<WriteVecStoreNT, [SLM_MEC_RSV]>; 308def : WriteRes<WriteVecStoreNTY, [SLM_MEC_RSV]>; 309def : WriteRes<WriteVecMaskedStore, [SLM_MEC_RSV]>; 310def : WriteRes<WriteVecMaskedStoreY, [SLM_MEC_RSV]>; 311def : WriteRes<WriteVecMove, [SLM_FPC_RSV01]>; 312def : WriteRes<WriteVecMoveX, [SLM_FPC_RSV01]>; 313def : WriteRes<WriteVecMoveY, [SLM_FPC_RSV01]>; 314def : WriteRes<WriteVecMoveToGpr, [SLM_IEC_RSV01]>; 315def : WriteRes<WriteVecMoveFromGpr, [SLM_IEC_RSV01]>; 316 317defm : SLMWriteResPair<WriteVecShift, [SLM_FPC_RSV0], 1>; 318defm : SLMWriteResPair<WriteVecShiftX, [SLM_FPC_RSV0], 1>; 319defm : SLMWriteResPair<WriteVecShiftY, [SLM_FPC_RSV0], 1>; 320defm : X86WriteResPairUnsupported<WriteVecShiftZ>; 321defm : SLMWriteResPair<WriteVecShiftImm, [SLM_FPC_RSV0], 1>; 322defm : SLMWriteResPair<WriteVecShiftImmX,[SLM_FPC_RSV0], 1>; 323defm : SLMWriteResPair<WriteVecShiftImmY,[SLM_FPC_RSV0], 1>; 324defm : X86WriteResPairUnsupported<WriteVecShiftImmZ>; 325defm : SLMWriteResPair<WriteVecLogic, [SLM_FPC_RSV01], 1>; 326defm : SLMWriteResPair<WriteVecLogicX,[SLM_FPC_RSV01], 1>; 327defm : SLMWriteResPair<WriteVecLogicY,[SLM_FPC_RSV01], 1>; 328defm : X86WriteResPairUnsupported<WriteVecLogicZ>; 329defm : SLMWriteResPair<WriteVecTest, [SLM_FPC_RSV01], 1>; 330defm : SLMWriteResPair<WriteVecTestY, [SLM_FPC_RSV01], 1>; 331defm : X86WriteResPairUnsupported<WriteVecTestZ>; 332defm : SLMWriteResPair<WriteVecALU, [SLM_FPC_RSV01], 1>; 333defm : SLMWriteResPair<WriteVecALUX, [SLM_FPC_RSV01], 1>; 334defm : SLMWriteResPair<WriteVecALUY, [SLM_FPC_RSV01], 1>; 335defm : X86WriteResPairUnsupported<WriteVecALUZ>; 336defm : SLMWriteResPair<WriteVecIMul, [SLM_FPC_RSV0], 4>; 337defm : SLMWriteResPair<WriteVecIMulX, [SLM_FPC_RSV0], 4>; 338defm : SLMWriteResPair<WriteVecIMulY, [SLM_FPC_RSV0], 4>; 339defm : X86WriteResPairUnsupported<WriteVecIMulZ>; 340// FIXME: The below is closer to correct, but caused some perf regressions. 341//defm : SLMWriteResPair<WritePMULLD, [SLM_FPC_RSV0], 11, [11], 7>; 342defm : SLMWriteResPair<WritePMULLD, [SLM_FPC_RSV0], 4>; 343defm : SLMWriteResPair<WritePMULLDY, [SLM_FPC_RSV0], 4>; 344defm : X86WriteResPairUnsupported<WritePMULLDZ>; 345defm : SLMWriteResPair<WriteShuffle, [SLM_FPC_RSV0], 1>; 346defm : SLMWriteResPair<WriteShuffleY, [SLM_FPC_RSV0], 1>; 347defm : X86WriteResPairUnsupported<WriteShuffleZ>; 348defm : SLMWriteResPair<WriteShuffleX, [SLM_FPC_RSV0], 1>; 349defm : SLMWriteResPair<WriteVarShuffle, [SLM_FPC_RSV0], 1>; 350defm : SLMWriteResPair<WriteVarShuffleX, [SLM_FPC_RSV0], 1>; 351defm : SLMWriteResPair<WriteVarShuffleY, [SLM_FPC_RSV0], 1>; 352defm : X86WriteResPairUnsupported<WriteVarShuffleZ>; 353defm : SLMWriteResPair<WriteBlend, [SLM_FPC_RSV0], 1>; 354defm : SLMWriteResPair<WriteBlendY, [SLM_FPC_RSV0], 1>; 355defm : X86WriteResPairUnsupported<WriteBlendZ>; 356defm : SLMWriteResPair<WriteMPSAD, [SLM_FPC_RSV0], 7>; 357defm : SLMWriteResPair<WriteMPSADY, [SLM_FPC_RSV0], 7>; 358defm : X86WriteResPairUnsupported<WriteMPSADZ>; 359defm : SLMWriteResPair<WritePSADBW, [SLM_FPC_RSV0], 4>; 360defm : SLMWriteResPair<WritePSADBWX, [SLM_FPC_RSV0], 4>; 361defm : SLMWriteResPair<WritePSADBWY, [SLM_FPC_RSV0], 4>; 362defm : X86WriteResPairUnsupported<WritePSADBWZ>; 363defm : SLMWriteResPair<WritePHMINPOS, [SLM_FPC_RSV0], 4>; 364 365// Vector insert/extract operations. 366defm : SLMWriteResPair<WriteVecInsert, [SLM_FPC_RSV0], 1>; 367 368def : WriteRes<WriteVecExtract, [SLM_FPC_RSV0]>; 369def : WriteRes<WriteVecExtractSt, [SLM_FPC_RSV0, SLM_MEC_RSV]> { 370 let Latency = 4; 371 let NumMicroOps = 2; 372 let ResourceCycles = [1, 2]; 373} 374 375//////////////////////////////////////////////////////////////////////////////// 376// Horizontal add/sub instructions. 377//////////////////////////////////////////////////////////////////////////////// 378 379defm : SLMWriteResPair<WriteFHAdd, [SLM_FPC_RSV01], 3, [2]>; 380defm : SLMWriteResPair<WriteFHAddY, [SLM_FPC_RSV01], 3, [2]>; 381defm : X86WriteResPairUnsupported<WriteFHAddZ>; 382defm : SLMWriteResPair<WritePHAdd, [SLM_FPC_RSV01], 1>; 383defm : SLMWriteResPair<WritePHAddX, [SLM_FPC_RSV01], 1>; 384defm : SLMWriteResPair<WritePHAddY, [SLM_FPC_RSV01], 1>; 385defm : X86WriteResPairUnsupported<WritePHAddZ>; 386 387// String instructions. 388// Packed Compare Implicit Length Strings, Return Mask 389def : WriteRes<WritePCmpIStrM, [SLM_FPC_RSV0]> { 390 let Latency = 13; 391 let ResourceCycles = [13]; 392} 393def : WriteRes<WritePCmpIStrMLd, [SLM_FPC_RSV0, SLM_MEC_RSV]> { 394 let Latency = 13; 395 let ResourceCycles = [13, 1]; 396} 397 398// Packed Compare Explicit Length Strings, Return Mask 399def : WriteRes<WritePCmpEStrM, [SLM_FPC_RSV0]> { 400 let Latency = 17; 401 let ResourceCycles = [17]; 402} 403def : WriteRes<WritePCmpEStrMLd, [SLM_FPC_RSV0, SLM_MEC_RSV]> { 404 let Latency = 17; 405 let ResourceCycles = [17, 1]; 406} 407 408// Packed Compare Implicit Length Strings, Return Index 409def : WriteRes<WritePCmpIStrI, [SLM_FPC_RSV0]> { 410 let Latency = 17; 411 let ResourceCycles = [17]; 412} 413def : WriteRes<WritePCmpIStrILd, [SLM_FPC_RSV0, SLM_MEC_RSV]> { 414 let Latency = 17; 415 let ResourceCycles = [17, 1]; 416} 417 418// Packed Compare Explicit Length Strings, Return Index 419def : WriteRes<WritePCmpEStrI, [SLM_FPC_RSV0]> { 420 let Latency = 21; 421 let ResourceCycles = [21]; 422} 423def : WriteRes<WritePCmpEStrILd, [SLM_FPC_RSV0, SLM_MEC_RSV]> { 424 let Latency = 21; 425 let ResourceCycles = [21, 1]; 426} 427 428// MOVMSK Instructions. 429def : WriteRes<WriteFMOVMSK, [SLM_FPC_RSV1]> { let Latency = 4; } 430def : WriteRes<WriteVecMOVMSK, [SLM_FPC_RSV1]> { let Latency = 4; } 431def : WriteRes<WriteVecMOVMSKY, [SLM_FPC_RSV1]> { let Latency = 4; } 432def : WriteRes<WriteMMXMOVMSK, [SLM_FPC_RSV1]> { let Latency = 4; } 433 434// AES Instructions. 435def : WriteRes<WriteAESDecEnc, [SLM_FPC_RSV0]> { 436 let Latency = 8; 437 let ResourceCycles = [5]; 438} 439def : WriteRes<WriteAESDecEncLd, [SLM_FPC_RSV0, SLM_MEC_RSV]> { 440 let Latency = 8; 441 let ResourceCycles = [5, 1]; 442} 443 444def : WriteRes<WriteAESIMC, [SLM_FPC_RSV0]> { 445 let Latency = 8; 446 let ResourceCycles = [5]; 447} 448def : WriteRes<WriteAESIMCLd, [SLM_FPC_RSV0, SLM_MEC_RSV]> { 449 let Latency = 8; 450 let ResourceCycles = [5, 1]; 451} 452 453def : WriteRes<WriteAESKeyGen, [SLM_FPC_RSV0]> { 454 let Latency = 8; 455 let ResourceCycles = [5]; 456} 457def : WriteRes<WriteAESKeyGenLd, [SLM_FPC_RSV0, SLM_MEC_RSV]> { 458 let Latency = 8; 459 let ResourceCycles = [5, 1]; 460} 461 462// Carry-less multiplication instructions. 463def : WriteRes<WriteCLMul, [SLM_FPC_RSV0]> { 464 let Latency = 10; 465 let ResourceCycles = [10]; 466} 467def : WriteRes<WriteCLMulLd, [SLM_FPC_RSV0, SLM_MEC_RSV]> { 468 let Latency = 10; 469 let ResourceCycles = [10, 1]; 470} 471 472def : WriteRes<WriteSystem, [SLM_FPC_RSV0]> { let Latency = 100; } 473def : WriteRes<WriteMicrocoded, [SLM_FPC_RSV0]> { let Latency = 100; } 474def : WriteRes<WriteFence, [SLM_MEC_RSV]>; 475def : WriteRes<WriteNop, []>; 476 477// AVX/FMA is not supported on that architecture, but we should define the basic 478// scheduling resources anyway. 479def : WriteRes<WriteIMulH, [SLM_FPC_RSV0]>; 480defm : X86WriteResPairUnsupported<WriteFBlendY>; 481defm : X86WriteResPairUnsupported<WriteFBlendZ>; 482defm : SLMWriteResPair<WriteVarBlend, [SLM_FPC_RSV0], 1>; 483defm : X86WriteResPairUnsupported<WriteVarBlendY>; 484defm : X86WriteResPairUnsupported<WriteVarBlendZ>; 485defm : SLMWriteResPair<WriteFVarBlend, [SLM_FPC_RSV0], 1>; 486defm : X86WriteResPairUnsupported<WriteFVarBlendY>; 487defm : X86WriteResPairUnsupported<WriteFVarBlendZ>; 488defm : X86WriteResPairUnsupported<WriteFShuffle256>; 489defm : X86WriteResPairUnsupported<WriteFVarShuffle256>; 490defm : X86WriteResPairUnsupported<WriteShuffle256>; 491defm : X86WriteResPairUnsupported<WriteVarShuffle256>; 492defm : SLMWriteResPair<WriteVarVecShift, [SLM_FPC_RSV0], 1>; 493defm : X86WriteResPairUnsupported<WriteVarVecShiftY>; 494defm : X86WriteResPairUnsupported<WriteVarVecShiftZ>; 495defm : X86WriteResPairUnsupported<WriteFMA>; 496defm : X86WriteResPairUnsupported<WriteFMAX>; 497defm : X86WriteResPairUnsupported<WriteFMAY>; 498defm : X86WriteResPairUnsupported<WriteFMAZ>; 499 500defm : X86WriteResPairUnsupported<WriteCvtPH2PS>; 501defm : X86WriteResPairUnsupported<WriteCvtPH2PSY>; 502defm : X86WriteResPairUnsupported<WriteCvtPH2PSZ>; 503defm : X86WriteResUnsupported<WriteCvtPS2PH>; 504defm : X86WriteResUnsupported<WriteCvtPS2PHY>; 505defm : X86WriteResUnsupported<WriteCvtPS2PHZ>; 506defm : X86WriteResUnsupported<WriteCvtPS2PHSt>; 507defm : X86WriteResUnsupported<WriteCvtPS2PHYSt>; 508defm : X86WriteResUnsupported<WriteCvtPS2PHZSt>; 509 510} // SchedModel 511