xref: /freebsd/contrib/llvm-project/llvm/lib/Target/X86/X86ScheduleSLM.td (revision 32100375a661c1e16588ddfa7b90ca8d26cb9786)
1//=- X86ScheduleSLM.td - X86 Silvermont Scheduling -----------*- tablegen -*-=//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the machine model for Intel Silvermont to support
10// instruction scheduling and other instruction cost heuristics.
11//
12//===----------------------------------------------------------------------===//
13
14def SLMModel : SchedMachineModel {
15  // All x86 instructions are modeled as a single micro-op, and SLM can decode 2
16  // instructions per cycle.
17  let IssueWidth = 2;
18  let MicroOpBufferSize = 32; // Based on the reorder buffer.
19  let LoadLatency = 3;
20  let MispredictPenalty = 10;
21  let PostRAScheduler = 1;
22
23  // For small loops, expand by a small factor to hide the backedge cost.
24  let LoopMicroOpBufferSize = 10;
25
26  // FIXME: SSE4 is unimplemented. This flag is set to allow
27  // the scheduler to assign a default model to unrecognized opcodes.
28  let CompleteModel = 0;
29}
30
31let SchedModel = SLMModel in {
32
33// Silvermont has 5 reservation stations for micro-ops
34def SLM_IEC_RSV0 : ProcResource<1>;
35def SLM_IEC_RSV1 : ProcResource<1>;
36def SLM_FPC_RSV0 : ProcResource<1> { let BufferSize = 1; }
37def SLM_FPC_RSV1 : ProcResource<1> { let BufferSize = 1; }
38def SLM_MEC_RSV  : ProcResource<1>;
39
40// Many micro-ops are capable of issuing on multiple ports.
41def SLM_IEC_RSV01  : ProcResGroup<[SLM_IEC_RSV0, SLM_IEC_RSV1]>;
42def SLM_FPC_RSV01  : ProcResGroup<[SLM_FPC_RSV0, SLM_FPC_RSV1]>;
43
44def SLMDivider      : ProcResource<1>;
45def SLMFPMultiplier : ProcResource<1>;
46def SLMFPDivider    : ProcResource<1>;
47
48// Loads are 3 cycles, so ReadAfterLd registers needn't be available until 3
49// cycles after the memory operand.
50def : ReadAdvance<ReadAfterLd, 3>;
51def : ReadAdvance<ReadAfterVecLd, 3>;
52def : ReadAdvance<ReadAfterVecXLd, 3>;
53def : ReadAdvance<ReadAfterVecYLd, 3>;
54
55def : ReadAdvance<ReadInt2Fpu, 0>;
56
57// Many SchedWrites are defined in pairs with and without a folded load.
58// Instructions with folded loads are usually micro-fused, so they only appear
59// as two micro-ops when queued in the reservation station.
60// This multiclass defines the resource usage for variants with and without
61// folded loads.
62multiclass SLMWriteResPair<X86FoldableSchedWrite SchedRW,
63                           list<ProcResourceKind> ExePorts,
64                           int Lat, list<int> Res = [1], int UOps = 1,
65                           int LoadLat = 3> {
66  // Register variant is using a single cycle on ExePort.
67  def : WriteRes<SchedRW, ExePorts> {
68    let Latency = Lat;
69    let ResourceCycles = Res;
70    let NumMicroOps = UOps;
71  }
72
73  // Memory variant also uses a cycle on MEC_RSV and adds LoadLat cycles to
74  // the latency (default = 3).
75  def : WriteRes<SchedRW.Folded, !listconcat([SLM_MEC_RSV], ExePorts)> {
76    let Latency = !add(Lat, LoadLat);
77    let ResourceCycles = !listconcat([1], Res);
78    let NumMicroOps = UOps;
79  }
80}
81
82// A folded store needs a cycle on MEC_RSV for the store data, but it does not
83// need an extra port cycle to recompute the address.
84def : WriteRes<WriteRMW, [SLM_MEC_RSV]>;
85
86def : WriteRes<WriteStore,   [SLM_IEC_RSV01, SLM_MEC_RSV]>;
87def : WriteRes<WriteStoreNT, [SLM_IEC_RSV01, SLM_MEC_RSV]>;
88def : WriteRes<WriteLoad,    [SLM_MEC_RSV]> { let Latency = 3; }
89def : WriteRes<WriteMove,    [SLM_IEC_RSV01]>;
90def : WriteRes<WriteZero,    []>;
91
92// Load/store MXCSR.
93// FIXME: These are probably wrong. They are copy pasted from WriteStore/Load.
94def : WriteRes<WriteSTMXCSR, [SLM_IEC_RSV01, SLM_MEC_RSV]>;
95def : WriteRes<WriteLDMXCSR,  [SLM_MEC_RSV]> { let Latency = 3; }
96
97// Treat misc copies as a move.
98def : InstRW<[WriteMove], (instrs COPY)>;
99
100defm : SLMWriteResPair<WriteALU,    [SLM_IEC_RSV01], 1>;
101defm : SLMWriteResPair<WriteADC,    [SLM_IEC_RSV01], 1>;
102
103defm : SLMWriteResPair<WriteIMul8,     [SLM_IEC_RSV1],  3>;
104defm : SLMWriteResPair<WriteIMul16,    [SLM_IEC_RSV1],  3>;
105defm : SLMWriteResPair<WriteIMul16Imm, [SLM_IEC_RSV1],  3>;
106defm : SLMWriteResPair<WriteIMul16Reg, [SLM_IEC_RSV1],  3>;
107defm : SLMWriteResPair<WriteIMul32,    [SLM_IEC_RSV1],  3>;
108defm : SLMWriteResPair<WriteIMul32Imm, [SLM_IEC_RSV1],  3>;
109defm : SLMWriteResPair<WriteIMul32Reg, [SLM_IEC_RSV1],  3>;
110defm : SLMWriteResPair<WriteIMul64,    [SLM_IEC_RSV1],  3>;
111defm : SLMWriteResPair<WriteIMul64Imm, [SLM_IEC_RSV1],  3>;
112defm : SLMWriteResPair<WriteIMul64Reg, [SLM_IEC_RSV1],  3>;
113
114defm : X86WriteRes<WriteBSWAP32, [SLM_IEC_RSV01], 1, [1], 1>;
115defm : X86WriteRes<WriteBSWAP64, [SLM_IEC_RSV01], 1, [1], 1>;
116defm : X86WriteRes<WriteCMPXCHG, [SLM_IEC_RSV01], 1, [1], 1>;
117defm : X86WriteRes<WriteCMPXCHGRMW, [SLM_IEC_RSV01, SLM_MEC_RSV], 4, [1, 2], 2>;
118defm : X86WriteRes<WriteXCHG,      [SLM_IEC_RSV01], 1, [1], 1>;
119
120defm : SLMWriteResPair<WriteShift,    [SLM_IEC_RSV0],  1>;
121defm : SLMWriteResPair<WriteShiftCL,  [SLM_IEC_RSV0],  1>;
122defm : SLMWriteResPair<WriteRotate,   [SLM_IEC_RSV0],  1>;
123defm : SLMWriteResPair<WriteRotateCL, [SLM_IEC_RSV0],  1>;
124
125defm : X86WriteRes<WriteSHDrri, [SLM_IEC_RSV0],  1, [1], 1>;
126defm : X86WriteRes<WriteSHDrrcl,[SLM_IEC_RSV0],  1, [1], 1>;
127defm : X86WriteRes<WriteSHDmri, [SLM_MEC_RSV, SLM_IEC_RSV0], 4, [2, 1], 2>;
128defm : X86WriteRes<WriteSHDmrcl,[SLM_MEC_RSV, SLM_IEC_RSV0], 4, [2, 1], 2>;
129
130defm : SLMWriteResPair<WriteJump,   [SLM_IEC_RSV1],  1>;
131defm : SLMWriteResPair<WriteCRC32,  [SLM_IEC_RSV1],  3>;
132
133defm : SLMWriteResPair<WriteCMOV,  [SLM_IEC_RSV01], 2, [2]>;
134defm : X86WriteRes<WriteFCMOV, [SLM_FPC_RSV1], 3, [1], 1>; // x87 conditional move.
135def  : WriteRes<WriteSETCC, [SLM_IEC_RSV01]>;
136def  : WriteRes<WriteSETCCStore, [SLM_IEC_RSV01, SLM_MEC_RSV]> {
137  // FIXME Latency and NumMicrOps?
138  let ResourceCycles = [2,1];
139}
140defm : X86WriteRes<WriteLAHFSAHF,        [SLM_IEC_RSV01], 1, [1], 1>;
141defm : X86WriteRes<WriteBitTest,         [SLM_IEC_RSV01], 1, [1], 1>;
142defm : X86WriteRes<WriteBitTestImmLd,    [SLM_IEC_RSV01, SLM_MEC_RSV], 4, [1,1], 1>;
143defm : X86WriteRes<WriteBitTestRegLd,    [SLM_IEC_RSV01, SLM_MEC_RSV], 4, [1,1], 1>;
144defm : X86WriteRes<WriteBitTestSet,      [SLM_IEC_RSV01], 1, [1], 1>;
145defm : X86WriteRes<WriteBitTestSetImmLd, [SLM_IEC_RSV01, SLM_MEC_RSV], 3, [1,1], 1>;
146defm : X86WriteRes<WriteBitTestSetRegLd, [SLM_IEC_RSV01, SLM_MEC_RSV], 3, [1,1], 1>;
147
148// This is for simple LEAs with one or two input operands.
149// The complex ones can only execute on port 1, and they require two cycles on
150// the port to read all inputs. We don't model that.
151def : WriteRes<WriteLEA, [SLM_IEC_RSV1]>;
152
153// Bit counts.
154defm : SLMWriteResPair<WriteBSF, [SLM_IEC_RSV01], 10, [20], 10>;
155defm : SLMWriteResPair<WriteBSR, [SLM_IEC_RSV01], 10, [20], 10>;
156defm : SLMWriteResPair<WriteLZCNT,          [SLM_IEC_RSV0], 3>;
157defm : SLMWriteResPair<WriteTZCNT,          [SLM_IEC_RSV0], 3>;
158defm : SLMWriteResPair<WritePOPCNT,         [SLM_IEC_RSV0], 3>;
159
160// BMI1 BEXTR/BLS, BMI2 BZHI
161defm : X86WriteResPairUnsupported<WriteBEXTR>;
162defm : X86WriteResPairUnsupported<WriteBLS>;
163defm : X86WriteResPairUnsupported<WriteBZHI>;
164
165defm : SLMWriteResPair<WriteDiv8,   [SLM_IEC_RSV01, SLMDivider], 25, [1,25], 1, 4>;
166defm : SLMWriteResPair<WriteDiv16,  [SLM_IEC_RSV01, SLMDivider], 25, [1,25], 1, 4>;
167defm : SLMWriteResPair<WriteDiv32,  [SLM_IEC_RSV01, SLMDivider], 25, [1,25], 1, 4>;
168defm : SLMWriteResPair<WriteDiv64,  [SLM_IEC_RSV01, SLMDivider], 25, [1,25], 1, 4>;
169defm : SLMWriteResPair<WriteIDiv8,  [SLM_IEC_RSV01, SLMDivider], 25, [1,25], 1, 4>;
170defm : SLMWriteResPair<WriteIDiv16, [SLM_IEC_RSV01, SLMDivider], 25, [1,25], 1, 4>;
171defm : SLMWriteResPair<WriteIDiv32, [SLM_IEC_RSV01, SLMDivider], 25, [1,25], 1, 4>;
172defm : SLMWriteResPair<WriteIDiv64, [SLM_IEC_RSV01, SLMDivider], 25, [1,25], 1, 4>;
173
174// Scalar and vector floating point.
175defm : X86WriteRes<WriteFLD0,       [SLM_FPC_RSV01], 1, [1], 1>;
176defm : X86WriteRes<WriteFLD1,       [SLM_FPC_RSV01], 1, [1], 1>;
177defm : X86WriteRes<WriteFLDC,       [SLM_FPC_RSV01], 1, [2], 2>;
178def  : WriteRes<WriteFLoad,         [SLM_MEC_RSV]> { let Latency = 3; }
179def  : WriteRes<WriteFLoadX,        [SLM_MEC_RSV]> { let Latency = 3; }
180def  : WriteRes<WriteFLoadY,        [SLM_MEC_RSV]> { let Latency = 3; }
181def  : WriteRes<WriteFMaskedLoad,   [SLM_MEC_RSV]> { let Latency = 3; }
182def  : WriteRes<WriteFMaskedLoadY,  [SLM_MEC_RSV]> { let Latency = 3; }
183def  : WriteRes<WriteFStore,        [SLM_MEC_RSV]>;
184def  : WriteRes<WriteFStoreX,       [SLM_MEC_RSV]>;
185def  : WriteRes<WriteFStoreY,       [SLM_MEC_RSV]>;
186def  : WriteRes<WriteFStoreNT,      [SLM_MEC_RSV]>;
187def  : WriteRes<WriteFStoreNTX,     [SLM_MEC_RSV]>;
188def  : WriteRes<WriteFStoreNTY,     [SLM_MEC_RSV]>;
189
190def  : WriteRes<WriteFMaskedStore32,    [SLM_MEC_RSV]>;
191def  : WriteRes<WriteFMaskedStore32Y,   [SLM_MEC_RSV]>;
192def  : WriteRes<WriteFMaskedStore64,    [SLM_MEC_RSV]>;
193def  : WriteRes<WriteFMaskedStore64Y,   [SLM_MEC_RSV]>;
194
195def  : WriteRes<WriteFMove,         [SLM_FPC_RSV01]>;
196def  : WriteRes<WriteFMoveX,        [SLM_FPC_RSV01]>;
197def  : WriteRes<WriteFMoveY,        [SLM_FPC_RSV01]>;
198defm : X86WriteRes<WriteEMMS,       [SLM_FPC_RSV01], 10, [10], 9>;
199
200defm : SLMWriteResPair<WriteFAdd,     [SLM_FPC_RSV1], 3>;
201defm : SLMWriteResPair<WriteFAddX,    [SLM_FPC_RSV1], 3>;
202defm : SLMWriteResPair<WriteFAddY,    [SLM_FPC_RSV1], 3>;
203defm : X86WriteResPairUnsupported<WriteFAddZ>;
204defm : SLMWriteResPair<WriteFAdd64,   [SLM_FPC_RSV1], 3>;
205defm : SLMWriteResPair<WriteFAdd64X,  [SLM_FPC_RSV1], 4, [2]>;
206defm : SLMWriteResPair<WriteFAdd64Y,  [SLM_FPC_RSV1], 4, [2]>;
207defm : X86WriteResPairUnsupported<WriteFAdd64Z>;
208defm : SLMWriteResPair<WriteFCmp,     [SLM_FPC_RSV1], 3>;
209defm : SLMWriteResPair<WriteFCmpX,    [SLM_FPC_RSV1], 3>;
210defm : SLMWriteResPair<WriteFCmpY,    [SLM_FPC_RSV1], 3>;
211defm : X86WriteResPairUnsupported<WriteFCmpZ>;
212defm : SLMWriteResPair<WriteFCmp64,   [SLM_FPC_RSV1], 3>;
213defm : SLMWriteResPair<WriteFCmp64X,  [SLM_FPC_RSV1], 3>;
214defm : SLMWriteResPair<WriteFCmp64Y,  [SLM_FPC_RSV1], 3>;
215defm : X86WriteResPairUnsupported<WriteFCmp64Z>;
216defm : SLMWriteResPair<WriteFCom,     [SLM_FPC_RSV1], 3>;
217defm : SLMWriteResPair<WriteFMul,     [SLM_FPC_RSV0, SLMFPMultiplier], 5, [1,2]>;
218defm : SLMWriteResPair<WriteFMulX,    [SLM_FPC_RSV0, SLMFPMultiplier], 5, [1,2]>;
219defm : SLMWriteResPair<WriteFMulY,    [SLM_FPC_RSV0, SLMFPMultiplier], 5, [1,2]>;
220defm : X86WriteResPairUnsupported<WriteFMulZ>;
221defm : SLMWriteResPair<WriteFMul64,   [SLM_FPC_RSV0, SLMFPMultiplier], 5, [1,2]>;
222defm : SLMWriteResPair<WriteFMul64X,  [SLM_FPC_RSV0, SLMFPMultiplier], 7, [1,4]>;
223defm : SLMWriteResPair<WriteFMul64Y,  [SLM_FPC_RSV0, SLMFPMultiplier], 7, [1,4]>;
224defm : X86WriteResPairUnsupported<WriteFMul64Z>;
225defm : SLMWriteResPair<WriteFDiv,     [SLM_FPC_RSV0, SLMFPDivider], 19, [1,17]>;
226defm : SLMWriteResPair<WriteFDivX,    [SLM_FPC_RSV0, SLMFPDivider], 39, [1,39]>;
227defm : SLMWriteResPair<WriteFDivY,    [SLM_FPC_RSV0, SLMFPDivider], 39, [1,39]>;
228defm : X86WriteResPairUnsupported<WriteFDivZ>;
229defm : SLMWriteResPair<WriteFDiv64,   [SLM_FPC_RSV0, SLMFPDivider], 34, [1,32]>;
230defm : SLMWriteResPair<WriteFDiv64X,  [SLM_FPC_RSV0, SLMFPDivider], 69, [1,69]>;
231defm : SLMWriteResPair<WriteFDiv64Y,  [SLM_FPC_RSV0, SLMFPDivider], 69, [1,69]>;
232defm : X86WriteResPairUnsupported<WriteFDiv64Z>;
233defm : SLMWriteResPair<WriteFRcp,     [SLM_FPC_RSV0], 5>;
234defm : SLMWriteResPair<WriteFRcpX,    [SLM_FPC_RSV0], 5>;
235defm : SLMWriteResPair<WriteFRcpY,    [SLM_FPC_RSV0], 5>;
236defm : X86WriteResPairUnsupported<WriteFRcpZ>;
237defm : SLMWriteResPair<WriteFRsqrt,   [SLM_FPC_RSV0], 5>;
238defm : SLMWriteResPair<WriteFRsqrtX,  [SLM_FPC_RSV0], 5>;
239defm : SLMWriteResPair<WriteFRsqrtY,  [SLM_FPC_RSV0], 5>;
240defm : X86WriteResPairUnsupported<WriteFRsqrtZ>;
241defm : SLMWriteResPair<WriteFSqrt,    [SLM_FPC_RSV0,SLMFPDivider], 20, [1,20], 1, 3>;
242defm : SLMWriteResPair<WriteFSqrtX,   [SLM_FPC_RSV0,SLMFPDivider], 41, [1,40], 1, 3>;
243defm : SLMWriteResPair<WriteFSqrtY,   [SLM_FPC_RSV0,SLMFPDivider], 41, [1,40], 1, 3>;
244defm : X86WriteResPairUnsupported<WriteFSqrtZ>;
245defm : SLMWriteResPair<WriteFSqrt64,  [SLM_FPC_RSV0,SLMFPDivider], 35, [1,35], 1, 3>;
246defm : SLMWriteResPair<WriteFSqrt64X, [SLM_FPC_RSV0,SLMFPDivider], 71, [1,70], 1, 3>;
247defm : SLMWriteResPair<WriteFSqrt64Y, [SLM_FPC_RSV0,SLMFPDivider], 71, [1,70], 1, 3>;
248defm : X86WriteResPairUnsupported<WriteFSqrt64Z>;
249defm : SLMWriteResPair<WriteFSqrt80,  [SLM_FPC_RSV0,SLMFPDivider], 40, [1,40]>;
250defm : SLMWriteResPair<WriteDPPD,   [SLM_FPC_RSV1], 3>;
251defm : SLMWriteResPair<WriteDPPS,   [SLM_FPC_RSV1], 3>;
252defm : SLMWriteResPair<WriteDPPSY,  [SLM_FPC_RSV1], 3>;
253defm : X86WriteResPairUnsupported<WriteDPPSZ>;
254defm : SLMWriteResPair<WriteFSign,  [SLM_FPC_RSV01], 1>;
255defm : SLMWriteResPair<WriteFRnd,   [SLM_FPC_RSV1], 3>;
256defm : SLMWriteResPair<WriteFRndY,  [SLM_FPC_RSV1], 3>;
257defm : X86WriteResPairUnsupported<WriteFRndZ>;
258defm : SLMWriteResPair<WriteFLogic, [SLM_FPC_RSV01], 1>;
259defm : SLMWriteResPair<WriteFLogicY, [SLM_FPC_RSV01], 1>;
260defm : X86WriteResPairUnsupported<WriteFLogicZ>;
261defm : SLMWriteResPair<WriteFTest,  [SLM_FPC_RSV01], 1>;
262defm : SLMWriteResPair<WriteFTestY, [SLM_FPC_RSV01], 1>;
263defm : X86WriteResPairUnsupported<WriteFTestZ>;
264defm : SLMWriteResPair<WriteFShuffle,  [SLM_FPC_RSV0], 1>;
265defm : SLMWriteResPair<WriteFShuffleY, [SLM_FPC_RSV0], 1>;
266defm : X86WriteResPairUnsupported<WriteFShuffleZ>;
267defm : SLMWriteResPair<WriteFVarShuffle, [SLM_FPC_RSV0],  1>;
268defm : SLMWriteResPair<WriteFVarShuffleY,[SLM_FPC_RSV0],  1>;
269defm : X86WriteResPairUnsupported<WriteFVarShuffleZ>;
270defm : SLMWriteResPair<WriteFBlend,  [SLM_FPC_RSV0],  1>;
271
272// Conversion between integer and float.
273defm : SLMWriteResPair<WriteCvtSS2I,   [SLM_FPC_RSV01], 4>;
274defm : SLMWriteResPair<WriteCvtPS2I,   [SLM_FPC_RSV01], 4>;
275defm : SLMWriteResPair<WriteCvtPS2IY,  [SLM_FPC_RSV01], 4>;
276defm : X86WriteResPairUnsupported<WriteCvtPS2IZ>;
277defm : SLMWriteResPair<WriteCvtSD2I,   [SLM_FPC_RSV01], 4>;
278defm : SLMWriteResPair<WriteCvtPD2I,   [SLM_FPC_RSV01], 4>;
279defm : SLMWriteResPair<WriteCvtPD2IY,  [SLM_FPC_RSV01], 4>;
280defm : X86WriteResPairUnsupported<WriteCvtPD2IZ>;
281
282defm : SLMWriteResPair<WriteCvtI2SS,   [SLM_FPC_RSV01], 4>;
283defm : SLMWriteResPair<WriteCvtI2PS,   [SLM_FPC_RSV01], 4>;
284defm : SLMWriteResPair<WriteCvtI2PSY,  [SLM_FPC_RSV01], 4>;
285defm : X86WriteResPairUnsupported<WriteCvtI2PSZ>;
286defm : SLMWriteResPair<WriteCvtI2SD,   [SLM_FPC_RSV01], 4>;
287defm : SLMWriteResPair<WriteCvtI2PD,   [SLM_FPC_RSV01], 4>;
288defm : SLMWriteResPair<WriteCvtI2PDY,  [SLM_FPC_RSV01], 4>;
289defm : X86WriteResPairUnsupported<WriteCvtI2PDZ>;
290
291defm : SLMWriteResPair<WriteCvtSS2SD,  [SLM_FPC_RSV01], 4>;
292defm : SLMWriteResPair<WriteCvtPS2PD,  [SLM_FPC_RSV01], 4>;
293defm : SLMWriteResPair<WriteCvtPS2PDY, [SLM_FPC_RSV01], 4>;
294defm : X86WriteResPairUnsupported<WriteCvtPS2PDZ>;
295defm : SLMWriteResPair<WriteCvtSD2SS,  [SLM_FPC_RSV01], 4>;
296defm : SLMWriteResPair<WriteCvtPD2PS,  [SLM_FPC_RSV01], 4>;
297defm : SLMWriteResPair<WriteCvtPD2PSY, [SLM_FPC_RSV01], 4>;
298defm : X86WriteResPairUnsupported<WriteCvtPD2PSZ>;
299
300// Vector integer operations.
301def  : WriteRes<WriteVecLoad,         [SLM_MEC_RSV]> { let Latency = 3; }
302def  : WriteRes<WriteVecLoadX,        [SLM_MEC_RSV]> { let Latency = 3; }
303def  : WriteRes<WriteVecLoadY,        [SLM_MEC_RSV]> { let Latency = 3; }
304def  : WriteRes<WriteVecLoadNT,       [SLM_MEC_RSV]> { let Latency = 3; }
305def  : WriteRes<WriteVecLoadNTY,      [SLM_MEC_RSV]> { let Latency = 3; }
306def  : WriteRes<WriteVecMaskedLoad,   [SLM_MEC_RSV]> { let Latency = 3; }
307def  : WriteRes<WriteVecMaskedLoadY,  [SLM_MEC_RSV]> { let Latency = 3; }
308def  : WriteRes<WriteVecStore,        [SLM_MEC_RSV]>;
309def  : WriteRes<WriteVecStoreX,       [SLM_MEC_RSV]>;
310def  : WriteRes<WriteVecStoreY,       [SLM_MEC_RSV]>;
311def  : WriteRes<WriteVecStoreNT,      [SLM_MEC_RSV]>;
312def  : WriteRes<WriteVecStoreNTY,     [SLM_MEC_RSV]>;
313def  : WriteRes<WriteVecMaskedStore,  [SLM_MEC_RSV]>;
314def  : WriteRes<WriteVecMaskedStoreY, [SLM_MEC_RSV]>;
315def  : WriteRes<WriteVecMove,         [SLM_FPC_RSV01]>;
316def  : WriteRes<WriteVecMoveX,        [SLM_FPC_RSV01]>;
317def  : WriteRes<WriteVecMoveY,        [SLM_FPC_RSV01]>;
318def  : WriteRes<WriteVecMoveToGpr,    [SLM_IEC_RSV01]>;
319def  : WriteRes<WriteVecMoveFromGpr,  [SLM_IEC_RSV01]>;
320
321defm : SLMWriteResPair<WriteVecShift,    [SLM_FPC_RSV0],  1>;
322defm : SLMWriteResPair<WriteVecShiftX,   [SLM_FPC_RSV0],  1>;
323defm : SLMWriteResPair<WriteVecShiftY,   [SLM_FPC_RSV0],  1>;
324defm : X86WriteResPairUnsupported<WriteVecShiftZ>;
325defm : SLMWriteResPair<WriteVecShiftImm, [SLM_FPC_RSV0],  1>;
326defm : SLMWriteResPair<WriteVecShiftImmX,[SLM_FPC_RSV0],  1>;
327defm : SLMWriteResPair<WriteVecShiftImmY,[SLM_FPC_RSV0],  1>;
328defm : X86WriteResPairUnsupported<WriteVecShiftImmZ>;
329defm : SLMWriteResPair<WriteVecLogic, [SLM_FPC_RSV01], 1>;
330defm : SLMWriteResPair<WriteVecLogicX,[SLM_FPC_RSV01], 1>;
331defm : SLMWriteResPair<WriteVecLogicY,[SLM_FPC_RSV01], 1>;
332defm : X86WriteResPairUnsupported<WriteVecLogicZ>;
333defm : SLMWriteResPair<WriteVecTest,  [SLM_FPC_RSV01], 1>;
334defm : SLMWriteResPair<WriteVecTestY, [SLM_FPC_RSV01], 1>;
335defm : X86WriteResPairUnsupported<WriteVecTestZ>;
336defm : SLMWriteResPair<WriteVecALU,   [SLM_FPC_RSV01],  1>;
337defm : SLMWriteResPair<WriteVecALUX,  [SLM_FPC_RSV01],  1>;
338defm : SLMWriteResPair<WriteVecALUY,  [SLM_FPC_RSV01],  1>;
339defm : X86WriteResPairUnsupported<WriteVecALUZ>;
340defm : SLMWriteResPair<WriteVecIMul,  [SLM_FPC_RSV0],   4>;
341defm : SLMWriteResPair<WriteVecIMulX, [SLM_FPC_RSV0],   4>;
342defm : SLMWriteResPair<WriteVecIMulY, [SLM_FPC_RSV0],   4>;
343defm : X86WriteResPairUnsupported<WriteVecIMulZ>;
344// FIXME: The below is closer to correct, but caused some perf regressions.
345//defm : SLMWriteResPair<WritePMULLD,  [SLM_FPC_RSV0],   11, [11], 7>;
346defm : SLMWriteResPair<WritePMULLD,  [SLM_FPC_RSV0],   4>;
347defm : SLMWriteResPair<WritePMULLDY, [SLM_FPC_RSV0],   4>;
348defm : X86WriteResPairUnsupported<WritePMULLDZ>;
349defm : SLMWriteResPair<WriteShuffle,  [SLM_FPC_RSV0],  1>;
350defm : SLMWriteResPair<WriteShuffleY, [SLM_FPC_RSV0],  1>;
351defm : X86WriteResPairUnsupported<WriteShuffleZ>;
352defm : SLMWriteResPair<WriteShuffleX, [SLM_FPC_RSV0],  1>;
353defm : SLMWriteResPair<WriteVarShuffle,  [SLM_FPC_RSV0],  1>;
354defm : SLMWriteResPair<WriteVarShuffleX, [SLM_FPC_RSV0],  1>;
355defm : SLMWriteResPair<WriteVarShuffleY, [SLM_FPC_RSV0],  1>;
356defm : X86WriteResPairUnsupported<WriteVarShuffleZ>;
357defm : SLMWriteResPair<WriteBlend,  [SLM_FPC_RSV0],  1>;
358defm : SLMWriteResPair<WriteBlendY, [SLM_FPC_RSV0],  1>;
359defm : X86WriteResPairUnsupported<WriteBlendZ>;
360defm : SLMWriteResPair<WriteMPSAD,  [SLM_FPC_RSV0],  7>;
361defm : SLMWriteResPair<WriteMPSADY, [SLM_FPC_RSV0],  7>;
362defm : X86WriteResPairUnsupported<WriteMPSADZ>;
363defm : SLMWriteResPair<WritePSADBW,  [SLM_FPC_RSV0],  4>;
364defm : SLMWriteResPair<WritePSADBWX, [SLM_FPC_RSV0],  4>;
365defm : SLMWriteResPair<WritePSADBWY, [SLM_FPC_RSV0],  4>;
366defm : X86WriteResPairUnsupported<WritePSADBWZ>;
367defm : SLMWriteResPair<WritePHMINPOS,  [SLM_FPC_RSV0],   4>;
368
369// Vector insert/extract operations.
370defm : SLMWriteResPair<WriteVecInsert, [SLM_FPC_RSV0],  1>;
371
372def  : WriteRes<WriteVecExtract, [SLM_FPC_RSV0]>;
373def  : WriteRes<WriteVecExtractSt, [SLM_FPC_RSV0, SLM_MEC_RSV]> {
374  let Latency = 4;
375  let NumMicroOps = 2;
376  let ResourceCycles = [1, 2];
377}
378
379////////////////////////////////////////////////////////////////////////////////
380// Horizontal add/sub  instructions.
381////////////////////////////////////////////////////////////////////////////////
382
383defm : SLMWriteResPair<WriteFHAdd,   [SLM_FPC_RSV01], 6, [6], 4>;
384defm : SLMWriteResPair<WriteFHAddY,  [SLM_FPC_RSV01], 6, [6], 4>;
385defm : X86WriteResPairUnsupported<WriteFHAddZ>;
386defm : SLMWriteResPair<WritePHAdd,   [SLM_FPC_RSV01], 1>;
387defm : SLMWriteResPair<WritePHAddX,  [SLM_FPC_RSV01], 1>;
388defm : SLMWriteResPair<WritePHAddY,  [SLM_FPC_RSV01], 1>;
389defm : X86WriteResPairUnsupported<WritePHAddZ>;
390
391// String instructions.
392// Packed Compare Implicit Length Strings, Return Mask
393def : WriteRes<WritePCmpIStrM, [SLM_FPC_RSV0]> {
394  let Latency = 13;
395  let ResourceCycles = [13];
396}
397def : WriteRes<WritePCmpIStrMLd, [SLM_FPC_RSV0, SLM_MEC_RSV]> {
398  let Latency = 13;
399  let ResourceCycles = [13, 1];
400}
401
402// Packed Compare Explicit Length Strings, Return Mask
403def : WriteRes<WritePCmpEStrM, [SLM_FPC_RSV0]> {
404  let Latency = 17;
405  let ResourceCycles = [17];
406}
407def : WriteRes<WritePCmpEStrMLd, [SLM_FPC_RSV0, SLM_MEC_RSV]> {
408  let Latency = 17;
409  let ResourceCycles = [17, 1];
410}
411
412// Packed Compare Implicit Length Strings, Return Index
413def : WriteRes<WritePCmpIStrI, [SLM_FPC_RSV0]> {
414  let Latency = 17;
415  let ResourceCycles = [17];
416}
417def : WriteRes<WritePCmpIStrILd, [SLM_FPC_RSV0, SLM_MEC_RSV]> {
418  let Latency = 17;
419  let ResourceCycles = [17, 1];
420}
421
422// Packed Compare Explicit Length Strings, Return Index
423def : WriteRes<WritePCmpEStrI, [SLM_FPC_RSV0]> {
424  let Latency = 21;
425  let ResourceCycles = [21];
426}
427def : WriteRes<WritePCmpEStrILd, [SLM_FPC_RSV0, SLM_MEC_RSV]> {
428  let Latency = 21;
429  let ResourceCycles = [21, 1];
430}
431
432// MOVMSK Instructions.
433def : WriteRes<WriteFMOVMSK,    [SLM_FPC_RSV1]> { let Latency = 4; }
434def : WriteRes<WriteVecMOVMSK,  [SLM_FPC_RSV1]> { let Latency = 4; }
435def : WriteRes<WriteVecMOVMSKY, [SLM_FPC_RSV1]> { let Latency = 4; }
436def : WriteRes<WriteMMXMOVMSK,  [SLM_FPC_RSV1]> { let Latency = 4; }
437
438// AES Instructions.
439def : WriteRes<WriteAESDecEnc, [SLM_FPC_RSV0]> {
440  let Latency = 8;
441  let ResourceCycles = [5];
442}
443def : WriteRes<WriteAESDecEncLd, [SLM_FPC_RSV0, SLM_MEC_RSV]> {
444  let Latency = 8;
445  let ResourceCycles = [5, 1];
446}
447
448def : WriteRes<WriteAESIMC, [SLM_FPC_RSV0]> {
449  let Latency = 8;
450  let ResourceCycles = [5];
451}
452def : WriteRes<WriteAESIMCLd, [SLM_FPC_RSV0, SLM_MEC_RSV]> {
453  let Latency = 8;
454  let ResourceCycles = [5, 1];
455}
456
457def : WriteRes<WriteAESKeyGen, [SLM_FPC_RSV0]> {
458  let Latency = 8;
459  let ResourceCycles = [5];
460}
461def : WriteRes<WriteAESKeyGenLd, [SLM_FPC_RSV0, SLM_MEC_RSV]> {
462  let Latency = 8;
463  let ResourceCycles = [5, 1];
464}
465
466// Carry-less multiplication instructions.
467def : WriteRes<WriteCLMul, [SLM_FPC_RSV0]> {
468  let Latency = 10;
469  let ResourceCycles = [10];
470}
471def : WriteRes<WriteCLMulLd, [SLM_FPC_RSV0, SLM_MEC_RSV]> {
472  let Latency = 10;
473  let ResourceCycles = [10, 1];
474}
475
476def : WriteRes<WriteSystem,     [SLM_FPC_RSV0]> { let Latency = 100; }
477def : WriteRes<WriteMicrocoded, [SLM_FPC_RSV0]> { let Latency = 100; }
478def : WriteRes<WriteFence, [SLM_MEC_RSV]>;
479def : WriteRes<WriteNop, []>;
480
481// AVX/FMA is not supported on that architecture, but we should define the basic
482// scheduling resources anyway.
483def  : WriteRes<WriteIMulH, [SLM_FPC_RSV0]>;
484defm : X86WriteResPairUnsupported<WriteFBlendY>;
485defm : X86WriteResPairUnsupported<WriteFBlendZ>;
486defm : SLMWriteResPair<WriteVarBlend, [SLM_FPC_RSV0], 1>;
487defm : X86WriteResPairUnsupported<WriteVarBlendY>;
488defm : X86WriteResPairUnsupported<WriteVarBlendZ>;
489defm : SLMWriteResPair<WriteFVarBlend, [SLM_FPC_RSV0], 4, [4], 3>;
490defm : X86WriteResPairUnsupported<WriteFVarBlendY>;
491defm : X86WriteResPairUnsupported<WriteFVarBlendZ>;
492defm : X86WriteResPairUnsupported<WriteFShuffle256>;
493defm : X86WriteResPairUnsupported<WriteFVarShuffle256>;
494defm : X86WriteResPairUnsupported<WriteShuffle256>;
495defm : X86WriteResPairUnsupported<WriteVarShuffle256>;
496defm : SLMWriteResPair<WriteVarVecShift,  [SLM_FPC_RSV0],  1>;
497defm : X86WriteResPairUnsupported<WriteVarVecShiftY>;
498defm : X86WriteResPairUnsupported<WriteVarVecShiftZ>;
499defm : X86WriteResPairUnsupported<WriteFMA>;
500defm : X86WriteResPairUnsupported<WriteFMAX>;
501defm : X86WriteResPairUnsupported<WriteFMAY>;
502defm : X86WriteResPairUnsupported<WriteFMAZ>;
503
504defm : X86WriteResPairUnsupported<WriteCvtPH2PS>;
505defm : X86WriteResPairUnsupported<WriteCvtPH2PSY>;
506defm : X86WriteResPairUnsupported<WriteCvtPH2PSZ>;
507defm : X86WriteResUnsupported<WriteCvtPS2PH>;
508defm : X86WriteResUnsupported<WriteCvtPS2PHY>;
509defm : X86WriteResUnsupported<WriteCvtPS2PHZ>;
510defm : X86WriteResUnsupported<WriteCvtPS2PHSt>;
511defm : X86WriteResUnsupported<WriteCvtPS2PHYSt>;
512defm : X86WriteResUnsupported<WriteCvtPS2PHZSt>;
513
514// Remaining SLM instrs.
515
516def SLMWriteResGroup1rr : SchedWriteRes<[SLM_FPC_RSV01]> {
517  let Latency = 4;
518  let NumMicroOps = 2;
519  let ResourceCycles = [4];
520}
521def: InstRW<[SLMWriteResGroup1rr], (instrs PADDQrr, PSUBQrr, PCMPEQQrr)>;
522
523def SLMWriteResGroup1rm : SchedWriteRes<[SLM_MEC_RSV,SLM_FPC_RSV01]> {
524  let Latency = 7;
525  let NumMicroOps = 3;
526  let ResourceCycles = [1,4];
527}
528def: InstRW<[SLMWriteResGroup1rm], (instrs PADDQrm, PSUBQrm, PCMPEQQrm)>;
529
530} // SchedModel
531