1//===- X86ScheduleAtom.td - X86 Atom Scheduling Definitions -*- tablegen -*-==// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the schedule class data for the Intel Atom 10// in order (Saltwell-32nm/Bonnell-45nm) processors. 11// 12//===----------------------------------------------------------------------===// 13 14// 15// Scheduling information derived from the "Intel 64 and IA32 Architectures 16// Optimization Reference Manual", Chapter 13, Section 4. 17 18// Atom machine model. 19def AtomModel : SchedMachineModel { 20 let IssueWidth = 2; // Allows 2 instructions per scheduling group. 21 let MicroOpBufferSize = 0; // In-order execution, always hide latency. 22 let LoadLatency = 3; // Expected cycles, may be overriden. 23 let HighLatency = 30;// Expected, may be overriden. 24 25 // On the Atom, the throughput for taken branches is 2 cycles. For small 26 // simple loops, expand by a small factor to hide the backedge cost. 27 let LoopMicroOpBufferSize = 10; 28 let PostRAScheduler = 1; 29 let CompleteModel = 0; 30} 31 32let SchedModel = AtomModel in { 33 34// Functional Units 35def AtomPort0 : ProcResource<1>; // ALU: ALU0, shift/rotate, load/store 36 // SIMD/FP: SIMD ALU, Shuffle,SIMD/FP multiply, divide 37def AtomPort1 : ProcResource<1>; // ALU: ALU1, bit processing, jump, and LEA 38 // SIMD/FP: SIMD ALU, FP Adder 39 40// NOTE: This is for ops that can use EITHER port, not for ops that require BOTH ports. 41def AtomPort01 : ProcResGroup<[AtomPort0, AtomPort1]>; 42 43// Loads are 3 cycles, so ReadAfterLd registers needn't be available until 3 44// cycles after the memory operand. 45def : ReadAdvance<ReadAfterLd, 3>; 46def : ReadAdvance<ReadAfterVecLd, 3>; 47def : ReadAdvance<ReadAfterVecXLd, 3>; 48def : ReadAdvance<ReadAfterVecYLd, 3>; 49 50def : ReadAdvance<ReadInt2Fpu, 0>; 51 52// This multiclass defines the resource usage for variants with and without 53// folded loads. 54multiclass AtomWriteResPair<X86FoldableSchedWrite SchedRW, 55 list<ProcResourceKind> RRPorts, 56 list<ProcResourceKind> RMPorts, 57 int RRLat = 1, int RMLat = 1, 58 list<int> RRRes = [1], 59 list<int> RMRes = [1], 60 int RRUOps = 1, 61 int RMUOps = 1> { 62 // Register variant. 63 def : WriteRes<SchedRW, RRPorts> { 64 let Latency = RRLat; 65 let ResourceCycles = RRRes; 66 let NumMicroOps = RRUOps; 67 } 68 69 // Memory variant. 70 def : WriteRes<SchedRW.Folded, RMPorts> { 71 let Latency = RMLat; 72 let ResourceCycles = RMRes; 73 let NumMicroOps = RMUOps; 74 } 75} 76 77// A folded store needs a cycle on Port0 for the store data. 78def : WriteRes<WriteRMW, [AtomPort0]>; 79 80//////////////////////////////////////////////////////////////////////////////// 81// Arithmetic. 82//////////////////////////////////////////////////////////////////////////////// 83 84defm : AtomWriteResPair<WriteALU, [AtomPort01], [AtomPort0]>; 85defm : AtomWriteResPair<WriteADC, [AtomPort01], [AtomPort0]>; 86 87defm : AtomWriteResPair<WriteIMul8, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 7, 7, [7,7], [7,7], 3, 3>; 88defm : AtomWriteResPair<WriteIMul16, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 7, 8, [7,7], [8,8], 4, 5>; 89defm : AtomWriteResPair<WriteIMul16Imm, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 6, 7, [6,6], [7,7], 2, 3>; 90defm : AtomWriteResPair<WriteIMul16Reg, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 6, 7, [6,6], [7,7], 2, 3>; 91defm : AtomWriteResPair<WriteIMul32, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 6, 7, [6,6], [7,7], 3, 4>; 92defm : AtomWriteResPair<WriteIMul32Imm, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>; 93defm : AtomWriteResPair<WriteIMul32Reg, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>; 94defm : AtomWriteResPair<WriteIMul64, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 12, 12, [12,12], [12,12], 8, 8>; 95defm : AtomWriteResPair<WriteIMul64Imm, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 14, 14, [14,14], [14,14], 7, 7>; 96defm : AtomWriteResPair<WriteIMul64Reg, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 12, 12, [12,12], [12,12], 6, 6>; 97defm : X86WriteResUnsupported<WriteIMulH>; 98defm : X86WriteResUnsupported<WriteIMulHLd>; 99defm : X86WriteResPairUnsupported<WriteMULX32>; 100defm : X86WriteResPairUnsupported<WriteMULX64>; 101 102defm : X86WriteRes<WriteXCHG, [AtomPort01], 2, [2], 1>; 103defm : X86WriteRes<WriteBSWAP32, [AtomPort0], 1, [1], 1>; 104defm : X86WriteRes<WriteBSWAP64, [AtomPort0], 1, [1], 1>; 105defm : AtomWriteResPair<WriteCMPXCHG, [AtomPort01], [AtomPort01], 15, 15, [15]>; 106defm : X86WriteRes<WriteCMPXCHGRMW, [AtomPort01, AtomPort0], 1, [1, 1], 1>; 107 108defm : AtomWriteResPair<WriteDiv8, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 50, 68, [50,50], [68,68], 9, 9>; 109defm : AtomWriteResPair<WriteDiv16, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 50, 50, [50,50], [50,50], 12, 12>; 110defm : AtomWriteResPair<WriteDiv32, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 50, 50, [50,50], [50,50], 12, 12>; 111defm : AtomWriteResPair<WriteDiv64, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1],130,130,[130,130],[130,130], 38, 38>; 112defm : AtomWriteResPair<WriteIDiv8, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 62, 62, [62,62], [62,62], 26, 26>; 113defm : AtomWriteResPair<WriteIDiv16, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 62, 62, [62,62], [62,62], 29, 29>; 114defm : AtomWriteResPair<WriteIDiv32, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 62, 62, [62,62], [62,62], 29, 29>; 115defm : AtomWriteResPair<WriteIDiv64, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1],130,130,[130,130],[130,130], 60, 60>; 116 117defm : X86WriteResPairUnsupported<WriteCRC32>; 118 119defm : AtomWriteResPair<WriteCMOV, [AtomPort01], [AtomPort0]>; 120defm : X86WriteRes<WriteFCMOV, [AtomPort01], 9, [9], 1>; // x87 conditional move. 121 122def : WriteRes<WriteSETCC, [AtomPort01]>; 123def : WriteRes<WriteSETCCStore, [AtomPort01]> { 124 let Latency = 2; 125 let ResourceCycles = [2]; 126} 127def : WriteRes<WriteLAHFSAHF, [AtomPort01]> { 128 let Latency = 2; 129 let ResourceCycles = [2]; 130} 131defm : X86WriteRes<WriteBitTest, [AtomPort1], 1, [1], 1>; 132defm : X86WriteRes<WriteBitTestImmLd, [AtomPort0], 1, [1], 1>; 133defm : X86WriteRes<WriteBitTestRegLd, [AtomPort01], 9, [9], 1>; 134defm : X86WriteRes<WriteBitTestSet, [AtomPort1], 1, [1], 1>; 135//defm : X86WriteRes<WriteBitTestSetImmLd, [AtomPort1], 1, [1], 1>; 136//defm : X86WriteRes<WriteBitTestSetRegLd, [AtomPort1], 1, [1], 1>; 137 138// This is for simple LEAs with one or two input operands. 139def : WriteRes<WriteLEA, [AtomPort1]>; 140 141// Bit counts. 142defm : AtomWriteResPair<WriteBSF, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 16, 16, [16,16], [16,16], 10, 10>; 143defm : AtomWriteResPair<WriteBSR, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 16, 16, [16,16], [16,16], 10, 10>; 144defm : X86WriteResPairUnsupported<WritePOPCNT>; 145defm : X86WriteResPairUnsupported<WriteLZCNT>; 146defm : X86WriteResPairUnsupported<WriteTZCNT>; 147 148// BMI1 BEXTR/BLS, BMI2 BZHI 149defm : X86WriteResPairUnsupported<WriteBEXTR>; 150defm : X86WriteResPairUnsupported<WriteBLS>; 151defm : X86WriteResPairUnsupported<WriteBZHI>; 152 153//////////////////////////////////////////////////////////////////////////////// 154// Integer shifts and rotates. 155//////////////////////////////////////////////////////////////////////////////// 156 157defm : AtomWriteResPair<WriteShift, [AtomPort0], [AtomPort0]>; 158defm : AtomWriteResPair<WriteShiftCL, [AtomPort0], [AtomPort0]>; 159defm : AtomWriteResPair<WriteRotate, [AtomPort0], [AtomPort0]>; 160defm : AtomWriteResPair<WriteRotateCL, [AtomPort0], [AtomPort0]>; 161 162defm : X86WriteRes<WriteSHDrri, [AtomPort01], 2, [2], 1>; 163defm : X86WriteRes<WriteSHDrrcl,[AtomPort01], 2, [2], 1>; 164defm : X86WriteRes<WriteSHDmri, [AtomPort01], 4, [4], 1>; 165defm : X86WriteRes<WriteSHDmrcl,[AtomPort01], 4, [4], 1>; 166 167//////////////////////////////////////////////////////////////////////////////// 168// Loads, stores, and moves, not folded with other operations. 169//////////////////////////////////////////////////////////////////////////////// 170 171def : WriteRes<WriteLoad, [AtomPort0]>; 172def : WriteRes<WriteStore, [AtomPort0]>; 173def : WriteRes<WriteStoreNT, [AtomPort0]>; 174def : WriteRes<WriteMove, [AtomPort01]>; 175defm : X86WriteResUnsupported<WriteVecMaskedGatherWriteback>; 176 177// Treat misc copies as a move. 178def : InstRW<[WriteMove], (instrs COPY)>; 179 180//////////////////////////////////////////////////////////////////////////////// 181// Idioms that clear a register, like xorps %xmm0, %xmm0. 182// These can often bypass execution ports completely. 183//////////////////////////////////////////////////////////////////////////////// 184 185def : WriteRes<WriteZero, []>; 186 187//////////////////////////////////////////////////////////////////////////////// 188// Branches don't produce values, so they have no latency, but they still 189// consume resources. Indirect branches can fold loads. 190//////////////////////////////////////////////////////////////////////////////// 191 192defm : AtomWriteResPair<WriteJump, [AtomPort1], [AtomPort1]>; 193 194//////////////////////////////////////////////////////////////////////////////// 195// Special case scheduling classes. 196//////////////////////////////////////////////////////////////////////////////// 197 198def : WriteRes<WriteSystem, [AtomPort01]> { let Latency = 100; } 199def : WriteRes<WriteMicrocoded, [AtomPort01]> { let Latency = 100; } 200def : WriteRes<WriteFence, [AtomPort0]>; 201 202// Nops don't have dependencies, so there's no actual latency, but we set this 203// to '1' to tell the scheduler that the nop uses an ALU slot for a cycle. 204def : WriteRes<WriteNop, [AtomPort01]>; 205 206//////////////////////////////////////////////////////////////////////////////// 207// Floating point. This covers both scalar and vector operations. 208//////////////////////////////////////////////////////////////////////////////// 209 210defm : X86WriteRes<WriteFLD0, [AtomPort01], 1, [1], 1>; 211defm : X86WriteRes<WriteFLD1, [AtomPort01], 6, [6], 1>; 212def : WriteRes<WriteFLoad, [AtomPort0]>; 213def : WriteRes<WriteFLoadX, [AtomPort0]>; 214defm : X86WriteResUnsupported<WriteFLoadY>; 215defm : X86WriteResUnsupported<WriteFMaskedLoad>; 216defm : X86WriteResUnsupported<WriteFMaskedLoadY>; 217 218def : WriteRes<WriteFStore, [AtomPort0]>; 219def : WriteRes<WriteFStoreX, [AtomPort0]>; 220defm : X86WriteResUnsupported<WriteFStoreY>; 221def : WriteRes<WriteFStoreNT, [AtomPort0]>; 222def : WriteRes<WriteFStoreNTX, [AtomPort0]>; 223defm : X86WriteResUnsupported<WriteFStoreNTY>; 224defm : X86WriteResUnsupported<WriteFMaskedStore32>; 225defm : X86WriteResUnsupported<WriteFMaskedStore32Y>; 226defm : X86WriteResUnsupported<WriteFMaskedStore64>; 227defm : X86WriteResUnsupported<WriteFMaskedStore64Y>; 228 229def : WriteRes<WriteFMove, [AtomPort01]>; 230def : WriteRes<WriteFMoveX, [AtomPort01]>; 231defm : X86WriteResUnsupported<WriteFMoveY>; 232defm : X86WriteResUnsupported<WriteFMoveZ>; 233 234defm : X86WriteRes<WriteEMMS, [AtomPort01], 5, [5], 1>; 235 236defm : AtomWriteResPair<WriteFAdd, [AtomPort1], [AtomPort0,AtomPort1], 5, 5, [1], [1,1]>; 237defm : AtomWriteResPair<WriteFAddX, [AtomPort1], [AtomPort0,AtomPort1], 5, 5, [1], [1,1]>; 238defm : X86WriteResPairUnsupported<WriteFAddY>; 239defm : X86WriteResPairUnsupported<WriteFAddZ>; 240defm : AtomWriteResPair<WriteFAdd64, [AtomPort1], [AtomPort0,AtomPort1], 5, 5, [1], [1,1]>; 241defm : AtomWriteResPair<WriteFAdd64X, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 6, 7, [5,5], [6,6], 3, 4>; 242defm : X86WriteResPairUnsupported<WriteFAdd64Y>; 243defm : X86WriteResPairUnsupported<WriteFAdd64Z>; 244defm : AtomWriteResPair<WriteFCmp, [AtomPort1], [AtomPort0,AtomPort1], 5, 5, [1], [1,1]>; 245defm : AtomWriteResPair<WriteFCmpX, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 6, 7, [5,5], [6,6], 3, 4>; 246defm : X86WriteResPairUnsupported<WriteFCmpY>; 247defm : X86WriteResPairUnsupported<WriteFCmpZ>; 248defm : AtomWriteResPair<WriteFCmp64, [AtomPort1], [AtomPort0,AtomPort1], 5, 5, [1], [1,1]>; 249defm : AtomWriteResPair<WriteFCmp64X, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 6, 7, [5,5], [6,6], 3, 4>; 250defm : X86WriteResPairUnsupported<WriteFCmp64Y>; 251defm : X86WriteResPairUnsupported<WriteFCmp64Z>; 252defm : AtomWriteResPair<WriteFCom, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>; 253defm : AtomWriteResPair<WriteFComX, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 9, 10, [9,9],[10,10], 4, 5>; 254defm : AtomWriteResPair<WriteFMul, [AtomPort0], [AtomPort0], 4, 4, [2], [2]>; 255defm : AtomWriteResPair<WriteFMulX, [AtomPort0], [AtomPort0], 5, 5, [2], [2]>; 256defm : X86WriteResPairUnsupported<WriteFMulY>; 257defm : X86WriteResPairUnsupported<WriteFMulZ>; 258defm : AtomWriteResPair<WriteFMul64, [AtomPort0], [AtomPort0], 5, 5, [2], [2]>; 259defm : AtomWriteResPair<WriteFMul64X, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 9, 10, [9,9],[10,10], 6, 7>; 260defm : X86WriteResPairUnsupported<WriteFMul64Y>; 261defm : X86WriteResPairUnsupported<WriteFMul64Z>; 262defm : AtomWriteResPair<WriteFRcp, [AtomPort0], [AtomPort0], 4, 4, [4], [4]>; 263defm : AtomWriteResPair<WriteFRcpX, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 9, 10, [9,9], [10,10], 5, 6>; 264defm : X86WriteResPairUnsupported<WriteFRcpY>; 265defm : X86WriteResPairUnsupported<WriteFRcpZ>; 266defm : AtomWriteResPair<WriteFRsqrt, [AtomPort0], [AtomPort0], 4, 4, [4], [4]>; 267defm : AtomWriteResPair<WriteFRsqrtX, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 9, 10, [9,9], [10,10], 5, 6>; 268defm : X86WriteResPairUnsupported<WriteFRsqrtY>; 269defm : X86WriteResPairUnsupported<WriteFRsqrtZ>; 270defm : AtomWriteResPair<WriteFDiv, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 34, 34, [34,34], [34,34], 3, 4>; 271defm : AtomWriteResPair<WriteFDivX, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 70, 70, [70,70], [70,70], 6, 7>; 272defm : X86WriteResPairUnsupported<WriteFDivY>; 273defm : X86WriteResPairUnsupported<WriteFDivZ>; 274defm : AtomWriteResPair<WriteFDiv64, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 62, 62, [62,62], [62,62], 3, 4>; 275defm : AtomWriteResPair<WriteFDiv64X, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1],125,125,[125,125],[125,125], 6, 7>; 276defm : X86WriteResPairUnsupported<WriteFDiv64Y>; 277defm : X86WriteResPairUnsupported<WriteFDiv64Z>; 278defm : AtomWriteResPair<WriteFSqrt, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 34, 34, [34,34], [34,34], 3, 4>; 279defm : AtomWriteResPair<WriteFSqrtX, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 70, 70, [70,70], [70,70], 5, 6>; 280defm : X86WriteResPairUnsupported<WriteFSqrtY>; 281defm : X86WriteResPairUnsupported<WriteFSqrtZ>; 282defm : AtomWriteResPair<WriteFSqrt64, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 62, 62, [62,62], [62,62], 3, 4>; 283defm : AtomWriteResPair<WriteFSqrt64X, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1],125,125,[125,125],[125,125], 5, 6>; 284defm : X86WriteResPairUnsupported<WriteFSqrt64Y>; 285defm : X86WriteResPairUnsupported<WriteFSqrt64Z>; 286defm : AtomWriteResPair<WriteFSqrt80, [AtomPort0], [AtomPort0], 71, 71, [71], [71]>; 287defm : AtomWriteResPair<WriteFSign, [AtomPort1], [AtomPort1]>; 288defm : AtomWriteResPair<WriteFRnd, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>; 289defm : X86WriteResPairUnsupported<WriteFRndY>; 290defm : X86WriteResPairUnsupported<WriteFRndZ>; 291defm : AtomWriteResPair<WriteFLogic, [AtomPort01], [AtomPort0]>; 292defm : X86WriteResPairUnsupported<WriteFLogicY>; 293defm : X86WriteResPairUnsupported<WriteFLogicZ>; 294defm : AtomWriteResPair<WriteFTest, [AtomPort01], [AtomPort0]>; 295defm : X86WriteResPairUnsupported<WriteFTestY>; 296defm : X86WriteResPairUnsupported<WriteFTestZ>; 297defm : AtomWriteResPair<WriteFShuffle, [AtomPort0], [AtomPort0]>; 298defm : X86WriteResPairUnsupported<WriteFShuffleY>; 299defm : X86WriteResPairUnsupported<WriteFShuffleZ>; 300defm : X86WriteResPairUnsupported<WriteFVarShuffle>; 301defm : X86WriteResPairUnsupported<WriteFVarShuffleY>; 302defm : X86WriteResPairUnsupported<WriteFVarShuffleZ>; 303defm : X86WriteResPairUnsupported<WriteFMA>; 304defm : X86WriteResPairUnsupported<WriteFMAX>; 305defm : X86WriteResPairUnsupported<WriteFMAY>; 306defm : X86WriteResPairUnsupported<WriteFMAZ>; 307defm : X86WriteResPairUnsupported<WriteDPPD>; 308defm : X86WriteResPairUnsupported<WriteDPPS>; 309defm : X86WriteResPairUnsupported<WriteDPPSY>; 310defm : X86WriteResPairUnsupported<WriteDPPSZ>; 311defm : X86WriteResPairUnsupported<WriteFBlend>; 312defm : X86WriteResPairUnsupported<WriteFBlendY>; 313defm : X86WriteResPairUnsupported<WriteFBlendZ>; 314defm : X86WriteResPairUnsupported<WriteFVarBlend>; 315defm : X86WriteResPairUnsupported<WriteFVarBlendY>; 316defm : X86WriteResPairUnsupported<WriteFVarBlendZ>; 317defm : X86WriteResPairUnsupported<WriteFShuffle256>; 318defm : X86WriteResPairUnsupported<WriteFVarShuffle256>; 319 320//////////////////////////////////////////////////////////////////////////////// 321// Conversions. 322//////////////////////////////////////////////////////////////////////////////// 323 324defm : AtomWriteResPair<WriteCvtSS2I, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 8, 9, [8,8], [9,9], 3, 4>; 325defm : AtomWriteResPair<WriteCvtPS2I, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 6, 7, [6,6], [7,7], 3, 4>; 326defm : X86WriteResPairUnsupported<WriteCvtPS2IY>; 327defm : X86WriteResPairUnsupported<WriteCvtPS2IZ>; 328defm : AtomWriteResPair<WriteCvtSD2I, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 8, 9, [8,8],[10,10], 3, 4>; 329defm : AtomWriteResPair<WriteCvtPD2I, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 7, 8, [7,7], [8,8], 4, 5>; 330defm : X86WriteResPairUnsupported<WriteCvtPD2IY>; 331defm : X86WriteResPairUnsupported<WriteCvtPD2IZ>; 332 333defm : AtomWriteResPair<WriteCvtI2SS, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 6, 7, [6,6], [6,6], 3, 1>; 334defm : AtomWriteResPair<WriteCvtI2PS, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 6, 7, [6,6], [7,7], 3, 4>; 335defm : X86WriteResPairUnsupported<WriteCvtI2PSY>; 336defm : X86WriteResPairUnsupported<WriteCvtI2PSZ>; 337defm : AtomWriteResPair<WriteCvtI2SD, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 6, 7, [6,6], [7,7], 3, 3>; 338defm : AtomWriteResPair<WriteCvtI2PD, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 7, 8, [6,6], [7,7], 3, 4>; 339defm : X86WriteResPairUnsupported<WriteCvtI2PDY>; 340defm : X86WriteResPairUnsupported<WriteCvtI2PDZ>; 341 342defm : AtomWriteResPair<WriteCvtSS2SD, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 6, 7, [6,6], [7,7], 3, 4>; 343defm : AtomWriteResPair<WriteCvtPS2PD, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 7, 8, [6,6], [7,7], 4, 5>; 344defm : X86WriteResPairUnsupported<WriteCvtPS2PDY>; 345defm : X86WriteResPairUnsupported<WriteCvtPS2PDZ>; 346defm : AtomWriteResPair<WriteCvtSD2SS, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 10, 11,[10,10],[12,12], 3, 4>; 347defm : AtomWriteResPair<WriteCvtPD2PS, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 11, 12,[11,11],[12,12], 4, 5>; 348defm : X86WriteResPairUnsupported<WriteCvtPD2PSY>; 349defm : X86WriteResPairUnsupported<WriteCvtPD2PSZ>; 350 351defm : X86WriteResPairUnsupported<WriteCvtPH2PS>; 352defm : X86WriteResPairUnsupported<WriteCvtPH2PSY>; 353defm : X86WriteResPairUnsupported<WriteCvtPH2PSZ>; 354defm : X86WriteResUnsupported<WriteCvtPS2PH>; 355defm : X86WriteResUnsupported<WriteCvtPS2PHSt>; 356defm : X86WriteResUnsupported<WriteCvtPS2PHY>; 357defm : X86WriteResUnsupported<WriteCvtPS2PHZ>; 358defm : X86WriteResUnsupported<WriteCvtPS2PHYSt>; 359defm : X86WriteResUnsupported<WriteCvtPS2PHZSt>; 360 361//////////////////////////////////////////////////////////////////////////////// 362// Vector integer operations. 363//////////////////////////////////////////////////////////////////////////////// 364 365def : WriteRes<WriteVecLoad, [AtomPort0]>; 366def : WriteRes<WriteVecLoadX, [AtomPort0]>; 367defm : X86WriteResUnsupported<WriteVecLoadY>; 368def : WriteRes<WriteVecLoadNT, [AtomPort0]>; 369defm : X86WriteResUnsupported<WriteVecLoadNTY>; 370defm : X86WriteResUnsupported<WriteVecMaskedLoad>; 371defm : X86WriteResUnsupported<WriteVecMaskedLoadY>; 372 373def : WriteRes<WriteVecStore, [AtomPort0]>; 374def : WriteRes<WriteVecStoreX, [AtomPort0]>; 375defm : X86WriteResUnsupported<WriteVecStoreY>; 376def : WriteRes<WriteVecStoreNT, [AtomPort0]>; 377defm : X86WriteResUnsupported<WriteVecStoreNTY>; 378defm : X86WriteResUnsupported<WriteVecMaskedStore32>; 379defm : X86WriteResUnsupported<WriteVecMaskedStore64>; 380defm : X86WriteResUnsupported<WriteVecMaskedStore32Y>; 381defm : X86WriteResUnsupported<WriteVecMaskedStore64Y>; 382 383def : WriteRes<WriteVecMove, [AtomPort0]>; 384def : WriteRes<WriteVecMoveX, [AtomPort01]>; 385defm : X86WriteResUnsupported<WriteVecMoveY>; 386defm : X86WriteResUnsupported<WriteVecMoveZ>; 387defm : X86WriteRes<WriteVecMoveToGpr, [AtomPort0], 3, [3], 1>; 388defm : X86WriteRes<WriteVecMoveFromGpr, [AtomPort0], 1, [1], 1>; 389 390defm : AtomWriteResPair<WriteVecALU, [AtomPort01], [AtomPort0], 1, 1>; 391defm : AtomWriteResPair<WriteVecALUX, [AtomPort01], [AtomPort0], 1, 1>; 392defm : X86WriteResPairUnsupported<WriteVecALUY>; 393defm : X86WriteResPairUnsupported<WriteVecALUZ>; 394defm : AtomWriteResPair<WriteVecLogic, [AtomPort01], [AtomPort0], 1, 1>; 395defm : AtomWriteResPair<WriteVecLogicX, [AtomPort01], [AtomPort0], 1, 1>; 396defm : X86WriteResPairUnsupported<WriteVecLogicY>; 397defm : X86WriteResPairUnsupported<WriteVecLogicZ>; 398defm : X86WriteResPairUnsupported<WriteVecTest>; 399defm : X86WriteResPairUnsupported<WriteVecTestY>; 400defm : X86WriteResPairUnsupported<WriteVecTestZ>; 401defm : AtomWriteResPair<WriteVecShift, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 2, 3, [1,1], [2,2], 2, 3>; 402defm : AtomWriteResPair<WriteVecShiftX, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 2, 3, [1,1], [2,2], 2, 3>; 403defm : X86WriteResPairUnsupported<WriteVecShiftY>; 404defm : X86WriteResPairUnsupported<WriteVecShiftZ>; 405defm : AtomWriteResPair<WriteVecShiftImm, [AtomPort0], [AtomPort0], 1, 1>; 406defm : AtomWriteResPair<WriteVecShiftImmX, [AtomPort0], [AtomPort0], 1, 1>; 407defm : X86WriteResPairUnsupported<WriteVecShiftImmY>; 408defm : X86WriteResPairUnsupported<WriteVecShiftImmZ>; 409defm : AtomWriteResPair<WriteVecIMul, [AtomPort0], [AtomPort0], 4, 4, [1], [1]>; 410defm : AtomWriteResPair<WriteVecIMulX, [AtomPort0], [AtomPort0], 5, 5, [2], [2]>; 411defm : X86WriteResPairUnsupported<WriteVecIMulY>; 412defm : X86WriteResPairUnsupported<WriteVecIMulZ>; 413defm : X86WriteResPairUnsupported<WritePMULLD>; 414defm : X86WriteResPairUnsupported<WritePMULLDY>; 415defm : X86WriteResPairUnsupported<WritePMULLDZ>; 416defm : X86WriteResPairUnsupported<WritePHMINPOS>; 417defm : X86WriteResPairUnsupported<WriteMPSAD>; 418defm : X86WriteResPairUnsupported<WriteMPSADY>; 419defm : X86WriteResPairUnsupported<WriteMPSADZ>; 420defm : AtomWriteResPair<WritePSADBW, [AtomPort0], [AtomPort0], 4, 4, [1], [1]>; 421defm : AtomWriteResPair<WritePSADBWX, [AtomPort0], [AtomPort0], 5, 5, [2], [2]>; 422defm : X86WriteResPairUnsupported<WritePSADBWY>; 423defm : X86WriteResPairUnsupported<WritePSADBWZ>; 424defm : AtomWriteResPair<WriteShuffle, [AtomPort0], [AtomPort0], 1, 1>; 425defm : AtomWriteResPair<WriteShuffleX, [AtomPort0], [AtomPort0], 1, 1>; 426defm : X86WriteResPairUnsupported<WriteShuffleY>; 427defm : X86WriteResPairUnsupported<WriteShuffleZ>; 428defm : AtomWriteResPair<WriteVarShuffle, [AtomPort0], [AtomPort0], 1, 1>; 429defm : AtomWriteResPair<WriteVarShuffleX, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 4, 5, [3,3], [4,4], 4, 5>; 430defm : X86WriteResPairUnsupported<WriteVarShuffleY>; 431defm : X86WriteResPairUnsupported<WriteVarShuffleZ>; 432defm : X86WriteResPairUnsupported<WriteBlend>; 433defm : X86WriteResPairUnsupported<WriteBlendY>; 434defm : X86WriteResPairUnsupported<WriteBlendZ>; 435defm : X86WriteResPairUnsupported<WriteVarBlend>; 436defm : X86WriteResPairUnsupported<WriteVarBlendY>; 437defm : X86WriteResPairUnsupported<WriteVarBlendZ>; 438defm : X86WriteResPairUnsupported<WriteShuffle256>; 439defm : X86WriteResPairUnsupported<WriteVPMOV256>; 440defm : X86WriteResPairUnsupported<WriteVarShuffle256>; 441defm : X86WriteResPairUnsupported<WriteVarVecShift>; 442defm : X86WriteResPairUnsupported<WriteVarVecShiftY>; 443defm : X86WriteResPairUnsupported<WriteVarVecShiftZ>; 444 445//////////////////////////////////////////////////////////////////////////////// 446// Vector insert/extract operations. 447//////////////////////////////////////////////////////////////////////////////// 448 449defm : AtomWriteResPair<WriteVecInsert, [AtomPort0], [AtomPort0], 1, 1>; 450def : WriteRes<WriteVecExtract, [AtomPort0]>; 451def : WriteRes<WriteVecExtractSt, [AtomPort0]>; 452 453//////////////////////////////////////////////////////////////////////////////// 454// SSE42 String instructions. 455//////////////////////////////////////////////////////////////////////////////// 456 457defm : X86WriteResPairUnsupported<WritePCmpIStrI>; 458defm : X86WriteResPairUnsupported<WritePCmpIStrM>; 459defm : X86WriteResPairUnsupported<WritePCmpEStrI>; 460defm : X86WriteResPairUnsupported<WritePCmpEStrM>; 461 462//////////////////////////////////////////////////////////////////////////////// 463// MOVMSK Instructions. 464//////////////////////////////////////////////////////////////////////////////// 465 466def : WriteRes<WriteFMOVMSK, [AtomPort0]> { let Latency = 3; let ResourceCycles = [3]; } 467def : WriteRes<WriteVecMOVMSK, [AtomPort0]> { let Latency = 3; let ResourceCycles = [3]; } 468defm : X86WriteResUnsupported<WriteVecMOVMSKY>; 469def : WriteRes<WriteMMXMOVMSK, [AtomPort0]> { let Latency = 3; let ResourceCycles = [3]; } 470 471//////////////////////////////////////////////////////////////////////////////// 472// AES instructions. 473//////////////////////////////////////////////////////////////////////////////// 474 475defm : X86WriteResPairUnsupported<WriteAESIMC>; 476defm : X86WriteResPairUnsupported<WriteAESKeyGen>; 477defm : X86WriteResPairUnsupported<WriteAESDecEnc>; 478 479//////////////////////////////////////////////////////////////////////////////// 480// Horizontal add/sub instructions. 481//////////////////////////////////////////////////////////////////////////////// 482 483defm : AtomWriteResPair<WriteFHAdd, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 8, 9, [8,8], [9,9], 5, 6>; 484defm : X86WriteResPairUnsupported<WriteFHAddY>; 485defm : AtomWriteResPair<WritePHAdd, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 3, 4, [3,3], [4,4], 3, 4>; 486defm : AtomWriteResPair<WritePHAddX, [AtomPort0,AtomPort1], [AtomPort0,AtomPort1], 7, 8, [7,7], [8,8], 3, 4>; 487defm : X86WriteResPairUnsupported<WritePHAddY>; 488 489//////////////////////////////////////////////////////////////////////////////// 490// Carry-less multiplication instructions. 491//////////////////////////////////////////////////////////////////////////////// 492 493defm : X86WriteResPairUnsupported<WriteCLMul>; 494 495//////////////////////////////////////////////////////////////////////////////// 496// Load/store MXCSR. 497//////////////////////////////////////////////////////////////////////////////// 498 499defm : X86WriteRes<WriteLDMXCSR, [AtomPort0,AtomPort1], 5, [5,5], 4>; 500defm : X86WriteRes<WriteSTMXCSR, [AtomPort0,AtomPort1], 15, [15,15], 4>; 501 502//////////////////////////////////////////////////////////////////////////////// 503// Special Cases. 504//////////////////////////////////////////////////////////////////////////////// 505 506// Port0 507def AtomWrite0_1 : SchedWriteRes<[AtomPort0]> { 508 let Latency = 1; 509 let ResourceCycles = [1]; 510} 511def : InstRW<[AtomWrite0_1], (instrs XAM_F, LD_Frr, 512 MOVSX64rr32)>; 513def : SchedAlias<WriteALURMW, AtomWrite0_1>; 514def : SchedAlias<WriteADCRMW, AtomWrite0_1>; 515def : InstRW<[AtomWrite0_1], (instregex "(RCL|RCR|ROL|ROR|SAR|SHL|SHR)(8|16|32|64)m", 516 "MOV(S|Z)X(32|64)rr(8|8_NOREX|16)")>; 517 518// Port1 519def AtomWrite1_1 : SchedWriteRes<[AtomPort1]> { 520 let Latency = 1; 521 let ResourceCycles = [1]; 522} 523def : InstRW<[AtomWrite1_1], (instrs FCOMPP)>; 524def : InstRW<[AtomWrite1_1], (instregex "UCOM_F(P|PP)?r")>; 525 526def AtomWrite1_5 : SchedWriteRes<[AtomPort1]> { 527 let Latency = 5; 528 let ResourceCycles = [5]; 529} 530def : InstRW<[AtomWrite1_5], (instrs MMX_CVTPI2PSrr, MMX_CVTPI2PSrm, 531 MMX_CVTPS2PIrr, MMX_CVTTPS2PIrr)>; 532 533// Port0 and Port1 534def AtomWrite0_1_1 : SchedWriteRes<[AtomPort0, AtomPort1]> { 535 let Latency = 1; 536 let ResourceCycles = [1, 1]; 537} 538def : InstRW<[AtomWrite0_1_1], (instrs POP32r, POP64r, 539 POP16rmr, POP32rmr, POP64rmr, 540 PUSH16r, PUSH32r, PUSH64r, 541 PUSHi16, PUSHi32, 542 PUSH16rmr, PUSH32rmr, PUSH64rmr, 543 PUSH16i8, PUSH32i8, PUSH64i8, PUSH64i32, 544 XCH_F)>; 545def : InstRW<[AtomWrite0_1_1], (instregex "RETI(16|32|64)$", 546 "IRET(16|32|64)?")>; 547 548def AtomWrite0_1_5 : SchedWriteRes<[AtomPort0, AtomPort1]> { 549 let Latency = 5; 550 let ResourceCycles = [5, 5]; 551} 552def : InstRW<[AtomWrite0_1_5], (instrs MMX_CVTPS2PIrm, MMX_CVTTPS2PIrm)>; 553def : InstRW<[AtomWrite0_1_5], (instregex "ILD_F(16|32|64)")>; 554 555def AtomWrite0_1_7 : SchedWriteRes<[AtomPort0,AtomPort1]> { 556 let Latency = 7; 557 let ResourceCycles = [6,6]; 558} 559def : InstRW<[AtomWrite0_1_7], (instregex "CVTSI642SDrm(_Int)?")>; 560 561def AtomWrite0_1_7_4 : SchedWriteRes<[AtomPort0,AtomPort1]> { 562 let Latency = 7; 563 let ResourceCycles = [8,8]; 564 let NumMicroOps = 4; 565} 566def : InstRW<[AtomWrite0_1_7_4], (instregex "CVTSI642SSrr(_Int)?")>; 567 568def AtomWrite0_1_8_4 : SchedWriteRes<[AtomPort0,AtomPort1]> { 569 let Latency = 8; 570 let ResourceCycles = [8,8]; 571 let NumMicroOps = 4; 572} 573def : InstRW<[AtomWrite0_1_7_4], (instregex "CVTSI642SSrm(_Int)?")>; 574 575def AtomWrite0_1_9 : SchedWriteRes<[AtomPort0,AtomPort1]> { 576 let Latency = 9; 577 let ResourceCycles = [9,9]; 578 let NumMicroOps = 4; 579} 580def : InstRW<[AtomWrite0_1_9], (instregex "CVT(T)?SS2SI64rr(_Int)?")>; 581 582def AtomWrite0_1_10 : SchedWriteRes<[AtomPort0,AtomPort1]> { 583 let Latency = 10; 584 let ResourceCycles = [11,11]; 585 let NumMicroOps = 5; 586} 587def : InstRW<[AtomWrite0_1_10], (instregex "CVT(T)?SS2SI64rm(_Int)?")>; 588 589// Port0 or Port1 590def AtomWrite01_1 : SchedWriteRes<[AtomPort01]> { 591 let Latency = 1; 592 let ResourceCycles = [1]; 593} 594def : InstRW<[AtomWrite01_1], (instrs FDECSTP, FFREE, FFREEP, FINCSTP, WAIT, 595 LFENCE, 596 STOSB, STOSL, STOSQ, STOSW, 597 MOVSSrr, MOVSSrr_REV)>; 598 599def AtomWrite01_2 : SchedWriteRes<[AtomPort01]> { 600 let Latency = 2; 601 let ResourceCycles = [2]; 602} 603def : InstRW<[AtomWrite01_2], (instrs LEAVE, LEAVE64, POP16r, 604 PUSH16rmm, PUSH32rmm, PUSH64rmm, 605 LODSB, LODSL, LODSQ, LODSW, 606 SCASB, SCASL, SCASQ, SCASW)>; 607def : InstRW<[AtomWrite01_2], (instregex "PUSH(CS|DS|ES|FS|GS|SS)(16|32|64)", 608 "(ST|ISTT)_F(P)?(16|32|64)?(m|rr)", 609 "MMX_P(ADD|SUB)Qrr", 610 "MOV(S|Z)X16rr8", 611 "MOV(UPS|UPD|DQU)mr", 612 "MASKMOVDQU(64)?", 613 "P(ADD|SUB)Qrr")>; 614def : SchedAlias<WriteBitTestSetImmRMW, AtomWrite01_2>; 615 616def AtomWrite01_3 : SchedWriteRes<[AtomPort01]> { 617 let Latency = 3; 618 let ResourceCycles = [3]; 619} 620def : InstRW<[AtomWrite01_3], (instrs CLD, LDDQUrm, 621 CMPSB, CMPSL, CMPSQ, CMPSW, 622 MOVSB, MOVSL, MOVSQ, MOVSW, 623 POP16rmm, POP32rmm, POP64rmm)>; 624def : InstRW<[AtomWrite01_3], (instregex "XADD(8|16|32|64)rm", 625 "XCHG(8|16|32|64)rm", 626 "PH(ADD|SUB)Drr", 627 "MOV(S|Z)X16rm8", 628 "MMX_P(ADD|SUB)Qrm", 629 "MOV(UPS|UPD|DQU)rm", 630 "P(ADD|SUB)Qrm")>; 631 632def AtomWrite01_4 : SchedWriteRes<[AtomPort01]> { 633 let Latency = 4; 634 let ResourceCycles = [4]; 635} 636def : InstRW<[AtomWrite01_4], (instrs CBW, CWD, CWDE, CDQ, CDQE, CQO, 637 JCXZ, JECXZ, JRCXZ, 638 LD_F80m)>; 639def : InstRW<[AtomWrite01_4], (instregex "PH(ADD|SUB)Drm", 640 "(MMX_)?PEXTRWrr(_REV)?")>; 641 642def AtomWrite01_5 : SchedWriteRes<[AtomPort01]> { 643 let Latency = 5; 644 let ResourceCycles = [5]; 645} 646def : InstRW<[AtomWrite01_5], (instrs FLDCW16m, ST_FP80m)>; 647def : InstRW<[AtomWrite01_5], (instregex "MMX_PH(ADD|SUB)S?Wrr")>; 648 649def AtomWrite01_6 : SchedWriteRes<[AtomPort01]> { 650 let Latency = 6; 651 let ResourceCycles = [6]; 652} 653def : InstRW<[AtomWrite01_6], (instrs CMPXCHG8rm, INTO, XLAT, 654 SHLD16rrCL, SHRD16rrCL, 655 SHLD16rri8, SHRD16rri8, 656 SHLD16mrCL, SHRD16mrCL, 657 SHLD16mri8, SHRD16mri8)>; 658def : InstRW<[AtomWrite01_6], (instregex "IST_F(P)?(16|32|64)?m", 659 "MMX_PH(ADD|SUB)S?Wrm")>; 660 661def AtomWrite01_7 : SchedWriteRes<[AtomPort01]> { 662 let Latency = 7; 663 let ResourceCycles = [7]; 664} 665def : InstRW<[AtomWrite01_7], (instrs AAD8i8)>; 666 667def AtomWrite01_8 : SchedWriteRes<[AtomPort01]> { 668 let Latency = 8; 669 let ResourceCycles = [8]; 670} 671def : InstRW<[AtomWrite01_8], (instrs LOOPE, 672 PUSHA16, PUSHA32, 673 SHLD64rrCL, SHRD64rrCL, 674 FNSTCW16m)>; 675 676def AtomWrite01_9 : SchedWriteRes<[AtomPort01]> { 677 let Latency = 9; 678 let ResourceCycles = [9]; 679} 680def : InstRW<[AtomWrite01_9], (instrs POPA16, POPA32, 681 PUSHF16, PUSHF32, PUSHF64, 682 SHLD64mrCL, SHRD64mrCL, 683 SHLD64mri8, SHRD64mri8, 684 SHLD64rri8, SHRD64rri8, 685 CMPXCHG8rr)>; 686def : InstRW<[AtomWrite01_9], (instregex "(U)?COM_FI", "TST_F")>; 687 688def AtomWrite01_10 : SchedWriteRes<[AtomPort01]> { 689 let Latency = 10; 690 let ResourceCycles = [10]; 691} 692def : SchedAlias<WriteFLDC, AtomWrite01_10>; 693 694def AtomWrite01_11 : SchedWriteRes<[AtomPort01]> { 695 let Latency = 11; 696 let ResourceCycles = [11]; 697} 698def : InstRW<[AtomWrite01_11], (instrs BOUNDS16rm, BOUNDS32rm)>; 699def : SchedAlias<WriteBitTestSetRegRMW, AtomWrite01_11>; 700 701def AtomWrite01_13 : SchedWriteRes<[AtomPort01]> { 702 let Latency = 13; 703 let ResourceCycles = [13]; 704} 705def : InstRW<[AtomWrite01_13], (instrs AAA, AAS)>; 706 707def AtomWrite01_14 : SchedWriteRes<[AtomPort01]> { 708 let Latency = 14; 709 let ResourceCycles = [14]; 710} 711def : InstRW<[AtomWrite01_14], (instrs CMPXCHG16rm, CMPXCHG32rm, CMPXCHG64rm)>; 712 713def AtomWrite01_17 : SchedWriteRes<[AtomPort01]> { 714 let Latency = 17; 715 let ResourceCycles = [17]; 716} 717def : InstRW<[AtomWrite01_17], (instrs LOOPNE, PAUSE)>; 718 719def AtomWrite01_18 : SchedWriteRes<[AtomPort01]> { 720 let Latency = 18; 721 let ResourceCycles = [18]; 722} 723def : InstRW<[AtomWrite01_18], (instrs CMPXCHG8B, DAA, LOOP)>; 724 725def AtomWrite01_20 : SchedWriteRes<[AtomPort01]> { 726 let Latency = 20; 727 let ResourceCycles = [20]; 728} 729def : InstRW<[AtomWrite01_20], (instrs DAS)>; 730 731def AtomWrite01_21 : SchedWriteRes<[AtomPort01]> { 732 let Latency = 21; 733 let ResourceCycles = [21]; 734} 735def : InstRW<[AtomWrite01_21], (instrs AAM8i8, STD)>; 736 737def AtomWrite01_22 : SchedWriteRes<[AtomPort01]> { 738 let Latency = 22; 739 let ResourceCycles = [22]; 740} 741def : InstRW<[AtomWrite01_22], (instrs CMPXCHG16B)>; 742 743def AtomWrite01_23 : SchedWriteRes<[AtomPort01]> { 744 let Latency = 23; 745 let ResourceCycles = [23]; 746} 747def : InstRW<[AtomWrite01_23], (instrs ARPL16mr, ARPL16rr)>; 748 749def AtomWrite01_25 : SchedWriteRes<[AtomPort01]> { 750 let Latency = 25; 751 let ResourceCycles = [25]; 752} 753def : InstRW<[AtomWrite01_25], (instrs FNCLEX, FXTRACT)>; 754 755def AtomWrite01_26 : SchedWriteRes<[AtomPort01]> { 756 let Latency = 26; 757 let ResourceCycles = [26]; 758} 759def : InstRW<[AtomWrite01_26], (instrs POPF32, POPF64)>; 760 761def AtomWrite01_29 : SchedWriteRes<[AtomPort01]> { 762 let Latency = 29; 763 let ResourceCycles = [29]; 764} 765def : InstRW<[AtomWrite01_29], (instregex "POP(DS|ES|FS|GS)(16|32|64)")>; 766 767def AtomWrite01_30 : SchedWriteRes<[AtomPort01]> { 768 let Latency = 30; 769 let ResourceCycles = [30]; 770} 771def : InstRW<[AtomWrite01_30], (instrs RDTSC, RDTSCP)>; 772 773def AtomWrite01_32 : SchedWriteRes<[AtomPort01]> { 774 let Latency = 32; 775 let ResourceCycles = [32]; 776} 777def : InstRW<[AtomWrite01_32], (instrs ENTER, POPF16)>; 778 779def AtomWrite01_45 : SchedWriteRes<[AtomPort01]> { 780 let Latency = 45; 781 let ResourceCycles = [45]; 782} 783def : InstRW<[AtomWrite01_45], (instrs MONITOR32rrr, MONITOR64rrr)>; 784 785def AtomWrite01_46 : SchedWriteRes<[AtomPort01]> { 786 let Latency = 46; 787 let ResourceCycles = [46]; 788} 789def : InstRW<[AtomWrite01_46], (instrs FRNDINT, MWAITrr, RDPMC)>; 790 791def AtomWrite01_48 : SchedWriteRes<[AtomPort01]> { 792 let Latency = 48; 793 let ResourceCycles = [48]; 794} 795def : InstRW<[AtomWrite01_48], (instrs POPSS16, POPSS32)>; 796 797def AtomWrite01_55 : SchedWriteRes<[AtomPort01]> { 798 let Latency = 55; 799 let ResourceCycles = [55]; 800} 801def : InstRW<[AtomWrite01_55], (instrs FPREM)>; 802 803def AtomWrite01_59 : SchedWriteRes<[AtomPort01]> { 804 let Latency = 59; 805 let ResourceCycles = [59]; 806} 807def : InstRW<[AtomWrite01_59], (instrs INSB, INSL, INSW)>; 808 809def AtomWrite01_63 : SchedWriteRes<[AtomPort01]> { 810 let Latency = 63; 811 let ResourceCycles = [63]; 812} 813def : InstRW<[AtomWrite01_63], (instrs FNINIT)>; 814 815def AtomWrite01_68 : SchedWriteRes<[AtomPort01]> { 816 let Latency = 68; 817 let ResourceCycles = [68]; 818} 819def : InstRW<[AtomWrite01_68], (instrs OUT8rr, OUT16rr, OUT32rr)>; 820 821def AtomWrite01_71 : SchedWriteRes<[AtomPort01]> { 822 let Latency = 71; 823 let ResourceCycles = [71]; 824} 825def : InstRW<[AtomWrite01_71], (instrs FPREM1, 826 INVLPG, INVLPGA32, INVLPGA64)>; 827 828def AtomWrite01_72 : SchedWriteRes<[AtomPort01]> { 829 let Latency = 72; 830 let ResourceCycles = [72]; 831} 832def : InstRW<[AtomWrite01_72], (instrs OUT8ir, OUT16ir, OUT32ir)>; 833 834def AtomWrite01_74 : SchedWriteRes<[AtomPort01]> { 835 let Latency = 74; 836 let ResourceCycles = [74]; 837} 838def : InstRW<[AtomWrite01_74], (instrs OUTSB, OUTSL, OUTSW)>; 839 840def AtomWrite01_77 : SchedWriteRes<[AtomPort01]> { 841 let Latency = 77; 842 let ResourceCycles = [77]; 843} 844def : InstRW<[AtomWrite01_77], (instrs FSCALE)>; 845 846def AtomWrite01_78 : SchedWriteRes<[AtomPort01]> { 847 let Latency = 78; 848 let ResourceCycles = [78]; 849} 850def : InstRW<[AtomWrite01_78], (instrs RDMSR)>; 851 852def AtomWrite01_79 : SchedWriteRes<[AtomPort01]> { 853 let Latency = 79; 854 let ResourceCycles = [79]; 855} 856def : InstRW<[AtomWrite01_79], (instregex "RET(16|32|64)?$", 857 "LRETI?(16|32|64)")>; 858 859def AtomWrite01_92 : SchedWriteRes<[AtomPort01]> { 860 let Latency = 92; 861 let ResourceCycles = [92]; 862} 863def : InstRW<[AtomWrite01_92], (instrs IN8ri, IN16ri, IN32ri)>; 864 865def AtomWrite01_94 : SchedWriteRes<[AtomPort01]> { 866 let Latency = 94; 867 let ResourceCycles = [94]; 868} 869def : InstRW<[AtomWrite01_94], (instrs IN8rr, IN16rr, IN32rr)>; 870 871def AtomWrite01_99 : SchedWriteRes<[AtomPort01]> { 872 let Latency = 99; 873 let ResourceCycles = [99]; 874} 875def : InstRW<[AtomWrite01_99], (instrs F2XM1)>; 876 877def AtomWrite01_121 : SchedWriteRes<[AtomPort01]> { 878 let Latency = 121; 879 let ResourceCycles = [121]; 880} 881def : InstRW<[AtomWrite01_121], (instrs CPUID)>; 882 883def AtomWrite01_127 : SchedWriteRes<[AtomPort01]> { 884 let Latency = 127; 885 let ResourceCycles = [127]; 886} 887def : InstRW<[AtomWrite01_127], (instrs INT)>; 888 889def AtomWrite01_130 : SchedWriteRes<[AtomPort01]> { 890 let Latency = 130; 891 let ResourceCycles = [130]; 892} 893def : InstRW<[AtomWrite01_130], (instrs INT3)>; 894 895def AtomWrite01_140 : SchedWriteRes<[AtomPort01]> { 896 let Latency = 140; 897 let ResourceCycles = [140]; 898} 899def : InstRW<[AtomWrite01_140], (instrs FXSAVE, FXSAVE64)>; 900 901def AtomWrite01_141 : SchedWriteRes<[AtomPort01]> { 902 let Latency = 141; 903 let ResourceCycles = [141]; 904} 905def : InstRW<[AtomWrite01_141], (instrs FXRSTOR, FXRSTOR64)>; 906 907def AtomWrite01_146 : SchedWriteRes<[AtomPort01]> { 908 let Latency = 146; 909 let ResourceCycles = [146]; 910} 911def : InstRW<[AtomWrite01_146], (instrs FYL2X)>; 912 913def AtomWrite01_147 : SchedWriteRes<[AtomPort01]> { 914 let Latency = 147; 915 let ResourceCycles = [147]; 916} 917def : InstRW<[AtomWrite01_147], (instrs FYL2XP1)>; 918 919def AtomWrite01_168 : SchedWriteRes<[AtomPort01]> { 920 let Latency = 168; 921 let ResourceCycles = [168]; 922} 923def : InstRW<[AtomWrite01_168], (instrs FPTAN)>; 924 925def AtomWrite01_174 : SchedWriteRes<[AtomPort01]> { 926 let Latency = 174; 927 let ResourceCycles = [174]; 928} 929def : InstRW<[AtomWrite01_174], (instrs FSINCOS, FSIN, FCOS)>; 930 931def AtomWrite01_183 : SchedWriteRes<[AtomPort01]> { 932 let Latency = 183; 933 let ResourceCycles = [183]; 934} 935def : InstRW<[AtomWrite01_183], (instrs FPATAN)>; 936 937def AtomWrite01_202 : SchedWriteRes<[AtomPort01]> { 938 let Latency = 202; 939 let ResourceCycles = [202]; 940} 941def : InstRW<[AtomWrite01_202], (instrs WRMSR)>; 942 943} // SchedModel 944