1//===- X86ScheduleAtom.td - X86 Atom Scheduling Definitions -*- tablegen -*-==// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the schedule class data for the Intel Atom 10// in order (Saltwell-32nm/Bonnell-45nm) processors. 11// 12//===----------------------------------------------------------------------===// 13 14// 15// Scheduling information derived from the "Intel 64 and IA32 Architectures 16// Optimization Reference Manual", Chapter 13, Section 4. 17 18// Atom machine model. 19def AtomModel : SchedMachineModel { 20 let IssueWidth = 2; // Allows 2 instructions per scheduling group. 21 let MicroOpBufferSize = 0; // In-order execution, always hide latency. 22 let LoadLatency = 3; // Expected cycles, may be overriden. 23 let HighLatency = 30;// Expected, may be overriden. 24 25 // On the Atom, the throughput for taken branches is 2 cycles. For small 26 // simple loops, expand by a small factor to hide the backedge cost. 27 let LoopMicroOpBufferSize = 10; 28 let PostRAScheduler = 1; 29 let CompleteModel = 0; 30} 31 32let SchedModel = AtomModel in { 33 34// Functional Units 35def AtomPort0 : ProcResource<1>; // ALU: ALU0, shift/rotate, load/store 36 // SIMD/FP: SIMD ALU, Shuffle,SIMD/FP multiply, divide 37def AtomPort1 : ProcResource<1>; // ALU: ALU1, bit processing, jump, and LEA 38 // SIMD/FP: SIMD ALU, FP Adder 39 40def AtomPort01 : ProcResGroup<[AtomPort0, AtomPort1]>; 41 42// Loads are 3 cycles, so ReadAfterLd registers needn't be available until 3 43// cycles after the memory operand. 44def : ReadAdvance<ReadAfterLd, 3>; 45def : ReadAdvance<ReadAfterVecLd, 3>; 46def : ReadAdvance<ReadAfterVecXLd, 3>; 47def : ReadAdvance<ReadAfterVecYLd, 3>; 48 49def : ReadAdvance<ReadInt2Fpu, 0>; 50 51// Many SchedWrites are defined in pairs with and without a folded load. 52// Instructions with folded loads are usually micro-fused, so they only appear 53// as two micro-ops when dispatched by the schedulers. 54// This multiclass defines the resource usage for variants with and without 55// folded loads. 56multiclass AtomWriteResPair<X86FoldableSchedWrite SchedRW, 57 list<ProcResourceKind> RRPorts, 58 list<ProcResourceKind> RMPorts, 59 int RRLat = 1, int RMLat = 1, 60 list<int> RRRes = [1], 61 list<int> RMRes = [1]> { 62 // Register variant is using a single cycle on ExePort. 63 def : WriteRes<SchedRW, RRPorts> { 64 let Latency = RRLat; 65 let ResourceCycles = RRRes; 66 } 67 68 // Memory variant also uses a cycle on JLAGU and adds 3 cycles to the 69 // latency. 70 def : WriteRes<SchedRW.Folded, RMPorts> { 71 let Latency = RMLat; 72 let ResourceCycles = RMRes; 73 } 74} 75 76// A folded store needs a cycle on Port0 for the store data. 77def : WriteRes<WriteRMW, [AtomPort0]>; 78 79//////////////////////////////////////////////////////////////////////////////// 80// Arithmetic. 81//////////////////////////////////////////////////////////////////////////////// 82 83defm : AtomWriteResPair<WriteALU, [AtomPort01], [AtomPort0]>; 84defm : AtomWriteResPair<WriteADC, [AtomPort01], [AtomPort0]>; 85 86defm : AtomWriteResPair<WriteIMul8, [AtomPort01], [AtomPort01], 7, 7, [7], [7]>; 87defm : AtomWriteResPair<WriteIMul16, [AtomPort01], [AtomPort01], 7, 8, [7], [8]>; 88defm : AtomWriteResPair<WriteIMul16Imm, [AtomPort01], [AtomPort01], 6, 7, [6], [7]>; 89defm : AtomWriteResPair<WriteIMul16Reg, [AtomPort01], [AtomPort01], 6, 7, [6], [7]>; 90defm : AtomWriteResPair<WriteIMul32, [AtomPort01], [AtomPort01], 6, 7, [6], [7]>; 91defm : AtomWriteResPair<WriteIMul32Imm, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>; 92defm : AtomWriteResPair<WriteIMul32Reg, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>; 93defm : AtomWriteResPair<WriteIMul64, [AtomPort01], [AtomPort01], 12, 12, [12], [12]>; 94defm : AtomWriteResPair<WriteIMul64Imm, [AtomPort01], [AtomPort01], 14, 14, [14], [14]>; 95defm : AtomWriteResPair<WriteIMul64Reg, [AtomPort01], [AtomPort01], 12, 12, [12], [12]>; 96defm : X86WriteResUnsupported<WriteIMulH>; 97 98defm : X86WriteRes<WriteXCHG, [AtomPort01], 2, [2], 1>; 99defm : X86WriteRes<WriteBSWAP32, [AtomPort0], 1, [1], 1>; 100defm : X86WriteRes<WriteBSWAP64, [AtomPort0], 1, [1], 1>; 101defm : AtomWriteResPair<WriteCMPXCHG, [AtomPort01], [AtomPort01], 15, 15, [15]>; 102defm : X86WriteRes<WriteCMPXCHGRMW, [AtomPort01, AtomPort0], 1, [1, 1], 1>; 103 104defm : AtomWriteResPair<WriteDiv8, [AtomPort01], [AtomPort01], 50, 68, [50], [68]>; 105defm : AtomWriteResPair<WriteDiv16, [AtomPort01], [AtomPort01], 50, 50, [50], [50]>; 106defm : AtomWriteResPair<WriteDiv32, [AtomPort01], [AtomPort01], 50, 50, [50], [50]>; 107defm : AtomWriteResPair<WriteDiv64, [AtomPort01], [AtomPort01],130,130,[130],[130]>; 108defm : AtomWriteResPair<WriteIDiv8, [AtomPort01], [AtomPort01], 62, 62, [62], [62]>; 109defm : AtomWriteResPair<WriteIDiv16, [AtomPort01], [AtomPort01], 62, 62, [62], [62]>; 110defm : AtomWriteResPair<WriteIDiv32, [AtomPort01], [AtomPort01], 62, 62, [62], [62]>; 111defm : AtomWriteResPair<WriteIDiv64, [AtomPort01], [AtomPort01],130,130,[130],[130]>; 112 113defm : X86WriteResPairUnsupported<WriteCRC32>; 114 115defm : AtomWriteResPair<WriteCMOV, [AtomPort01], [AtomPort0]>; 116defm : X86WriteRes<WriteFCMOV, [AtomPort01], 9, [9], 1>; // x87 conditional move. 117 118def : WriteRes<WriteSETCC, [AtomPort01]>; 119def : WriteRes<WriteSETCCStore, [AtomPort01]> { 120 let Latency = 2; 121 let ResourceCycles = [2]; 122} 123def : WriteRes<WriteLAHFSAHF, [AtomPort01]> { 124 let Latency = 2; 125 let ResourceCycles = [2]; 126} 127defm : X86WriteRes<WriteBitTest, [AtomPort1], 1, [1], 1>; 128defm : X86WriteRes<WriteBitTestImmLd, [AtomPort0], 1, [1], 1>; 129defm : X86WriteRes<WriteBitTestRegLd, [AtomPort01], 9, [9], 1>; 130defm : X86WriteRes<WriteBitTestSet, [AtomPort1], 1, [1], 1>; 131//defm : X86WriteRes<WriteBitTestSetImmLd, [AtomPort1], 1, [1], 1>; 132//defm : X86WriteRes<WriteBitTestSetRegLd, [AtomPort1], 1, [1], 1>; 133 134// This is for simple LEAs with one or two input operands. 135def : WriteRes<WriteLEA, [AtomPort1]>; 136 137// Bit counts. 138defm : AtomWriteResPair<WriteBSF, [AtomPort01], [AtomPort01], 16, 16, [16], [16]>; 139defm : AtomWriteResPair<WriteBSR, [AtomPort01], [AtomPort01], 16, 16, [16], [16]>; 140defm : X86WriteResPairUnsupported<WritePOPCNT>; 141defm : X86WriteResPairUnsupported<WriteLZCNT>; 142defm : X86WriteResPairUnsupported<WriteTZCNT>; 143 144// BMI1 BEXTR/BLS, BMI2 BZHI 145defm : X86WriteResPairUnsupported<WriteBEXTR>; 146defm : X86WriteResPairUnsupported<WriteBLS>; 147defm : X86WriteResPairUnsupported<WriteBZHI>; 148 149//////////////////////////////////////////////////////////////////////////////// 150// Integer shifts and rotates. 151//////////////////////////////////////////////////////////////////////////////// 152 153defm : AtomWriteResPair<WriteShift, [AtomPort0], [AtomPort0]>; 154defm : AtomWriteResPair<WriteShiftCL, [AtomPort0], [AtomPort0]>; 155defm : AtomWriteResPair<WriteRotate, [AtomPort0], [AtomPort0]>; 156defm : AtomWriteResPair<WriteRotateCL, [AtomPort0], [AtomPort0]>; 157 158defm : X86WriteRes<WriteSHDrri, [AtomPort01], 2, [2], 1>; 159defm : X86WriteRes<WriteSHDrrcl,[AtomPort01], 2, [2], 1>; 160defm : X86WriteRes<WriteSHDmri, [AtomPort01], 4, [4], 1>; 161defm : X86WriteRes<WriteSHDmrcl,[AtomPort01], 4, [4], 1>; 162 163//////////////////////////////////////////////////////////////////////////////// 164// Loads, stores, and moves, not folded with other operations. 165//////////////////////////////////////////////////////////////////////////////// 166 167def : WriteRes<WriteLoad, [AtomPort0]>; 168def : WriteRes<WriteStore, [AtomPort0]>; 169def : WriteRes<WriteStoreNT, [AtomPort0]>; 170def : WriteRes<WriteMove, [AtomPort01]>; 171 172// Treat misc copies as a move. 173def : InstRW<[WriteMove], (instrs COPY)>; 174 175//////////////////////////////////////////////////////////////////////////////// 176// Idioms that clear a register, like xorps %xmm0, %xmm0. 177// These can often bypass execution ports completely. 178//////////////////////////////////////////////////////////////////////////////// 179 180def : WriteRes<WriteZero, []>; 181 182//////////////////////////////////////////////////////////////////////////////// 183// Branches don't produce values, so they have no latency, but they still 184// consume resources. Indirect branches can fold loads. 185//////////////////////////////////////////////////////////////////////////////// 186 187defm : AtomWriteResPair<WriteJump, [AtomPort1], [AtomPort1]>; 188 189//////////////////////////////////////////////////////////////////////////////// 190// Special case scheduling classes. 191//////////////////////////////////////////////////////////////////////////////// 192 193def : WriteRes<WriteSystem, [AtomPort01]> { let Latency = 100; } 194def : WriteRes<WriteMicrocoded, [AtomPort01]> { let Latency = 100; } 195def : WriteRes<WriteFence, [AtomPort0]>; 196 197// Nops don't have dependencies, so there's no actual latency, but we set this 198// to '1' to tell the scheduler that the nop uses an ALU slot for a cycle. 199def : WriteRes<WriteNop, [AtomPort01]>; 200 201//////////////////////////////////////////////////////////////////////////////// 202// Floating point. This covers both scalar and vector operations. 203//////////////////////////////////////////////////////////////////////////////// 204 205defm : X86WriteRes<WriteFLD0, [AtomPort01], 1, [1], 1>; 206defm : X86WriteRes<WriteFLD1, [AtomPort01], 6, [6], 1>; 207def : WriteRes<WriteFLoad, [AtomPort0]>; 208def : WriteRes<WriteFLoadX, [AtomPort0]>; 209defm : X86WriteResUnsupported<WriteFLoadY>; 210defm : X86WriteResUnsupported<WriteFMaskedLoad>; 211defm : X86WriteResUnsupported<WriteFMaskedLoadY>; 212 213def : WriteRes<WriteFStore, [AtomPort0]>; 214def : WriteRes<WriteFStoreX, [AtomPort0]>; 215defm : X86WriteResUnsupported<WriteFStoreY>; 216def : WriteRes<WriteFStoreNT, [AtomPort0]>; 217def : WriteRes<WriteFStoreNTX, [AtomPort0]>; 218defm : X86WriteResUnsupported<WriteFStoreNTY>; 219defm : X86WriteResUnsupported<WriteFMaskedStore>; 220defm : X86WriteResUnsupported<WriteFMaskedStoreY>; 221 222def : WriteRes<WriteFMove, [AtomPort01]>; 223def : WriteRes<WriteFMoveX, [AtomPort01]>; 224defm : X86WriteResUnsupported<WriteFMoveY>; 225 226defm : X86WriteRes<WriteEMMS, [AtomPort01], 5, [5], 1>; 227 228defm : AtomWriteResPair<WriteFAdd, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>; 229defm : AtomWriteResPair<WriteFAddX, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>; 230defm : X86WriteResPairUnsupported<WriteFAddY>; 231defm : X86WriteResPairUnsupported<WriteFAddZ>; 232defm : AtomWriteResPair<WriteFAdd64, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>; 233defm : AtomWriteResPair<WriteFAdd64X, [AtomPort01], [AtomPort01], 6, 7, [6], [7]>; 234defm : X86WriteResPairUnsupported<WriteFAdd64Y>; 235defm : X86WriteResPairUnsupported<WriteFAdd64Z>; 236defm : AtomWriteResPair<WriteFCmp, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>; 237defm : AtomWriteResPair<WriteFCmpX, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>; 238defm : X86WriteResPairUnsupported<WriteFCmpY>; 239defm : X86WriteResPairUnsupported<WriteFCmpZ>; 240defm : AtomWriteResPair<WriteFCmp64, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>; 241defm : AtomWriteResPair<WriteFCmp64X, [AtomPort01], [AtomPort01], 6, 7, [6], [7]>; 242defm : X86WriteResPairUnsupported<WriteFCmp64Y>; 243defm : X86WriteResPairUnsupported<WriteFCmp64Z>; 244defm : AtomWriteResPair<WriteFCom, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>; 245defm : AtomWriteResPair<WriteFMul, [AtomPort0], [AtomPort0], 4, 4, [4], [4]>; 246defm : AtomWriteResPair<WriteFMulX, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>; 247defm : X86WriteResPairUnsupported<WriteFMulY>; 248defm : X86WriteResPairUnsupported<WriteFMulZ>; 249defm : AtomWriteResPair<WriteFMul64, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>; 250defm : AtomWriteResPair<WriteFMul64X, [AtomPort01], [AtomPort01], 9, 10, [9], [10]>; 251defm : X86WriteResPairUnsupported<WriteFMul64Y>; 252defm : X86WriteResPairUnsupported<WriteFMul64Z>; 253defm : AtomWriteResPair<WriteFRcp, [AtomPort0], [AtomPort0], 4, 4, [4], [4]>; 254defm : AtomWriteResPair<WriteFRcpX, [AtomPort01], [AtomPort01], 9, 10, [9], [10]>; 255defm : X86WriteResPairUnsupported<WriteFRcpY>; 256defm : X86WriteResPairUnsupported<WriteFRcpZ>; 257defm : AtomWriteResPair<WriteFRsqrt, [AtomPort0], [AtomPort0], 4, 4, [4], [4]>; 258defm : AtomWriteResPair<WriteFRsqrtX, [AtomPort01], [AtomPort01], 9, 10, [9], [10]>; 259defm : X86WriteResPairUnsupported<WriteFRsqrtY>; 260defm : X86WriteResPairUnsupported<WriteFRsqrtZ>; 261defm : AtomWriteResPair<WriteFDiv, [AtomPort01], [AtomPort01], 34, 34, [34], [34]>; 262defm : AtomWriteResPair<WriteFDivX, [AtomPort01], [AtomPort01], 70, 70, [70], [70]>; 263defm : X86WriteResPairUnsupported<WriteFDivY>; 264defm : X86WriteResPairUnsupported<WriteFDivZ>; 265defm : AtomWriteResPair<WriteFDiv64, [AtomPort01], [AtomPort01], 62, 62, [62], [62]>; 266defm : AtomWriteResPair<WriteFDiv64X, [AtomPort01], [AtomPort01],125,125,[125],[125]>; 267defm : X86WriteResPairUnsupported<WriteFDiv64Y>; 268defm : X86WriteResPairUnsupported<WriteFDiv64Z>; 269defm : AtomWriteResPair<WriteFSqrt, [AtomPort01], [AtomPort01], 34, 34, [34], [34]>; 270defm : AtomWriteResPair<WriteFSqrtX, [AtomPort01], [AtomPort01], 70, 70, [70], [70]>; 271defm : X86WriteResPairUnsupported<WriteFSqrtY>; 272defm : X86WriteResPairUnsupported<WriteFSqrtZ>; 273defm : AtomWriteResPair<WriteFSqrt64, [AtomPort01], [AtomPort01], 62, 62, [62], [62]>; 274defm : AtomWriteResPair<WriteFSqrt64X, [AtomPort01], [AtomPort01],125,125,[125],[125]>; 275defm : X86WriteResPairUnsupported<WriteFSqrt64Y>; 276defm : X86WriteResPairUnsupported<WriteFSqrt64Z>; 277defm : AtomWriteResPair<WriteFSqrt80, [AtomPort01], [AtomPort01], 71, 71, [71], [71]>; 278defm : AtomWriteResPair<WriteFSign, [AtomPort1], [AtomPort1]>; 279defm : AtomWriteResPair<WriteFRnd, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>; 280defm : X86WriteResPairUnsupported<WriteFRndY>; 281defm : X86WriteResPairUnsupported<WriteFRndZ>; 282defm : AtomWriteResPair<WriteFLogic, [AtomPort01], [AtomPort0]>; 283defm : X86WriteResPairUnsupported<WriteFLogicY>; 284defm : X86WriteResPairUnsupported<WriteFLogicZ>; 285defm : AtomWriteResPair<WriteFTest, [AtomPort01], [AtomPort0]>; 286defm : X86WriteResPairUnsupported<WriteFTestY>; 287defm : X86WriteResPairUnsupported<WriteFTestZ>; 288defm : AtomWriteResPair<WriteFShuffle, [AtomPort0], [AtomPort0]>; 289defm : X86WriteResPairUnsupported<WriteFShuffleY>; 290defm : X86WriteResPairUnsupported<WriteFShuffleZ>; 291defm : X86WriteResPairUnsupported<WriteFVarShuffle>; 292defm : X86WriteResPairUnsupported<WriteFVarShuffleY>; 293defm : X86WriteResPairUnsupported<WriteFVarShuffleZ>; 294defm : X86WriteResPairUnsupported<WriteFMA>; 295defm : X86WriteResPairUnsupported<WriteFMAX>; 296defm : X86WriteResPairUnsupported<WriteFMAY>; 297defm : X86WriteResPairUnsupported<WriteFMAZ>; 298defm : X86WriteResPairUnsupported<WriteDPPD>; 299defm : X86WriteResPairUnsupported<WriteDPPS>; 300defm : X86WriteResPairUnsupported<WriteDPPSY>; 301defm : X86WriteResPairUnsupported<WriteDPPSZ>; 302defm : X86WriteResPairUnsupported<WriteFBlend>; 303defm : X86WriteResPairUnsupported<WriteFBlendY>; 304defm : X86WriteResPairUnsupported<WriteFBlendZ>; 305defm : X86WriteResPairUnsupported<WriteFVarBlend>; 306defm : X86WriteResPairUnsupported<WriteFVarBlendY>; 307defm : X86WriteResPairUnsupported<WriteFVarBlendZ>; 308defm : X86WriteResPairUnsupported<WriteFShuffle256>; 309defm : X86WriteResPairUnsupported<WriteFVarShuffle256>; 310 311//////////////////////////////////////////////////////////////////////////////// 312// Conversions. 313//////////////////////////////////////////////////////////////////////////////// 314 315defm : AtomWriteResPair<WriteCvtSS2I, [AtomPort01], [AtomPort01], 8, 9, [8], [9]>; 316defm : AtomWriteResPair<WriteCvtPS2I, [AtomPort01], [AtomPort01], 6, 7, [6], [7]>; 317defm : X86WriteResPairUnsupported<WriteCvtPS2IY>; 318defm : X86WriteResPairUnsupported<WriteCvtPS2IZ>; 319defm : AtomWriteResPair<WriteCvtSD2I, [AtomPort01], [AtomPort01], 8, 9, [8], [9]>; 320defm : AtomWriteResPair<WriteCvtPD2I, [AtomPort01], [AtomPort01], 7, 8, [7], [8]>; 321defm : X86WriteResPairUnsupported<WriteCvtPD2IY>; 322defm : X86WriteResPairUnsupported<WriteCvtPD2IZ>; 323 324defm : AtomWriteResPair<WriteCvtI2SS, [AtomPort01], [AtomPort01], 6, 7, [6], [7]>; 325defm : AtomWriteResPair<WriteCvtI2PS, [AtomPort01], [AtomPort01], 6, 7, [6], [7]>; 326defm : X86WriteResPairUnsupported<WriteCvtI2PSY>; 327defm : X86WriteResPairUnsupported<WriteCvtI2PSZ>; 328defm : AtomWriteResPair<WriteCvtI2SD, [AtomPort01], [AtomPort01], 6, 7, [6], [7]>; 329defm : AtomWriteResPair<WriteCvtI2PD, [AtomPort01], [AtomPort01], 7, 8, [7], [8]>; 330defm : X86WriteResPairUnsupported<WriteCvtI2PDY>; 331defm : X86WriteResPairUnsupported<WriteCvtI2PDZ>; 332 333defm : AtomWriteResPair<WriteCvtSS2SD, [AtomPort01], [AtomPort01], 6, 7, [6], [7]>; 334defm : AtomWriteResPair<WriteCvtPS2PD, [AtomPort01], [AtomPort01], 7, 8, [7], [8]>; 335defm : X86WriteResPairUnsupported<WriteCvtPS2PDY>; 336defm : X86WriteResPairUnsupported<WriteCvtPS2PDZ>; 337defm : AtomWriteResPair<WriteCvtSD2SS, [AtomPort01], [AtomPort01], 6, 7, [6], [7]>; 338defm : AtomWriteResPair<WriteCvtPD2PS, [AtomPort01], [AtomPort01], 7, 8, [7], [8]>; 339defm : X86WriteResPairUnsupported<WriteCvtPD2PSY>; 340defm : X86WriteResPairUnsupported<WriteCvtPD2PSZ>; 341 342defm : X86WriteResPairUnsupported<WriteCvtPH2PS>; 343defm : X86WriteResPairUnsupported<WriteCvtPH2PSY>; 344defm : X86WriteResPairUnsupported<WriteCvtPH2PSZ>; 345defm : X86WriteResUnsupported<WriteCvtPS2PH>; 346defm : X86WriteResUnsupported<WriteCvtPS2PHSt>; 347defm : X86WriteResUnsupported<WriteCvtPS2PHY>; 348defm : X86WriteResUnsupported<WriteCvtPS2PHZ>; 349defm : X86WriteResUnsupported<WriteCvtPS2PHYSt>; 350defm : X86WriteResUnsupported<WriteCvtPS2PHZSt>; 351 352//////////////////////////////////////////////////////////////////////////////// 353// Vector integer operations. 354//////////////////////////////////////////////////////////////////////////////// 355 356def : WriteRes<WriteVecLoad, [AtomPort0]>; 357def : WriteRes<WriteVecLoadX, [AtomPort0]>; 358defm : X86WriteResUnsupported<WriteVecLoadY>; 359def : WriteRes<WriteVecLoadNT, [AtomPort0]>; 360defm : X86WriteResUnsupported<WriteVecLoadNTY>; 361defm : X86WriteResUnsupported<WriteVecMaskedLoad>; 362defm : X86WriteResUnsupported<WriteVecMaskedLoadY>; 363 364def : WriteRes<WriteVecStore, [AtomPort0]>; 365def : WriteRes<WriteVecStoreX, [AtomPort0]>; 366defm : X86WriteResUnsupported<WriteVecStoreY>; 367def : WriteRes<WriteVecStoreNT, [AtomPort0]>; 368defm : X86WriteResUnsupported<WriteVecStoreNTY>; 369def : WriteRes<WriteVecMaskedStore, [AtomPort0]>; 370defm : X86WriteResUnsupported<WriteVecMaskedStoreY>; 371 372def : WriteRes<WriteVecMove, [AtomPort0]>; 373def : WriteRes<WriteVecMoveX, [AtomPort01]>; 374defm : X86WriteResUnsupported<WriteVecMoveY>; 375defm : X86WriteRes<WriteVecMoveToGpr, [AtomPort0], 3, [3], 1>; 376defm : X86WriteRes<WriteVecMoveFromGpr, [AtomPort0], 1, [1], 1>; 377 378defm : AtomWriteResPair<WriteVecALU, [AtomPort01], [AtomPort0], 1, 1>; 379defm : AtomWriteResPair<WriteVecALUX, [AtomPort01], [AtomPort0], 1, 1>; 380defm : X86WriteResPairUnsupported<WriteVecALUY>; 381defm : X86WriteResPairUnsupported<WriteVecALUZ>; 382defm : AtomWriteResPair<WriteVecLogic, [AtomPort01], [AtomPort0], 1, 1>; 383defm : AtomWriteResPair<WriteVecLogicX, [AtomPort01], [AtomPort0], 1, 1>; 384defm : X86WriteResPairUnsupported<WriteVecLogicY>; 385defm : X86WriteResPairUnsupported<WriteVecLogicZ>; 386defm : AtomWriteResPair<WriteVecTest, [AtomPort01], [AtomPort0], 1, 1>; 387defm : X86WriteResPairUnsupported<WriteVecTestY>; 388defm : X86WriteResPairUnsupported<WriteVecTestZ>; 389defm : AtomWriteResPair<WriteVecShift, [AtomPort01], [AtomPort01], 2, 3, [2], [3]>; 390defm : AtomWriteResPair<WriteVecShiftX, [AtomPort01], [AtomPort01], 2, 3, [2], [3]>; 391defm : X86WriteResPairUnsupported<WriteVecShiftY>; 392defm : X86WriteResPairUnsupported<WriteVecShiftZ>; 393defm : AtomWriteResPair<WriteVecShiftImm, [AtomPort01], [AtomPort01], 1, 1, [1], [1]>; 394defm : AtomWriteResPair<WriteVecShiftImmX, [AtomPort01], [AtomPort01], 1, 1, [1], [1]>; 395defm : X86WriteResPairUnsupported<WriteVecShiftImmY>; 396defm : X86WriteResPairUnsupported<WriteVecShiftImmZ>; 397defm : AtomWriteResPair<WriteVecIMul, [AtomPort0], [AtomPort0], 4, 4, [4], [4]>; 398defm : AtomWriteResPair<WriteVecIMulX, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>; 399defm : X86WriteResPairUnsupported<WriteVecIMulY>; 400defm : X86WriteResPairUnsupported<WriteVecIMulZ>; 401defm : X86WriteResPairUnsupported<WritePMULLD>; 402defm : X86WriteResPairUnsupported<WritePMULLDY>; 403defm : X86WriteResPairUnsupported<WritePMULLDZ>; 404defm : X86WriteResPairUnsupported<WritePHMINPOS>; 405defm : X86WriteResPairUnsupported<WriteMPSAD>; 406defm : X86WriteResPairUnsupported<WriteMPSADY>; 407defm : X86WriteResPairUnsupported<WriteMPSADZ>; 408defm : AtomWriteResPair<WritePSADBW, [AtomPort01], [AtomPort01], 4, 4, [4], [4]>; 409defm : AtomWriteResPair<WritePSADBWX, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>; 410defm : X86WriteResPairUnsupported<WritePSADBWY>; 411defm : X86WriteResPairUnsupported<WritePSADBWZ>; 412defm : AtomWriteResPair<WriteShuffle, [AtomPort0], [AtomPort0], 1, 1>; 413defm : AtomWriteResPair<WriteShuffleX, [AtomPort0], [AtomPort0], 1, 1>; 414defm : X86WriteResPairUnsupported<WriteShuffleY>; 415defm : X86WriteResPairUnsupported<WriteShuffleZ>; 416defm : AtomWriteResPair<WriteVarShuffle, [AtomPort0], [AtomPort0], 1, 1>; 417defm : AtomWriteResPair<WriteVarShuffleX, [AtomPort01], [AtomPort01], 4, 5, [4], [5]>; 418defm : X86WriteResPairUnsupported<WriteVarShuffleY>; 419defm : X86WriteResPairUnsupported<WriteVarShuffleZ>; 420defm : X86WriteResPairUnsupported<WriteBlend>; 421defm : X86WriteResPairUnsupported<WriteBlendY>; 422defm : X86WriteResPairUnsupported<WriteBlendZ>; 423defm : X86WriteResPairUnsupported<WriteVarBlend>; 424defm : X86WriteResPairUnsupported<WriteVarBlendY>; 425defm : X86WriteResPairUnsupported<WriteVarBlendZ>; 426defm : X86WriteResPairUnsupported<WriteShuffle256>; 427defm : X86WriteResPairUnsupported<WriteVarShuffle256>; 428defm : X86WriteResPairUnsupported<WriteVarVecShift>; 429defm : X86WriteResPairUnsupported<WriteVarVecShiftY>; 430defm : X86WriteResPairUnsupported<WriteVarVecShiftZ>; 431 432//////////////////////////////////////////////////////////////////////////////// 433// Vector insert/extract operations. 434//////////////////////////////////////////////////////////////////////////////// 435 436defm : AtomWriteResPair<WriteVecInsert, [AtomPort0], [AtomPort0], 1, 1>; 437def : WriteRes<WriteVecExtract, [AtomPort0]>; 438def : WriteRes<WriteVecExtractSt, [AtomPort0]>; 439 440//////////////////////////////////////////////////////////////////////////////// 441// SSE42 String instructions. 442//////////////////////////////////////////////////////////////////////////////// 443 444defm : X86WriteResPairUnsupported<WritePCmpIStrI>; 445defm : X86WriteResPairUnsupported<WritePCmpIStrM>; 446defm : X86WriteResPairUnsupported<WritePCmpEStrI>; 447defm : X86WriteResPairUnsupported<WritePCmpEStrM>; 448 449//////////////////////////////////////////////////////////////////////////////// 450// MOVMSK Instructions. 451//////////////////////////////////////////////////////////////////////////////// 452 453def : WriteRes<WriteFMOVMSK, [AtomPort0]> { let Latency = 3; let ResourceCycles = [3]; } 454def : WriteRes<WriteVecMOVMSK, [AtomPort0]> { let Latency = 3; let ResourceCycles = [3]; } 455defm : X86WriteResUnsupported<WriteVecMOVMSKY>; 456def : WriteRes<WriteMMXMOVMSK, [AtomPort0]> { let Latency = 3; let ResourceCycles = [3]; } 457 458//////////////////////////////////////////////////////////////////////////////// 459// AES instructions. 460//////////////////////////////////////////////////////////////////////////////// 461 462defm : X86WriteResPairUnsupported<WriteAESIMC>; 463defm : X86WriteResPairUnsupported<WriteAESKeyGen>; 464defm : X86WriteResPairUnsupported<WriteAESDecEnc>; 465 466//////////////////////////////////////////////////////////////////////////////// 467// Horizontal add/sub instructions. 468//////////////////////////////////////////////////////////////////////////////// 469 470defm : AtomWriteResPair<WriteFHAdd, [AtomPort01], [AtomPort01], 8, 9, [8], [9]>; 471defm : AtomWriteResPair<WriteFHAddY, [AtomPort01], [AtomPort01], 8, 9, [8], [9]>; 472defm : AtomWriteResPair<WritePHAdd, [AtomPort01], [AtomPort01], 3, 4, [3], [4]>; 473defm : AtomWriteResPair<WritePHAddX, [AtomPort01], [AtomPort01], 7, 8, [7], [8]>; 474defm : AtomWriteResPair<WritePHAddY, [AtomPort01], [AtomPort01], 7, 8, [7], [8]>; 475 476//////////////////////////////////////////////////////////////////////////////// 477// Carry-less multiplication instructions. 478//////////////////////////////////////////////////////////////////////////////// 479 480defm : X86WriteResPairUnsupported<WriteCLMul>; 481 482//////////////////////////////////////////////////////////////////////////////// 483// Load/store MXCSR. 484//////////////////////////////////////////////////////////////////////////////// 485 486def : WriteRes<WriteLDMXCSR, [AtomPort01]> { let Latency = 5; let ResourceCycles = [5]; } 487def : WriteRes<WriteSTMXCSR, [AtomPort01]> { let Latency = 15; let ResourceCycles = [15]; } 488 489//////////////////////////////////////////////////////////////////////////////// 490// Special Cases. 491//////////////////////////////////////////////////////////////////////////////// 492 493// Port0 494def AtomWrite0_1 : SchedWriteRes<[AtomPort0]> { 495 let Latency = 1; 496 let ResourceCycles = [1]; 497} 498def : InstRW<[AtomWrite0_1], (instrs FXAM, LD_Frr, 499 MOVSX64rr32)>; 500def : SchedAlias<WriteALURMW, AtomWrite0_1>; 501def : SchedAlias<WriteADCRMW, AtomWrite0_1>; 502def : InstRW<[AtomWrite0_1], (instregex "(RCL|RCR|ROL|ROR|SAR|SHL|SHR)(8|16|32|64)m", 503 "MOV(S|Z)X(32|64)rr(8|8_NOREX|16)")>; 504 505// Port1 506def AtomWrite1_1 : SchedWriteRes<[AtomPort1]> { 507 let Latency = 1; 508 let ResourceCycles = [1]; 509} 510def : InstRW<[AtomWrite1_1], (instrs FCOMPP)>; 511def : InstRW<[AtomWrite1_1], (instregex "UCOM_F(P|PP)?r")>; 512 513def AtomWrite1_5 : SchedWriteRes<[AtomPort1]> { 514 let Latency = 5; 515 let ResourceCycles = [5]; 516} 517def : InstRW<[AtomWrite1_5], (instrs MMX_CVTPI2PSirr, MMX_CVTPI2PSirm, 518 MMX_CVTPS2PIirr, MMX_CVTTPS2PIirr)>; 519 520// Port0 and Port1 521def AtomWrite0_1_1 : SchedWriteRes<[AtomPort0, AtomPort1]> { 522 let Latency = 1; 523 let ResourceCycles = [1, 1]; 524} 525def : InstRW<[AtomWrite0_1_1], (instrs POP32r, POP64r, 526 POP16rmr, POP32rmr, POP64rmr, 527 PUSH16r, PUSH32r, PUSH64r, 528 PUSHi16, PUSHi32, 529 PUSH16rmr, PUSH32rmr, PUSH64rmr, 530 PUSH16i8, PUSH32i8, PUSH64i8, PUSH64i32, 531 XCH_F)>; 532def : InstRW<[AtomWrite0_1_1], (instregex "RETI(L|Q|W)$", 533 "IRET(16|32|64)?")>; 534 535def AtomWrite0_1_5 : SchedWriteRes<[AtomPort0, AtomPort1]> { 536 let Latency = 5; 537 let ResourceCycles = [5, 5]; 538} 539def : InstRW<[AtomWrite0_1_5], (instrs MMX_CVTPS2PIirm, MMX_CVTTPS2PIirm)>; 540def : InstRW<[AtomWrite0_1_5], (instregex "ILD_F(16|32|64)")>; 541 542// Port0 or Port1 543def AtomWrite01_1 : SchedWriteRes<[AtomPort01]> { 544 let Latency = 1; 545 let ResourceCycles = [1]; 546} 547def : InstRW<[AtomWrite01_1], (instrs FDECSTP, FFREE, FFREEP, FINCSTP, WAIT, 548 LFENCE, 549 STOSB, STOSL, STOSQ, STOSW, 550 MOVSSrr, MOVSSrr_REV, 551 PSLLDQri, PSRLDQri)>; 552def : InstRW<[AtomWrite01_1], (instregex "MMX_PACK(SSDW|SSWB|USWB)irr", 553 "MMX_PUNPCKH(BW|DQ|WD)irr")>; 554 555def AtomWrite01_2 : SchedWriteRes<[AtomPort01]> { 556 let Latency = 2; 557 let ResourceCycles = [2]; 558} 559def : InstRW<[AtomWrite01_2], (instrs LEAVE, LEAVE64, POP16r, 560 PUSH16rmm, PUSH32rmm, PUSH64rmm, 561 LODSB, LODSL, LODSQ, LODSW, 562 SCASB, SCASL, SCASQ, SCASW)>; 563def : InstRW<[AtomWrite01_2], (instregex "PUSH(CS|DS|ES|FS|GS|SS)(16|32|64)", 564 "(ST|ISTT)_F(P)?(16|32|64)?(m|rr)", 565 "MMX_P(ADD|SUB)Qirr", 566 "MOV(S|Z)X16rr8", 567 "MOV(UPS|UPD|DQU)mr", 568 "MASKMOVDQU(64)?", 569 "P(ADD|SUB)Qrr")>; 570def : SchedAlias<WriteBitTestSetImmRMW, AtomWrite01_2>; 571 572def AtomWrite01_3 : SchedWriteRes<[AtomPort01]> { 573 let Latency = 3; 574 let ResourceCycles = [3]; 575} 576def : InstRW<[AtomWrite01_3], (instrs CLD, LDDQUrm, 577 CMPSB, CMPSL, CMPSQ, CMPSW, 578 MOVSB, MOVSL, MOVSQ, MOVSW, 579 POP16rmm, POP32rmm, POP64rmm)>; 580def : InstRW<[AtomWrite01_3], (instregex "XADD(8|16|32|64)rm", 581 "XCHG(8|16|32|64)rm", 582 "PH(ADD|SUB)Drr", 583 "MOV(S|Z)X16rm8", 584 "MMX_P(ADD|SUB)Qirm", 585 "MOV(UPS|UPD|DQU)rm", 586 "P(ADD|SUB)Qrm")>; 587 588def AtomWrite01_4 : SchedWriteRes<[AtomPort01]> { 589 let Latency = 4; 590 let ResourceCycles = [4]; 591} 592def : InstRW<[AtomWrite01_4], (instrs CBW, CWD, CWDE, CDQ, CDQE, CQO, 593 JCXZ, JECXZ, JRCXZ, 594 LD_F80m)>; 595def : InstRW<[AtomWrite01_4], (instregex "PH(ADD|SUB)Drm", 596 "(MMX_)?PEXTRWrr(_REV)?")>; 597 598def AtomWrite01_5 : SchedWriteRes<[AtomPort01]> { 599 let Latency = 5; 600 let ResourceCycles = [5]; 601} 602def : InstRW<[AtomWrite01_5], (instrs FLDCW16m, ST_FP80m)>; 603def : InstRW<[AtomWrite01_5], (instregex "MMX_PH(ADD|SUB)S?Wrr")>; 604 605def AtomWrite01_6 : SchedWriteRes<[AtomPort01]> { 606 let Latency = 6; 607 let ResourceCycles = [6]; 608} 609def : InstRW<[AtomWrite01_6], (instrs CMPXCHG8rm, INTO, XLAT, 610 SHLD16rrCL, SHRD16rrCL, 611 SHLD16rri8, SHRD16rri8, 612 SHLD16mrCL, SHRD16mrCL, 613 SHLD16mri8, SHRD16mri8)>; 614def : InstRW<[AtomWrite01_6], (instregex "IST_F(P)?(16|32|64)?m", 615 "MMX_PH(ADD|SUB)S?Wrm")>; 616 617def AtomWrite01_7 : SchedWriteRes<[AtomPort01]> { 618 let Latency = 7; 619 let ResourceCycles = [7]; 620} 621def : InstRW<[AtomWrite01_7], (instrs AAD8i8)>; 622 623def AtomWrite01_8 : SchedWriteRes<[AtomPort01]> { 624 let Latency = 8; 625 let ResourceCycles = [8]; 626} 627def : InstRW<[AtomWrite01_8], (instrs LOOPE, 628 PUSHA16, PUSHA32, 629 SHLD64rrCL, SHRD64rrCL, 630 FNSTCW16m)>; 631 632def AtomWrite01_9 : SchedWriteRes<[AtomPort01]> { 633 let Latency = 9; 634 let ResourceCycles = [9]; 635} 636def : InstRW<[AtomWrite01_9], (instrs POPA16, POPA32, 637 PUSHF16, PUSHF32, PUSHF64, 638 SHLD64mrCL, SHRD64mrCL, 639 SHLD64mri8, SHRD64mri8, 640 SHLD64rri8, SHRD64rri8, 641 CMPXCHG8rr)>; 642def : InstRW<[AtomWrite01_9], (instregex "(U)?COM_FI", "TST_F", 643 "(U)?COMIS(D|S)rr", 644 "CVT(T)?SS2SI64rr(_Int)?")>; 645 646def AtomWrite01_10 : SchedWriteRes<[AtomPort01]> { 647 let Latency = 10; 648 let ResourceCycles = [10]; 649} 650def : SchedAlias<WriteFLDC, AtomWrite01_10>; 651def : InstRW<[AtomWrite01_10], (instregex "(U)?COMIS(D|S)rm", 652 "CVT(T)?SS2SI64rm(_Int)?")>; 653 654def AtomWrite01_11 : SchedWriteRes<[AtomPort01]> { 655 let Latency = 11; 656 let ResourceCycles = [11]; 657} 658def : InstRW<[AtomWrite01_11], (instrs BOUNDS16rm, BOUNDS32rm)>; 659def : SchedAlias<WriteBitTestSetRegRMW, AtomWrite01_11>; 660 661def AtomWrite01_13 : SchedWriteRes<[AtomPort01]> { 662 let Latency = 13; 663 let ResourceCycles = [13]; 664} 665def : InstRW<[AtomWrite01_13], (instrs AAA, AAS)>; 666 667def AtomWrite01_14 : SchedWriteRes<[AtomPort01]> { 668 let Latency = 14; 669 let ResourceCycles = [14]; 670} 671def : InstRW<[AtomWrite01_14], (instrs CMPXCHG16rm, CMPXCHG32rm, CMPXCHG64rm)>; 672 673def AtomWrite01_17 : SchedWriteRes<[AtomPort01]> { 674 let Latency = 17; 675 let ResourceCycles = [17]; 676} 677def : InstRW<[AtomWrite01_17], (instrs LOOPNE, PAUSE)>; 678 679def AtomWrite01_18 : SchedWriteRes<[AtomPort01]> { 680 let Latency = 18; 681 let ResourceCycles = [18]; 682} 683def : InstRW<[AtomWrite01_18], (instrs CMPXCHG8B, DAA, LOOP)>; 684 685def AtomWrite01_20 : SchedWriteRes<[AtomPort01]> { 686 let Latency = 20; 687 let ResourceCycles = [20]; 688} 689def : InstRW<[AtomWrite01_20], (instrs DAS)>; 690 691def AtomWrite01_21 : SchedWriteRes<[AtomPort01]> { 692 let Latency = 21; 693 let ResourceCycles = [21]; 694} 695def : InstRW<[AtomWrite01_21], (instrs AAM8i8, STD)>; 696 697def AtomWrite01_22 : SchedWriteRes<[AtomPort01]> { 698 let Latency = 22; 699 let ResourceCycles = [22]; 700} 701def : InstRW<[AtomWrite01_22], (instrs CMPXCHG16B)>; 702 703def AtomWrite01_23 : SchedWriteRes<[AtomPort01]> { 704 let Latency = 23; 705 let ResourceCycles = [23]; 706} 707def : InstRW<[AtomWrite01_23], (instrs ARPL16mr, ARPL16rr)>; 708 709def AtomWrite01_25 : SchedWriteRes<[AtomPort01]> { 710 let Latency = 25; 711 let ResourceCycles = [25]; 712} 713def : InstRW<[AtomWrite01_25], (instrs FNCLEX, FXTRACT)>; 714 715def AtomWrite01_26 : SchedWriteRes<[AtomPort01]> { 716 let Latency = 26; 717 let ResourceCycles = [26]; 718} 719def : InstRW<[AtomWrite01_26], (instrs POPF32, POPF64)>; 720 721def AtomWrite01_29 : SchedWriteRes<[AtomPort01]> { 722 let Latency = 29; 723 let ResourceCycles = [29]; 724} 725def : InstRW<[AtomWrite01_29], (instregex "POP(DS|ES|FS|GS)(16|32|64)")>; 726 727def AtomWrite01_30 : SchedWriteRes<[AtomPort01]> { 728 let Latency = 30; 729 let ResourceCycles = [30]; 730} 731def : InstRW<[AtomWrite01_30], (instrs RDTSC, RDTSCP)>; 732 733def AtomWrite01_32 : SchedWriteRes<[AtomPort01]> { 734 let Latency = 32; 735 let ResourceCycles = [32]; 736} 737def : InstRW<[AtomWrite01_32], (instrs ENTER, POPF16)>; 738 739def AtomWrite01_45 : SchedWriteRes<[AtomPort01]> { 740 let Latency = 45; 741 let ResourceCycles = [45]; 742} 743def : InstRW<[AtomWrite01_45], (instrs MONITOR32rrr, MONITOR64rrr)>; 744 745def AtomWrite01_46 : SchedWriteRes<[AtomPort01]> { 746 let Latency = 46; 747 let ResourceCycles = [46]; 748} 749def : InstRW<[AtomWrite01_46], (instrs FRNDINT, MWAITrr, RDPMC)>; 750 751def AtomWrite01_48 : SchedWriteRes<[AtomPort01]> { 752 let Latency = 48; 753 let ResourceCycles = [48]; 754} 755def : InstRW<[AtomWrite01_48], (instrs POPSS16, POPSS32)>; 756 757def AtomWrite01_55 : SchedWriteRes<[AtomPort01]> { 758 let Latency = 55; 759 let ResourceCycles = [55]; 760} 761def : InstRW<[AtomWrite01_55], (instrs FPREM)>; 762 763def AtomWrite01_59 : SchedWriteRes<[AtomPort01]> { 764 let Latency = 59; 765 let ResourceCycles = [59]; 766} 767def : InstRW<[AtomWrite01_59], (instrs INSB, INSL, INSW)>; 768 769def AtomWrite01_63 : SchedWriteRes<[AtomPort01]> { 770 let Latency = 63; 771 let ResourceCycles = [63]; 772} 773def : InstRW<[AtomWrite01_63], (instrs FNINIT)>; 774 775def AtomWrite01_68 : SchedWriteRes<[AtomPort01]> { 776 let Latency = 68; 777 let ResourceCycles = [68]; 778} 779def : InstRW<[AtomWrite01_68], (instrs OUT8rr, OUT16rr, OUT32rr)>; 780 781def AtomWrite01_71 : SchedWriteRes<[AtomPort01]> { 782 let Latency = 71; 783 let ResourceCycles = [71]; 784} 785def : InstRW<[AtomWrite01_71], (instrs FPREM1, 786 INVLPG, INVLPGA32, INVLPGA64)>; 787 788def AtomWrite01_72 : SchedWriteRes<[AtomPort01]> { 789 let Latency = 72; 790 let ResourceCycles = [72]; 791} 792def : InstRW<[AtomWrite01_72], (instrs OUT8ir, OUT16ir, OUT32ir)>; 793 794def AtomWrite01_74 : SchedWriteRes<[AtomPort01]> { 795 let Latency = 74; 796 let ResourceCycles = [74]; 797} 798def : InstRW<[AtomWrite01_74], (instrs OUTSB, OUTSL, OUTSW)>; 799 800def AtomWrite01_77 : SchedWriteRes<[AtomPort01]> { 801 let Latency = 77; 802 let ResourceCycles = [77]; 803} 804def : InstRW<[AtomWrite01_77], (instrs FSCALE)>; 805 806def AtomWrite01_78 : SchedWriteRes<[AtomPort01]> { 807 let Latency = 78; 808 let ResourceCycles = [78]; 809} 810def : InstRW<[AtomWrite01_78], (instrs RDMSR)>; 811 812def AtomWrite01_79 : SchedWriteRes<[AtomPort01]> { 813 let Latency = 79; 814 let ResourceCycles = [79]; 815} 816def : InstRW<[AtomWrite01_79], (instregex "RET(L|Q|W)?$", 817 "LRETI?(L|Q|W)")>; 818 819def AtomWrite01_92 : SchedWriteRes<[AtomPort01]> { 820 let Latency = 92; 821 let ResourceCycles = [92]; 822} 823def : InstRW<[AtomWrite01_92], (instrs IN8ri, IN16ri, IN32ri)>; 824 825def AtomWrite01_94 : SchedWriteRes<[AtomPort01]> { 826 let Latency = 94; 827 let ResourceCycles = [94]; 828} 829def : InstRW<[AtomWrite01_94], (instrs IN8rr, IN16rr, IN32rr)>; 830 831def AtomWrite01_99 : SchedWriteRes<[AtomPort01]> { 832 let Latency = 99; 833 let ResourceCycles = [99]; 834} 835def : InstRW<[AtomWrite01_99], (instrs F2XM1)>; 836 837def AtomWrite01_121 : SchedWriteRes<[AtomPort01]> { 838 let Latency = 121; 839 let ResourceCycles = [121]; 840} 841def : InstRW<[AtomWrite01_121], (instrs CPUID)>; 842 843def AtomWrite01_127 : SchedWriteRes<[AtomPort01]> { 844 let Latency = 127; 845 let ResourceCycles = [127]; 846} 847def : InstRW<[AtomWrite01_127], (instrs INT)>; 848 849def AtomWrite01_130 : SchedWriteRes<[AtomPort01]> { 850 let Latency = 130; 851 let ResourceCycles = [130]; 852} 853def : InstRW<[AtomWrite01_130], (instrs INT3)>; 854 855def AtomWrite01_140 : SchedWriteRes<[AtomPort01]> { 856 let Latency = 140; 857 let ResourceCycles = [140]; 858} 859def : InstRW<[AtomWrite01_140], (instrs FXSAVE, FXSAVE64)>; 860 861def AtomWrite01_141 : SchedWriteRes<[AtomPort01]> { 862 let Latency = 141; 863 let ResourceCycles = [141]; 864} 865def : InstRW<[AtomWrite01_141], (instrs FXRSTOR, FXRSTOR64)>; 866 867def AtomWrite01_146 : SchedWriteRes<[AtomPort01]> { 868 let Latency = 146; 869 let ResourceCycles = [146]; 870} 871def : InstRW<[AtomWrite01_146], (instrs FYL2X)>; 872 873def AtomWrite01_147 : SchedWriteRes<[AtomPort01]> { 874 let Latency = 147; 875 let ResourceCycles = [147]; 876} 877def : InstRW<[AtomWrite01_147], (instrs FYL2XP1)>; 878 879def AtomWrite01_168 : SchedWriteRes<[AtomPort01]> { 880 let Latency = 168; 881 let ResourceCycles = [168]; 882} 883def : InstRW<[AtomWrite01_168], (instrs FPTAN)>; 884 885def AtomWrite01_174 : SchedWriteRes<[AtomPort01]> { 886 let Latency = 174; 887 let ResourceCycles = [174]; 888} 889def : InstRW<[AtomWrite01_174], (instrs FSINCOS)>; 890def : InstRW<[AtomWrite01_174], (instregex "(COS|SIN)_F")>; 891 892def AtomWrite01_183 : SchedWriteRes<[AtomPort01]> { 893 let Latency = 183; 894 let ResourceCycles = [183]; 895} 896def : InstRW<[AtomWrite01_183], (instrs FPATAN)>; 897 898def AtomWrite01_202 : SchedWriteRes<[AtomPort01]> { 899 let Latency = 202; 900 let ResourceCycles = [202]; 901} 902def : InstRW<[AtomWrite01_202], (instrs WRMSR)>; 903 904} // SchedModel 905