1//===- X86ScheduleAtom.td - X86 Atom Scheduling Definitions -*- tablegen -*-==// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the schedule class data for the Intel Atom 10// in order (Saltwell-32nm/Bonnell-45nm) processors. 11// 12//===----------------------------------------------------------------------===// 13 14// 15// Scheduling information derived from the "Intel 64 and IA32 Architectures 16// Optimization Reference Manual", Chapter 13, Section 4. 17 18// Atom machine model. 19def AtomModel : SchedMachineModel { 20 let IssueWidth = 2; // Allows 2 instructions per scheduling group. 21 let MicroOpBufferSize = 0; // In-order execution, always hide latency. 22 let LoadLatency = 3; // Expected cycles, may be overriden. 23 let HighLatency = 30;// Expected, may be overriden. 24 25 // On the Atom, the throughput for taken branches is 2 cycles. For small 26 // simple loops, expand by a small factor to hide the backedge cost. 27 let LoopMicroOpBufferSize = 10; 28 let PostRAScheduler = 1; 29 let CompleteModel = 0; 30} 31 32let SchedModel = AtomModel in { 33 34// Functional Units 35def AtomPort0 : ProcResource<1>; // ALU: ALU0, shift/rotate, load/store 36 // SIMD/FP: SIMD ALU, Shuffle,SIMD/FP multiply, divide 37def AtomPort1 : ProcResource<1>; // ALU: ALU1, bit processing, jump, and LEA 38 // SIMD/FP: SIMD ALU, FP Adder 39 40def AtomPort01 : ProcResGroup<[AtomPort0, AtomPort1]>; 41 42// Loads are 3 cycles, so ReadAfterLd registers needn't be available until 3 43// cycles after the memory operand. 44def : ReadAdvance<ReadAfterLd, 3>; 45def : ReadAdvance<ReadAfterVecLd, 3>; 46def : ReadAdvance<ReadAfterVecXLd, 3>; 47def : ReadAdvance<ReadAfterVecYLd, 3>; 48 49def : ReadAdvance<ReadInt2Fpu, 0>; 50 51// Many SchedWrites are defined in pairs with and without a folded load. 52// Instructions with folded loads are usually micro-fused, so they only appear 53// as two micro-ops when dispatched by the schedulers. 54// This multiclass defines the resource usage for variants with and without 55// folded loads. 56multiclass AtomWriteResPair<X86FoldableSchedWrite SchedRW, 57 list<ProcResourceKind> RRPorts, 58 list<ProcResourceKind> RMPorts, 59 int RRLat = 1, int RMLat = 1, 60 list<int> RRRes = [1], 61 list<int> RMRes = [1]> { 62 // Register variant is using a single cycle on ExePort. 63 def : WriteRes<SchedRW, RRPorts> { 64 let Latency = RRLat; 65 let ResourceCycles = RRRes; 66 } 67 68 // Memory variant also uses a cycle on JLAGU and adds 3 cycles to the 69 // latency. 70 def : WriteRes<SchedRW.Folded, RMPorts> { 71 let Latency = RMLat; 72 let ResourceCycles = RMRes; 73 } 74} 75 76// A folded store needs a cycle on Port0 for the store data. 77def : WriteRes<WriteRMW, [AtomPort0]>; 78 79//////////////////////////////////////////////////////////////////////////////// 80// Arithmetic. 81//////////////////////////////////////////////////////////////////////////////// 82 83defm : AtomWriteResPair<WriteALU, [AtomPort01], [AtomPort0]>; 84defm : AtomWriteResPair<WriteADC, [AtomPort01], [AtomPort0]>; 85 86defm : AtomWriteResPair<WriteIMul8, [AtomPort01], [AtomPort01], 7, 7, [7], [7]>; 87defm : AtomWriteResPair<WriteIMul16, [AtomPort01], [AtomPort01], 7, 8, [7], [8]>; 88defm : AtomWriteResPair<WriteIMul16Imm, [AtomPort01], [AtomPort01], 6, 7, [6], [7]>; 89defm : AtomWriteResPair<WriteIMul16Reg, [AtomPort01], [AtomPort01], 6, 7, [6], [7]>; 90defm : AtomWriteResPair<WriteIMul32, [AtomPort01], [AtomPort01], 6, 7, [6], [7]>; 91defm : AtomWriteResPair<WriteIMul32Imm, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>; 92defm : AtomWriteResPair<WriteIMul32Reg, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>; 93defm : AtomWriteResPair<WriteIMul64, [AtomPort01], [AtomPort01], 12, 12, [12], [12]>; 94defm : AtomWriteResPair<WriteIMul64Imm, [AtomPort01], [AtomPort01], 14, 14, [14], [14]>; 95defm : AtomWriteResPair<WriteIMul64Reg, [AtomPort01], [AtomPort01], 12, 12, [12], [12]>; 96defm : X86WriteResUnsupported<WriteIMulH>; 97 98defm : X86WriteRes<WriteXCHG, [AtomPort01], 2, [2], 1>; 99defm : X86WriteRes<WriteBSWAP32, [AtomPort0], 1, [1], 1>; 100defm : X86WriteRes<WriteBSWAP64, [AtomPort0], 1, [1], 1>; 101defm : AtomWriteResPair<WriteCMPXCHG, [AtomPort01], [AtomPort01], 15, 15, [15]>; 102defm : X86WriteRes<WriteCMPXCHGRMW, [AtomPort01, AtomPort0], 1, [1, 1], 1>; 103 104defm : AtomWriteResPair<WriteDiv8, [AtomPort01], [AtomPort01], 50, 68, [50], [68]>; 105defm : AtomWriteResPair<WriteDiv16, [AtomPort01], [AtomPort01], 50, 50, [50], [50]>; 106defm : AtomWriteResPair<WriteDiv32, [AtomPort01], [AtomPort01], 50, 50, [50], [50]>; 107defm : AtomWriteResPair<WriteDiv64, [AtomPort01], [AtomPort01],130,130,[130],[130]>; 108defm : AtomWriteResPair<WriteIDiv8, [AtomPort01], [AtomPort01], 62, 62, [62], [62]>; 109defm : AtomWriteResPair<WriteIDiv16, [AtomPort01], [AtomPort01], 62, 62, [62], [62]>; 110defm : AtomWriteResPair<WriteIDiv32, [AtomPort01], [AtomPort01], 62, 62, [62], [62]>; 111defm : AtomWriteResPair<WriteIDiv64, [AtomPort01], [AtomPort01],130,130,[130],[130]>; 112 113defm : X86WriteResPairUnsupported<WriteCRC32>; 114 115defm : AtomWriteResPair<WriteCMOV, [AtomPort01], [AtomPort0]>; 116defm : X86WriteRes<WriteFCMOV, [AtomPort01], 9, [9], 1>; // x87 conditional move. 117 118def : WriteRes<WriteSETCC, [AtomPort01]>; 119def : WriteRes<WriteSETCCStore, [AtomPort01]> { 120 let Latency = 2; 121 let ResourceCycles = [2]; 122} 123def : WriteRes<WriteLAHFSAHF, [AtomPort01]> { 124 let Latency = 2; 125 let ResourceCycles = [2]; 126} 127defm : X86WriteRes<WriteBitTest, [AtomPort1], 1, [1], 1>; 128defm : X86WriteRes<WriteBitTestImmLd, [AtomPort0], 1, [1], 1>; 129defm : X86WriteRes<WriteBitTestRegLd, [AtomPort01], 9, [9], 1>; 130defm : X86WriteRes<WriteBitTestSet, [AtomPort1], 1, [1], 1>; 131//defm : X86WriteRes<WriteBitTestSetImmLd, [AtomPort1], 1, [1], 1>; 132//defm : X86WriteRes<WriteBitTestSetRegLd, [AtomPort1], 1, [1], 1>; 133 134// This is for simple LEAs with one or two input operands. 135def : WriteRes<WriteLEA, [AtomPort1]>; 136 137// Bit counts. 138defm : AtomWriteResPair<WriteBSF, [AtomPort01], [AtomPort01], 16, 16, [16], [16]>; 139defm : AtomWriteResPair<WriteBSR, [AtomPort01], [AtomPort01], 16, 16, [16], [16]>; 140defm : X86WriteResPairUnsupported<WritePOPCNT>; 141defm : X86WriteResPairUnsupported<WriteLZCNT>; 142defm : X86WriteResPairUnsupported<WriteTZCNT>; 143 144// BMI1 BEXTR/BLS, BMI2 BZHI 145defm : X86WriteResPairUnsupported<WriteBEXTR>; 146defm : X86WriteResPairUnsupported<WriteBLS>; 147defm : X86WriteResPairUnsupported<WriteBZHI>; 148 149//////////////////////////////////////////////////////////////////////////////// 150// Integer shifts and rotates. 151//////////////////////////////////////////////////////////////////////////////// 152 153defm : AtomWriteResPair<WriteShift, [AtomPort0], [AtomPort0]>; 154defm : AtomWriteResPair<WriteShiftCL, [AtomPort0], [AtomPort0]>; 155defm : AtomWriteResPair<WriteRotate, [AtomPort0], [AtomPort0]>; 156defm : AtomWriteResPair<WriteRotateCL, [AtomPort0], [AtomPort0]>; 157 158defm : X86WriteRes<WriteSHDrri, [AtomPort01], 2, [2], 1>; 159defm : X86WriteRes<WriteSHDrrcl,[AtomPort01], 2, [2], 1>; 160defm : X86WriteRes<WriteSHDmri, [AtomPort01], 4, [4], 1>; 161defm : X86WriteRes<WriteSHDmrcl,[AtomPort01], 4, [4], 1>; 162 163//////////////////////////////////////////////////////////////////////////////// 164// Loads, stores, and moves, not folded with other operations. 165//////////////////////////////////////////////////////////////////////////////// 166 167def : WriteRes<WriteLoad, [AtomPort0]>; 168def : WriteRes<WriteStore, [AtomPort0]>; 169def : WriteRes<WriteStoreNT, [AtomPort0]>; 170def : WriteRes<WriteMove, [AtomPort01]>; 171 172// Treat misc copies as a move. 173def : InstRW<[WriteMove], (instrs COPY)>; 174 175//////////////////////////////////////////////////////////////////////////////// 176// Idioms that clear a register, like xorps %xmm0, %xmm0. 177// These can often bypass execution ports completely. 178//////////////////////////////////////////////////////////////////////////////// 179 180def : WriteRes<WriteZero, []>; 181 182//////////////////////////////////////////////////////////////////////////////// 183// Branches don't produce values, so they have no latency, but they still 184// consume resources. Indirect branches can fold loads. 185//////////////////////////////////////////////////////////////////////////////// 186 187defm : AtomWriteResPair<WriteJump, [AtomPort1], [AtomPort1]>; 188 189//////////////////////////////////////////////////////////////////////////////// 190// Special case scheduling classes. 191//////////////////////////////////////////////////////////////////////////////// 192 193def : WriteRes<WriteSystem, [AtomPort01]> { let Latency = 100; } 194def : WriteRes<WriteMicrocoded, [AtomPort01]> { let Latency = 100; } 195def : WriteRes<WriteFence, [AtomPort0]>; 196 197// Nops don't have dependencies, so there's no actual latency, but we set this 198// to '1' to tell the scheduler that the nop uses an ALU slot for a cycle. 199def : WriteRes<WriteNop, [AtomPort01]>; 200 201//////////////////////////////////////////////////////////////////////////////// 202// Floating point. This covers both scalar and vector operations. 203//////////////////////////////////////////////////////////////////////////////// 204 205defm : X86WriteRes<WriteFLD0, [AtomPort01], 1, [1], 1>; 206defm : X86WriteRes<WriteFLD1, [AtomPort01], 6, [6], 1>; 207def : WriteRes<WriteFLoad, [AtomPort0]>; 208def : WriteRes<WriteFLoadX, [AtomPort0]>; 209defm : X86WriteResUnsupported<WriteFLoadY>; 210defm : X86WriteResUnsupported<WriteFMaskedLoad>; 211defm : X86WriteResUnsupported<WriteFMaskedLoadY>; 212 213def : WriteRes<WriteFStore, [AtomPort0]>; 214def : WriteRes<WriteFStoreX, [AtomPort0]>; 215defm : X86WriteResUnsupported<WriteFStoreY>; 216def : WriteRes<WriteFStoreNT, [AtomPort0]>; 217def : WriteRes<WriteFStoreNTX, [AtomPort0]>; 218defm : X86WriteResUnsupported<WriteFStoreNTY>; 219defm : X86WriteResUnsupported<WriteFMaskedStore32>; 220defm : X86WriteResUnsupported<WriteFMaskedStore32Y>; 221defm : X86WriteResUnsupported<WriteFMaskedStore64>; 222defm : X86WriteResUnsupported<WriteFMaskedStore64Y>; 223 224def : WriteRes<WriteFMove, [AtomPort01]>; 225def : WriteRes<WriteFMoveX, [AtomPort01]>; 226defm : X86WriteResUnsupported<WriteFMoveY>; 227 228defm : X86WriteRes<WriteEMMS, [AtomPort01], 5, [5], 1>; 229 230defm : AtomWriteResPair<WriteFAdd, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>; 231defm : AtomWriteResPair<WriteFAddX, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>; 232defm : X86WriteResPairUnsupported<WriteFAddY>; 233defm : X86WriteResPairUnsupported<WriteFAddZ>; 234defm : AtomWriteResPair<WriteFAdd64, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>; 235defm : AtomWriteResPair<WriteFAdd64X, [AtomPort01], [AtomPort01], 6, 7, [6], [7]>; 236defm : X86WriteResPairUnsupported<WriteFAdd64Y>; 237defm : X86WriteResPairUnsupported<WriteFAdd64Z>; 238defm : AtomWriteResPair<WriteFCmp, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>; 239defm : AtomWriteResPair<WriteFCmpX, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>; 240defm : X86WriteResPairUnsupported<WriteFCmpY>; 241defm : X86WriteResPairUnsupported<WriteFCmpZ>; 242defm : AtomWriteResPair<WriteFCmp64, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>; 243defm : AtomWriteResPair<WriteFCmp64X, [AtomPort01], [AtomPort01], 6, 7, [6], [7]>; 244defm : X86WriteResPairUnsupported<WriteFCmp64Y>; 245defm : X86WriteResPairUnsupported<WriteFCmp64Z>; 246defm : AtomWriteResPair<WriteFCom, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>; 247defm : AtomWriteResPair<WriteFComX, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>; 248defm : AtomWriteResPair<WriteFMul, [AtomPort0], [AtomPort0], 4, 4, [4], [4]>; 249defm : AtomWriteResPair<WriteFMulX, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>; 250defm : X86WriteResPairUnsupported<WriteFMulY>; 251defm : X86WriteResPairUnsupported<WriteFMulZ>; 252defm : AtomWriteResPair<WriteFMul64, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>; 253defm : AtomWriteResPair<WriteFMul64X, [AtomPort01], [AtomPort01], 9, 10, [9], [10]>; 254defm : X86WriteResPairUnsupported<WriteFMul64Y>; 255defm : X86WriteResPairUnsupported<WriteFMul64Z>; 256defm : AtomWriteResPair<WriteFRcp, [AtomPort0], [AtomPort0], 4, 4, [4], [4]>; 257defm : AtomWriteResPair<WriteFRcpX, [AtomPort01], [AtomPort01], 9, 10, [9], [10]>; 258defm : X86WriteResPairUnsupported<WriteFRcpY>; 259defm : X86WriteResPairUnsupported<WriteFRcpZ>; 260defm : AtomWriteResPair<WriteFRsqrt, [AtomPort0], [AtomPort0], 4, 4, [4], [4]>; 261defm : AtomWriteResPair<WriteFRsqrtX, [AtomPort01], [AtomPort01], 9, 10, [9], [10]>; 262defm : X86WriteResPairUnsupported<WriteFRsqrtY>; 263defm : X86WriteResPairUnsupported<WriteFRsqrtZ>; 264defm : AtomWriteResPair<WriteFDiv, [AtomPort01], [AtomPort01], 34, 34, [34], [34]>; 265defm : AtomWriteResPair<WriteFDivX, [AtomPort01], [AtomPort01], 70, 70, [70], [70]>; 266defm : X86WriteResPairUnsupported<WriteFDivY>; 267defm : X86WriteResPairUnsupported<WriteFDivZ>; 268defm : AtomWriteResPair<WriteFDiv64, [AtomPort01], [AtomPort01], 62, 62, [62], [62]>; 269defm : AtomWriteResPair<WriteFDiv64X, [AtomPort01], [AtomPort01],125,125,[125],[125]>; 270defm : X86WriteResPairUnsupported<WriteFDiv64Y>; 271defm : X86WriteResPairUnsupported<WriteFDiv64Z>; 272defm : AtomWriteResPair<WriteFSqrt, [AtomPort01], [AtomPort01], 34, 34, [34], [34]>; 273defm : AtomWriteResPair<WriteFSqrtX, [AtomPort01], [AtomPort01], 70, 70, [70], [70]>; 274defm : X86WriteResPairUnsupported<WriteFSqrtY>; 275defm : X86WriteResPairUnsupported<WriteFSqrtZ>; 276defm : AtomWriteResPair<WriteFSqrt64, [AtomPort01], [AtomPort01], 62, 62, [62], [62]>; 277defm : AtomWriteResPair<WriteFSqrt64X, [AtomPort01], [AtomPort01],125,125,[125],[125]>; 278defm : X86WriteResPairUnsupported<WriteFSqrt64Y>; 279defm : X86WriteResPairUnsupported<WriteFSqrt64Z>; 280defm : AtomWriteResPair<WriteFSqrt80, [AtomPort01], [AtomPort01], 71, 71, [71], [71]>; 281defm : AtomWriteResPair<WriteFSign, [AtomPort1], [AtomPort1]>; 282defm : AtomWriteResPair<WriteFRnd, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>; 283defm : X86WriteResPairUnsupported<WriteFRndY>; 284defm : X86WriteResPairUnsupported<WriteFRndZ>; 285defm : AtomWriteResPair<WriteFLogic, [AtomPort01], [AtomPort0]>; 286defm : X86WriteResPairUnsupported<WriteFLogicY>; 287defm : X86WriteResPairUnsupported<WriteFLogicZ>; 288defm : AtomWriteResPair<WriteFTest, [AtomPort01], [AtomPort0]>; 289defm : X86WriteResPairUnsupported<WriteFTestY>; 290defm : X86WriteResPairUnsupported<WriteFTestZ>; 291defm : AtomWriteResPair<WriteFShuffle, [AtomPort0], [AtomPort0]>; 292defm : X86WriteResPairUnsupported<WriteFShuffleY>; 293defm : X86WriteResPairUnsupported<WriteFShuffleZ>; 294defm : X86WriteResPairUnsupported<WriteFVarShuffle>; 295defm : X86WriteResPairUnsupported<WriteFVarShuffleY>; 296defm : X86WriteResPairUnsupported<WriteFVarShuffleZ>; 297defm : X86WriteResPairUnsupported<WriteFMA>; 298defm : X86WriteResPairUnsupported<WriteFMAX>; 299defm : X86WriteResPairUnsupported<WriteFMAY>; 300defm : X86WriteResPairUnsupported<WriteFMAZ>; 301defm : X86WriteResPairUnsupported<WriteDPPD>; 302defm : X86WriteResPairUnsupported<WriteDPPS>; 303defm : X86WriteResPairUnsupported<WriteDPPSY>; 304defm : X86WriteResPairUnsupported<WriteDPPSZ>; 305defm : X86WriteResPairUnsupported<WriteFBlend>; 306defm : X86WriteResPairUnsupported<WriteFBlendY>; 307defm : X86WriteResPairUnsupported<WriteFBlendZ>; 308defm : X86WriteResPairUnsupported<WriteFVarBlend>; 309defm : X86WriteResPairUnsupported<WriteFVarBlendY>; 310defm : X86WriteResPairUnsupported<WriteFVarBlendZ>; 311defm : X86WriteResPairUnsupported<WriteFShuffle256>; 312defm : X86WriteResPairUnsupported<WriteFVarShuffle256>; 313 314//////////////////////////////////////////////////////////////////////////////// 315// Conversions. 316//////////////////////////////////////////////////////////////////////////////// 317 318defm : AtomWriteResPair<WriteCvtSS2I, [AtomPort01], [AtomPort01], 8, 9, [8], [9]>; 319defm : AtomWriteResPair<WriteCvtPS2I, [AtomPort01], [AtomPort01], 6, 7, [6], [7]>; 320defm : X86WriteResPairUnsupported<WriteCvtPS2IY>; 321defm : X86WriteResPairUnsupported<WriteCvtPS2IZ>; 322defm : AtomWriteResPair<WriteCvtSD2I, [AtomPort01], [AtomPort01], 8, 9, [8], [9]>; 323defm : AtomWriteResPair<WriteCvtPD2I, [AtomPort01], [AtomPort01], 7, 8, [7], [8]>; 324defm : X86WriteResPairUnsupported<WriteCvtPD2IY>; 325defm : X86WriteResPairUnsupported<WriteCvtPD2IZ>; 326 327defm : AtomWriteResPair<WriteCvtI2SS, [AtomPort01], [AtomPort01], 6, 7, [6], [7]>; 328defm : AtomWriteResPair<WriteCvtI2PS, [AtomPort01], [AtomPort01], 6, 7, [6], [7]>; 329defm : X86WriteResPairUnsupported<WriteCvtI2PSY>; 330defm : X86WriteResPairUnsupported<WriteCvtI2PSZ>; 331defm : AtomWriteResPair<WriteCvtI2SD, [AtomPort01], [AtomPort01], 6, 7, [6], [7]>; 332defm : AtomWriteResPair<WriteCvtI2PD, [AtomPort01], [AtomPort01], 7, 8, [7], [8]>; 333defm : X86WriteResPairUnsupported<WriteCvtI2PDY>; 334defm : X86WriteResPairUnsupported<WriteCvtI2PDZ>; 335 336defm : AtomWriteResPair<WriteCvtSS2SD, [AtomPort01], [AtomPort01], 6, 7, [6], [7]>; 337defm : AtomWriteResPair<WriteCvtPS2PD, [AtomPort01], [AtomPort01], 7, 8, [7], [8]>; 338defm : X86WriteResPairUnsupported<WriteCvtPS2PDY>; 339defm : X86WriteResPairUnsupported<WriteCvtPS2PDZ>; 340defm : AtomWriteResPair<WriteCvtSD2SS, [AtomPort01], [AtomPort01], 6, 7, [6], [7]>; 341defm : AtomWriteResPair<WriteCvtPD2PS, [AtomPort01], [AtomPort01], 7, 8, [7], [8]>; 342defm : X86WriteResPairUnsupported<WriteCvtPD2PSY>; 343defm : X86WriteResPairUnsupported<WriteCvtPD2PSZ>; 344 345defm : X86WriteResPairUnsupported<WriteCvtPH2PS>; 346defm : X86WriteResPairUnsupported<WriteCvtPH2PSY>; 347defm : X86WriteResPairUnsupported<WriteCvtPH2PSZ>; 348defm : X86WriteResUnsupported<WriteCvtPS2PH>; 349defm : X86WriteResUnsupported<WriteCvtPS2PHSt>; 350defm : X86WriteResUnsupported<WriteCvtPS2PHY>; 351defm : X86WriteResUnsupported<WriteCvtPS2PHZ>; 352defm : X86WriteResUnsupported<WriteCvtPS2PHYSt>; 353defm : X86WriteResUnsupported<WriteCvtPS2PHZSt>; 354 355//////////////////////////////////////////////////////////////////////////////// 356// Vector integer operations. 357//////////////////////////////////////////////////////////////////////////////// 358 359def : WriteRes<WriteVecLoad, [AtomPort0]>; 360def : WriteRes<WriteVecLoadX, [AtomPort0]>; 361defm : X86WriteResUnsupported<WriteVecLoadY>; 362def : WriteRes<WriteVecLoadNT, [AtomPort0]>; 363defm : X86WriteResUnsupported<WriteVecLoadNTY>; 364defm : X86WriteResUnsupported<WriteVecMaskedLoad>; 365defm : X86WriteResUnsupported<WriteVecMaskedLoadY>; 366 367def : WriteRes<WriteVecStore, [AtomPort0]>; 368def : WriteRes<WriteVecStoreX, [AtomPort0]>; 369defm : X86WriteResUnsupported<WriteVecStoreY>; 370def : WriteRes<WriteVecStoreNT, [AtomPort0]>; 371defm : X86WriteResUnsupported<WriteVecStoreNTY>; 372defm : X86WriteResUnsupported<WriteVecMaskedStore32>; 373defm : X86WriteResUnsupported<WriteVecMaskedStore64>; 374defm : X86WriteResUnsupported<WriteVecMaskedStore32Y>; 375defm : X86WriteResUnsupported<WriteVecMaskedStore64Y>; 376 377def : WriteRes<WriteVecMove, [AtomPort0]>; 378def : WriteRes<WriteVecMoveX, [AtomPort01]>; 379defm : X86WriteResUnsupported<WriteVecMoveY>; 380defm : X86WriteRes<WriteVecMoveToGpr, [AtomPort0], 3, [3], 1>; 381defm : X86WriteRes<WriteVecMoveFromGpr, [AtomPort0], 1, [1], 1>; 382 383defm : AtomWriteResPair<WriteVecALU, [AtomPort01], [AtomPort0], 1, 1>; 384defm : AtomWriteResPair<WriteVecALUX, [AtomPort01], [AtomPort0], 1, 1>; 385defm : X86WriteResPairUnsupported<WriteVecALUY>; 386defm : X86WriteResPairUnsupported<WriteVecALUZ>; 387defm : AtomWriteResPair<WriteVecLogic, [AtomPort01], [AtomPort0], 1, 1>; 388defm : AtomWriteResPair<WriteVecLogicX, [AtomPort01], [AtomPort0], 1, 1>; 389defm : X86WriteResPairUnsupported<WriteVecLogicY>; 390defm : X86WriteResPairUnsupported<WriteVecLogicZ>; 391defm : AtomWriteResPair<WriteVecTest, [AtomPort01], [AtomPort0], 1, 1>; 392defm : X86WriteResPairUnsupported<WriteVecTestY>; 393defm : X86WriteResPairUnsupported<WriteVecTestZ>; 394defm : AtomWriteResPair<WriteVecShift, [AtomPort01], [AtomPort01], 2, 3, [2], [3]>; 395defm : AtomWriteResPair<WriteVecShiftX, [AtomPort01], [AtomPort01], 2, 3, [2], [3]>; 396defm : X86WriteResPairUnsupported<WriteVecShiftY>; 397defm : X86WriteResPairUnsupported<WriteVecShiftZ>; 398defm : AtomWriteResPair<WriteVecShiftImm, [AtomPort01], [AtomPort01], 1, 1, [1], [1]>; 399defm : AtomWriteResPair<WriteVecShiftImmX, [AtomPort01], [AtomPort01], 1, 1, [1], [1]>; 400defm : X86WriteResPairUnsupported<WriteVecShiftImmY>; 401defm : X86WriteResPairUnsupported<WriteVecShiftImmZ>; 402defm : AtomWriteResPair<WriteVecIMul, [AtomPort0], [AtomPort0], 4, 4, [4], [4]>; 403defm : AtomWriteResPair<WriteVecIMulX, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>; 404defm : X86WriteResPairUnsupported<WriteVecIMulY>; 405defm : X86WriteResPairUnsupported<WriteVecIMulZ>; 406defm : X86WriteResPairUnsupported<WritePMULLD>; 407defm : X86WriteResPairUnsupported<WritePMULLDY>; 408defm : X86WriteResPairUnsupported<WritePMULLDZ>; 409defm : X86WriteResPairUnsupported<WritePHMINPOS>; 410defm : X86WriteResPairUnsupported<WriteMPSAD>; 411defm : X86WriteResPairUnsupported<WriteMPSADY>; 412defm : X86WriteResPairUnsupported<WriteMPSADZ>; 413defm : AtomWriteResPair<WritePSADBW, [AtomPort01], [AtomPort01], 4, 4, [4], [4]>; 414defm : AtomWriteResPair<WritePSADBWX, [AtomPort0], [AtomPort0], 5, 5, [5], [5]>; 415defm : X86WriteResPairUnsupported<WritePSADBWY>; 416defm : X86WriteResPairUnsupported<WritePSADBWZ>; 417defm : AtomWriteResPair<WriteShuffle, [AtomPort0], [AtomPort0], 1, 1>; 418defm : AtomWriteResPair<WriteShuffleX, [AtomPort0], [AtomPort0], 1, 1>; 419defm : X86WriteResPairUnsupported<WriteShuffleY>; 420defm : X86WriteResPairUnsupported<WriteShuffleZ>; 421defm : AtomWriteResPair<WriteVarShuffle, [AtomPort0], [AtomPort0], 1, 1>; 422defm : AtomWriteResPair<WriteVarShuffleX, [AtomPort01], [AtomPort01], 4, 5, [4], [5]>; 423defm : X86WriteResPairUnsupported<WriteVarShuffleY>; 424defm : X86WriteResPairUnsupported<WriteVarShuffleZ>; 425defm : X86WriteResPairUnsupported<WriteBlend>; 426defm : X86WriteResPairUnsupported<WriteBlendY>; 427defm : X86WriteResPairUnsupported<WriteBlendZ>; 428defm : X86WriteResPairUnsupported<WriteVarBlend>; 429defm : X86WriteResPairUnsupported<WriteVarBlendY>; 430defm : X86WriteResPairUnsupported<WriteVarBlendZ>; 431defm : X86WriteResPairUnsupported<WriteShuffle256>; 432defm : X86WriteResPairUnsupported<WriteVarShuffle256>; 433defm : X86WriteResPairUnsupported<WriteVarVecShift>; 434defm : X86WriteResPairUnsupported<WriteVarVecShiftY>; 435defm : X86WriteResPairUnsupported<WriteVarVecShiftZ>; 436 437//////////////////////////////////////////////////////////////////////////////// 438// Vector insert/extract operations. 439//////////////////////////////////////////////////////////////////////////////// 440 441defm : AtomWriteResPair<WriteVecInsert, [AtomPort0], [AtomPort0], 1, 1>; 442def : WriteRes<WriteVecExtract, [AtomPort0]>; 443def : WriteRes<WriteVecExtractSt, [AtomPort0]>; 444 445//////////////////////////////////////////////////////////////////////////////// 446// SSE42 String instructions. 447//////////////////////////////////////////////////////////////////////////////// 448 449defm : X86WriteResPairUnsupported<WritePCmpIStrI>; 450defm : X86WriteResPairUnsupported<WritePCmpIStrM>; 451defm : X86WriteResPairUnsupported<WritePCmpEStrI>; 452defm : X86WriteResPairUnsupported<WritePCmpEStrM>; 453 454//////////////////////////////////////////////////////////////////////////////// 455// MOVMSK Instructions. 456//////////////////////////////////////////////////////////////////////////////// 457 458def : WriteRes<WriteFMOVMSK, [AtomPort0]> { let Latency = 3; let ResourceCycles = [3]; } 459def : WriteRes<WriteVecMOVMSK, [AtomPort0]> { let Latency = 3; let ResourceCycles = [3]; } 460defm : X86WriteResUnsupported<WriteVecMOVMSKY>; 461def : WriteRes<WriteMMXMOVMSK, [AtomPort0]> { let Latency = 3; let ResourceCycles = [3]; } 462 463//////////////////////////////////////////////////////////////////////////////// 464// AES instructions. 465//////////////////////////////////////////////////////////////////////////////// 466 467defm : X86WriteResPairUnsupported<WriteAESIMC>; 468defm : X86WriteResPairUnsupported<WriteAESKeyGen>; 469defm : X86WriteResPairUnsupported<WriteAESDecEnc>; 470 471//////////////////////////////////////////////////////////////////////////////// 472// Horizontal add/sub instructions. 473//////////////////////////////////////////////////////////////////////////////// 474 475defm : AtomWriteResPair<WriteFHAdd, [AtomPort01], [AtomPort01], 8, 9, [8], [9]>; 476defm : AtomWriteResPair<WriteFHAddY, [AtomPort01], [AtomPort01], 8, 9, [8], [9]>; 477defm : AtomWriteResPair<WritePHAdd, [AtomPort01], [AtomPort01], 3, 4, [3], [4]>; 478defm : AtomWriteResPair<WritePHAddX, [AtomPort01], [AtomPort01], 7, 8, [7], [8]>; 479defm : AtomWriteResPair<WritePHAddY, [AtomPort01], [AtomPort01], 7, 8, [7], [8]>; 480 481//////////////////////////////////////////////////////////////////////////////// 482// Carry-less multiplication instructions. 483//////////////////////////////////////////////////////////////////////////////// 484 485defm : X86WriteResPairUnsupported<WriteCLMul>; 486 487//////////////////////////////////////////////////////////////////////////////// 488// Load/store MXCSR. 489//////////////////////////////////////////////////////////////////////////////// 490 491def : WriteRes<WriteLDMXCSR, [AtomPort01]> { let Latency = 5; let ResourceCycles = [5]; } 492def : WriteRes<WriteSTMXCSR, [AtomPort01]> { let Latency = 15; let ResourceCycles = [15]; } 493 494//////////////////////////////////////////////////////////////////////////////// 495// Special Cases. 496//////////////////////////////////////////////////////////////////////////////// 497 498// Port0 499def AtomWrite0_1 : SchedWriteRes<[AtomPort0]> { 500 let Latency = 1; 501 let ResourceCycles = [1]; 502} 503def : InstRW<[AtomWrite0_1], (instrs FXAM, LD_Frr, 504 MOVSX64rr32)>; 505def : SchedAlias<WriteALURMW, AtomWrite0_1>; 506def : SchedAlias<WriteADCRMW, AtomWrite0_1>; 507def : InstRW<[AtomWrite0_1], (instregex "(RCL|RCR|ROL|ROR|SAR|SHL|SHR)(8|16|32|64)m", 508 "MOV(S|Z)X(32|64)rr(8|8_NOREX|16)")>; 509 510// Port1 511def AtomWrite1_1 : SchedWriteRes<[AtomPort1]> { 512 let Latency = 1; 513 let ResourceCycles = [1]; 514} 515def : InstRW<[AtomWrite1_1], (instrs FCOMPP)>; 516def : InstRW<[AtomWrite1_1], (instregex "UCOM_F(P|PP)?r")>; 517 518def AtomWrite1_5 : SchedWriteRes<[AtomPort1]> { 519 let Latency = 5; 520 let ResourceCycles = [5]; 521} 522def : InstRW<[AtomWrite1_5], (instrs MMX_CVTPI2PSirr, MMX_CVTPI2PSirm, 523 MMX_CVTPS2PIirr, MMX_CVTTPS2PIirr)>; 524 525// Port0 and Port1 526def AtomWrite0_1_1 : SchedWriteRes<[AtomPort0, AtomPort1]> { 527 let Latency = 1; 528 let ResourceCycles = [1, 1]; 529} 530def : InstRW<[AtomWrite0_1_1], (instrs POP32r, POP64r, 531 POP16rmr, POP32rmr, POP64rmr, 532 PUSH16r, PUSH32r, PUSH64r, 533 PUSHi16, PUSHi32, 534 PUSH16rmr, PUSH32rmr, PUSH64rmr, 535 PUSH16i8, PUSH32i8, PUSH64i8, PUSH64i32, 536 XCH_F)>; 537def : InstRW<[AtomWrite0_1_1], (instregex "RETI(L|Q|W)$", 538 "IRET(16|32|64)?")>; 539 540def AtomWrite0_1_5 : SchedWriteRes<[AtomPort0, AtomPort1]> { 541 let Latency = 5; 542 let ResourceCycles = [5, 5]; 543} 544def : InstRW<[AtomWrite0_1_5], (instrs MMX_CVTPS2PIirm, MMX_CVTTPS2PIirm)>; 545def : InstRW<[AtomWrite0_1_5], (instregex "ILD_F(16|32|64)")>; 546 547// Port0 or Port1 548def AtomWrite01_1 : SchedWriteRes<[AtomPort01]> { 549 let Latency = 1; 550 let ResourceCycles = [1]; 551} 552def : InstRW<[AtomWrite01_1], (instrs FDECSTP, FFREE, FFREEP, FINCSTP, WAIT, 553 LFENCE, 554 STOSB, STOSL, STOSQ, STOSW, 555 MOVSSrr, MOVSSrr_REV, 556 PSLLDQri, PSRLDQri)>; 557def : InstRW<[AtomWrite01_1], (instregex "MMX_PACK(SSDW|SSWB|USWB)irr", 558 "MMX_PUNPCKH(BW|DQ|WD)irr")>; 559 560def AtomWrite01_2 : SchedWriteRes<[AtomPort01]> { 561 let Latency = 2; 562 let ResourceCycles = [2]; 563} 564def : InstRW<[AtomWrite01_2], (instrs LEAVE, LEAVE64, POP16r, 565 PUSH16rmm, PUSH32rmm, PUSH64rmm, 566 LODSB, LODSL, LODSQ, LODSW, 567 SCASB, SCASL, SCASQ, SCASW)>; 568def : InstRW<[AtomWrite01_2], (instregex "PUSH(CS|DS|ES|FS|GS|SS)(16|32|64)", 569 "(ST|ISTT)_F(P)?(16|32|64)?(m|rr)", 570 "MMX_P(ADD|SUB)Qirr", 571 "MOV(S|Z)X16rr8", 572 "MOV(UPS|UPD|DQU)mr", 573 "MASKMOVDQU(64)?", 574 "P(ADD|SUB)Qrr")>; 575def : SchedAlias<WriteBitTestSetImmRMW, AtomWrite01_2>; 576 577def AtomWrite01_3 : SchedWriteRes<[AtomPort01]> { 578 let Latency = 3; 579 let ResourceCycles = [3]; 580} 581def : InstRW<[AtomWrite01_3], (instrs CLD, LDDQUrm, 582 CMPSB, CMPSL, CMPSQ, CMPSW, 583 MOVSB, MOVSL, MOVSQ, MOVSW, 584 POP16rmm, POP32rmm, POP64rmm)>; 585def : InstRW<[AtomWrite01_3], (instregex "XADD(8|16|32|64)rm", 586 "XCHG(8|16|32|64)rm", 587 "PH(ADD|SUB)Drr", 588 "MOV(S|Z)X16rm8", 589 "MMX_P(ADD|SUB)Qirm", 590 "MOV(UPS|UPD|DQU)rm", 591 "P(ADD|SUB)Qrm")>; 592 593def AtomWrite01_4 : SchedWriteRes<[AtomPort01]> { 594 let Latency = 4; 595 let ResourceCycles = [4]; 596} 597def : InstRW<[AtomWrite01_4], (instrs CBW, CWD, CWDE, CDQ, CDQE, CQO, 598 JCXZ, JECXZ, JRCXZ, 599 LD_F80m)>; 600def : InstRW<[AtomWrite01_4], (instregex "PH(ADD|SUB)Drm", 601 "(MMX_)?PEXTRWrr(_REV)?")>; 602 603def AtomWrite01_5 : SchedWriteRes<[AtomPort01]> { 604 let Latency = 5; 605 let ResourceCycles = [5]; 606} 607def : InstRW<[AtomWrite01_5], (instrs FLDCW16m, ST_FP80m)>; 608def : InstRW<[AtomWrite01_5], (instregex "MMX_PH(ADD|SUB)S?Wrr")>; 609 610def AtomWrite01_6 : SchedWriteRes<[AtomPort01]> { 611 let Latency = 6; 612 let ResourceCycles = [6]; 613} 614def : InstRW<[AtomWrite01_6], (instrs CMPXCHG8rm, INTO, XLAT, 615 SHLD16rrCL, SHRD16rrCL, 616 SHLD16rri8, SHRD16rri8, 617 SHLD16mrCL, SHRD16mrCL, 618 SHLD16mri8, SHRD16mri8)>; 619def : InstRW<[AtomWrite01_6], (instregex "IST_F(P)?(16|32|64)?m", 620 "MMX_PH(ADD|SUB)S?Wrm")>; 621 622def AtomWrite01_7 : SchedWriteRes<[AtomPort01]> { 623 let Latency = 7; 624 let ResourceCycles = [7]; 625} 626def : InstRW<[AtomWrite01_7], (instrs AAD8i8)>; 627 628def AtomWrite01_8 : SchedWriteRes<[AtomPort01]> { 629 let Latency = 8; 630 let ResourceCycles = [8]; 631} 632def : InstRW<[AtomWrite01_8], (instrs LOOPE, 633 PUSHA16, PUSHA32, 634 SHLD64rrCL, SHRD64rrCL, 635 FNSTCW16m)>; 636 637def AtomWrite01_9 : SchedWriteRes<[AtomPort01]> { 638 let Latency = 9; 639 let ResourceCycles = [9]; 640} 641def : InstRW<[AtomWrite01_9], (instrs POPA16, POPA32, 642 PUSHF16, PUSHF32, PUSHF64, 643 SHLD64mrCL, SHRD64mrCL, 644 SHLD64mri8, SHRD64mri8, 645 SHLD64rri8, SHRD64rri8, 646 CMPXCHG8rr)>; 647def : InstRW<[AtomWrite01_9], (instregex "(U)?COM_FI", "TST_F", 648 "(U)?COMIS(D|S)rr", 649 "CVT(T)?SS2SI64rr(_Int)?")>; 650 651def AtomWrite01_10 : SchedWriteRes<[AtomPort01]> { 652 let Latency = 10; 653 let ResourceCycles = [10]; 654} 655def : SchedAlias<WriteFLDC, AtomWrite01_10>; 656def : InstRW<[AtomWrite01_10], (instregex "(U)?COMIS(D|S)rm", 657 "CVT(T)?SS2SI64rm(_Int)?")>; 658 659def AtomWrite01_11 : SchedWriteRes<[AtomPort01]> { 660 let Latency = 11; 661 let ResourceCycles = [11]; 662} 663def : InstRW<[AtomWrite01_11], (instrs BOUNDS16rm, BOUNDS32rm)>; 664def : SchedAlias<WriteBitTestSetRegRMW, AtomWrite01_11>; 665 666def AtomWrite01_13 : SchedWriteRes<[AtomPort01]> { 667 let Latency = 13; 668 let ResourceCycles = [13]; 669} 670def : InstRW<[AtomWrite01_13], (instrs AAA, AAS)>; 671 672def AtomWrite01_14 : SchedWriteRes<[AtomPort01]> { 673 let Latency = 14; 674 let ResourceCycles = [14]; 675} 676def : InstRW<[AtomWrite01_14], (instrs CMPXCHG16rm, CMPXCHG32rm, CMPXCHG64rm)>; 677 678def AtomWrite01_17 : SchedWriteRes<[AtomPort01]> { 679 let Latency = 17; 680 let ResourceCycles = [17]; 681} 682def : InstRW<[AtomWrite01_17], (instrs LOOPNE, PAUSE)>; 683 684def AtomWrite01_18 : SchedWriteRes<[AtomPort01]> { 685 let Latency = 18; 686 let ResourceCycles = [18]; 687} 688def : InstRW<[AtomWrite01_18], (instrs CMPXCHG8B, DAA, LOOP)>; 689 690def AtomWrite01_20 : SchedWriteRes<[AtomPort01]> { 691 let Latency = 20; 692 let ResourceCycles = [20]; 693} 694def : InstRW<[AtomWrite01_20], (instrs DAS)>; 695 696def AtomWrite01_21 : SchedWriteRes<[AtomPort01]> { 697 let Latency = 21; 698 let ResourceCycles = [21]; 699} 700def : InstRW<[AtomWrite01_21], (instrs AAM8i8, STD)>; 701 702def AtomWrite01_22 : SchedWriteRes<[AtomPort01]> { 703 let Latency = 22; 704 let ResourceCycles = [22]; 705} 706def : InstRW<[AtomWrite01_22], (instrs CMPXCHG16B)>; 707 708def AtomWrite01_23 : SchedWriteRes<[AtomPort01]> { 709 let Latency = 23; 710 let ResourceCycles = [23]; 711} 712def : InstRW<[AtomWrite01_23], (instrs ARPL16mr, ARPL16rr)>; 713 714def AtomWrite01_25 : SchedWriteRes<[AtomPort01]> { 715 let Latency = 25; 716 let ResourceCycles = [25]; 717} 718def : InstRW<[AtomWrite01_25], (instrs FNCLEX, FXTRACT)>; 719 720def AtomWrite01_26 : SchedWriteRes<[AtomPort01]> { 721 let Latency = 26; 722 let ResourceCycles = [26]; 723} 724def : InstRW<[AtomWrite01_26], (instrs POPF32, POPF64)>; 725 726def AtomWrite01_29 : SchedWriteRes<[AtomPort01]> { 727 let Latency = 29; 728 let ResourceCycles = [29]; 729} 730def : InstRW<[AtomWrite01_29], (instregex "POP(DS|ES|FS|GS)(16|32|64)")>; 731 732def AtomWrite01_30 : SchedWriteRes<[AtomPort01]> { 733 let Latency = 30; 734 let ResourceCycles = [30]; 735} 736def : InstRW<[AtomWrite01_30], (instrs RDTSC, RDTSCP)>; 737 738def AtomWrite01_32 : SchedWriteRes<[AtomPort01]> { 739 let Latency = 32; 740 let ResourceCycles = [32]; 741} 742def : InstRW<[AtomWrite01_32], (instrs ENTER, POPF16)>; 743 744def AtomWrite01_45 : SchedWriteRes<[AtomPort01]> { 745 let Latency = 45; 746 let ResourceCycles = [45]; 747} 748def : InstRW<[AtomWrite01_45], (instrs MONITOR32rrr, MONITOR64rrr)>; 749 750def AtomWrite01_46 : SchedWriteRes<[AtomPort01]> { 751 let Latency = 46; 752 let ResourceCycles = [46]; 753} 754def : InstRW<[AtomWrite01_46], (instrs FRNDINT, MWAITrr, RDPMC)>; 755 756def AtomWrite01_48 : SchedWriteRes<[AtomPort01]> { 757 let Latency = 48; 758 let ResourceCycles = [48]; 759} 760def : InstRW<[AtomWrite01_48], (instrs POPSS16, POPSS32)>; 761 762def AtomWrite01_55 : SchedWriteRes<[AtomPort01]> { 763 let Latency = 55; 764 let ResourceCycles = [55]; 765} 766def : InstRW<[AtomWrite01_55], (instrs FPREM)>; 767 768def AtomWrite01_59 : SchedWriteRes<[AtomPort01]> { 769 let Latency = 59; 770 let ResourceCycles = [59]; 771} 772def : InstRW<[AtomWrite01_59], (instrs INSB, INSL, INSW)>; 773 774def AtomWrite01_63 : SchedWriteRes<[AtomPort01]> { 775 let Latency = 63; 776 let ResourceCycles = [63]; 777} 778def : InstRW<[AtomWrite01_63], (instrs FNINIT)>; 779 780def AtomWrite01_68 : SchedWriteRes<[AtomPort01]> { 781 let Latency = 68; 782 let ResourceCycles = [68]; 783} 784def : InstRW<[AtomWrite01_68], (instrs OUT8rr, OUT16rr, OUT32rr)>; 785 786def AtomWrite01_71 : SchedWriteRes<[AtomPort01]> { 787 let Latency = 71; 788 let ResourceCycles = [71]; 789} 790def : InstRW<[AtomWrite01_71], (instrs FPREM1, 791 INVLPG, INVLPGA32, INVLPGA64)>; 792 793def AtomWrite01_72 : SchedWriteRes<[AtomPort01]> { 794 let Latency = 72; 795 let ResourceCycles = [72]; 796} 797def : InstRW<[AtomWrite01_72], (instrs OUT8ir, OUT16ir, OUT32ir)>; 798 799def AtomWrite01_74 : SchedWriteRes<[AtomPort01]> { 800 let Latency = 74; 801 let ResourceCycles = [74]; 802} 803def : InstRW<[AtomWrite01_74], (instrs OUTSB, OUTSL, OUTSW)>; 804 805def AtomWrite01_77 : SchedWriteRes<[AtomPort01]> { 806 let Latency = 77; 807 let ResourceCycles = [77]; 808} 809def : InstRW<[AtomWrite01_77], (instrs FSCALE)>; 810 811def AtomWrite01_78 : SchedWriteRes<[AtomPort01]> { 812 let Latency = 78; 813 let ResourceCycles = [78]; 814} 815def : InstRW<[AtomWrite01_78], (instrs RDMSR)>; 816 817def AtomWrite01_79 : SchedWriteRes<[AtomPort01]> { 818 let Latency = 79; 819 let ResourceCycles = [79]; 820} 821def : InstRW<[AtomWrite01_79], (instregex "RET(L|Q|W)?$", 822 "LRETI?(L|Q|W)")>; 823 824def AtomWrite01_92 : SchedWriteRes<[AtomPort01]> { 825 let Latency = 92; 826 let ResourceCycles = [92]; 827} 828def : InstRW<[AtomWrite01_92], (instrs IN8ri, IN16ri, IN32ri)>; 829 830def AtomWrite01_94 : SchedWriteRes<[AtomPort01]> { 831 let Latency = 94; 832 let ResourceCycles = [94]; 833} 834def : InstRW<[AtomWrite01_94], (instrs IN8rr, IN16rr, IN32rr)>; 835 836def AtomWrite01_99 : SchedWriteRes<[AtomPort01]> { 837 let Latency = 99; 838 let ResourceCycles = [99]; 839} 840def : InstRW<[AtomWrite01_99], (instrs F2XM1)>; 841 842def AtomWrite01_121 : SchedWriteRes<[AtomPort01]> { 843 let Latency = 121; 844 let ResourceCycles = [121]; 845} 846def : InstRW<[AtomWrite01_121], (instrs CPUID)>; 847 848def AtomWrite01_127 : SchedWriteRes<[AtomPort01]> { 849 let Latency = 127; 850 let ResourceCycles = [127]; 851} 852def : InstRW<[AtomWrite01_127], (instrs INT)>; 853 854def AtomWrite01_130 : SchedWriteRes<[AtomPort01]> { 855 let Latency = 130; 856 let ResourceCycles = [130]; 857} 858def : InstRW<[AtomWrite01_130], (instrs INT3)>; 859 860def AtomWrite01_140 : SchedWriteRes<[AtomPort01]> { 861 let Latency = 140; 862 let ResourceCycles = [140]; 863} 864def : InstRW<[AtomWrite01_140], (instrs FXSAVE, FXSAVE64)>; 865 866def AtomWrite01_141 : SchedWriteRes<[AtomPort01]> { 867 let Latency = 141; 868 let ResourceCycles = [141]; 869} 870def : InstRW<[AtomWrite01_141], (instrs FXRSTOR, FXRSTOR64)>; 871 872def AtomWrite01_146 : SchedWriteRes<[AtomPort01]> { 873 let Latency = 146; 874 let ResourceCycles = [146]; 875} 876def : InstRW<[AtomWrite01_146], (instrs FYL2X)>; 877 878def AtomWrite01_147 : SchedWriteRes<[AtomPort01]> { 879 let Latency = 147; 880 let ResourceCycles = [147]; 881} 882def : InstRW<[AtomWrite01_147], (instrs FYL2XP1)>; 883 884def AtomWrite01_168 : SchedWriteRes<[AtomPort01]> { 885 let Latency = 168; 886 let ResourceCycles = [168]; 887} 888def : InstRW<[AtomWrite01_168], (instrs FPTAN)>; 889 890def AtomWrite01_174 : SchedWriteRes<[AtomPort01]> { 891 let Latency = 174; 892 let ResourceCycles = [174]; 893} 894def : InstRW<[AtomWrite01_174], (instrs FSINCOS, FSIN, FCOS)>; 895 896def AtomWrite01_183 : SchedWriteRes<[AtomPort01]> { 897 let Latency = 183; 898 let ResourceCycles = [183]; 899} 900def : InstRW<[AtomWrite01_183], (instrs FPATAN)>; 901 902def AtomWrite01_202 : SchedWriteRes<[AtomPort01]> { 903 let Latency = 202; 904 let ResourceCycles = [202]; 905} 906def : InstRW<[AtomWrite01_202], (instrs WRMSR)>; 907 908} // SchedModel 909