1//=- X86SchedSkylake.td - X86 Skylake Server Scheduling ------*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the machine model for Skylake Server to support 10// instruction scheduling and other instruction cost heuristics. 11// 12//===----------------------------------------------------------------------===// 13 14def SkylakeServerModel : SchedMachineModel { 15 // All x86 instructions are modeled as a single micro-op, and SKylake can 16 // decode 6 instructions per cycle. 17 let IssueWidth = 6; 18 let MicroOpBufferSize = 224; // Based on the reorder buffer. 19 let LoadLatency = 5; 20 let MispredictPenalty = 14; 21 22 // Based on the LSD (loop-stream detector) queue size and benchmarking data. 23 let LoopMicroOpBufferSize = 50; 24 25 // This flag is set to allow the scheduler to assign a default model to 26 // unrecognized opcodes. 27 let CompleteModel = 0; 28} 29 30let SchedModel = SkylakeServerModel in { 31 32// Skylake Server can issue micro-ops to 8 different ports in one cycle. 33 34// Ports 0, 1, 5, and 6 handle all computation. 35// Port 4 gets the data half of stores. Store data can be available later than 36// the store address, but since we don't model the latency of stores, we can 37// ignore that. 38// Ports 2 and 3 are identical. They handle loads and the address half of 39// stores. Port 7 can handle address calculations. 40def SKXPort0 : ProcResource<1>; 41def SKXPort1 : ProcResource<1>; 42def SKXPort2 : ProcResource<1>; 43def SKXPort3 : ProcResource<1>; 44def SKXPort4 : ProcResource<1>; 45def SKXPort5 : ProcResource<1>; 46def SKXPort6 : ProcResource<1>; 47def SKXPort7 : ProcResource<1>; 48 49// Many micro-ops are capable of issuing on multiple ports. 50def SKXPort01 : ProcResGroup<[SKXPort0, SKXPort1]>; 51def SKXPort23 : ProcResGroup<[SKXPort2, SKXPort3]>; 52def SKXPort237 : ProcResGroup<[SKXPort2, SKXPort3, SKXPort7]>; 53def SKXPort04 : ProcResGroup<[SKXPort0, SKXPort4]>; 54def SKXPort05 : ProcResGroup<[SKXPort0, SKXPort5]>; 55def SKXPort06 : ProcResGroup<[SKXPort0, SKXPort6]>; 56def SKXPort15 : ProcResGroup<[SKXPort1, SKXPort5]>; 57def SKXPort16 : ProcResGroup<[SKXPort1, SKXPort6]>; 58def SKXPort56 : ProcResGroup<[SKXPort5, SKXPort6]>; 59def SKXPort015 : ProcResGroup<[SKXPort0, SKXPort1, SKXPort5]>; 60def SKXPort056 : ProcResGroup<[SKXPort0, SKXPort5, SKXPort6]>; 61def SKXPort0156: ProcResGroup<[SKXPort0, SKXPort1, SKXPort5, SKXPort6]>; 62 63def SKXDivider : ProcResource<1>; // Integer division issued on port 0. 64// FP division and sqrt on port 0. 65def SKXFPDivider : ProcResource<1>; 66 67// 60 Entry Unified Scheduler 68def SKXPortAny : ProcResGroup<[SKXPort0, SKXPort1, SKXPort2, SKXPort3, SKXPort4, 69 SKXPort5, SKXPort6, SKXPort7]> { 70 let BufferSize=60; 71} 72 73// Integer loads are 5 cycles, so ReadAfterLd registers needn't be available until 5 74// cycles after the memory operand. 75def : ReadAdvance<ReadAfterLd, 5>; 76 77// Vector loads are 5/6/7 cycles, so ReadAfterVec*Ld registers needn't be available 78// until 5/6/7 cycles after the memory operand. 79def : ReadAdvance<ReadAfterVecLd, 5>; 80def : ReadAdvance<ReadAfterVecXLd, 6>; 81def : ReadAdvance<ReadAfterVecYLd, 7>; 82 83def : ReadAdvance<ReadInt2Fpu, 0>; 84 85// Many SchedWrites are defined in pairs with and without a folded load. 86// Instructions with folded loads are usually micro-fused, so they only appear 87// as two micro-ops when queued in the reservation station. 88// This multiclass defines the resource usage for variants with and without 89// folded loads. 90multiclass SKXWriteResPair<X86FoldableSchedWrite SchedRW, 91 list<ProcResourceKind> ExePorts, 92 int Lat, list<int> Res = [1], int UOps = 1, 93 int LoadLat = 5> { 94 // Register variant is using a single cycle on ExePort. 95 def : WriteRes<SchedRW, ExePorts> { 96 let Latency = Lat; 97 let ResourceCycles = Res; 98 let NumMicroOps = UOps; 99 } 100 101 // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to 102 // the latency (default = 5). 103 def : WriteRes<SchedRW.Folded, !listconcat([SKXPort23], ExePorts)> { 104 let Latency = !add(Lat, LoadLat); 105 let ResourceCycles = !listconcat([1], Res); 106 let NumMicroOps = !add(UOps, 1); 107 } 108} 109 110// A folded store needs a cycle on port 4 for the store data, and an extra port 111// 2/3/7 cycle to recompute the address. 112def : WriteRes<WriteRMW, [SKXPort237,SKXPort4]>; 113 114// Arithmetic. 115defm : SKXWriteResPair<WriteALU, [SKXPort0156], 1>; // Simple integer ALU op. 116defm : SKXWriteResPair<WriteADC, [SKXPort06], 1>; // Integer ALU + flags op. 117 118// Integer multiplication. 119defm : SKXWriteResPair<WriteIMul8, [SKXPort1], 3>; 120defm : SKXWriteResPair<WriteIMul16, [SKXPort1,SKXPort06,SKXPort0156], 4, [1,1,2], 4>; 121defm : X86WriteRes<WriteIMul16Imm, [SKXPort1,SKXPort0156], 4, [1,1], 2>; 122defm : X86WriteRes<WriteIMul16ImmLd, [SKXPort1,SKXPort0156,SKXPort23], 8, [1,1,1], 3>; 123defm : X86WriteRes<WriteIMul16Reg, [SKXPort1], 3, [1], 1>; 124defm : X86WriteRes<WriteIMul16RegLd, [SKXPort1,SKXPort0156,SKXPort23], 8, [1,1,1], 3>; 125defm : SKXWriteResPair<WriteIMul32, [SKXPort1,SKXPort06,SKXPort0156], 4, [1,1,1], 3>; 126defm : SKXWriteResPair<WriteIMul32Imm, [SKXPort1], 3>; 127defm : SKXWriteResPair<WriteIMul32Reg, [SKXPort1], 3>; 128defm : SKXWriteResPair<WriteIMul64, [SKXPort1,SKXPort5], 4, [1,1], 2>; 129defm : SKXWriteResPair<WriteIMul64Imm, [SKXPort1], 3>; 130defm : SKXWriteResPair<WriteIMul64Reg, [SKXPort1], 3>; 131def : WriteRes<WriteIMulH, []> { let Latency = 3; } 132 133defm : X86WriteRes<WriteBSWAP32, [SKXPort15], 1, [1], 1>; 134defm : X86WriteRes<WriteBSWAP64, [SKXPort06, SKXPort15], 2, [1,1], 2>; 135defm : X86WriteRes<WriteCMPXCHG,[SKXPort06, SKXPort0156], 5, [2,3], 5>; 136defm : X86WriteRes<WriteCMPXCHGRMW,[SKXPort23,SKXPort06,SKXPort0156,SKXPort237,SKXPort4], 8, [1,2,1,1,1], 6>; 137defm : X86WriteRes<WriteXCHG, [SKXPort0156], 2, [3], 3>; 138 139// TODO: Why isn't the SKXDivider used? 140defm : SKXWriteResPair<WriteDiv8, [SKXPort0, SKXDivider], 25, [1,10], 1, 4>; 141defm : X86WriteRes<WriteDiv16, [SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort05,SKXPort0156], 76, [7,2,8,3,1,11], 32>; 142defm : X86WriteRes<WriteDiv32, [SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort05,SKXPort0156], 76, [7,2,8,3,1,11], 32>; 143defm : X86WriteRes<WriteDiv64, [SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort05,SKXPort0156], 76, [7,2,8,3,1,11], 32>; 144defm : X86WriteRes<WriteDiv16Ld, [SKXPort0,SKXPort23,SKXDivider], 29, [1,1,10], 2>; 145defm : X86WriteRes<WriteDiv32Ld, [SKXPort0,SKXPort23,SKXDivider], 29, [1,1,10], 2>; 146defm : X86WriteRes<WriteDiv64Ld, [SKXPort0,SKXPort23,SKXDivider], 29, [1,1,10], 2>; 147 148defm : X86WriteRes<WriteIDiv8, [SKXPort0, SKXDivider], 25, [1,10], 1>; 149defm : X86WriteRes<WriteIDiv16, [SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort06,SKXPort0156], 102, [4,2,4,8,14,34], 66>; 150defm : X86WriteRes<WriteIDiv32, [SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort06,SKXPort0156], 102, [4,2,4,8,14,34], 66>; 151defm : X86WriteRes<WriteIDiv64, [SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort06,SKXPort0156], 102, [4,2,4,8,14,34], 66>; 152defm : X86WriteRes<WriteIDiv8Ld, [SKXPort0,SKXPort5,SKXPort23,SKXPort0156], 28, [2,4,1,1], 8>; 153defm : X86WriteRes<WriteIDiv16Ld, [SKXPort0,SKXPort5,SKXPort23,SKXPort0156], 28, [2,4,1,1], 8>; 154defm : X86WriteRes<WriteIDiv32Ld, [SKXPort0,SKXPort5,SKXPort23,SKXPort0156], 28, [2,4,1,1], 8>; 155defm : X86WriteRes<WriteIDiv64Ld, [SKXPort0,SKXPort5,SKXPort23,SKXPort0156], 28, [2,4,1,1], 8>; 156 157defm : SKXWriteResPair<WriteCRC32, [SKXPort1], 3>; 158 159def : WriteRes<WriteLEA, [SKXPort15]>; // LEA instructions can't fold loads. 160 161defm : SKXWriteResPair<WriteCMOV, [SKXPort06], 1, [1], 1>; // Conditional move. 162defm : X86WriteRes<WriteFCMOV, [SKXPort1], 3, [1], 1>; // x87 conditional move. 163def : WriteRes<WriteSETCC, [SKXPort06]>; // Setcc. 164def : WriteRes<WriteSETCCStore, [SKXPort06,SKXPort4,SKXPort237]> { 165 let Latency = 2; 166 let NumMicroOps = 3; 167} 168defm : X86WriteRes<WriteLAHFSAHF, [SKXPort06], 1, [1], 1>; 169defm : X86WriteRes<WriteBitTest, [SKXPort06], 1, [1], 1>; 170defm : X86WriteRes<WriteBitTestImmLd, [SKXPort06,SKXPort23], 6, [1,1], 2>; 171defm : X86WriteRes<WriteBitTestRegLd, [SKXPort0156,SKXPort23], 6, [1,1], 2>; 172defm : X86WriteRes<WriteBitTestSet, [SKXPort06], 1, [1], 1>; 173defm : X86WriteRes<WriteBitTestSetImmLd, [SKXPort06,SKXPort23], 5, [1,1], 3>; 174defm : X86WriteRes<WriteBitTestSetRegLd, [SKXPort0156,SKXPort23], 5, [1,1], 2>; 175 176// Integer shifts and rotates. 177defm : SKXWriteResPair<WriteShift, [SKXPort06], 1>; 178defm : SKXWriteResPair<WriteShiftCL, [SKXPort06], 3, [3], 3>; 179defm : SKXWriteResPair<WriteRotate, [SKXPort06], 1, [1], 1>; 180defm : SKXWriteResPair<WriteRotateCL, [SKXPort06], 3, [3], 3>; 181 182// SHLD/SHRD. 183defm : X86WriteRes<WriteSHDrri, [SKXPort1], 3, [1], 1>; 184defm : X86WriteRes<WriteSHDrrcl,[SKXPort1,SKXPort06,SKXPort0156], 6, [1, 2, 1], 4>; 185defm : X86WriteRes<WriteSHDmri, [SKXPort1,SKXPort23,SKXPort237,SKXPort0156], 9, [1, 1, 1, 1], 4>; 186defm : X86WriteRes<WriteSHDmrcl,[SKXPort1,SKXPort23,SKXPort237,SKXPort06,SKXPort0156], 11, [1, 1, 1, 2, 1], 6>; 187 188// Bit counts. 189defm : SKXWriteResPair<WriteBSF, [SKXPort1], 3>; 190defm : SKXWriteResPair<WriteBSR, [SKXPort1], 3>; 191defm : SKXWriteResPair<WriteLZCNT, [SKXPort1], 3>; 192defm : SKXWriteResPair<WriteTZCNT, [SKXPort1], 3>; 193defm : SKXWriteResPair<WritePOPCNT, [SKXPort1], 3>; 194 195// BMI1 BEXTR/BLS, BMI2 BZHI 196defm : SKXWriteResPair<WriteBEXTR, [SKXPort06,SKXPort15], 2, [1,1], 2>; 197defm : SKXWriteResPair<WriteBLS, [SKXPort15], 1>; 198defm : SKXWriteResPair<WriteBZHI, [SKXPort15], 1>; 199 200// Loads, stores, and moves, not folded with other operations. 201defm : X86WriteRes<WriteLoad, [SKXPort23], 5, [1], 1>; 202defm : X86WriteRes<WriteStore, [SKXPort237, SKXPort4], 1, [1,1], 1>; 203defm : X86WriteRes<WriteStoreNT, [SKXPort237, SKXPort4], 1, [1,1], 2>; 204defm : X86WriteRes<WriteMove, [SKXPort0156], 1, [1], 1>; 205 206// Idioms that clear a register, like xorps %xmm0, %xmm0. 207// These can often bypass execution ports completely. 208def : WriteRes<WriteZero, []>; 209 210// Branches don't produce values, so they have no latency, but they still 211// consume resources. Indirect branches can fold loads. 212defm : SKXWriteResPair<WriteJump, [SKXPort06], 1>; 213 214// Floating point. This covers both scalar and vector operations. 215defm : X86WriteRes<WriteFLD0, [SKXPort05], 1, [1], 1>; 216defm : X86WriteRes<WriteFLD1, [SKXPort05], 1, [2], 2>; 217defm : X86WriteRes<WriteFLDC, [SKXPort05], 1, [2], 2>; 218defm : X86WriteRes<WriteFLoad, [SKXPort23], 5, [1], 1>; 219defm : X86WriteRes<WriteFLoadX, [SKXPort23], 6, [1], 1>; 220defm : X86WriteRes<WriteFLoadY, [SKXPort23], 7, [1], 1>; 221defm : X86WriteRes<WriteFMaskedLoad, [SKXPort23,SKXPort015], 7, [1,1], 2>; 222defm : X86WriteRes<WriteFMaskedLoadY, [SKXPort23,SKXPort015], 8, [1,1], 2>; 223defm : X86WriteRes<WriteFStore, [SKXPort237,SKXPort4], 1, [1,1], 2>; 224defm : X86WriteRes<WriteFStoreX, [SKXPort237,SKXPort4], 1, [1,1], 2>; 225defm : X86WriteRes<WriteFStoreY, [SKXPort237,SKXPort4], 1, [1,1], 2>; 226defm : X86WriteRes<WriteFStoreNT, [SKXPort237,SKXPort4], 1, [1,1], 2>; 227defm : X86WriteRes<WriteFStoreNTX, [SKXPort237,SKXPort4], 1, [1,1], 2>; 228defm : X86WriteRes<WriteFStoreNTY, [SKXPort237,SKXPort4], 1, [1,1], 2>; 229 230defm : X86WriteRes<WriteFMaskedStore32, [SKXPort237,SKXPort0], 2, [1,1], 2>; 231defm : X86WriteRes<WriteFMaskedStore32Y, [SKXPort237,SKXPort0], 2, [1,1], 2>; 232defm : X86WriteRes<WriteFMaskedStore64, [SKXPort237,SKXPort0], 2, [1,1], 2>; 233defm : X86WriteRes<WriteFMaskedStore64Y, [SKXPort237,SKXPort0], 2, [1,1], 2>; 234 235defm : X86WriteRes<WriteFMove, [SKXPort015], 1, [1], 1>; 236defm : X86WriteRes<WriteFMoveX, [SKXPort015], 1, [1], 1>; 237defm : X86WriteRes<WriteFMoveY, [SKXPort015], 1, [1], 1>; 238defm : X86WriteRes<WriteEMMS, [SKXPort05,SKXPort0156], 10, [9,1], 10>; 239 240defm : SKXWriteResPair<WriteFAdd, [SKXPort01], 4, [1], 1, 5>; // Floating point add/sub. 241defm : SKXWriteResPair<WriteFAddX, [SKXPort01], 4, [1], 1, 6>; 242defm : SKXWriteResPair<WriteFAddY, [SKXPort01], 4, [1], 1, 7>; 243defm : SKXWriteResPair<WriteFAddZ, [SKXPort05], 4, [1], 1, 7>; 244defm : SKXWriteResPair<WriteFAdd64, [SKXPort01], 4, [1], 1, 5>; // Floating point double add/sub. 245defm : SKXWriteResPair<WriteFAdd64X, [SKXPort01], 4, [1], 1, 6>; 246defm : SKXWriteResPair<WriteFAdd64Y, [SKXPort01], 4, [1], 1, 7>; 247defm : SKXWriteResPair<WriteFAdd64Z, [SKXPort05], 4, [1], 1, 7>; 248 249defm : SKXWriteResPair<WriteFCmp, [SKXPort01], 4, [1], 1, 5>; // Floating point compare. 250defm : SKXWriteResPair<WriteFCmpX, [SKXPort01], 4, [1], 1, 6>; 251defm : SKXWriteResPair<WriteFCmpY, [SKXPort01], 4, [1], 1, 7>; 252defm : SKXWriteResPair<WriteFCmpZ, [SKXPort05], 4, [1], 1, 7>; 253defm : SKXWriteResPair<WriteFCmp64, [SKXPort01], 4, [1], 1, 5>; // Floating point double compare. 254defm : SKXWriteResPair<WriteFCmp64X, [SKXPort01], 4, [1], 1, 6>; 255defm : SKXWriteResPair<WriteFCmp64Y, [SKXPort01], 4, [1], 1, 7>; 256defm : SKXWriteResPair<WriteFCmp64Z, [SKXPort05], 4, [1], 1, 7>; 257 258defm : SKXWriteResPair<WriteFCom, [SKXPort0], 2>; // Floating point compare to flags. 259 260defm : SKXWriteResPair<WriteFMul, [SKXPort01], 4, [1], 1, 5>; // Floating point multiplication. 261defm : SKXWriteResPair<WriteFMulX, [SKXPort01], 4, [1], 1, 6>; 262defm : SKXWriteResPair<WriteFMulY, [SKXPort01], 4, [1], 1, 7>; 263defm : SKXWriteResPair<WriteFMulZ, [SKXPort05], 4, [1], 1, 7>; 264defm : SKXWriteResPair<WriteFMul64, [SKXPort01], 4, [1], 1, 5>; // Floating point double multiplication. 265defm : SKXWriteResPair<WriteFMul64X, [SKXPort01], 4, [1], 1, 6>; 266defm : SKXWriteResPair<WriteFMul64Y, [SKXPort01], 4, [1], 1, 7>; 267defm : SKXWriteResPair<WriteFMul64Z, [SKXPort05], 4, [1], 1, 7>; 268 269defm : SKXWriteResPair<WriteFDiv, [SKXPort0,SKXFPDivider], 11, [1,3], 1, 5>; // 10-14 cycles. // Floating point division. 270//defm : SKXWriteResPair<WriteFDivX, [SKXPort0,SKXFPDivider], 11, [1,3], 1, 6>; // 10-14 cycles. 271defm : SKXWriteResPair<WriteFDivY, [SKXPort0,SKXFPDivider], 11, [1,5], 1, 7>; // 10-14 cycles. 272defm : SKXWriteResPair<WriteFDivZ, [SKXPort0,SKXPort5,SKXFPDivider], 18, [2,1,10], 3, 7>; // 10-14 cycles. 273//defm : SKXWriteResPair<WriteFDiv64, [SKXPort0,SKXFPDivider], 14, [1,3], 1, 5>; // 10-14 cycles. // Floating point division. 274//defm : SKXWriteResPair<WriteFDiv64X, [SKXPort0,SKXFPDivider], 14, [1,3], 1, 6>; // 10-14 cycles. 275//defm : SKXWriteResPair<WriteFDiv64Y, [SKXPort0,SKXFPDivider], 14, [1,5], 1, 7>; // 10-14 cycles. 276defm : SKXWriteResPair<WriteFDiv64Z, [SKXPort0,SKXPort5,SKXFPDivider], 23, [2,1,16], 3, 7>; // 10-14 cycles. 277 278defm : SKXWriteResPair<WriteFSqrt, [SKXPort0,SKXFPDivider], 12, [1,3], 1, 5>; // Floating point square root. 279defm : SKXWriteResPair<WriteFSqrtX, [SKXPort0,SKXFPDivider], 12, [1,3], 1, 6>; 280defm : SKXWriteResPair<WriteFSqrtY, [SKXPort0,SKXFPDivider], 12, [1,6], 1, 7>; 281defm : SKXWriteResPair<WriteFSqrtZ, [SKXPort0,SKXPort5,SKXFPDivider], 20, [2,1,12], 3, 7>; 282defm : SKXWriteResPair<WriteFSqrt64, [SKXPort0,SKXFPDivider], 18, [1,6], 1, 5>; // Floating point double square root. 283defm : SKXWriteResPair<WriteFSqrt64X, [SKXPort0,SKXFPDivider], 18, [1,6], 1, 6>; 284defm : SKXWriteResPair<WriteFSqrt64Y, [SKXPort0,SKXFPDivider], 18, [1,12],1, 7>; 285defm : SKXWriteResPair<WriteFSqrt64Z, [SKXPort0,SKXPort5,SKXFPDivider], 32, [2,1,24], 3, 7>; 286defm : SKXWriteResPair<WriteFSqrt80, [SKXPort0,SKXFPDivider], 21, [1,7]>; // Floating point long double square root. 287 288defm : SKXWriteResPair<WriteFRcp, [SKXPort0], 4, [1], 1, 5>; // Floating point reciprocal estimate. 289defm : SKXWriteResPair<WriteFRcpX, [SKXPort0], 4, [1], 1, 6>; 290defm : SKXWriteResPair<WriteFRcpY, [SKXPort0], 4, [1], 1, 7>; 291defm : SKXWriteResPair<WriteFRcpZ, [SKXPort0,SKXPort5], 4, [2,1], 3, 7>; 292 293defm : SKXWriteResPair<WriteFRsqrt, [SKXPort0], 4, [1], 1, 5>; // Floating point reciprocal square root estimate. 294defm : SKXWriteResPair<WriteFRsqrtX,[SKXPort0], 4, [1], 1, 6>; 295defm : SKXWriteResPair<WriteFRsqrtY,[SKXPort0], 4, [1], 1, 7>; 296defm : SKXWriteResPair<WriteFRsqrtZ,[SKXPort0,SKXPort5], 9, [2,1], 3, 7>; 297 298defm : SKXWriteResPair<WriteFMA, [SKXPort01], 4, [1], 1, 5>; // Fused Multiply Add. 299defm : SKXWriteResPair<WriteFMAX, [SKXPort01], 4, [1], 1, 6>; 300defm : SKXWriteResPair<WriteFMAY, [SKXPort01], 4, [1], 1, 7>; 301defm : SKXWriteResPair<WriteFMAZ, [SKXPort05], 4, [1], 1, 7>; 302defm : SKXWriteResPair<WriteDPPD, [SKXPort5,SKXPort015], 9, [1,2], 3, 6>; // Floating point double dot product. 303defm : SKXWriteResPair<WriteDPPS, [SKXPort5,SKXPort015], 13, [1,3], 4, 6>; 304defm : SKXWriteResPair<WriteDPPSY,[SKXPort5,SKXPort015], 13, [1,3], 4, 7>; 305defm : SKXWriteResPair<WriteDPPSZ,[SKXPort5,SKXPort015], 13, [1,3], 4, 7>; 306defm : SKXWriteResPair<WriteFSign, [SKXPort0], 1>; // Floating point fabs/fchs. 307defm : SKXWriteResPair<WriteFRnd, [SKXPort01], 8, [2], 2, 6>; // Floating point rounding. 308defm : SKXWriteResPair<WriteFRndY, [SKXPort01], 8, [2], 2, 7>; 309defm : SKXWriteResPair<WriteFRndZ, [SKXPort05], 8, [2], 2, 7>; 310defm : SKXWriteResPair<WriteFLogic, [SKXPort015], 1, [1], 1, 6>; // Floating point and/or/xor logicals. 311defm : SKXWriteResPair<WriteFLogicY, [SKXPort015], 1, [1], 1, 7>; 312defm : SKXWriteResPair<WriteFLogicZ, [SKXPort05], 1, [1], 1, 7>; 313defm : SKXWriteResPair<WriteFTest, [SKXPort0], 2, [1], 1, 6>; // Floating point TEST instructions. 314defm : SKXWriteResPair<WriteFTestY, [SKXPort0], 2, [1], 1, 7>; 315defm : SKXWriteResPair<WriteFTestZ, [SKXPort0], 2, [1], 1, 7>; 316defm : SKXWriteResPair<WriteFShuffle, [SKXPort5], 1, [1], 1, 6>; // Floating point vector shuffles. 317defm : SKXWriteResPair<WriteFShuffleY, [SKXPort5], 1, [1], 1, 7>; 318defm : SKXWriteResPair<WriteFShuffleZ, [SKXPort5], 1, [1], 1, 7>; 319defm : SKXWriteResPair<WriteFVarShuffle, [SKXPort5], 1, [1], 1, 6>; // Floating point vector variable shuffles. 320defm : SKXWriteResPair<WriteFVarShuffleY, [SKXPort5], 1, [1], 1, 7>; 321defm : SKXWriteResPair<WriteFVarShuffleZ, [SKXPort5], 1, [1], 1, 7>; 322defm : SKXWriteResPair<WriteFBlend, [SKXPort015], 1, [1], 1, 6>; // Floating point vector blends. 323defm : SKXWriteResPair<WriteFBlendY,[SKXPort015], 1, [1], 1, 7>; 324defm : SKXWriteResPair<WriteFBlendZ,[SKXPort015], 1, [1], 1, 7>; 325defm : SKXWriteResPair<WriteFVarBlend, [SKXPort015], 2, [2], 2, 6>; // Fp vector variable blends. 326defm : SKXWriteResPair<WriteFVarBlendY,[SKXPort015], 2, [2], 2, 7>; 327defm : SKXWriteResPair<WriteFVarBlendZ,[SKXPort015], 2, [2], 2, 7>; 328 329// FMA Scheduling helper class. 330// class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; } 331 332// Vector integer operations. 333defm : X86WriteRes<WriteVecLoad, [SKXPort23], 5, [1], 1>; 334defm : X86WriteRes<WriteVecLoadX, [SKXPort23], 6, [1], 1>; 335defm : X86WriteRes<WriteVecLoadY, [SKXPort23], 7, [1], 1>; 336defm : X86WriteRes<WriteVecLoadNT, [SKXPort23], 6, [1], 1>; 337defm : X86WriteRes<WriteVecLoadNTY, [SKXPort23], 7, [1], 1>; 338defm : X86WriteRes<WriteVecMaskedLoad, [SKXPort23,SKXPort015], 7, [1,1], 2>; 339defm : X86WriteRes<WriteVecMaskedLoadY, [SKXPort23,SKXPort015], 8, [1,1], 2>; 340defm : X86WriteRes<WriteVecStore, [SKXPort237,SKXPort4], 1, [1,1], 2>; 341defm : X86WriteRes<WriteVecStoreX, [SKXPort237,SKXPort4], 1, [1,1], 2>; 342defm : X86WriteRes<WriteVecStoreY, [SKXPort237,SKXPort4], 1, [1,1], 2>; 343defm : X86WriteRes<WriteVecStoreNT, [SKXPort237,SKXPort4], 1, [1,1], 2>; 344defm : X86WriteRes<WriteVecStoreNTY, [SKXPort237,SKXPort4], 1, [1,1], 2>; 345defm : X86WriteRes<WriteVecMaskedStore, [SKXPort237,SKXPort0], 2, [1,1], 2>; 346defm : X86WriteRes<WriteVecMaskedStoreY, [SKXPort237,SKXPort0], 2, [1,1], 2>; 347defm : X86WriteRes<WriteVecMove, [SKXPort05], 1, [1], 1>; 348defm : X86WriteRes<WriteVecMoveX, [SKXPort015], 1, [1], 1>; 349defm : X86WriteRes<WriteVecMoveY, [SKXPort015], 1, [1], 1>; 350defm : X86WriteRes<WriteVecMoveToGpr, [SKXPort0], 2, [1], 1>; 351defm : X86WriteRes<WriteVecMoveFromGpr, [SKXPort5], 1, [1], 1>; 352 353defm : SKXWriteResPair<WriteVecALU, [SKXPort05], 1, [1], 1, 5>; // Vector integer ALU op, no logicals. 354defm : SKXWriteResPair<WriteVecALUX, [SKXPort01], 1, [1], 1, 6>; 355defm : SKXWriteResPair<WriteVecALUY, [SKXPort01], 1, [1], 1, 7>; 356defm : SKXWriteResPair<WriteVecALUZ, [SKXPort0], 1, [1], 1, 7>; 357defm : SKXWriteResPair<WriteVecLogic, [SKXPort05], 1, [1], 1, 5>; // Vector integer and/or/xor. 358defm : SKXWriteResPair<WriteVecLogicX,[SKXPort015], 1, [1], 1, 6>; 359defm : SKXWriteResPair<WriteVecLogicY,[SKXPort015], 1, [1], 1, 7>; 360defm : SKXWriteResPair<WriteVecLogicZ,[SKXPort05], 1, [1], 1, 7>; 361defm : SKXWriteResPair<WriteVecTest, [SKXPort0,SKXPort5], 3, [1,1], 2, 6>; // Vector integer TEST instructions. 362defm : SKXWriteResPair<WriteVecTestY, [SKXPort0,SKXPort5], 3, [1,1], 2, 7>; 363defm : SKXWriteResPair<WriteVecTestZ, [SKXPort0,SKXPort5], 3, [1,1], 2, 7>; 364defm : SKXWriteResPair<WriteVecIMul, [SKXPort0], 4, [1], 1, 5>; // Vector integer multiply. 365defm : SKXWriteResPair<WriteVecIMulX, [SKXPort01], 4, [1], 1, 6>; 366defm : SKXWriteResPair<WriteVecIMulY, [SKXPort01], 4, [1], 1, 7>; 367defm : SKXWriteResPair<WriteVecIMulZ, [SKXPort05], 4, [1], 1, 7>; 368defm : SKXWriteResPair<WritePMULLD, [SKXPort01], 10, [2], 2, 6>; // Vector PMULLD. 369defm : SKXWriteResPair<WritePMULLDY, [SKXPort01], 10, [2], 2, 7>; 370defm : SKXWriteResPair<WritePMULLDZ, [SKXPort05], 10, [2], 2, 7>; 371defm : SKXWriteResPair<WriteShuffle, [SKXPort5], 1, [1], 1, 5>; // Vector shuffles. 372defm : SKXWriteResPair<WriteShuffleX, [SKXPort5], 1, [1], 1, 6>; 373defm : SKXWriteResPair<WriteShuffleY, [SKXPort5], 1, [1], 1, 7>; 374defm : SKXWriteResPair<WriteShuffleZ, [SKXPort5], 1, [1], 1, 7>; 375defm : SKXWriteResPair<WriteVarShuffle, [SKXPort5], 1, [1], 1, 5>; // Vector variable shuffles. 376defm : SKXWriteResPair<WriteVarShuffleX, [SKXPort5], 1, [1], 1, 6>; 377defm : SKXWriteResPair<WriteVarShuffleY, [SKXPort5], 1, [1], 1, 7>; 378defm : SKXWriteResPair<WriteVarShuffleZ, [SKXPort5], 1, [1], 1, 7>; 379defm : SKXWriteResPair<WriteBlend, [SKXPort5], 1, [1], 1, 6>; // Vector blends. 380defm : SKXWriteResPair<WriteBlendY,[SKXPort5], 1, [1], 1, 7>; 381defm : SKXWriteResPair<WriteBlendZ,[SKXPort5], 1, [1], 1, 7>; 382defm : SKXWriteResPair<WriteVarBlend, [SKXPort015], 2, [2], 2, 6>; // Vector variable blends. 383defm : SKXWriteResPair<WriteVarBlendY,[SKXPort015], 2, [2], 2, 6>; 384defm : SKXWriteResPair<WriteVarBlendZ,[SKXPort05], 2, [1], 1, 6>; 385defm : SKXWriteResPair<WriteMPSAD, [SKXPort5], 4, [2], 2, 6>; // Vector MPSAD. 386defm : SKXWriteResPair<WriteMPSADY, [SKXPort5], 4, [2], 2, 7>; 387defm : SKXWriteResPair<WriteMPSADZ, [SKXPort5], 4, [2], 2, 7>; 388defm : SKXWriteResPair<WritePSADBW, [SKXPort5], 3, [1], 1, 5>; // Vector PSADBW. 389defm : SKXWriteResPair<WritePSADBWX, [SKXPort5], 3, [1], 1, 6>; 390defm : SKXWriteResPair<WritePSADBWY, [SKXPort5], 3, [1], 1, 7>; 391defm : SKXWriteResPair<WritePSADBWZ, [SKXPort5], 3, [1], 1, 7>; 392defm : SKXWriteResPair<WritePHMINPOS, [SKXPort0], 4, [1], 1, 6>; // Vector PHMINPOS. 393 394// Vector integer shifts. 395defm : SKXWriteResPair<WriteVecShift, [SKXPort0], 1, [1], 1, 5>; 396defm : X86WriteRes<WriteVecShiftX, [SKXPort5,SKXPort01], 2, [1,1], 2>; 397defm : X86WriteRes<WriteVecShiftY, [SKXPort5,SKXPort01], 4, [1,1], 2>; 398defm : X86WriteRes<WriteVecShiftZ, [SKXPort5,SKXPort0], 4, [1,1], 2>; 399defm : X86WriteRes<WriteVecShiftXLd, [SKXPort01,SKXPort23], 7, [1,1], 2>; 400defm : X86WriteRes<WriteVecShiftYLd, [SKXPort01,SKXPort23], 8, [1,1], 2>; 401defm : X86WriteRes<WriteVecShiftZLd, [SKXPort0,SKXPort23], 8, [1,1], 2>; 402 403defm : SKXWriteResPair<WriteVecShiftImm, [SKXPort0], 1, [1], 1, 5>; 404defm : SKXWriteResPair<WriteVecShiftImmX, [SKXPort01], 1, [1], 1, 6>; // Vector integer immediate shifts. 405defm : SKXWriteResPair<WriteVecShiftImmY, [SKXPort01], 1, [1], 1, 7>; 406defm : SKXWriteResPair<WriteVecShiftImmZ, [SKXPort0], 1, [1], 1, 7>; 407defm : SKXWriteResPair<WriteVarVecShift, [SKXPort01], 1, [1], 1, 6>; // Variable vector shifts. 408defm : SKXWriteResPair<WriteVarVecShiftY, [SKXPort01], 1, [1], 1, 7>; 409defm : SKXWriteResPair<WriteVarVecShiftZ, [SKXPort0], 1, [1], 1, 7>; 410 411// Vector insert/extract operations. 412def : WriteRes<WriteVecInsert, [SKXPort5]> { 413 let Latency = 2; 414 let NumMicroOps = 2; 415 let ResourceCycles = [2]; 416} 417def : WriteRes<WriteVecInsertLd, [SKXPort5,SKXPort23]> { 418 let Latency = 6; 419 let NumMicroOps = 2; 420} 421def: InstRW<[WriteVecInsertLd], (instregex "(V?)MOV(H|L)(PD|PS)rm")>; 422 423def : WriteRes<WriteVecExtract, [SKXPort0,SKXPort5]> { 424 let Latency = 3; 425 let NumMicroOps = 2; 426} 427def : WriteRes<WriteVecExtractSt, [SKXPort4,SKXPort5,SKXPort237]> { 428 let Latency = 2; 429 let NumMicroOps = 3; 430} 431 432// Conversion between integer and float. 433defm : SKXWriteResPair<WriteCvtSS2I, [SKXPort01], 6, [2], 2>; // Needs more work: DD vs DQ. 434defm : SKXWriteResPair<WriteCvtPS2I, [SKXPort01], 3>; 435defm : SKXWriteResPair<WriteCvtPS2IY, [SKXPort01], 3>; 436defm : SKXWriteResPair<WriteCvtPS2IZ, [SKXPort05], 3>; 437defm : SKXWriteResPair<WriteCvtSD2I, [SKXPort01], 6, [2], 2>; 438defm : SKXWriteResPair<WriteCvtPD2I, [SKXPort01], 3>; 439defm : SKXWriteResPair<WriteCvtPD2IY, [SKXPort01], 3>; 440defm : SKXWriteResPair<WriteCvtPD2IZ, [SKXPort05], 3>; 441 442defm : SKXWriteResPair<WriteCvtI2SS, [SKXPort1], 4>; 443defm : SKXWriteResPair<WriteCvtI2PS, [SKXPort01], 4>; 444defm : SKXWriteResPair<WriteCvtI2PSY, [SKXPort01], 4>; 445defm : SKXWriteResPair<WriteCvtI2PSZ, [SKXPort05], 4>; // Needs more work: DD vs DQ. 446defm : SKXWriteResPair<WriteCvtI2SD, [SKXPort1], 4>; 447defm : SKXWriteResPair<WriteCvtI2PD, [SKXPort01], 4>; 448defm : SKXWriteResPair<WriteCvtI2PDY, [SKXPort01], 4>; 449defm : SKXWriteResPair<WriteCvtI2PDZ, [SKXPort05], 4>; 450 451defm : SKXWriteResPair<WriteCvtSS2SD, [SKXPort1], 3>; 452defm : SKXWriteResPair<WriteCvtPS2PD, [SKXPort1], 3>; 453defm : SKXWriteResPair<WriteCvtPS2PDY, [SKXPort5,SKXPort01], 3, [1,1], 2>; 454defm : SKXWriteResPair<WriteCvtPS2PDZ, [SKXPort05], 3, [2], 2>; 455defm : SKXWriteResPair<WriteCvtSD2SS, [SKXPort1], 3>; 456defm : SKXWriteResPair<WriteCvtPD2PS, [SKXPort1], 3>; 457defm : SKXWriteResPair<WriteCvtPD2PSY, [SKXPort5,SKXPort01], 3, [1,1], 2>; 458defm : SKXWriteResPair<WriteCvtPD2PSZ, [SKXPort05], 3, [2], 2>; 459 460defm : X86WriteRes<WriteCvtPH2PS, [SKXPort5,SKXPort01], 5, [1,1], 2>; 461defm : X86WriteRes<WriteCvtPH2PSY, [SKXPort5,SKXPort01], 7, [1,1], 2>; 462defm : X86WriteRes<WriteCvtPH2PSZ, [SKXPort5,SKXPort0], 7, [1,1], 2>; 463defm : X86WriteRes<WriteCvtPH2PSLd, [SKXPort23,SKXPort01], 9, [1,1], 2>; 464defm : X86WriteRes<WriteCvtPH2PSYLd, [SKXPort23,SKXPort01], 10, [1,1], 2>; 465defm : X86WriteRes<WriteCvtPH2PSZLd, [SKXPort23,SKXPort05], 10, [1,1], 2>; 466 467defm : X86WriteRes<WriteCvtPS2PH, [SKXPort5,SKXPort01], 5, [1,1], 2>; 468defm : X86WriteRes<WriteCvtPS2PHY, [SKXPort5,SKXPort01], 7, [1,1], 2>; 469defm : X86WriteRes<WriteCvtPS2PHZ, [SKXPort5,SKXPort05], 7, [1,1], 2>; 470defm : X86WriteRes<WriteCvtPS2PHSt, [SKXPort4,SKXPort5,SKXPort237,SKXPort01], 6, [1,1,1,1], 4>; 471defm : X86WriteRes<WriteCvtPS2PHYSt, [SKXPort4,SKXPort5,SKXPort237,SKXPort01], 8, [1,1,1,1], 4>; 472defm : X86WriteRes<WriteCvtPS2PHZSt, [SKXPort4,SKXPort5,SKXPort237,SKXPort05], 8, [1,1,1,1], 4>; 473 474// Strings instructions. 475 476// Packed Compare Implicit Length Strings, Return Mask 477def : WriteRes<WritePCmpIStrM, [SKXPort0]> { 478 let Latency = 10; 479 let NumMicroOps = 3; 480 let ResourceCycles = [3]; 481} 482def : WriteRes<WritePCmpIStrMLd, [SKXPort0, SKXPort23]> { 483 let Latency = 16; 484 let NumMicroOps = 4; 485 let ResourceCycles = [3,1]; 486} 487 488// Packed Compare Explicit Length Strings, Return Mask 489def : WriteRes<WritePCmpEStrM, [SKXPort0, SKXPort5, SKXPort015, SKXPort0156]> { 490 let Latency = 19; 491 let NumMicroOps = 9; 492 let ResourceCycles = [4,3,1,1]; 493} 494def : WriteRes<WritePCmpEStrMLd, [SKXPort0, SKXPort5, SKXPort23, SKXPort015, SKXPort0156]> { 495 let Latency = 25; 496 let NumMicroOps = 10; 497 let ResourceCycles = [4,3,1,1,1]; 498} 499 500// Packed Compare Implicit Length Strings, Return Index 501def : WriteRes<WritePCmpIStrI, [SKXPort0]> { 502 let Latency = 10; 503 let NumMicroOps = 3; 504 let ResourceCycles = [3]; 505} 506def : WriteRes<WritePCmpIStrILd, [SKXPort0, SKXPort23]> { 507 let Latency = 16; 508 let NumMicroOps = 4; 509 let ResourceCycles = [3,1]; 510} 511 512// Packed Compare Explicit Length Strings, Return Index 513def : WriteRes<WritePCmpEStrI, [SKXPort0,SKXPort5,SKXPort0156]> { 514 let Latency = 18; 515 let NumMicroOps = 8; 516 let ResourceCycles = [4,3,1]; 517} 518def : WriteRes<WritePCmpEStrILd, [SKXPort0, SKXPort5, SKXPort23, SKXPort0156]> { 519 let Latency = 24; 520 let NumMicroOps = 9; 521 let ResourceCycles = [4,3,1,1]; 522} 523 524// MOVMSK Instructions. 525def : WriteRes<WriteFMOVMSK, [SKXPort0]> { let Latency = 2; } 526def : WriteRes<WriteVecMOVMSK, [SKXPort0]> { let Latency = 2; } 527def : WriteRes<WriteVecMOVMSKY, [SKXPort0]> { let Latency = 2; } 528def : WriteRes<WriteMMXMOVMSK, [SKXPort0]> { let Latency = 2; } 529 530// AES instructions. 531def : WriteRes<WriteAESDecEnc, [SKXPort0]> { // Decryption, encryption. 532 let Latency = 4; 533 let NumMicroOps = 1; 534 let ResourceCycles = [1]; 535} 536def : WriteRes<WriteAESDecEncLd, [SKXPort0, SKXPort23]> { 537 let Latency = 10; 538 let NumMicroOps = 2; 539 let ResourceCycles = [1,1]; 540} 541 542def : WriteRes<WriteAESIMC, [SKXPort0]> { // InvMixColumn. 543 let Latency = 8; 544 let NumMicroOps = 2; 545 let ResourceCycles = [2]; 546} 547def : WriteRes<WriteAESIMCLd, [SKXPort0, SKXPort23]> { 548 let Latency = 14; 549 let NumMicroOps = 3; 550 let ResourceCycles = [2,1]; 551} 552 553def : WriteRes<WriteAESKeyGen, [SKXPort0,SKXPort5,SKXPort015]> { // Key Generation. 554 let Latency = 20; 555 let NumMicroOps = 11; 556 let ResourceCycles = [3,6,2]; 557} 558def : WriteRes<WriteAESKeyGenLd, [SKXPort0,SKXPort5,SKXPort23,SKXPort015]> { 559 let Latency = 25; 560 let NumMicroOps = 11; 561 let ResourceCycles = [3,6,1,1]; 562} 563 564// Carry-less multiplication instructions. 565def : WriteRes<WriteCLMul, [SKXPort5]> { 566 let Latency = 6; 567 let NumMicroOps = 1; 568 let ResourceCycles = [1]; 569} 570def : WriteRes<WriteCLMulLd, [SKXPort5, SKXPort23]> { 571 let Latency = 12; 572 let NumMicroOps = 2; 573 let ResourceCycles = [1,1]; 574} 575 576// Catch-all for expensive system instructions. 577def : WriteRes<WriteSystem, [SKXPort0156]> { let Latency = 100; } // def WriteSystem : SchedWrite; 578 579// AVX2. 580defm : SKXWriteResPair<WriteFShuffle256, [SKXPort5], 3, [1], 1, 7>; // Fp 256-bit width vector shuffles. 581defm : SKXWriteResPair<WriteFVarShuffle256, [SKXPort5], 3, [1], 1, 7>; // Fp 256-bit width vector variable shuffles. 582defm : SKXWriteResPair<WriteShuffle256, [SKXPort5], 3, [1], 1, 7>; // 256-bit width vector shuffles. 583defm : SKXWriteResPair<WriteVarShuffle256, [SKXPort5], 3, [1], 1, 7>; // 256-bit width vector variable shuffles. 584 585// Old microcoded instructions that nobody use. 586def : WriteRes<WriteMicrocoded, [SKXPort0156]> { let Latency = 100; } // def WriteMicrocoded : SchedWrite; 587 588// Fence instructions. 589def : WriteRes<WriteFence, [SKXPort23, SKXPort4]>; 590 591// Load/store MXCSR. 592def : WriteRes<WriteLDMXCSR, [SKXPort0,SKXPort23,SKXPort0156]> { let Latency = 7; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } 593def : WriteRes<WriteSTMXCSR, [SKXPort4,SKXPort5,SKXPort237]> { let Latency = 2; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } 594 595// Nop, not very useful expect it provides a model for nops! 596def : WriteRes<WriteNop, []>; 597 598//////////////////////////////////////////////////////////////////////////////// 599// Horizontal add/sub instructions. 600//////////////////////////////////////////////////////////////////////////////// 601 602defm : SKXWriteResPair<WriteFHAdd, [SKXPort5,SKXPort015], 6, [2,1], 3, 6>; 603defm : SKXWriteResPair<WriteFHAddY, [SKXPort5,SKXPort015], 6, [2,1], 3, 7>; 604defm : SKXWriteResPair<WritePHAdd, [SKXPort5,SKXPort05], 3, [2,1], 3, 5>; 605defm : SKXWriteResPair<WritePHAddX, [SKXPort5,SKXPort015], 3, [2,1], 3, 6>; 606defm : SKXWriteResPair<WritePHAddY, [SKXPort5,SKXPort015], 3, [2,1], 3, 7>; 607 608// Remaining instrs. 609 610def SKXWriteResGroup1 : SchedWriteRes<[SKXPort0]> { 611 let Latency = 1; 612 let NumMicroOps = 1; 613 let ResourceCycles = [1]; 614} 615def: InstRW<[SKXWriteResGroup1], (instregex "KAND(B|D|Q|W)rr", 616 "KANDN(B|D|Q|W)rr", 617 "KMOV(B|D|Q|W)kk", 618 "KNOT(B|D|Q|W)rr", 619 "KOR(B|D|Q|W)rr", 620 "KXNOR(B|D|Q|W)rr", 621 "KXOR(B|D|Q|W)rr", 622 "MMX_PADDS(B|W)irr", 623 "MMX_PADDUS(B|W)irr", 624 "MMX_PAVG(B|W)irr", 625 "MMX_PCMPEQ(B|D|W)irr", 626 "MMX_PCMPGT(B|D|W)irr", 627 "MMX_P(MAX|MIN)SWirr", 628 "MMX_P(MAX|MIN)UBirr", 629 "MMX_PSUBS(B|W)irr", 630 "MMX_PSUBUS(B|W)irr", 631 "VPMOVB2M(Z|Z128|Z256)rr", 632 "VPMOVD2M(Z|Z128|Z256)rr", 633 "VPMOVQ2M(Z|Z128|Z256)rr", 634 "VPMOVW2M(Z|Z128|Z256)rr")>; 635 636def SKXWriteResGroup3 : SchedWriteRes<[SKXPort5]> { 637 let Latency = 1; 638 let NumMicroOps = 1; 639 let ResourceCycles = [1]; 640} 641def: InstRW<[SKXWriteResGroup3], (instregex "COM(P?)_FST0r", 642 "KMOV(B|D|Q|W)kr", 643 "UCOM_F(P?)r")>; 644 645def SKXWriteResGroup4 : SchedWriteRes<[SKXPort6]> { 646 let Latency = 1; 647 let NumMicroOps = 1; 648 let ResourceCycles = [1]; 649} 650def: InstRW<[SKXWriteResGroup4], (instregex "JMP(16|32|64)r")>; 651 652def SKXWriteResGroup6 : SchedWriteRes<[SKXPort05]> { 653 let Latency = 1; 654 let NumMicroOps = 1; 655 let ResourceCycles = [1]; 656} 657def: InstRW<[SKXWriteResGroup6], (instrs FINCSTP, FNOP)>; 658 659def SKXWriteResGroup7 : SchedWriteRes<[SKXPort06]> { 660 let Latency = 1; 661 let NumMicroOps = 1; 662 let ResourceCycles = [1]; 663} 664def: InstRW<[SKXWriteResGroup7], (instrs CDQ, CQO, CLAC, STAC)>; 665 666def SKXWriteResGroup8 : SchedWriteRes<[SKXPort15]> { 667 let Latency = 1; 668 let NumMicroOps = 1; 669 let ResourceCycles = [1]; 670} 671def: InstRW<[SKXWriteResGroup8], (instregex "ANDN(32|64)rr")>; 672 673def SKXWriteResGroup9 : SchedWriteRes<[SKXPort015]> { 674 let Latency = 1; 675 let NumMicroOps = 1; 676 let ResourceCycles = [1]; 677} 678def: InstRW<[SKXWriteResGroup9], (instregex "VBLENDMPD(Z128|Z256)rr", 679 "VBLENDMPS(Z128|Z256)rr", 680 "VPADD(B|D|Q|W)(Y|Z|Z128|Z256)rr", 681 "(V?)PADD(B|D|Q|W)rr", 682 "VPBLENDD(Y?)rri", 683 "VPBLENDMB(Z128|Z256)rr", 684 "VPBLENDMD(Z128|Z256)rr", 685 "VPBLENDMQ(Z128|Z256)rr", 686 "VPBLENDMW(Z128|Z256)rr", 687 "VPSUB(B|D|Q|W)(Y|Z|Z128|Z256)rrk", 688 "VPTERNLOGD(Z|Z128|Z256)rri", 689 "VPTERNLOGQ(Z|Z128|Z256)rri")>; 690 691def SKXWriteResGroup10 : SchedWriteRes<[SKXPort0156]> { 692 let Latency = 1; 693 let NumMicroOps = 1; 694 let ResourceCycles = [1]; 695} 696def: InstRW<[SKXWriteResGroup10], (instrs CBW, CWDE, CDQE, 697 CMC, STC, 698 SGDT64m, 699 SIDT64m, 700 SMSW16m, 701 STRm, 702 SYSCALL)>; 703 704def SKXWriteResGroup11 : SchedWriteRes<[SKXPort4,SKXPort237]> { 705 let Latency = 1; 706 let NumMicroOps = 2; 707 let ResourceCycles = [1,1]; 708} 709def: InstRW<[SKXWriteResGroup11], (instrs FBSTPm, VMPTRSTm)>; 710def: InstRW<[SKXWriteResGroup11], (instregex "KMOV(B|D|Q|W)mk", 711 "ST_FP(32|64|80)m")>; 712 713def SKXWriteResGroup13 : SchedWriteRes<[SKXPort5]> { 714 let Latency = 2; 715 let NumMicroOps = 2; 716 let ResourceCycles = [2]; 717} 718def: InstRW<[SKXWriteResGroup13], (instrs MMX_MOVQ2DQrr)>; 719 720def SKXWriteResGroup14 : SchedWriteRes<[SKXPort05]> { 721 let Latency = 2; 722 let NumMicroOps = 2; 723 let ResourceCycles = [2]; 724} 725def: InstRW<[SKXWriteResGroup14], (instrs FDECSTP, 726 MMX_MOVDQ2Qrr)>; 727 728def SKXWriteResGroup17 : SchedWriteRes<[SKXPort0156]> { 729 let Latency = 2; 730 let NumMicroOps = 2; 731 let ResourceCycles = [2]; 732} 733def: InstRW<[SKXWriteResGroup17], (instrs LFENCE, 734 WAIT, 735 XGETBV)>; 736 737def SKXWriteResGroup20 : SchedWriteRes<[SKXPort6,SKXPort0156]> { 738 let Latency = 2; 739 let NumMicroOps = 2; 740 let ResourceCycles = [1,1]; 741} 742def: InstRW<[SKXWriteResGroup20], (instregex "CLFLUSH")>; 743 744def SKXWriteResGroup21 : SchedWriteRes<[SKXPort237,SKXPort0156]> { 745 let Latency = 2; 746 let NumMicroOps = 2; 747 let ResourceCycles = [1,1]; 748} 749def: InstRW<[SKXWriteResGroup21], (instrs SFENCE)>; 750 751def SKXWriteResGroup23 : SchedWriteRes<[SKXPort06,SKXPort0156]> { 752 let Latency = 2; 753 let NumMicroOps = 2; 754 let ResourceCycles = [1,1]; 755} 756def: InstRW<[SKXWriteResGroup23], (instrs CWD, 757 JCXZ, JECXZ, JRCXZ, 758 ADC8i8, SBB8i8, 759 ADC16i16, SBB16i16, 760 ADC32i32, SBB32i32, 761 ADC64i32, SBB64i32)>; 762 763def SKXWriteResGroup25 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort237]> { 764 let Latency = 2; 765 let NumMicroOps = 3; 766 let ResourceCycles = [1,1,1]; 767} 768def: InstRW<[SKXWriteResGroup25], (instrs FNSTCW16m)>; 769 770def SKXWriteResGroup27 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort15]> { 771 let Latency = 2; 772 let NumMicroOps = 3; 773 let ResourceCycles = [1,1,1]; 774} 775def: InstRW<[SKXWriteResGroup27], (instregex "MOVBE(16|32|64)mr")>; 776 777def SKXWriteResGroup28 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort0156]> { 778 let Latency = 2; 779 let NumMicroOps = 3; 780 let ResourceCycles = [1,1,1]; 781} 782def: InstRW<[SKXWriteResGroup28], (instrs PUSH16r, PUSH32r, PUSH64r, PUSH64i8, 783 STOSB, STOSL, STOSQ, STOSW)>; 784def: InstRW<[SKXWriteResGroup28], (instregex "PUSH(16|32|64)rmr")>; 785 786def SKXWriteResGroup29 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort15]> { 787 let Latency = 2; 788 let NumMicroOps = 5; 789 let ResourceCycles = [2,2,1]; 790} 791def: InstRW<[SKXWriteResGroup29], (instregex "VMOVDQU8Zmr(b?)")>; 792 793def SKXWriteResGroup30 : SchedWriteRes<[SKXPort0]> { 794 let Latency = 3; 795 let NumMicroOps = 1; 796 let ResourceCycles = [1]; 797} 798def: InstRW<[SKXWriteResGroup30], (instregex "KMOV(B|D|Q|W)rk", 799 "KORTEST(B|D|Q|W)rr", 800 "KTEST(B|D|Q|W)rr")>; 801 802def SKXWriteResGroup31 : SchedWriteRes<[SKXPort1]> { 803 let Latency = 3; 804 let NumMicroOps = 1; 805 let ResourceCycles = [1]; 806} 807def: InstRW<[SKXWriteResGroup31], (instregex "PDEP(32|64)rr", 808 "PEXT(32|64)rr")>; 809 810def SKXWriteResGroup32 : SchedWriteRes<[SKXPort5]> { 811 let Latency = 3; 812 let NumMicroOps = 1; 813 let ResourceCycles = [1]; 814} 815def: InstRW<[SKXWriteResGroup32], (instrs VPSADBWZrr)>; // TODO: 512-bit ops require ports 0/1 to be joined. 816def: InstRW<[SKXWriteResGroup32], (instregex "(ADD|SUB|SUBR)_(FPrST0|FST0r|FrST0)", 817 "KADD(B|D|Q|W)rr", 818 "KSHIFTL(B|D|Q|W)ri", 819 "KSHIFTR(B|D|Q|W)ri", 820 "KUNPCK(BW|DQ|WD)rr", 821 "VALIGND(Z|Z128|Z256)rri", 822 "VALIGNQ(Z|Z128|Z256)rri", 823 "VCMPPD(Z|Z128|Z256)rri", 824 "VCMPPS(Z|Z128|Z256)rri", 825 "VCMP(SD|SS)Zrr", 826 "VDBPSADBWZrri", // TODO: 512-bit ops require ports 0/1 to be joined. 827 "VFPCLASS(PD|PS)(Z|Z128|Z256)rr", 828 "VFPCLASS(SD|SS)Zrr", 829 "VPBROADCAST(B|W)rr", 830 "VPCMPB(Z|Z128|Z256)rri", 831 "VPCMPD(Z|Z128|Z256)rri", 832 "VPCMPEQ(B|D|Q|W)(Z|Z128|Z256)rr", 833 "VPCMPGT(B|D|Q|W)(Z|Z128|Z256)rr", 834 "VPCMPQ(Z|Z128|Z256)rri", 835 "VPCMPU(B|D|Q|W)(Z|Z128|Z256)rri", 836 "VPCMPW(Z|Z128|Z256)rri", 837 "VP(MAX|MIN)(S|U)Q(Z|Z128|Z256)rr", 838 "VPTEST(N?)M(B|D|Q|W)(Z|Z128|Z256)rr")>; 839 840def SKXWriteResGroup34 : SchedWriteRes<[SKXPort0,SKXPort0156]> { 841 let Latency = 3; 842 let NumMicroOps = 2; 843 let ResourceCycles = [1,1]; 844} 845def: InstRW<[SKXWriteResGroup34], (instrs FNSTSW16r)>; 846 847def SKXWriteResGroup37 : SchedWriteRes<[SKXPort0,SKXPort5]> { 848 let Latency = 3; 849 let NumMicroOps = 3; 850 let ResourceCycles = [1,2]; 851} 852def: InstRW<[SKXWriteResGroup37], (instregex "MMX_PH(ADD|SUB)SWrr")>; 853 854def SKXWriteResGroup38 : SchedWriteRes<[SKXPort5,SKXPort01]> { 855 let Latency = 3; 856 let NumMicroOps = 3; 857 let ResourceCycles = [2,1]; 858} 859def: InstRW<[SKXWriteResGroup38], (instregex "(V?)PH(ADD|SUB)SW(Y?)rr")>; 860 861def SKXWriteResGroup41 : SchedWriteRes<[SKXPort5,SKXPort0156]> { 862 let Latency = 3; 863 let NumMicroOps = 3; 864 let ResourceCycles = [2,1]; 865} 866def: InstRW<[SKXWriteResGroup41], (instrs MMX_PACKSSDWirr, 867 MMX_PACKSSWBirr, 868 MMX_PACKUSWBirr)>; 869 870def SKXWriteResGroup42 : SchedWriteRes<[SKXPort6,SKXPort0156]> { 871 let Latency = 3; 872 let NumMicroOps = 3; 873 let ResourceCycles = [1,2]; 874} 875def: InstRW<[SKXWriteResGroup42], (instregex "CLD")>; 876 877def SKXWriteResGroup43 : SchedWriteRes<[SKXPort237,SKXPort0156]> { 878 let Latency = 3; 879 let NumMicroOps = 3; 880 let ResourceCycles = [1,2]; 881} 882def: InstRW<[SKXWriteResGroup43], (instrs MFENCE)>; 883 884def SKXWriteResGroup44 : SchedWriteRes<[SKXPort06,SKXPort0156]> { 885 let Latency = 3; 886 let NumMicroOps = 3; 887 let ResourceCycles = [1,2]; 888} 889def: InstRW<[SKXWriteResGroup44], (instregex "RCL(8|16|32|64)r(1|i)", 890 "RCR(8|16|32|64)r(1|i)")>; 891 892def SKXWriteResGroup45 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort237]> { 893 let Latency = 3; 894 let NumMicroOps = 3; 895 let ResourceCycles = [1,1,1]; 896} 897def: InstRW<[SKXWriteResGroup45], (instrs FNSTSWm)>; 898 899def SKXWriteResGroup47 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort237,SKXPort0156]> { 900 let Latency = 3; 901 let NumMicroOps = 4; 902 let ResourceCycles = [1,1,1,1]; 903} 904def: InstRW<[SKXWriteResGroup47], (instregex "CALL(16|32|64)r")>; 905 906def SKXWriteResGroup48 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort06,SKXPort0156]> { 907 let Latency = 3; 908 let NumMicroOps = 4; 909 let ResourceCycles = [1,1,1,1]; 910} 911def: InstRW<[SKXWriteResGroup48], (instrs CALL64pcrel32)>; 912 913def SKXWriteResGroup49 : SchedWriteRes<[SKXPort0]> { 914 let Latency = 4; 915 let NumMicroOps = 1; 916 let ResourceCycles = [1]; 917} 918def: InstRW<[SKXWriteResGroup49], (instregex "MUL_(FPrST0|FST0r|FrST0)")>; 919 920def SKXWriteResGroup50 : SchedWriteRes<[SKXPort01]> { 921 let Latency = 4; 922 let NumMicroOps = 1; 923 let ResourceCycles = [1]; 924} 925def: InstRW<[SKXWriteResGroup50], (instregex "VCVTDQ2PS(Y|Z128|Z256)rr", 926 "(V?)CVTDQ2PSrr", 927 "VCVTPD2QQ(Z128|Z256)rr", 928 "VCVTPD2UQQ(Z128|Z256)rr", 929 "VCVTPS2DQ(Y|Z128|Z256)rr", 930 "(V?)CVTPS2DQrr", 931 "VCVTPS2UDQ(Z128|Z256)rr", 932 "VCVTQQ2PD(Z128|Z256)rr", 933 "VCVTTPD2QQ(Z128|Z256)rr", 934 "VCVTTPD2UQQ(Z128|Z256)rr", 935 "VCVTTPS2DQ(Z128|Z256)rr", 936 "(V?)CVTTPS2DQrr", 937 "VCVTTPS2UDQ(Z128|Z256)rr", 938 "VCVTUDQ2PS(Z128|Z256)rr", 939 "VCVTUQQ2PD(Z128|Z256)rr")>; 940 941def SKXWriteResGroup50z : SchedWriteRes<[SKXPort05]> { 942 let Latency = 4; 943 let NumMicroOps = 1; 944 let ResourceCycles = [1]; 945} 946def: InstRW<[SKXWriteResGroup50z], (instrs VCVTDQ2PSZrr, 947 VCVTPD2QQZrr, 948 VCVTPD2UQQZrr, 949 VCVTPS2DQZrr, 950 VCVTPS2UDQZrr, 951 VCVTQQ2PDZrr, 952 VCVTTPD2QQZrr, 953 VCVTTPD2UQQZrr, 954 VCVTTPS2DQZrr, 955 VCVTTPS2UDQZrr, 956 VCVTUDQ2PSZrr, 957 VCVTUQQ2PDZrr)>; 958 959def SKXWriteResGroup51 : SchedWriteRes<[SKXPort5]> { 960 let Latency = 4; 961 let NumMicroOps = 2; 962 let ResourceCycles = [2]; 963} 964def: InstRW<[SKXWriteResGroup51], (instregex "VEXPANDPD(Z|Z128|Z256)rr", 965 "VEXPANDPS(Z|Z128|Z256)rr", 966 "VPEXPANDD(Z|Z128|Z256)rr", 967 "VPEXPANDQ(Z|Z128|Z256)rr", 968 "VPMOVDB(Z|Z128|Z256)rr", 969 "VPMOVDW(Z|Z128|Z256)rr", 970 "VPMOVQB(Z|Z128|Z256)rr", 971 "VPMOVQW(Z|Z128|Z256)rr", 972 "VPMOVSDB(Z|Z128|Z256)rr", 973 "VPMOVSDW(Z|Z128|Z256)rr", 974 "VPMOVSQB(Z|Z128|Z256)rr", 975 "VPMOVSQD(Z|Z128|Z256)rr", 976 "VPMOVSQW(Z|Z128|Z256)rr", 977 "VPMOVSWB(Z|Z128|Z256)rr", 978 "VPMOVUSDB(Z|Z128|Z256)rr", 979 "VPMOVUSDW(Z|Z128|Z256)rr", 980 "VPMOVUSQB(Z|Z128|Z256)rr", 981 "VPMOVUSQD(Z|Z128|Z256)rr", 982 "VPMOVUSWB(Z|Z128|Z256)rr", 983 "VPMOVWB(Z|Z128|Z256)rr")>; 984 985def SKXWriteResGroup54 : SchedWriteRes<[SKXPort4,SKXPort5,SKXPort237]> { 986 let Latency = 4; 987 let NumMicroOps = 3; 988 let ResourceCycles = [1,1,1]; 989} 990def: InstRW<[SKXWriteResGroup54], (instregex "IST(T?)_FP(16|32|64)m", 991 "IST_F(16|32)m", 992 "VPMOVQD(Z|Z128|Z256)mr(b?)")>; 993 994def SKXWriteResGroup55 : SchedWriteRes<[SKXPort0156]> { 995 let Latency = 4; 996 let NumMicroOps = 4; 997 let ResourceCycles = [4]; 998} 999def: InstRW<[SKXWriteResGroup55], (instrs FNCLEX)>; 1000 1001def SKXWriteResGroup56 : SchedWriteRes<[]> { 1002 let Latency = 0; 1003 let NumMicroOps = 4; 1004 let ResourceCycles = []; 1005} 1006def: InstRW<[SKXWriteResGroup56], (instrs VZEROUPPER)>; 1007 1008def SKXWriteResGroup57 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort0156]> { 1009 let Latency = 4; 1010 let NumMicroOps = 4; 1011 let ResourceCycles = [1,1,2]; 1012} 1013def: InstRW<[SKXWriteResGroup57], (instregex "LAR(16|32|64)rr")>; 1014 1015def SKXWriteResGroup58 : SchedWriteRes<[SKXPort23]> { 1016 let Latency = 5; 1017 let NumMicroOps = 1; 1018 let ResourceCycles = [1]; 1019} 1020def: InstRW<[SKXWriteResGroup58], (instregex "MOVSX(16|32|64)rm(8|16|32)", 1021 "MOVZX(16|32|64)rm(8|16)", 1022 "(V?)MOVDDUPrm")>; // TODO: Should this be SKXWriteResGroup71? 1023 1024def SKXWriteResGroup61 : SchedWriteRes<[SKXPort5,SKXPort015]> { 1025 let Latency = 5; 1026 let NumMicroOps = 2; 1027 let ResourceCycles = [1,1]; 1028} 1029def: InstRW<[SKXWriteResGroup61], (instregex "MMX_CVT(T?)PD2PIirr", 1030 "MMX_CVT(T?)PS2PIirr", 1031 "VCVTDQ2PDZ128rr", 1032 "VCVTPD2DQZ128rr", 1033 "(V?)CVT(T?)PD2DQrr", 1034 "VCVTPD2PSZ128rr", 1035 "(V?)CVTPD2PSrr", 1036 "VCVTPD2UDQZ128rr", 1037 "VCVTPS2PDZ128rr", 1038 "(V?)CVTPS2PDrr", 1039 "VCVTPS2QQZ128rr", 1040 "VCVTPS2UQQZ128rr", 1041 "VCVTQQ2PSZ128rr", 1042 "(V?)CVTSD2SS(Z?)rr", 1043 "(V?)CVTSI(64)?2SDrr", 1044 "VCVTSI2SSZrr", 1045 "(V?)CVTSI2SSrr", 1046 "VCVTSI(64)?2SDZrr", 1047 "VCVTSS2SDZrr", 1048 "(V?)CVTSS2SDrr", 1049 "VCVTTPD2DQZ128rr", 1050 "VCVTTPD2UDQZ128rr", 1051 "VCVTTPS2QQZ128rr", 1052 "VCVTTPS2UQQZ128rr", 1053 "VCVTUDQ2PDZ128rr", 1054 "VCVTUQQ2PSZ128rr", 1055 "VCVTUSI2SSZrr", 1056 "VCVTUSI(64)?2SDZrr")>; 1057 1058def SKXWriteResGroup62 : SchedWriteRes<[SKXPort5,SKXPort015]> { 1059 let Latency = 5; 1060 let NumMicroOps = 3; 1061 let ResourceCycles = [2,1]; 1062} 1063def: InstRW<[SKXWriteResGroup62], (instregex "VPCONFLICTQZ128rr")>; 1064 1065def SKXWriteResGroup63 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort06]> { 1066 let Latency = 5; 1067 let NumMicroOps = 3; 1068 let ResourceCycles = [1,1,1]; 1069} 1070def: InstRW<[SKXWriteResGroup63], (instregex "STR(16|32|64)r")>; 1071 1072def SKXWriteResGroup65 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort015]> { 1073 let Latency = 5; 1074 let NumMicroOps = 3; 1075 let ResourceCycles = [1,1,1]; 1076} 1077def: InstRW<[SKXWriteResGroup65], (instregex "VCVTPS2PHZ128mr(b?)", 1078 "VCVTPS2PHZ256mr(b?)", 1079 "VCVTPS2PHZmr(b?)")>; 1080 1081def SKXWriteResGroup66 : SchedWriteRes<[SKXPort4,SKXPort5,SKXPort237]> { 1082 let Latency = 5; 1083 let NumMicroOps = 4; 1084 let ResourceCycles = [1,2,1]; 1085} 1086def: InstRW<[SKXWriteResGroup66], (instregex "VPMOVDB(Z|Z128|Z256)mr(b?)", 1087 "VPMOVDW(Z|Z128|Z256)mr(b?)", 1088 "VPMOVQB(Z|Z128|Z256)mr(b?)", 1089 "VPMOVQW(Z|Z128|Z256)mr(b?)", 1090 "VPMOVSDB(Z|Z128|Z256)mr(b?)", 1091 "VPMOVSDW(Z|Z128|Z256)mr(b?)", 1092 "VPMOVSQB(Z|Z128|Z256)mr(b?)", 1093 "VPMOVSQD(Z|Z128|Z256)mr(b?)", 1094 "VPMOVSQW(Z|Z128|Z256)mr(b?)", 1095 "VPMOVSWB(Z|Z128|Z256)mr(b?)", 1096 "VPMOVUSDB(Z|Z128|Z256)mr(b?)", 1097 "VPMOVUSDW(Z|Z128|Z256)mr(b?)", 1098 "VPMOVUSQB(Z|Z128|Z256)mr(b?)", 1099 "VPMOVUSQD(Z|Z128|Z256)mr(b?)", 1100 "VPMOVUSQW(Z|Z128|Z256)mr(b?)", 1101 "VPMOVUSWB(Z|Z128|Z256)mr(b?)", 1102 "VPMOVWB(Z|Z128|Z256)mr(b?)")>; 1103 1104def SKXWriteResGroup67 : SchedWriteRes<[SKXPort06,SKXPort0156]> { 1105 let Latency = 5; 1106 let NumMicroOps = 5; 1107 let ResourceCycles = [1,4]; 1108} 1109def: InstRW<[SKXWriteResGroup67], (instrs XSETBV)>; 1110 1111def SKXWriteResGroup69 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort0156]> { 1112 let Latency = 5; 1113 let NumMicroOps = 6; 1114 let ResourceCycles = [1,1,4]; 1115} 1116def: InstRW<[SKXWriteResGroup69], (instregex "PUSHF(16|64)")>; 1117 1118def SKXWriteResGroup71 : SchedWriteRes<[SKXPort23]> { 1119 let Latency = 6; 1120 let NumMicroOps = 1; 1121 let ResourceCycles = [1]; 1122} 1123def: InstRW<[SKXWriteResGroup71], (instrs VBROADCASTSSrm, 1124 VPBROADCASTDrm, 1125 VPBROADCASTQrm, 1126 VMOVSHDUPrm, 1127 VMOVSLDUPrm, 1128 MOVSHDUPrm, 1129 MOVSLDUPrm)>; 1130 1131def SKXWriteResGroup72 : SchedWriteRes<[SKXPort5]> { 1132 let Latency = 6; 1133 let NumMicroOps = 2; 1134 let ResourceCycles = [2]; 1135} 1136def: InstRW<[SKXWriteResGroup72], (instrs MMX_CVTPI2PSirr)>; 1137def: InstRW<[SKXWriteResGroup72], (instregex "VCOMPRESSPD(Z|Z128|Z256)rr", 1138 "VCOMPRESSPS(Z|Z128|Z256)rr", 1139 "VPCOMPRESSD(Z|Z128|Z256)rr", 1140 "VPCOMPRESSQ(Z|Z128|Z256)rr", 1141 "VPERMW(Z|Z128|Z256)rr")>; 1142 1143def SKXWriteResGroup73 : SchedWriteRes<[SKXPort0,SKXPort23]> { 1144 let Latency = 6; 1145 let NumMicroOps = 2; 1146 let ResourceCycles = [1,1]; 1147} 1148def: InstRW<[SKXWriteResGroup73], (instrs MMX_PADDSBirm, 1149 MMX_PADDSWirm, 1150 MMX_PADDUSBirm, 1151 MMX_PADDUSWirm, 1152 MMX_PAVGBirm, 1153 MMX_PAVGWirm, 1154 MMX_PCMPEQBirm, 1155 MMX_PCMPEQDirm, 1156 MMX_PCMPEQWirm, 1157 MMX_PCMPGTBirm, 1158 MMX_PCMPGTDirm, 1159 MMX_PCMPGTWirm, 1160 MMX_PMAXSWirm, 1161 MMX_PMAXUBirm, 1162 MMX_PMINSWirm, 1163 MMX_PMINUBirm, 1164 MMX_PSUBSBirm, 1165 MMX_PSUBSWirm, 1166 MMX_PSUBUSBirm, 1167 MMX_PSUBUSWirm)>; 1168 1169def SKXWriteResGroup76 : SchedWriteRes<[SKXPort6,SKXPort23]> { 1170 let Latency = 6; 1171 let NumMicroOps = 2; 1172 let ResourceCycles = [1,1]; 1173} 1174def: InstRW<[SKXWriteResGroup76], (instrs FARJMP64)>; 1175def: InstRW<[SKXWriteResGroup76], (instregex "JMP(16|32|64)m")>; 1176 1177def SKXWriteResGroup79 : SchedWriteRes<[SKXPort23,SKXPort15]> { 1178 let Latency = 6; 1179 let NumMicroOps = 2; 1180 let ResourceCycles = [1,1]; 1181} 1182def: InstRW<[SKXWriteResGroup79], (instregex "ANDN(32|64)rm", 1183 "MOVBE(16|32|64)rm")>; 1184 1185def SKXWriteResGroup80 : SchedWriteRes<[SKXPort23,SKXPort015]> { 1186 let Latency = 6; 1187 let NumMicroOps = 2; 1188 let ResourceCycles = [1,1]; 1189} 1190def: InstRW<[SKXWriteResGroup80], (instregex "VMOV(64to|QI2)PQIZrm(b?)")>; 1191def: InstRW<[SKXWriteResGroup80], (instrs VMOVDI2PDIZrm)>; 1192 1193def SKXWriteResGroup81 : SchedWriteRes<[SKXPort23,SKXPort0156]> { 1194 let Latency = 6; 1195 let NumMicroOps = 2; 1196 let ResourceCycles = [1,1]; 1197} 1198def: InstRW<[SKXWriteResGroup81], (instrs POP16r, POP32r, POP64r)>; 1199def: InstRW<[SKXWriteResGroup81], (instregex "POP(16|32|64)rmr")>; 1200 1201def SKXWriteResGroup82 : SchedWriteRes<[SKXPort5,SKXPort015]> { 1202 let Latency = 6; 1203 let NumMicroOps = 3; 1204 let ResourceCycles = [2,1]; 1205} 1206def: InstRW<[SKXWriteResGroup82], (instregex "(V?)CVTSI642SSrr", 1207 "VCVTSI642SSZrr", 1208 "VCVTUSI642SSZrr")>; 1209 1210def SKXWriteResGroup84 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort06,SKXPort0156]> { 1211 let Latency = 6; 1212 let NumMicroOps = 4; 1213 let ResourceCycles = [1,1,1,1]; 1214} 1215def: InstRW<[SKXWriteResGroup84], (instregex "SLDT(16|32|64)r")>; 1216 1217def SKXWriteResGroup86 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06]> { 1218 let Latency = 6; 1219 let NumMicroOps = 4; 1220 let ResourceCycles = [1,1,1,1]; 1221} 1222def: InstRW<[SKXWriteResGroup86], (instregex "SAR(8|16|32|64)m(1|i)", 1223 "SHL(8|16|32|64)m(1|i)", 1224 "SHR(8|16|32|64)m(1|i)")>; 1225 1226def SKXWriteResGroup87 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort0156]> { 1227 let Latency = 6; 1228 let NumMicroOps = 4; 1229 let ResourceCycles = [1,1,1,1]; 1230} 1231def: InstRW<[SKXWriteResGroup87], (instregex "POP(16|32|64)rmm", 1232 "PUSH(16|32|64)rmm")>; 1233 1234def SKXWriteResGroup88 : SchedWriteRes<[SKXPort6,SKXPort0156]> { 1235 let Latency = 6; 1236 let NumMicroOps = 6; 1237 let ResourceCycles = [1,5]; 1238} 1239def: InstRW<[SKXWriteResGroup88], (instrs STD)>; 1240 1241def SKXWriteResGroup89 : SchedWriteRes<[SKXPort23]> { 1242 let Latency = 7; 1243 let NumMicroOps = 1; 1244 let ResourceCycles = [1]; 1245} 1246def: InstRW<[SKXWriteResGroup89], (instregex "LD_F(32|64|80)m")>; 1247def: InstRW<[SKXWriteResGroup89], (instrs VBROADCASTF128, 1248 VBROADCASTI128, 1249 VBROADCASTSDYrm, 1250 VBROADCASTSSYrm, 1251 VMOVDDUPYrm, 1252 VMOVSHDUPYrm, 1253 VMOVSLDUPYrm, 1254 VPBROADCASTDYrm, 1255 VPBROADCASTQYrm)>; 1256 1257def SKXWriteResGroup90 : SchedWriteRes<[SKXPort01,SKXPort5]> { 1258 let Latency = 7; 1259 let NumMicroOps = 2; 1260 let ResourceCycles = [1,1]; 1261} 1262def: InstRW<[SKXWriteResGroup90], (instrs VCVTDQ2PDYrr)>; 1263 1264def SKXWriteResGroup92 : SchedWriteRes<[SKXPort5,SKXPort23]> { 1265 let Latency = 7; 1266 let NumMicroOps = 2; 1267 let ResourceCycles = [1,1]; 1268} 1269def: InstRW<[SKXWriteResGroup92], (instregex "VMOVSDZrm(b?)", 1270 "VMOVSSZrm(b?)")>; 1271 1272def SKXWriteResGroup92a : SchedWriteRes<[SKXPort5,SKXPort23]> { 1273 let Latency = 6; 1274 let NumMicroOps = 2; 1275 let ResourceCycles = [1,1]; 1276} 1277def: InstRW<[SKXWriteResGroup92a], (instregex "(V?)PMOV(SX|ZX)BDrm", 1278 "(V?)PMOV(SX|ZX)BQrm", 1279 "(V?)PMOV(SX|ZX)BWrm", 1280 "(V?)PMOV(SX|ZX)DQrm", 1281 "(V?)PMOV(SX|ZX)WDrm", 1282 "(V?)PMOV(SX|ZX)WQrm")>; 1283 1284def SKXWriteResGroup93 : SchedWriteRes<[SKXPort5,SKXPort015]> { 1285 let Latency = 7; 1286 let NumMicroOps = 2; 1287 let ResourceCycles = [1,1]; 1288} 1289def: InstRW<[SKXWriteResGroup93], (instregex "VCVTDQ2PDZ256rr", 1290 "VCVTPD2DQ(Y|Z256)rr", 1291 "VCVTPD2PS(Y|Z256)rr", 1292 "VCVTPD2UDQZ256rr", 1293 "VCVTPS2PD(Y|Z256)rr", 1294 "VCVTPS2QQZ256rr", 1295 "VCVTPS2UQQZ256rr", 1296 "VCVTQQ2PSZ256rr", 1297 "VCVTTPD2DQ(Y|Z256)rr", 1298 "VCVTTPD2UDQZ256rr", 1299 "VCVTTPS2QQZ256rr", 1300 "VCVTTPS2UQQZ256rr", 1301 "VCVTUDQ2PDZ256rr", 1302 "VCVTUQQ2PSZ256rr")>; 1303 1304def SKXWriteResGroup93z : SchedWriteRes<[SKXPort5,SKXPort05]> { 1305 let Latency = 7; 1306 let NumMicroOps = 2; 1307 let ResourceCycles = [1,1]; 1308} 1309def: InstRW<[SKXWriteResGroup93z], (instrs VCVTDQ2PDZrr, 1310 VCVTPD2DQZrr, 1311 VCVTPD2PSZrr, 1312 VCVTPD2UDQZrr, 1313 VCVTPS2PDZrr, 1314 VCVTPS2QQZrr, 1315 VCVTPS2UQQZrr, 1316 VCVTQQ2PSZrr, 1317 VCVTTPD2DQZrr, 1318 VCVTTPD2UDQZrr, 1319 VCVTTPS2QQZrr, 1320 VCVTTPS2UQQZrr, 1321 VCVTUDQ2PDZrr, 1322 VCVTUQQ2PSZrr)>; 1323 1324def SKXWriteResGroup95 : SchedWriteRes<[SKXPort23,SKXPort015]> { 1325 let Latency = 7; 1326 let NumMicroOps = 2; 1327 let ResourceCycles = [1,1]; 1328} 1329def: InstRW<[SKXWriteResGroup95], (instrs VMOVNTDQAZ128rm, 1330 VPBLENDDrmi)>; 1331def: InstRW<[SKXWriteResGroup95, ReadAfterVecXLd], 1332 (instregex "VBLENDMPDZ128rm(b?)", 1333 "VBLENDMPSZ128rm(b?)", 1334 "VBROADCASTI32X2Z128m(b?)", 1335 "VBROADCASTSSZ128m(b?)", 1336 "VINSERT(F|I)128rm", 1337 "VMOVAPDZ128rm(b?)", 1338 "VMOVAPSZ128rm(b?)", 1339 "VMOVDDUPZ128rm(b?)", 1340 "VMOVDQA32Z128rm(b?)", 1341 "VMOVDQA64Z128rm(b?)", 1342 "VMOVDQU16Z128rm(b?)", 1343 "VMOVDQU32Z128rm(b?)", 1344 "VMOVDQU64Z128rm(b?)", 1345 "VMOVDQU8Z128rm(b?)", 1346 "VMOVSHDUPZ128rm(b?)", 1347 "VMOVSLDUPZ128rm(b?)", 1348 "VMOVUPDZ128rm(b?)", 1349 "VMOVUPSZ128rm(b?)", 1350 "VPADD(B|D|Q|W)Z128rm(b?)", 1351 "(V?)PADD(B|D|Q|W)rm", 1352 "VPBLENDM(B|D|Q|W)Z128rm(b?)", 1353 "VPBROADCASTDZ128m(b?)", 1354 "VPBROADCASTQZ128m(b?)", 1355 "VPSUB(B|D|Q|W)Z128rm(b?)", 1356 "(V?)PSUB(B|D|Q|W)rm", 1357 "VPTERNLOGDZ128rm(b?)i", 1358 "VPTERNLOGQZ128rm(b?)i")>; 1359 1360def SKXWriteResGroup96 : SchedWriteRes<[SKXPort5,SKXPort23]> { 1361 let Latency = 7; 1362 let NumMicroOps = 3; 1363 let ResourceCycles = [2,1]; 1364} 1365def: InstRW<[SKXWriteResGroup96], (instrs MMX_PACKSSDWirm, 1366 MMX_PACKSSWBirm, 1367 MMX_PACKUSWBirm)>; 1368 1369def SKXWriteResGroup97 : SchedWriteRes<[SKXPort5,SKXPort015]> { 1370 let Latency = 7; 1371 let NumMicroOps = 3; 1372 let ResourceCycles = [2,1]; 1373} 1374def: InstRW<[SKXWriteResGroup97], (instregex "VPERMI2W128rr", 1375 "VPERMI2W256rr", 1376 "VPERMI2Wrr", 1377 "VPERMT2W128rr", 1378 "VPERMT2W256rr", 1379 "VPERMT2Wrr")>; 1380 1381def SKXWriteResGroup99 : SchedWriteRes<[SKXPort23,SKXPort0156]> { 1382 let Latency = 7; 1383 let NumMicroOps = 3; 1384 let ResourceCycles = [1,2]; 1385} 1386def: InstRW<[SKXWriteResGroup99], (instrs LEAVE, LEAVE64, 1387 SCASB, SCASL, SCASQ, SCASW)>; 1388 1389def SKXWriteResGroup100 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort015]> { 1390 let Latency = 7; 1391 let NumMicroOps = 3; 1392 let ResourceCycles = [1,1,1]; 1393} 1394def: InstRW<[SKXWriteResGroup100], (instregex "VCVTSS2USI64Zrr", 1395 "(V?)CVTSS2SI64(Z?)rr", 1396 "(V?)CVTTSS2SI64(Z?)rr", 1397 "VCVTTSS2USI64Zrr")>; 1398 1399def SKXWriteResGroup101 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort05]> { 1400 let Latency = 7; 1401 let NumMicroOps = 3; 1402 let ResourceCycles = [1,1,1]; 1403} 1404def: InstRW<[SKXWriteResGroup101], (instrs FLDCW16m)>; 1405 1406def SKXWriteResGroup103 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort0156]> { 1407 let Latency = 7; 1408 let NumMicroOps = 3; 1409 let ResourceCycles = [1,1,1]; 1410} 1411def: InstRW<[SKXWriteResGroup103], (instregex "KMOV(B|D|Q|W)km")>; 1412 1413def SKXWriteResGroup104 : SchedWriteRes<[SKXPort6,SKXPort23,SKXPort0156]> { 1414 let Latency = 7; 1415 let NumMicroOps = 3; 1416 let ResourceCycles = [1,1,1]; 1417} 1418def: InstRW<[SKXWriteResGroup104], (instrs LRETQ, RETQ)>; 1419 1420def SKXWriteResGroup106 : SchedWriteRes<[SKXPort4,SKXPort5,SKXPort237]> { 1421 let Latency = 7; 1422 let NumMicroOps = 4; 1423 let ResourceCycles = [1,2,1]; 1424} 1425def: InstRW<[SKXWriteResGroup106], (instregex "VCOMPRESSPD(Z|Z128|Z256)mr(b?)", 1426 "VCOMPRESSPS(Z|Z128|Z256)mr(b?)", 1427 "VPCOMPRESSD(Z|Z128|Z256)mr(b?)", 1428 "VPCOMPRESSQ(Z|Z128|Z256)mr(b?)")>; 1429 1430def SKXWriteResGroup107 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06]> { 1431 let Latency = 7; 1432 let NumMicroOps = 5; 1433 let ResourceCycles = [1,1,1,2]; 1434} 1435def: InstRW<[SKXWriteResGroup107], (instregex "ROL(8|16|32|64)m(1|i)", 1436 "ROR(8|16|32|64)m(1|i)")>; 1437 1438def SKXWriteResGroup107_1 : SchedWriteRes<[SKXPort06]> { 1439 let Latency = 2; 1440 let NumMicroOps = 2; 1441 let ResourceCycles = [2]; 1442} 1443def: InstRW<[SKXWriteResGroup107_1], (instrs ROL8r1, ROL16r1, ROL32r1, ROL64r1, 1444 ROR8r1, ROR16r1, ROR32r1, ROR64r1)>; 1445 1446def SKXWriteResGroup108 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort0156]> { 1447 let Latency = 7; 1448 let NumMicroOps = 5; 1449 let ResourceCycles = [1,1,1,2]; 1450} 1451def: InstRW<[SKXWriteResGroup108], (instregex "XADD(8|16|32|64)rm")>; 1452 1453def SKXWriteResGroup109 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort23,SKXPort237,SKXPort0156]> { 1454 let Latency = 7; 1455 let NumMicroOps = 5; 1456 let ResourceCycles = [1,1,1,1,1]; 1457} 1458def: InstRW<[SKXWriteResGroup109], (instregex "CALL(16|32|64)m")>; 1459def: InstRW<[SKXWriteResGroup109], (instrs FARCALL64)>; 1460 1461def SKXWriteResGroup110 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort237,SKXPort0156]> { 1462 let Latency = 7; 1463 let NumMicroOps = 7; 1464 let ResourceCycles = [1,2,2,2]; 1465} 1466def: InstRW<[SKXWriteResGroup110], (instrs VPSCATTERDQZ128mr, 1467 VPSCATTERQQZ128mr, 1468 VSCATTERDPDZ128mr, 1469 VSCATTERQPDZ128mr)>; 1470 1471def SKXWriteResGroup111 : SchedWriteRes<[SKXPort6,SKXPort06,SKXPort15,SKXPort0156]> { 1472 let Latency = 7; 1473 let NumMicroOps = 7; 1474 let ResourceCycles = [1,3,1,2]; 1475} 1476def: InstRW<[SKXWriteResGroup111], (instrs LOOP)>; 1477 1478def SKXWriteResGroup112 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort237,SKXPort0156]> { 1479 let Latency = 7; 1480 let NumMicroOps = 11; 1481 let ResourceCycles = [1,4,4,2]; 1482} 1483def: InstRW<[SKXWriteResGroup112], (instrs VPSCATTERDQZ256mr, 1484 VPSCATTERQQZ256mr, 1485 VSCATTERDPDZ256mr, 1486 VSCATTERQPDZ256mr)>; 1487 1488def SKXWriteResGroup113 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort237,SKXPort0156]> { 1489 let Latency = 7; 1490 let NumMicroOps = 19; 1491 let ResourceCycles = [1,8,8,2]; 1492} 1493def: InstRW<[SKXWriteResGroup113], (instrs VPSCATTERDQZmr, 1494 VPSCATTERQQZmr, 1495 VSCATTERDPDZmr, 1496 VSCATTERQPDZmr)>; 1497 1498def SKXWriteResGroup114 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> { 1499 let Latency = 7; 1500 let NumMicroOps = 36; 1501 let ResourceCycles = [1,16,1,16,2]; 1502} 1503def: InstRW<[SKXWriteResGroup114], (instrs VSCATTERDPSZmr)>; 1504 1505def SKXWriteResGroup118 : SchedWriteRes<[SKXPort1,SKXPort23]> { 1506 let Latency = 8; 1507 let NumMicroOps = 2; 1508 let ResourceCycles = [1,1]; 1509} 1510def: InstRW<[SKXWriteResGroup118], (instregex "PDEP(32|64)rm", 1511 "PEXT(32|64)rm")>; 1512 1513def SKXWriteResGroup119 : SchedWriteRes<[SKXPort5,SKXPort23]> { 1514 let Latency = 8; 1515 let NumMicroOps = 2; 1516 let ResourceCycles = [1,1]; 1517} 1518def: InstRW<[SKXWriteResGroup119], (instregex "FCOM(P?)(32|64)m", 1519 "VFPCLASSSDZrm(b?)", 1520 "VPBROADCASTB(Z|Z256)m(b?)", 1521 "VPBROADCASTW(Z|Z256)m(b?)")>; 1522def: InstRW<[SKXWriteResGroup119], (instrs VPBROADCASTBYrm, 1523 VPBROADCASTWYrm, 1524 VPMOVSXBDYrm, 1525 VPMOVSXBQYrm, 1526 VPMOVSXWQYrm)>; 1527 1528def SKXWriteResGroup121 : SchedWriteRes<[SKXPort23,SKXPort015]> { 1529 let Latency = 8; 1530 let NumMicroOps = 2; 1531 let ResourceCycles = [1,1]; 1532} 1533def: InstRW<[SKXWriteResGroup121], (instrs VMOVNTDQAZ256rm, 1534 VPBLENDDYrmi)>; 1535def: InstRW<[SKXWriteResGroup121, ReadAfterVecYLd], 1536 (instregex "VBLENDMPD(Z|Z256)rm(b?)", 1537 "VBLENDMPS(Z|Z256)rm(b?)", 1538 "VBROADCASTF32X2Z256m(b?)", 1539 "VBROADCASTF32X2Zm(b?)", 1540 "VBROADCASTF32X4Z256rm(b?)", 1541 "VBROADCASTF32X4rm(b?)", 1542 "VBROADCASTF32X8rm(b?)", 1543 "VBROADCASTF64X2Z128rm(b?)", 1544 "VBROADCASTF64X2rm(b?)", 1545 "VBROADCASTF64X4rm(b?)", 1546 "VBROADCASTI32X2Z256m(b?)", 1547 "VBROADCASTI32X2Zm(b?)", 1548 "VBROADCASTI32X4Z256rm(b?)", 1549 "VBROADCASTI32X4rm(b?)", 1550 "VBROADCASTI32X8rm(b?)", 1551 "VBROADCASTI64X2Z128rm(b?)", 1552 "VBROADCASTI64X2rm(b?)", 1553 "VBROADCASTI64X4rm(b?)", 1554 "VBROADCASTSD(Z|Z256)m(b?)", 1555 "VBROADCASTSS(Z|Z256)m(b?)", 1556 "VINSERTF32x4(Z|Z256)rm(b?)", 1557 "VINSERTF32x8Zrm(b?)", 1558 "VINSERTF64x2(Z|Z256)rm(b?)", 1559 "VINSERTF64x4Zrm(b?)", 1560 "VINSERTI32x4(Z|Z256)rm(b?)", 1561 "VINSERTI32x8Zrm(b?)", 1562 "VINSERTI64x2(Z|Z256)rm(b?)", 1563 "VINSERTI64x4Zrm(b?)", 1564 "VMOVAPD(Z|Z256)rm(b?)", 1565 "VMOVAPS(Z|Z256)rm(b?)", 1566 "VMOVDDUP(Z|Z256)rm(b?)", 1567 "VMOVDQA32(Z|Z256)rm(b?)", 1568 "VMOVDQA64(Z|Z256)rm(b?)", 1569 "VMOVDQU16(Z|Z256)rm(b?)", 1570 "VMOVDQU32(Z|Z256)rm(b?)", 1571 "VMOVDQU64(Z|Z256)rm(b?)", 1572 "VMOVDQU8(Z|Z256)rm(b?)", 1573 "VMOVSHDUP(Z|Z256)rm(b?)", 1574 "VMOVSLDUP(Z|Z256)rm(b?)", 1575 "VMOVUPD(Z|Z256)rm(b?)", 1576 "VMOVUPS(Z|Z256)rm(b?)", 1577 "VPADD(B|D|Q|W)Yrm", 1578 "VPADD(B|D|Q|W)(Z|Z256)rm(b?)", 1579 "VPBLENDM(B|D|Q|W)(Z|Z256)rm(b?)", 1580 "VPBROADCASTD(Z|Z256)m(b?)", 1581 "VPBROADCASTQ(Z|Z256)m(b?)", 1582 "VPSUB(B|D|Q|W)Yrm", 1583 "VPSUB(B|D|Q|W)(Z|Z256)rm(b?)", 1584 "VPTERNLOGD(Z|Z256)rm(b?)i", 1585 "VPTERNLOGQ(Z|Z256)rm(b?)i")>; 1586 1587def SKXWriteResGroup123 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> { 1588 let Latency = 8; 1589 let NumMicroOps = 4; 1590 let ResourceCycles = [1,2,1]; 1591} 1592def: InstRW<[SKXWriteResGroup123], (instregex "MMX_PH(ADD|SUB)SWrm")>; 1593 1594def SKXWriteResGroup127 : SchedWriteRes<[SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> { 1595 let Latency = 8; 1596 let NumMicroOps = 5; 1597 let ResourceCycles = [1,1,1,2]; 1598} 1599def: InstRW<[SKXWriteResGroup127], (instregex "RCL(8|16|32|64)m(1|i)", 1600 "RCR(8|16|32|64)m(1|i)")>; 1601 1602def SKXWriteResGroup128 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06]> { 1603 let Latency = 8; 1604 let NumMicroOps = 6; 1605 let ResourceCycles = [1,1,1,3]; 1606} 1607def: InstRW<[SKXWriteResGroup128], (instregex "ROL(8|16|32|64)mCL", 1608 "ROR(8|16|32|64)mCL", 1609 "SAR(8|16|32|64)mCL", 1610 "SHL(8|16|32|64)mCL", 1611 "SHR(8|16|32|64)mCL")>; 1612 1613def SKXWriteResGroup130 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> { 1614 let Latency = 8; 1615 let NumMicroOps = 6; 1616 let ResourceCycles = [1,1,1,2,1]; 1617} 1618def: SchedAlias<WriteADCRMW, SKXWriteResGroup130>; 1619 1620def SKXWriteResGroup131 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> { 1621 let Latency = 8; 1622 let NumMicroOps = 8; 1623 let ResourceCycles = [1,2,1,2,2]; 1624} 1625def: InstRW<[SKXWriteResGroup131], (instrs VPSCATTERQDZ128mr, 1626 VPSCATTERQDZ256mr, 1627 VSCATTERQPSZ128mr, 1628 VSCATTERQPSZ256mr)>; 1629 1630def SKXWriteResGroup132 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> { 1631 let Latency = 8; 1632 let NumMicroOps = 12; 1633 let ResourceCycles = [1,4,1,4,2]; 1634} 1635def: InstRW<[SKXWriteResGroup132], (instrs VPSCATTERDDZ128mr, 1636 VSCATTERDPSZ128mr)>; 1637 1638def SKXWriteResGroup133 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> { 1639 let Latency = 8; 1640 let NumMicroOps = 20; 1641 let ResourceCycles = [1,8,1,8,2]; 1642} 1643def: InstRW<[SKXWriteResGroup133], (instrs VPSCATTERDDZ256mr, 1644 VSCATTERDPSZ256mr)>; 1645 1646def SKXWriteResGroup134 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> { 1647 let Latency = 8; 1648 let NumMicroOps = 36; 1649 let ResourceCycles = [1,16,1,16,2]; 1650} 1651def: InstRW<[SKXWriteResGroup134], (instrs VPSCATTERDDZmr)>; 1652 1653def SKXWriteResGroup135 : SchedWriteRes<[SKXPort0,SKXPort23]> { 1654 let Latency = 9; 1655 let NumMicroOps = 2; 1656 let ResourceCycles = [1,1]; 1657} 1658def: InstRW<[SKXWriteResGroup135], (instrs MMX_CVTPI2PSirm)>; 1659 1660def SKXWriteResGroup136 : SchedWriteRes<[SKXPort5,SKXPort23]> { 1661 let Latency = 9; 1662 let NumMicroOps = 2; 1663 let ResourceCycles = [1,1]; 1664} 1665def: InstRW<[SKXWriteResGroup136], (instrs VPMOVSXBWYrm, 1666 VPMOVSXDQYrm, 1667 VPMOVSXWDYrm, 1668 VPMOVZXWDYrm)>; 1669def: InstRW<[SKXWriteResGroup136], (instregex "VALIGN(D|Q)Z128rm(b?)i", 1670 "VCMP(PD|PS)Z128rm(b?)i", 1671 "VCMP(SD|SS)Zrm", 1672 "VFPCLASSSSZrm(b?)", 1673 "VPCMPBZ128rmi(b?)", 1674 "VPCMPDZ128rmi(b?)", 1675 "VPCMPEQ(B|D|Q|W)Z128rm(b?)", 1676 "VPCMPGT(B|D|Q|W)Z128rm(b?)", 1677 "(V?)PCMPGTQrm", 1678 "VPCMPQZ128rmi(b?)", 1679 "VPCMPU(B|D|Q|W)Z128rmi(b?)", 1680 "VPCMPWZ128rmi(b?)", 1681 "VPERMI2D128rm(b?)", 1682 "VPERMI2PD128rm(b?)", 1683 "VPERMI2PS128rm(b?)", 1684 "VPERMI2Q128rm(b?)", 1685 "VPERMT2D128rm(b?)", 1686 "VPERMT2PD128rm(b?)", 1687 "VPERMT2PS128rm(b?)", 1688 "VPERMT2Q128rm(b?)", 1689 "VPMAXSQZ128rm(b?)", 1690 "VPMAXUQZ128rm(b?)", 1691 "VPMINSQZ128rm(b?)", 1692 "VPMINUQZ128rm(b?)", 1693 "VPMOVSXBDZ128rm(b?)", 1694 "VPMOVSXBQZ128rm(b?)", 1695 "VPMOVSXBWZ128rm(b?)", 1696 "VPMOVSXDQZ128rm(b?)", 1697 "VPMOVSXWDZ128rm(b?)", 1698 "VPMOVSXWQZ128rm(b?)", 1699 "VPMOVZXBDZ128rm(b?)", 1700 "VPMOVZXBQZ128rm(b?)", 1701 "VPMOVZXBWZ128rm(b?)", 1702 "VPMOVZXDQZ128rm(b?)", 1703 "VPMOVZXWDZ128rm(b?)", 1704 "VPMOVZXWQZ128rm(b?)", 1705 "VPTESTMBZ128rm(b?)", 1706 "VPTESTMDZ128rm(b?)", 1707 "VPTESTMQZ128rm(b?)", 1708 "VPTESTMWZ128rm(b?)", 1709 "VPTESTNMBZ128rm(b?)", 1710 "VPTESTNMDZ128rm(b?)", 1711 "VPTESTNMQZ128rm(b?)", 1712 "VPTESTNMWZ128rm(b?)")>; 1713 1714def SKXWriteResGroup137 : SchedWriteRes<[SKXPort23,SKXPort015]> { 1715 let Latency = 9; 1716 let NumMicroOps = 2; 1717 let ResourceCycles = [1,1]; 1718} 1719def: InstRW<[SKXWriteResGroup137], (instregex "MMX_CVT(T?)PS2PIirm", 1720 "(V?)CVTPS2PDrm")>; 1721 1722def SKXWriteResGroup143 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23]> { 1723 let Latency = 9; 1724 let NumMicroOps = 4; 1725 let ResourceCycles = [2,1,1]; 1726} 1727def: InstRW<[SKXWriteResGroup143], (instregex "(V?)PHADDSWrm", 1728 "(V?)PHSUBSWrm")>; 1729 1730def SKXWriteResGroup146 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort23,SKXPort0156]> { 1731 let Latency = 9; 1732 let NumMicroOps = 5; 1733 let ResourceCycles = [1,2,1,1]; 1734} 1735def: InstRW<[SKXWriteResGroup146], (instregex "LAR(16|32|64)rm", 1736 "LSL(16|32|64)rm")>; 1737 1738def SKXWriteResGroup148 : SchedWriteRes<[SKXPort5,SKXPort23]> { 1739 let Latency = 10; 1740 let NumMicroOps = 2; 1741 let ResourceCycles = [1,1]; 1742} 1743def: InstRW<[SKXWriteResGroup148], (instrs VPCMPGTQYrm)>; 1744def: InstRW<[SKXWriteResGroup148], (instregex "(ADD|SUB|SUBR)_F(32|64)m", 1745 "ILD_F(16|32|64)m", 1746 "VALIGND(Z|Z256)rm(b?)i", 1747 "VALIGNQ(Z|Z256)rm(b?)i", 1748 "VCMPPD(Z|Z256)rm(b?)i", 1749 "VCMPPS(Z|Z256)rm(b?)i", 1750 "VPCMPB(Z|Z256)rmi(b?)", 1751 "VPCMPD(Z|Z256)rmi(b?)", 1752 "VPCMPEQB(Z|Z256)rm(b?)", 1753 "VPCMPEQD(Z|Z256)rm(b?)", 1754 "VPCMPEQQ(Z|Z256)rm(b?)", 1755 "VPCMPEQW(Z|Z256)rm(b?)", 1756 "VPCMPGTB(Z|Z256)rm(b?)", 1757 "VPCMPGTD(Z|Z256)rm(b?)", 1758 "VPCMPGTQ(Z|Z256)rm(b?)", 1759 "VPCMPGTW(Z|Z256)rm(b?)", 1760 "VPCMPQ(Z|Z256)rmi(b?)", 1761 "VPCMPU(B|D|Q|W)Z256rmi(b?)", 1762 "VPCMPU(B|D|Q|W)Zrmi(b?)", 1763 "VPCMPW(Z|Z256)rmi(b?)", 1764 "VPMAXSQ(Z|Z256)rm(b?)", 1765 "VPMAXUQ(Z|Z256)rm(b?)", 1766 "VPMINSQ(Z|Z256)rm(b?)", 1767 "VPMINUQ(Z|Z256)rm(b?)", 1768 "VPTESTM(B|D|Q|W)Z256rm(b?)", 1769 "VPTESTM(B|D|Q|W)Zrm(b?)", 1770 "VPTESTNM(B|D|Q|W)Z256rm(b?)", 1771 "VPTESTNM(B|D|Q|W)Zrm(b?)")>; 1772 1773def SKXWriteResGroup149 : SchedWriteRes<[SKXPort23,SKXPort015]> { 1774 let Latency = 10; 1775 let NumMicroOps = 2; 1776 let ResourceCycles = [1,1]; 1777} 1778def: InstRW<[SKXWriteResGroup149], (instregex "VCVTDQ2PDZ128rm(b?)", 1779 "VCVTDQ2PSZ128rm(b?)", 1780 "(V?)CVTDQ2PSrm", 1781 "VCVTPD2QQZ128rm(b?)", 1782 "VCVTPD2UQQZ128rm(b?)", 1783 "VCVTPH2PSZ128rm(b?)", 1784 "VCVTPS2DQZ128rm(b?)", 1785 "(V?)CVTPS2DQrm", 1786 "VCVTPS2PDZ128rm(b?)", 1787 "VCVTPS2QQZ128rm(b?)", 1788 "VCVTPS2UDQZ128rm(b?)", 1789 "VCVTPS2UQQZ128rm(b?)", 1790 "VCVTQQ2PDZ128rm(b?)", 1791 "VCVTQQ2PSZ128rm(b?)", 1792 "VCVTSS2SDZrm", 1793 "(V?)CVTSS2SDrm", 1794 "VCVTTPD2QQZ128rm(b?)", 1795 "VCVTTPD2UQQZ128rm(b?)", 1796 "VCVTTPS2DQZ128rm(b?)", 1797 "(V?)CVTTPS2DQrm", 1798 "VCVTTPS2QQZ128rm(b?)", 1799 "VCVTTPS2UDQZ128rm(b?)", 1800 "VCVTTPS2UQQZ128rm(b?)", 1801 "VCVTUDQ2PDZ128rm(b?)", 1802 "VCVTUDQ2PSZ128rm(b?)", 1803 "VCVTUQQ2PDZ128rm(b?)", 1804 "VCVTUQQ2PSZ128rm(b?)")>; 1805 1806def SKXWriteResGroup151 : SchedWriteRes<[SKXPort5,SKXPort23]> { 1807 let Latency = 10; 1808 let NumMicroOps = 3; 1809 let ResourceCycles = [2,1]; 1810} 1811def: InstRW<[SKXWriteResGroup151], (instregex "VEXPANDPDZ128rm(b?)", 1812 "VEXPANDPSZ128rm(b?)", 1813 "VPEXPANDDZ128rm(b?)", 1814 "VPEXPANDQZ128rm(b?)")>; 1815 1816def SKXWriteResGroup153 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> { 1817 let Latency = 10; 1818 let NumMicroOps = 3; 1819 let ResourceCycles = [1,1,1]; 1820} 1821def: InstRW<[SKXWriteResGroup153], (instregex "(V?)CVTSD2SSrm")>; 1822 1823def SKXWriteResGroup154 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23]> { 1824 let Latency = 10; 1825 let NumMicroOps = 4; 1826 let ResourceCycles = [2,1,1]; 1827} 1828def: InstRW<[SKXWriteResGroup154], (instrs VPHADDSWYrm, 1829 VPHSUBSWYrm)>; 1830 1831def SKXWriteResGroup157 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> { 1832 let Latency = 10; 1833 let NumMicroOps = 8; 1834 let ResourceCycles = [1,1,1,1,1,3]; 1835} 1836def: InstRW<[SKXWriteResGroup157], (instregex "XCHG(8|16|32|64)rm")>; 1837 1838def SKXWriteResGroup159 : SchedWriteRes<[SKXPort0,SKXFPDivider]> { 1839 let Latency = 11; 1840 let NumMicroOps = 1; 1841 let ResourceCycles = [1,3]; 1842} 1843def : SchedAlias<WriteFDivX, SKXWriteResGroup159>; // TODO - convert to ZnWriteResFpuPair 1844 1845def SKXWriteResGroup160 : SchedWriteRes<[SKXPort0,SKXPort23]> { 1846 let Latency = 11; 1847 let NumMicroOps = 2; 1848 let ResourceCycles = [1,1]; 1849} 1850def: InstRW<[SKXWriteResGroup160], (instregex "MUL_F(32|64)m")>; 1851 1852def SKXWriteResGroup161 : SchedWriteRes<[SKXPort23,SKXPort015]> { 1853 let Latency = 11; 1854 let NumMicroOps = 2; 1855 let ResourceCycles = [1,1]; 1856} 1857def: InstRW<[SKXWriteResGroup161], (instrs VCVTDQ2PSYrm, 1858 VCVTPS2PDYrm)>; 1859def: InstRW<[SKXWriteResGroup161], (instregex "VCVTDQ2(PD|PS)(Z|Z256)rm(b?)", 1860 "VCVTPH2PS(Z|Z256)rm(b?)", 1861 "VCVTPS2PD(Z|Z256)rm(b?)", 1862 "VCVTQQ2PD(Z|Z256)rm(b?)", 1863 "VCVTQQ2PSZ256rm(b?)", 1864 "VCVT(T?)PD2QQ(Z|Z256)rm(b?)", 1865 "VCVT(T?)PD2UQQ(Z|Z256)rm(b?)", 1866 "VCVT(T?)PS2DQYrm", 1867 "VCVT(T?)PS2DQ(Z|Z256)rm(b?)", 1868 "VCVT(T?)PS2QQZ256rm(b?)", 1869 "VCVT(T?)PS2UDQ(Z|Z256)rm(b?)", 1870 "VCVT(T?)PS2UQQZ256rm(b?)", 1871 "VCVTUDQ2(PD|PS)(Z|Z256)rm(b?)", 1872 "VCVTUQQ2PD(Z|Z256)rm(b?)", 1873 "VCVTUQQ2PSZ256rm(b?)")>; 1874 1875def SKXWriteResGroup162 : SchedWriteRes<[SKXPort5,SKXPort23]> { 1876 let Latency = 11; 1877 let NumMicroOps = 3; 1878 let ResourceCycles = [2,1]; 1879} 1880def: InstRW<[SKXWriteResGroup162], (instregex "FICOM(P?)(16|32)m", 1881 "VEXPANDPD(Z|Z256)rm(b?)", 1882 "VEXPANDPS(Z|Z256)rm(b?)", 1883 "VPEXPANDD(Z|Z256)rm(b?)", 1884 "VPEXPANDQ(Z|Z256)rm(b?)")>; 1885 1886def SKXWriteResGroup163 : SchedWriteRes<[SKXPort23,SKXPort015]> { 1887 let Latency = 11; 1888 let NumMicroOps = 3; 1889 let ResourceCycles = [1,2]; 1890} 1891def: InstRW<[SKXWriteResGroup163], (instregex "VCVTSD2SSZrm")>; 1892 1893def SKXWriteResGroup164 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> { 1894 let Latency = 11; 1895 let NumMicroOps = 3; 1896 let ResourceCycles = [1,1,1]; 1897} 1898def: InstRW<[SKXWriteResGroup164], (instregex "(V?)CVTDQ2PDrm")>; 1899 1900def SKXWriteResGroup166 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> { 1901 let Latency = 11; 1902 let NumMicroOps = 3; 1903 let ResourceCycles = [1,1,1]; 1904} 1905def: InstRW<[SKXWriteResGroup166], (instrs CVTPD2PSrm, 1906 CVTPD2DQrm, 1907 CVTTPD2DQrm, 1908 MMX_CVTPD2PIirm, 1909 MMX_CVTTPD2PIirm)>; 1910 1911def SKXWriteResGroup167 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> { 1912 let Latency = 11; 1913 let NumMicroOps = 4; 1914 let ResourceCycles = [2,1,1]; 1915} 1916def: InstRW<[SKXWriteResGroup167], (instregex "VPCONFLICTQZ128rm(b?)")>; 1917 1918def SKXWriteResGroup169 : SchedWriteRes<[SKXPort1,SKXPort06,SKXPort0156]> { 1919 let Latency = 11; 1920 let NumMicroOps = 7; 1921 let ResourceCycles = [2,3,2]; 1922} 1923def: InstRW<[SKXWriteResGroup169], (instregex "RCL(16|32|64)rCL", 1924 "RCR(16|32|64)rCL")>; 1925 1926def SKXWriteResGroup170 : SchedWriteRes<[SKXPort1,SKXPort06,SKXPort15,SKXPort0156]> { 1927 let Latency = 11; 1928 let NumMicroOps = 9; 1929 let ResourceCycles = [1,5,1,2]; 1930} 1931def: InstRW<[SKXWriteResGroup170], (instrs RCL8rCL)>; 1932 1933def SKXWriteResGroup171 : SchedWriteRes<[SKXPort06,SKXPort0156]> { 1934 let Latency = 11; 1935 let NumMicroOps = 11; 1936 let ResourceCycles = [2,9]; 1937} 1938def: InstRW<[SKXWriteResGroup171], (instrs LOOPE, LOOPNE)>; 1939 1940def SKXWriteResGroup174 : SchedWriteRes<[SKXPort01]> { 1941 let Latency = 12; 1942 let NumMicroOps = 3; 1943 let ResourceCycles = [3]; 1944} 1945def: InstRW<[SKXWriteResGroup174], (instregex "VPMULLQ(Z128|Z256)rr")>; 1946 1947def SKXWriteResGroup174z : SchedWriteRes<[SKXPort05]> { 1948 let Latency = 12; 1949 let NumMicroOps = 3; 1950 let ResourceCycles = [3]; 1951} 1952def: InstRW<[SKXWriteResGroup174z], (instregex "VPMULLQZrr")>; 1953 1954def SKXWriteResGroup175 : SchedWriteRes<[SKXPort5,SKXPort23]> { 1955 let Latency = 12; 1956 let NumMicroOps = 3; 1957 let ResourceCycles = [2,1]; 1958} 1959def: InstRW<[SKXWriteResGroup175], (instregex "VPERMWZ128rm(b?)")>; 1960 1961def SKXWriteResGroup176 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015]> { 1962 let Latency = 12; 1963 let NumMicroOps = 3; 1964 let ResourceCycles = [1,1,1]; 1965} 1966def: InstRW<[SKXWriteResGroup176], (instregex "VCVT(T?)SD2USIZrm(b?)", 1967 "VCVT(T?)SS2USI64Zrm(b?)")>; 1968 1969def SKXWriteResGroup177 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> { 1970 let Latency = 12; 1971 let NumMicroOps = 3; 1972 let ResourceCycles = [1,1,1]; 1973} 1974def: InstRW<[SKXWriteResGroup177], (instregex "VCVT(T?)PS2QQZrm(b?)", 1975 "VCVT(T?)PS2UQQZrm(b?)")>; 1976 1977def SKXWriteResGroup179 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23,SKXPort015]> { 1978 let Latency = 12; 1979 let NumMicroOps = 4; 1980 let ResourceCycles = [1,1,1,1]; 1981} 1982def: InstRW<[SKXWriteResGroup179], (instregex "CVTTSS2SI64rm")>; 1983 1984def SKXWriteResGroup180 : SchedWriteRes<[SKXPort5,SKXPort23]> { 1985 let Latency = 13; 1986 let NumMicroOps = 3; 1987 let ResourceCycles = [2,1]; 1988} 1989def: InstRW<[SKXWriteResGroup180], (instregex "(ADD|SUB|SUBR)_FI(16|32)m", 1990 "VPERMWZ256rm(b?)", 1991 "VPERMWZrm(b?)")>; 1992 1993def SKXWriteResGroup181 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> { 1994 let Latency = 13; 1995 let NumMicroOps = 3; 1996 let ResourceCycles = [1,1,1]; 1997} 1998def: InstRW<[SKXWriteResGroup181], (instrs VCVTDQ2PDYrm)>; 1999 2000def SKXWriteResGroup183 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> { 2001 let Latency = 13; 2002 let NumMicroOps = 4; 2003 let ResourceCycles = [2,1,1]; 2004} 2005def: InstRW<[SKXWriteResGroup183], (instregex "VPERMI2W128rm(b?)", 2006 "VPERMT2W128rm(b?)")>; 2007 2008def SKXWriteResGroup184 : SchedWriteRes<[SKXPort0,SKXFPDivider]> { 2009 let Latency = 14; 2010 let NumMicroOps = 1; 2011 let ResourceCycles = [1,3]; 2012} 2013def : SchedAlias<WriteFDiv64, SKXWriteResGroup184>; // TODO - convert to ZnWriteResFpuPair 2014def : SchedAlias<WriteFDiv64X, SKXWriteResGroup184>; // TODO - convert to ZnWriteResFpuPair 2015 2016def SKXWriteResGroup184_1 : SchedWriteRes<[SKXPort0,SKXFPDivider]> { 2017 let Latency = 14; 2018 let NumMicroOps = 1; 2019 let ResourceCycles = [1,5]; 2020} 2021def : SchedAlias<WriteFDiv64Y, SKXWriteResGroup184_1>; // TODO - convert to ZnWriteResFpuPair 2022 2023def SKXWriteResGroup187 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> { 2024 let Latency = 14; 2025 let NumMicroOps = 3; 2026 let ResourceCycles = [1,1,1]; 2027} 2028def: InstRW<[SKXWriteResGroup187], (instregex "MUL_FI(16|32)m")>; 2029 2030def SKXWriteResGroup188 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> { 2031 let Latency = 14; 2032 let NumMicroOps = 3; 2033 let ResourceCycles = [1,1,1]; 2034} 2035def: InstRW<[SKXWriteResGroup188], (instregex "VCVTPD2DQZrm(b?)", 2036 "VCVTPD2PSZrm(b?)", 2037 "VCVTPD2UDQZrm(b?)", 2038 "VCVTQQ2PSZrm(b?)", 2039 "VCVTTPD2DQZrm(b?)", 2040 "VCVTTPD2UDQZrm(b?)", 2041 "VCVTUQQ2PSZrm(b?)")>; 2042 2043def SKXWriteResGroup189 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> { 2044 let Latency = 14; 2045 let NumMicroOps = 4; 2046 let ResourceCycles = [2,1,1]; 2047} 2048def: InstRW<[SKXWriteResGroup189], (instregex "VPERMI2W256rm(b?)", 2049 "VPERMI2Wrm(b?)", 2050 "VPERMT2W256rm(b?)", 2051 "VPERMT2Wrm(b?)")>; 2052 2053def SKXWriteResGroup190 : SchedWriteRes<[SKXPort1,SKXPort06,SKXPort15,SKXPort0156]> { 2054 let Latency = 14; 2055 let NumMicroOps = 10; 2056 let ResourceCycles = [2,4,1,3]; 2057} 2058def: InstRW<[SKXWriteResGroup190], (instrs RCR8rCL)>; 2059 2060def SKXWriteResGroup191 : SchedWriteRes<[SKXPort0]> { 2061 let Latency = 15; 2062 let NumMicroOps = 1; 2063 let ResourceCycles = [1]; 2064} 2065def: InstRW<[SKXWriteResGroup191], (instregex "DIVR_(FPrST0|FST0r|FrST0)")>; 2066 2067def SKXWriteResGroup194 : SchedWriteRes<[SKXPort1,SKXPort5,SKXPort01,SKXPort23,SKXPort015]> { 2068 let Latency = 15; 2069 let NumMicroOps = 8; 2070 let ResourceCycles = [1,2,2,1,2]; 2071} 2072def: InstRW<[SKXWriteResGroup194], (instregex "VPCONFLICTDZ128rm(b?)")>; 2073 2074def SKXWriteResGroup195 : SchedWriteRes<[SKXPort1,SKXPort23,SKXPort237,SKXPort06,SKXPort15,SKXPort0156]> { 2075 let Latency = 15; 2076 let NumMicroOps = 10; 2077 let ResourceCycles = [1,1,1,5,1,1]; 2078} 2079def: InstRW<[SKXWriteResGroup195], (instregex "RCL(8|16|32|64)mCL")>; 2080 2081def SKXWriteResGroup199 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06,SKXPort15,SKXPort0156]> { 2082 let Latency = 16; 2083 let NumMicroOps = 14; 2084 let ResourceCycles = [1,1,1,4,2,5]; 2085} 2086def: InstRW<[SKXWriteResGroup199], (instrs CMPXCHG8B)>; 2087 2088def SKXWriteResGroup200 : SchedWriteRes<[SKXPort1, SKXPort05, SKXPort6]> { 2089 let Latency = 12; 2090 let NumMicroOps = 34; 2091 let ResourceCycles = [1, 4, 5]; 2092} 2093def: InstRW<[SKXWriteResGroup200], (instrs VZEROALL)>; 2094 2095def SKXWriteResGroup201 : SchedWriteRes<[SKXPort0,SKXPort23,SKXFPDivider]> { 2096 let Latency = 17; 2097 let NumMicroOps = 2; 2098 let ResourceCycles = [1,1,5]; 2099} 2100def : SchedAlias<WriteFDivXLd, SKXWriteResGroup201>; // TODO - convert to ZnWriteResFpuPair 2101 2102def SKXWriteResGroup202 : SchedWriteRes<[SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort05,SKXPort0156]> { 2103 let Latency = 17; 2104 let NumMicroOps = 15; 2105 let ResourceCycles = [2,1,2,4,2,4]; 2106} 2107def: InstRW<[SKXWriteResGroup202], (instrs XCH_F)>; 2108 2109def SKXWriteResGroup205 : SchedWriteRes<[SKXPort23,SKXPort015]> { 2110 let Latency = 18; 2111 let NumMicroOps = 4; 2112 let ResourceCycles = [1,3]; 2113} 2114def: InstRW<[SKXWriteResGroup205], (instregex "VPMULLQZ128rm(b?)")>; 2115 2116def SKXWriteResGroup207 : SchedWriteRes<[SKXPort5,SKXPort6,SKXPort06,SKXPort0156]> { 2117 let Latency = 18; 2118 let NumMicroOps = 8; 2119 let ResourceCycles = [1,1,1,5]; 2120} 2121def: InstRW<[SKXWriteResGroup207], (instrs CPUID, RDTSC)>; 2122 2123def SKXWriteResGroup208 : SchedWriteRes<[SKXPort1,SKXPort23,SKXPort237,SKXPort06,SKXPort15,SKXPort0156]> { 2124 let Latency = 18; 2125 let NumMicroOps = 11; 2126 let ResourceCycles = [2,1,1,4,1,2]; 2127} 2128def: InstRW<[SKXWriteResGroup208], (instregex "RCR(8|16|32|64)mCL")>; 2129 2130def SKXWriteResGroup209 : SchedWriteRes<[SKXPort0,SKXPort23,SKXFPDivider]> { 2131 let Latency = 19; 2132 let NumMicroOps = 2; 2133 let ResourceCycles = [1,1,4]; 2134} 2135def : SchedAlias<WriteFDiv64Ld, SKXWriteResGroup209>; // TODO - convert to ZnWriteResFpuPair 2136 2137def SKXWriteResGroup211 : SchedWriteRes<[SKXPort23,SKXPort015]> { 2138 let Latency = 19; 2139 let NumMicroOps = 4; 2140 let ResourceCycles = [1,3]; 2141} 2142def: InstRW<[SKXWriteResGroup211], (instregex "VPMULLQZ256rm(b?)", 2143 "VPMULLQZrm(b?)")>; 2144 2145def SKXWriteResGroup214 : SchedWriteRes<[]> { 2146 let Latency = 20; 2147 let NumMicroOps = 0; 2148} 2149def: InstRW<[SKXWriteResGroup214], (instrs VGATHERDPSZ128rm, 2150 VGATHERQPSZrm, 2151 VPGATHERDDZ128rm)>; 2152 2153def SKXWriteResGroup215 : SchedWriteRes<[SKXPort0]> { 2154 let Latency = 20; 2155 let NumMicroOps = 1; 2156 let ResourceCycles = [1]; 2157} 2158def: InstRW<[SKXWriteResGroup215], (instregex "DIV_(FPrST0|FST0r|FrST0)")>; 2159 2160def SKXWriteResGroup216 : SchedWriteRes<[SKXPort0,SKXPort23,SKXFPDivider]> { 2161 let Latency = 20; 2162 let NumMicroOps = 2; 2163 let ResourceCycles = [1,1,4]; 2164} 2165def : SchedAlias<WriteFDiv64XLd, SKXWriteResGroup216>; // TODO - convert to ZnWriteResFpuPair 2166 2167def SKXWriteResGroup218 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> { 2168 let Latency = 20; 2169 let NumMicroOps = 5; 2170 let ResourceCycles = [1,2,1,1]; 2171} 2172def: InstRW<[SKXWriteResGroup218], (instrs VGATHERQPSZ128rm, 2173 VGATHERQPSZ256rm, 2174 VPGATHERQDZ128rm, 2175 VPGATHERQDZ256rm)>; 2176 2177def SKXWriteResGroup219 : SchedWriteRes<[SKXPort4,SKXPort5,SKXPort6,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> { 2178 let Latency = 20; 2179 let NumMicroOps = 8; 2180 let ResourceCycles = [1,1,1,1,1,1,2]; 2181} 2182def: InstRW<[SKXWriteResGroup219], (instrs INSB, INSL, INSW)>; 2183 2184def SKXWriteResGroup220 : SchedWriteRes<[SKXPort5,SKXPort6,SKXPort0156]> { 2185 let Latency = 20; 2186 let NumMicroOps = 10; 2187 let ResourceCycles = [1,2,7]; 2188} 2189def: InstRW<[SKXWriteResGroup220], (instrs MWAITrr)>; 2190 2191def SKXWriteResGroup222 : SchedWriteRes<[SKXPort0,SKXPort23,SKXFPDivider]> { 2192 let Latency = 21; 2193 let NumMicroOps = 2; 2194 let ResourceCycles = [1,1,8]; 2195} 2196def : SchedAlias<WriteFDiv64YLd, SKXWriteResGroup222>; // TODO - convert to ZnWriteResFpuPair 2197 2198def SKXWriteResGroup223 : SchedWriteRes<[SKXPort0,SKXPort23]> { 2199 let Latency = 22; 2200 let NumMicroOps = 2; 2201 let ResourceCycles = [1,1]; 2202} 2203def: InstRW<[SKXWriteResGroup223], (instregex "DIV_F(32|64)m")>; 2204 2205def SKXWriteResGroup224 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> { 2206 let Latency = 22; 2207 let NumMicroOps = 5; 2208 let ResourceCycles = [1,2,1,1]; 2209} 2210def: InstRW<[SKXWriteResGroup224], (instrs VGATHERDPDZ128rm, 2211 VGATHERQPDZ128rm, 2212 VPGATHERDQZ128rm, 2213 VPGATHERQQZ128rm)>; 2214 2215def SKXWriteResGroup224_2 : SchedWriteRes<[SKXPort0, SKXPort23, SKXPort5, SKXPort015]> { 2216 let Latency = 22; 2217 let NumMicroOps = 5; 2218 let ResourceCycles = [1,2,1,1]; 2219} 2220def: InstRW<[SKXWriteResGroup224_2], (instrs VGATHERDPSrm, 2221 VGATHERDPDrm, 2222 VGATHERQPDrm, 2223 VGATHERQPSrm, 2224 VPGATHERDDrm, 2225 VPGATHERDQrm, 2226 VPGATHERQDrm, 2227 VPGATHERQQrm, 2228 VPGATHERDDrm, 2229 VPGATHERQDrm, 2230 VPGATHERDQrm, 2231 VPGATHERQQrm, 2232 VGATHERDPSrm, 2233 VGATHERQPSrm, 2234 VGATHERDPDrm, 2235 VGATHERQPDrm)>; 2236 2237def SKXWriteResGroup224_3 : SchedWriteRes<[SKXPort0, SKXPort23, SKXPort5, SKXPort015]> { 2238 let Latency = 25; 2239 let NumMicroOps = 5; 2240 let ResourceCycles = [1,2,1,1]; 2241} 2242def: InstRW<[SKXWriteResGroup224_3], (instrs VGATHERDPSYrm, 2243 VGATHERQPDYrm, 2244 VGATHERQPSYrm, 2245 VPGATHERDDYrm, 2246 VPGATHERDQYrm, 2247 VPGATHERQDYrm, 2248 VPGATHERQQYrm, 2249 VPGATHERDDYrm, 2250 VPGATHERQDYrm, 2251 VPGATHERDQYrm, 2252 VPGATHERQQYrm, 2253 VGATHERDPSYrm, 2254 VGATHERQPSYrm, 2255 VGATHERDPDYrm)>; 2256 2257def SKXWriteResGroup225 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort015]> { 2258 let Latency = 22; 2259 let NumMicroOps = 14; 2260 let ResourceCycles = [5,5,4]; 2261} 2262def: InstRW<[SKXWriteResGroup225], (instregex "VPCONFLICTDZ128rr", 2263 "VPCONFLICTQZ256rr")>; 2264 2265def SKXWriteResGroup228 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> { 2266 let Latency = 23; 2267 let NumMicroOps = 19; 2268 let ResourceCycles = [2,1,4,1,1,4,6]; 2269} 2270def: InstRW<[SKXWriteResGroup228], (instrs CMPXCHG16B)>; 2271 2272def SKXWriteResGroup233 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> { 2273 let Latency = 25; 2274 let NumMicroOps = 3; 2275 let ResourceCycles = [1,1,1]; 2276} 2277def: InstRW<[SKXWriteResGroup233], (instregex "DIV_FI(16|32)m")>; 2278 2279def SKXWriteResGroup234 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> { 2280 let Latency = 25; 2281 let NumMicroOps = 5; 2282 let ResourceCycles = [1,2,1,1]; 2283} 2284def: InstRW<[SKXWriteResGroup234], (instrs VGATHERDPDZ256rm, 2285 VGATHERQPDZ256rm, 2286 VPGATHERDQZ256rm, 2287 VPGATHERQDZrm, 2288 VPGATHERQQZ256rm)>; 2289 2290def SKXWriteResGroup238 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> { 2291 let Latency = 26; 2292 let NumMicroOps = 5; 2293 let ResourceCycles = [1,2,1,1]; 2294} 2295def: InstRW<[SKXWriteResGroup238], (instrs VGATHERDPDZrm, 2296 VGATHERQPDZrm, 2297 VPGATHERDQZrm, 2298 VPGATHERQQZrm)>; 2299 2300def SKXWriteResGroup239 : SchedWriteRes<[SKXPort0,SKXPort23]> { 2301 let Latency = 27; 2302 let NumMicroOps = 2; 2303 let ResourceCycles = [1,1]; 2304} 2305def: InstRW<[SKXWriteResGroup239], (instregex "DIVR_F(32|64)m")>; 2306 2307def SKXWriteResGroup240 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> { 2308 let Latency = 27; 2309 let NumMicroOps = 5; 2310 let ResourceCycles = [1,2,1,1]; 2311} 2312def: InstRW<[SKXWriteResGroup240], (instrs VGATHERDPSZ256rm, 2313 VPGATHERDDZ256rm)>; 2314 2315def SKXWriteResGroup242 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23,SKXPort015]> { 2316 let Latency = 29; 2317 let NumMicroOps = 15; 2318 let ResourceCycles = [5,5,1,4]; 2319} 2320def: InstRW<[SKXWriteResGroup242], (instregex "VPCONFLICTQZ256rm(b?)")>; 2321 2322def SKXWriteResGroup243 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> { 2323 let Latency = 30; 2324 let NumMicroOps = 3; 2325 let ResourceCycles = [1,1,1]; 2326} 2327def: InstRW<[SKXWriteResGroup243], (instregex "DIVR_FI(16|32)m")>; 2328 2329def SKXWriteResGroup245 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> { 2330 let Latency = 30; 2331 let NumMicroOps = 5; 2332 let ResourceCycles = [1,2,1,1]; 2333} 2334def: InstRW<[SKXWriteResGroup245], (instrs VGATHERDPSZrm, 2335 VPGATHERDDZrm)>; 2336 2337def SKXWriteResGroup247 : SchedWriteRes<[SKXPort5,SKXPort6,SKXPort23,SKXPort06,SKXPort0156]> { 2338 let Latency = 35; 2339 let NumMicroOps = 23; 2340 let ResourceCycles = [1,5,3,4,10]; 2341} 2342def: InstRW<[SKXWriteResGroup247], (instregex "IN(8|16|32)ri", 2343 "IN(8|16|32)rr")>; 2344 2345def SKXWriteResGroup248 : SchedWriteRes<[SKXPort5,SKXPort6,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> { 2346 let Latency = 35; 2347 let NumMicroOps = 23; 2348 let ResourceCycles = [1,5,2,1,4,10]; 2349} 2350def: InstRW<[SKXWriteResGroup248], (instregex "OUT(8|16|32)ir", 2351 "OUT(8|16|32)rr")>; 2352 2353def SKXWriteResGroup249 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort015]> { 2354 let Latency = 37; 2355 let NumMicroOps = 21; 2356 let ResourceCycles = [9,7,5]; 2357} 2358def: InstRW<[SKXWriteResGroup249], (instregex "VPCONFLICTDZ256rr", 2359 "VPCONFLICTQZrr")>; 2360 2361def SKXWriteResGroup250 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort23,SKXPort0156]> { 2362 let Latency = 37; 2363 let NumMicroOps = 31; 2364 let ResourceCycles = [1,8,1,21]; 2365} 2366def: InstRW<[SKXWriteResGroup250], (instregex "XRSTOR(64)?")>; 2367 2368def SKXWriteResGroup252 : SchedWriteRes<[SKXPort1,SKXPort4,SKXPort5,SKXPort6,SKXPort23,SKXPort237,SKXPort15,SKXPort0156]> { 2369 let Latency = 40; 2370 let NumMicroOps = 18; 2371 let ResourceCycles = [1,1,2,3,1,1,1,8]; 2372} 2373def: InstRW<[SKXWriteResGroup252], (instrs VMCLEARm)>; 2374 2375def SKXWriteResGroup253 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort23,SKXPort237,SKXPort0156]> { 2376 let Latency = 41; 2377 let NumMicroOps = 39; 2378 let ResourceCycles = [1,10,1,1,26]; 2379} 2380def: InstRW<[SKXWriteResGroup253], (instrs XSAVE64)>; 2381 2382def SKXWriteResGroup254 : SchedWriteRes<[SKXPort5,SKXPort0156]> { 2383 let Latency = 42; 2384 let NumMicroOps = 22; 2385 let ResourceCycles = [2,20]; 2386} 2387def: InstRW<[SKXWriteResGroup254], (instrs RDTSCP)>; 2388 2389def SKXWriteResGroup255 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort23,SKXPort237,SKXPort0156]> { 2390 let Latency = 42; 2391 let NumMicroOps = 40; 2392 let ResourceCycles = [1,11,1,1,26]; 2393} 2394def: InstRW<[SKXWriteResGroup255], (instrs XSAVE)>; 2395def: InstRW<[SKXWriteResGroup255], (instregex "XSAVEC", "XSAVES", "XSAVEOPT")>; 2396 2397def SKXWriteResGroup256 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23,SKXPort015]> { 2398 let Latency = 44; 2399 let NumMicroOps = 22; 2400 let ResourceCycles = [9,7,1,5]; 2401} 2402def: InstRW<[SKXWriteResGroup256], (instregex "VPCONFLICTDZ256rm(b?)", 2403 "VPCONFLICTQZrm(b?)")>; 2404 2405def SKXWriteResGroup258 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort05,SKXPort06,SKXPort0156]> { 2406 let Latency = 62; 2407 let NumMicroOps = 64; 2408 let ResourceCycles = [2,8,5,10,39]; 2409} 2410def: InstRW<[SKXWriteResGroup258], (instrs FLDENVm)>; 2411 2412def SKXWriteResGroup259 : SchedWriteRes<[SKXPort0,SKXPort6,SKXPort23,SKXPort05,SKXPort06,SKXPort15,SKXPort0156]> { 2413 let Latency = 63; 2414 let NumMicroOps = 88; 2415 let ResourceCycles = [4,4,31,1,2,1,45]; 2416} 2417def: InstRW<[SKXWriteResGroup259], (instrs FXRSTOR64)>; 2418 2419def SKXWriteResGroup260 : SchedWriteRes<[SKXPort0,SKXPort6,SKXPort23,SKXPort05,SKXPort06,SKXPort15,SKXPort0156]> { 2420 let Latency = 63; 2421 let NumMicroOps = 90; 2422 let ResourceCycles = [4,2,33,1,2,1,47]; 2423} 2424def: InstRW<[SKXWriteResGroup260], (instrs FXRSTOR)>; 2425 2426def SKXWriteResGroup261 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort015]> { 2427 let Latency = 67; 2428 let NumMicroOps = 35; 2429 let ResourceCycles = [17,11,7]; 2430} 2431def: InstRW<[SKXWriteResGroup261], (instregex "VPCONFLICTDZrr")>; 2432 2433def SKXWriteResGroup262 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23,SKXPort015]> { 2434 let Latency = 74; 2435 let NumMicroOps = 36; 2436 let ResourceCycles = [17,11,1,7]; 2437} 2438def: InstRW<[SKXWriteResGroup262], (instregex "VPCONFLICTDZrm(b?)")>; 2439 2440def SKXWriteResGroup263 : SchedWriteRes<[SKXPort5,SKXPort05,SKXPort0156]> { 2441 let Latency = 75; 2442 let NumMicroOps = 15; 2443 let ResourceCycles = [6,3,6]; 2444} 2445def: InstRW<[SKXWriteResGroup263], (instrs FNINIT)>; 2446 2447def SKXWriteResGroup266 : SchedWriteRes<[SKXPort0,SKXPort1,SKXPort4,SKXPort5,SKXPort6,SKXPort237,SKXPort06,SKXPort0156]> { 2448 let Latency = 106; 2449 let NumMicroOps = 100; 2450 let ResourceCycles = [9,1,11,16,1,11,21,30]; 2451} 2452def: InstRW<[SKXWriteResGroup266], (instrs FSTENVm)>; 2453 2454def SKXWriteResGroup267 : SchedWriteRes<[SKXPort6,SKXPort0156]> { 2455 let Latency = 140; 2456 let NumMicroOps = 4; 2457 let ResourceCycles = [1,3]; 2458} 2459def: InstRW<[SKXWriteResGroup267], (instrs PAUSE)>; 2460 2461def: InstRW<[WriteZero], (instrs CLC)>; 2462 2463 2464// Intruction variants handled by the renamer. These might not need execution 2465// ports in certain conditions. 2466// See Agner's Fog "The microarchitecture of Intel, AMD and VIA CPUs", 2467// section "Skylake Pipeline" > "Register allocation and renaming". 2468// These can be investigated with llvm-exegesis, e.g. 2469// echo 'pxor %mm0, %mm0' | /tmp/llvm-exegesis -mode=uops -snippets-file=- 2470// echo 'vxorpd %xmm0, %xmm0, %xmm1' | /tmp/llvm-exegesis -mode=uops -snippets-file=- 2471 2472def SKXWriteZeroLatency : SchedWriteRes<[]> { 2473 let Latency = 0; 2474} 2475 2476def SKXWriteZeroIdiom : SchedWriteVariant<[ 2477 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>, 2478 SchedVar<NoSchedPred, [WriteALU]> 2479]>; 2480def : InstRW<[SKXWriteZeroIdiom], (instrs SUB32rr, SUB64rr, 2481 XOR32rr, XOR64rr)>; 2482 2483def SKXWriteFZeroIdiom : SchedWriteVariant<[ 2484 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>, 2485 SchedVar<NoSchedPred, [WriteFLogic]> 2486]>; 2487def : InstRW<[SKXWriteFZeroIdiom], (instrs XORPSrr, VXORPSrr, 2488 XORPDrr, VXORPDrr, 2489 VXORPSZ128rr, 2490 VXORPDZ128rr)>; 2491 2492def SKXWriteFZeroIdiomY : SchedWriteVariant<[ 2493 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>, 2494 SchedVar<NoSchedPred, [WriteFLogicY]> 2495]>; 2496def : InstRW<[SKXWriteFZeroIdiomY], (instrs VXORPSYrr, VXORPDYrr, 2497 VXORPSZ256rr, VXORPDZ256rr)>; 2498 2499def SKXWriteFZeroIdiomZ : SchedWriteVariant<[ 2500 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>, 2501 SchedVar<NoSchedPred, [WriteFLogicZ]> 2502]>; 2503def : InstRW<[SKXWriteFZeroIdiomZ], (instrs VXORPSZrr, VXORPDZrr)>; 2504 2505def SKXWriteVZeroIdiomLogicX : SchedWriteVariant<[ 2506 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>, 2507 SchedVar<NoSchedPred, [WriteVecLogicX]> 2508]>; 2509def : InstRW<[SKXWriteVZeroIdiomLogicX], (instrs PXORrr, VPXORrr, 2510 VPXORDZ128rr, VPXORQZ128rr)>; 2511 2512def SKXWriteVZeroIdiomLogicY : SchedWriteVariant<[ 2513 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>, 2514 SchedVar<NoSchedPred, [WriteVecLogicY]> 2515]>; 2516def : InstRW<[SKXWriteVZeroIdiomLogicY], (instrs VPXORYrr, 2517 VPXORDZ256rr, VPXORQZ256rr)>; 2518 2519def SKXWriteVZeroIdiomLogicZ : SchedWriteVariant<[ 2520 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>, 2521 SchedVar<NoSchedPred, [WriteVecLogicZ]> 2522]>; 2523def : InstRW<[SKXWriteVZeroIdiomLogicZ], (instrs VPXORDZrr, VPXORQZrr)>; 2524 2525def SKXWriteVZeroIdiomALUX : SchedWriteVariant<[ 2526 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>, 2527 SchedVar<NoSchedPred, [WriteVecALUX]> 2528]>; 2529def : InstRW<[SKXWriteVZeroIdiomALUX], (instrs PCMPGTBrr, VPCMPGTBrr, 2530 PCMPGTDrr, VPCMPGTDrr, 2531 PCMPGTWrr, VPCMPGTWrr)>; 2532 2533def SKXWriteVZeroIdiomALUY : SchedWriteVariant<[ 2534 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>, 2535 SchedVar<NoSchedPred, [WriteVecALUY]> 2536]>; 2537def : InstRW<[SKXWriteVZeroIdiomALUY], (instrs VPCMPGTBYrr, 2538 VPCMPGTDYrr, 2539 VPCMPGTWYrr)>; 2540 2541def SKXWritePSUB : SchedWriteRes<[SKXPort015]> { 2542 let Latency = 1; 2543 let NumMicroOps = 1; 2544 let ResourceCycles = [1]; 2545} 2546 2547def SKXWriteVZeroIdiomPSUB : SchedWriteVariant<[ 2548 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>, 2549 SchedVar<NoSchedPred, [SKXWritePSUB]> 2550]>; 2551 2552def : InstRW<[SKXWriteVZeroIdiomPSUB], (instrs PSUBBrr, VPSUBBrr, VPSUBBZ128rr, 2553 PSUBDrr, VPSUBDrr, VPSUBDZ128rr, 2554 PSUBQrr, VPSUBQrr, VPSUBQZ128rr, 2555 PSUBWrr, VPSUBWrr, VPSUBWZ128rr, 2556 VPSUBBYrr, VPSUBBZ256rr, 2557 VPSUBDYrr, VPSUBDZ256rr, 2558 VPSUBQYrr, VPSUBQZ256rr, 2559 VPSUBWYrr, VPSUBWZ256rr, 2560 VPSUBBZrr, 2561 VPSUBDZrr, 2562 VPSUBQZrr, 2563 VPSUBWZrr)>; 2564def SKXWritePCMPGTQ : SchedWriteRes<[SKXPort5]> { 2565 let Latency = 3; 2566 let NumMicroOps = 1; 2567 let ResourceCycles = [1]; 2568} 2569 2570def SKXWriteVZeroIdiomPCMPGTQ : SchedWriteVariant<[ 2571 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>, 2572 SchedVar<NoSchedPred, [SKXWritePCMPGTQ]> 2573]>; 2574def : InstRW<[SKXWriteVZeroIdiomPCMPGTQ], (instrs PCMPGTQrr, VPCMPGTQrr, 2575 VPCMPGTQYrr)>; 2576 2577 2578// CMOVs that use both Z and C flag require an extra uop. 2579def SKXWriteCMOVA_CMOVBErr : SchedWriteRes<[SKXPort06]> { 2580 let Latency = 2; 2581 let ResourceCycles = [2]; 2582 let NumMicroOps = 2; 2583} 2584 2585def SKXWriteCMOVA_CMOVBErm : SchedWriteRes<[SKXPort23,SKXPort06]> { 2586 let Latency = 7; 2587 let ResourceCycles = [1,2]; 2588 let NumMicroOps = 3; 2589} 2590 2591def SKXCMOVA_CMOVBErr : SchedWriteVariant<[ 2592 SchedVar<MCSchedPredicate<IsCMOVArr_Or_CMOVBErr>, [SKXWriteCMOVA_CMOVBErr]>, 2593 SchedVar<NoSchedPred, [WriteCMOV]> 2594]>; 2595 2596def SKXCMOVA_CMOVBErm : SchedWriteVariant<[ 2597 SchedVar<MCSchedPredicate<IsCMOVArm_Or_CMOVBErm>, [SKXWriteCMOVA_CMOVBErm]>, 2598 SchedVar<NoSchedPred, [WriteCMOV.Folded]> 2599]>; 2600 2601def : InstRW<[SKXCMOVA_CMOVBErr], (instrs CMOV16rr, CMOV32rr, CMOV64rr)>; 2602def : InstRW<[SKXCMOVA_CMOVBErm], (instrs CMOV16rm, CMOV32rm, CMOV64rm)>; 2603 2604// SETCCs that use both Z and C flag require an extra uop. 2605def SKXWriteSETA_SETBEr : SchedWriteRes<[SKXPort06]> { 2606 let Latency = 2; 2607 let ResourceCycles = [2]; 2608 let NumMicroOps = 2; 2609} 2610 2611def SKXWriteSETA_SETBEm : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort06]> { 2612 let Latency = 3; 2613 let ResourceCycles = [1,1,2]; 2614 let NumMicroOps = 4; 2615} 2616 2617def SKXSETA_SETBErr : SchedWriteVariant<[ 2618 SchedVar<MCSchedPredicate<IsSETAr_Or_SETBEr>, [SKXWriteSETA_SETBEr]>, 2619 SchedVar<NoSchedPred, [WriteSETCC]> 2620]>; 2621 2622def SKXSETA_SETBErm : SchedWriteVariant<[ 2623 SchedVar<MCSchedPredicate<IsSETAm_Or_SETBEm>, [SKXWriteSETA_SETBEm]>, 2624 SchedVar<NoSchedPred, [WriteSETCCStore]> 2625]>; 2626 2627def : InstRW<[SKXSETA_SETBErr], (instrs SETCCr)>; 2628def : InstRW<[SKXSETA_SETBErm], (instrs SETCCm)>; 2629 2630} // SchedModel 2631