1//=- X86SchedSkylake.td - X86 Skylake Server Scheduling ------*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the machine model for Skylake Server to support 10// instruction scheduling and other instruction cost heuristics. 11// 12//===----------------------------------------------------------------------===// 13 14def SkylakeServerModel : SchedMachineModel { 15 // All x86 instructions are modeled as a single micro-op, and SKylake can 16 // decode 6 instructions per cycle. 17 let IssueWidth = 6; 18 let MicroOpBufferSize = 224; // Based on the reorder buffer. 19 let LoadLatency = 5; 20 let MispredictPenalty = 14; 21 22 // Based on the LSD (loop-stream detector) queue size and benchmarking data. 23 let LoopMicroOpBufferSize = 50; 24 25 // This flag is set to allow the scheduler to assign a default model to 26 // unrecognized opcodes. 27 let CompleteModel = 0; 28} 29 30let SchedModel = SkylakeServerModel in { 31 32// Skylake Server can issue micro-ops to 8 different ports in one cycle. 33 34// Ports 0, 1, 5, and 6 handle all computation. 35// Port 4 gets the data half of stores. Store data can be available later than 36// the store address, but since we don't model the latency of stores, we can 37// ignore that. 38// Ports 2 and 3 are identical. They handle loads and the address half of 39// stores. Port 7 can handle address calculations. 40def SKXPort0 : ProcResource<1>; 41def SKXPort1 : ProcResource<1>; 42def SKXPort2 : ProcResource<1>; 43def SKXPort3 : ProcResource<1>; 44def SKXPort4 : ProcResource<1>; 45def SKXPort5 : ProcResource<1>; 46def SKXPort6 : ProcResource<1>; 47def SKXPort7 : ProcResource<1>; 48 49// Many micro-ops are capable of issuing on multiple ports. 50def SKXPort01 : ProcResGroup<[SKXPort0, SKXPort1]>; 51def SKXPort23 : ProcResGroup<[SKXPort2, SKXPort3]>; 52def SKXPort237 : ProcResGroup<[SKXPort2, SKXPort3, SKXPort7]>; 53def SKXPort04 : ProcResGroup<[SKXPort0, SKXPort4]>; 54def SKXPort05 : ProcResGroup<[SKXPort0, SKXPort5]>; 55def SKXPort06 : ProcResGroup<[SKXPort0, SKXPort6]>; 56def SKXPort15 : ProcResGroup<[SKXPort1, SKXPort5]>; 57def SKXPort16 : ProcResGroup<[SKXPort1, SKXPort6]>; 58def SKXPort56 : ProcResGroup<[SKXPort5, SKXPort6]>; 59def SKXPort015 : ProcResGroup<[SKXPort0, SKXPort1, SKXPort5]>; 60def SKXPort056 : ProcResGroup<[SKXPort0, SKXPort5, SKXPort6]>; 61def SKXPort0156: ProcResGroup<[SKXPort0, SKXPort1, SKXPort5, SKXPort6]>; 62 63def SKXDivider : ProcResource<1>; // Integer division issued on port 0. 64// FP division and sqrt on port 0. 65def SKXFPDivider : ProcResource<1>; 66 67// 60 Entry Unified Scheduler 68def SKXPortAny : ProcResGroup<[SKXPort0, SKXPort1, SKXPort2, SKXPort3, SKXPort4, 69 SKXPort5, SKXPort6, SKXPort7]> { 70 let BufferSize=60; 71} 72 73// Integer loads are 5 cycles, so ReadAfterLd registers needn't be available until 5 74// cycles after the memory operand. 75def : ReadAdvance<ReadAfterLd, 5>; 76 77// Vector loads are 5/6/7 cycles, so ReadAfterVec*Ld registers needn't be available 78// until 5/6/7 cycles after the memory operand. 79def : ReadAdvance<ReadAfterVecLd, 5>; 80def : ReadAdvance<ReadAfterVecXLd, 6>; 81def : ReadAdvance<ReadAfterVecYLd, 7>; 82 83def : ReadAdvance<ReadInt2Fpu, 0>; 84 85// Many SchedWrites are defined in pairs with and without a folded load. 86// Instructions with folded loads are usually micro-fused, so they only appear 87// as two micro-ops when queued in the reservation station. 88// This multiclass defines the resource usage for variants with and without 89// folded loads. 90multiclass SKXWriteResPair<X86FoldableSchedWrite SchedRW, 91 list<ProcResourceKind> ExePorts, 92 int Lat, list<int> Res = [1], int UOps = 1, 93 int LoadLat = 5> { 94 // Register variant is using a single cycle on ExePort. 95 def : WriteRes<SchedRW, ExePorts> { 96 let Latency = Lat; 97 let ResourceCycles = Res; 98 let NumMicroOps = UOps; 99 } 100 101 // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to 102 // the latency (default = 5). 103 def : WriteRes<SchedRW.Folded, !listconcat([SKXPort23], ExePorts)> { 104 let Latency = !add(Lat, LoadLat); 105 let ResourceCycles = !listconcat([1], Res); 106 let NumMicroOps = !add(UOps, 1); 107 } 108} 109 110// A folded store needs a cycle on port 4 for the store data, and an extra port 111// 2/3/7 cycle to recompute the address. 112def : WriteRes<WriteRMW, [SKXPort237,SKXPort4]>; 113 114// Arithmetic. 115defm : SKXWriteResPair<WriteALU, [SKXPort0156], 1>; // Simple integer ALU op. 116defm : SKXWriteResPair<WriteADC, [SKXPort06], 1>; // Integer ALU + flags op. 117 118// Integer multiplication. 119defm : SKXWriteResPair<WriteIMul8, [SKXPort1], 3>; 120defm : SKXWriteResPair<WriteIMul16, [SKXPort1,SKXPort06,SKXPort0156], 4, [1,1,2], 4>; 121defm : X86WriteRes<WriteIMul16Imm, [SKXPort1,SKXPort0156], 4, [1,1], 2>; 122defm : X86WriteRes<WriteIMul16ImmLd, [SKXPort1,SKXPort0156,SKXPort23], 8, [1,1,1], 3>; 123defm : X86WriteRes<WriteIMul16Reg, [SKXPort1], 3, [1], 1>; 124defm : X86WriteRes<WriteIMul16RegLd, [SKXPort1,SKXPort0156,SKXPort23], 8, [1,1,1], 3>; 125defm : SKXWriteResPair<WriteIMul32, [SKXPort1,SKXPort06,SKXPort0156], 4, [1,1,1], 3>; 126defm : SKXWriteResPair<WriteMULX32, [SKXPort1,SKXPort06,SKXPort0156], 3, [1,1,1], 3>; 127defm : SKXWriteResPair<WriteIMul32Imm, [SKXPort1], 3>; 128defm : SKXWriteResPair<WriteIMul32Reg, [SKXPort1], 3>; 129defm : SKXWriteResPair<WriteIMul64, [SKXPort1,SKXPort5], 4, [1,1], 2>; 130defm : SKXWriteResPair<WriteMULX64, [SKXPort1,SKXPort5], 3, [1,1], 2>; 131defm : SKXWriteResPair<WriteIMul64Imm, [SKXPort1], 3>; 132defm : SKXWriteResPair<WriteIMul64Reg, [SKXPort1], 3>; 133def SKXWriteIMulH : WriteRes<WriteIMulH, []> { let Latency = 4; } 134def : WriteRes<WriteIMulHLd, []> { 135 let Latency = !add(SKXWriteIMulH.Latency, SkylakeServerModel.LoadLatency); 136} 137 138defm : X86WriteRes<WriteBSWAP32, [SKXPort15], 1, [1], 1>; 139defm : X86WriteRes<WriteBSWAP64, [SKXPort06, SKXPort15], 2, [1,1], 2>; 140defm : X86WriteRes<WriteCMPXCHG,[SKXPort06, SKXPort0156], 5, [2,3], 5>; 141defm : X86WriteRes<WriteCMPXCHGRMW,[SKXPort23,SKXPort06,SKXPort0156,SKXPort237,SKXPort4], 8, [1,2,1,1,1], 6>; 142defm : X86WriteRes<WriteXCHG, [SKXPort0156], 2, [3], 3>; 143 144// TODO: Why isn't the SKXDivider used? 145defm : SKXWriteResPair<WriteDiv8, [SKXPort0, SKXDivider], 25, [1,10], 1, 4>; 146defm : X86WriteRes<WriteDiv16, [SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort05,SKXPort0156], 76, [7,2,8,3,1,11], 32>; 147defm : X86WriteRes<WriteDiv32, [SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort05,SKXPort0156], 76, [7,2,8,3,1,11], 32>; 148defm : X86WriteRes<WriteDiv64, [SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort05,SKXPort0156], 76, [7,2,8,3,1,11], 32>; 149defm : X86WriteRes<WriteDiv16Ld, [SKXPort0,SKXPort23,SKXDivider], 29, [1,1,10], 2>; 150defm : X86WriteRes<WriteDiv32Ld, [SKXPort0,SKXPort23,SKXDivider], 29, [1,1,10], 2>; 151defm : X86WriteRes<WriteDiv64Ld, [SKXPort0,SKXPort23,SKXDivider], 29, [1,1,10], 2>; 152 153defm : X86WriteRes<WriteIDiv8, [SKXPort0, SKXDivider], 25, [1,10], 1>; 154defm : X86WriteRes<WriteIDiv16, [SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort06,SKXPort0156], 102, [4,2,4,8,14,34], 66>; 155defm : X86WriteRes<WriteIDiv32, [SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort06,SKXPort0156], 102, [4,2,4,8,14,34], 66>; 156defm : X86WriteRes<WriteIDiv64, [SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort06,SKXPort0156], 102, [4,2,4,8,14,34], 66>; 157defm : X86WriteRes<WriteIDiv8Ld, [SKXPort0,SKXPort5,SKXPort23,SKXPort0156], 28, [2,4,1,1], 8>; 158defm : X86WriteRes<WriteIDiv16Ld, [SKXPort0,SKXPort5,SKXPort23,SKXPort0156], 28, [2,4,1,1], 8>; 159defm : X86WriteRes<WriteIDiv32Ld, [SKXPort0,SKXPort5,SKXPort23,SKXPort0156], 28, [2,4,1,1], 8>; 160defm : X86WriteRes<WriteIDiv64Ld, [SKXPort0,SKXPort5,SKXPort23,SKXPort0156], 28, [2,4,1,1], 8>; 161 162defm : SKXWriteResPair<WriteCRC32, [SKXPort1], 3>; 163 164def : WriteRes<WriteLEA, [SKXPort15]>; // LEA instructions can't fold loads. 165 166defm : SKXWriteResPair<WriteCMOV, [SKXPort06], 1, [1], 1>; // Conditional move. 167defm : X86WriteRes<WriteFCMOV, [SKXPort1], 3, [1], 1>; // x87 conditional move. 168def : WriteRes<WriteSETCC, [SKXPort06]>; // Setcc. 169def : WriteRes<WriteSETCCStore, [SKXPort06,SKXPort4,SKXPort237]> { 170 let Latency = 2; 171 let NumMicroOps = 3; 172} 173defm : X86WriteRes<WriteLAHFSAHF, [SKXPort06], 1, [1], 1>; 174defm : X86WriteRes<WriteBitTest, [SKXPort06], 1, [1], 1>; 175defm : X86WriteRes<WriteBitTestImmLd, [SKXPort06,SKXPort23], 6, [1,1], 2>; 176defm : X86WriteRes<WriteBitTestRegLd, [SKXPort0156,SKXPort23], 6, [1,1], 2>; 177defm : X86WriteRes<WriteBitTestSet, [SKXPort06], 1, [1], 1>; 178defm : X86WriteRes<WriteBitTestSetImmLd, [SKXPort06,SKXPort23], 5, [1,1], 3>; 179defm : X86WriteRes<WriteBitTestSetRegLd, [SKXPort0156,SKXPort23], 5, [1,1], 2>; 180 181// Integer shifts and rotates. 182defm : SKXWriteResPair<WriteShift, [SKXPort06], 1>; 183defm : SKXWriteResPair<WriteShiftCL, [SKXPort06], 3, [3], 3>; 184defm : SKXWriteResPair<WriteRotate, [SKXPort06], 1, [1], 1>; 185defm : SKXWriteResPair<WriteRotateCL, [SKXPort06], 3, [3], 3>; 186 187// SHLD/SHRD. 188defm : X86WriteRes<WriteSHDrri, [SKXPort1], 3, [1], 1>; 189defm : X86WriteRes<WriteSHDrrcl,[SKXPort1,SKXPort06,SKXPort0156], 6, [1, 2, 1], 4>; 190defm : X86WriteRes<WriteSHDmri, [SKXPort1,SKXPort23,SKXPort237,SKXPort0156], 9, [1, 1, 1, 1], 4>; 191defm : X86WriteRes<WriteSHDmrcl,[SKXPort1,SKXPort23,SKXPort237,SKXPort06,SKXPort0156], 11, [1, 1, 1, 2, 1], 6>; 192 193// Bit counts. 194defm : SKXWriteResPair<WriteBSF, [SKXPort1], 3>; 195defm : SKXWriteResPair<WriteBSR, [SKXPort1], 3>; 196defm : SKXWriteResPair<WriteLZCNT, [SKXPort1], 3>; 197defm : SKXWriteResPair<WriteTZCNT, [SKXPort1], 3>; 198defm : SKXWriteResPair<WritePOPCNT, [SKXPort1], 3>; 199 200// BMI1 BEXTR/BLS, BMI2 BZHI 201defm : SKXWriteResPair<WriteBEXTR, [SKXPort06,SKXPort15], 2, [1,1], 2>; 202defm : SKXWriteResPair<WriteBLS, [SKXPort15], 1>; 203defm : SKXWriteResPair<WriteBZHI, [SKXPort15], 1>; 204 205// Loads, stores, and moves, not folded with other operations. 206defm : X86WriteRes<WriteLoad, [SKXPort23], 5, [1], 1>; 207defm : X86WriteRes<WriteStore, [SKXPort237, SKXPort4], 1, [1,1], 1>; 208defm : X86WriteRes<WriteStoreNT, [SKXPort237, SKXPort4], 1, [1,1], 2>; 209defm : X86WriteRes<WriteMove, [SKXPort0156], 1, [1], 1>; 210 211// Model the effect of clobbering the read-write mask operand of the GATHER operation. 212// Does not cost anything by itself, only has latency, matching that of the WriteLoad, 213defm : X86WriteRes<WriteVecMaskedGatherWriteback, [], 5, [], 0>; 214 215// Idioms that clear a register, like xorps %xmm0, %xmm0. 216// These can often bypass execution ports completely. 217def : WriteRes<WriteZero, []>; 218 219// Branches don't produce values, so they have no latency, but they still 220// consume resources. Indirect branches can fold loads. 221defm : SKXWriteResPair<WriteJump, [SKXPort06], 1>; 222 223// Floating point. This covers both scalar and vector operations. 224defm : X86WriteRes<WriteFLD0, [SKXPort05], 1, [1], 1>; 225defm : X86WriteRes<WriteFLD1, [SKXPort05], 1, [2], 2>; 226defm : X86WriteRes<WriteFLDC, [SKXPort05], 1, [2], 2>; 227defm : X86WriteRes<WriteFLoad, [SKXPort23], 5, [1], 1>; 228defm : X86WriteRes<WriteFLoadX, [SKXPort23], 6, [1], 1>; 229defm : X86WriteRes<WriteFLoadY, [SKXPort23], 7, [1], 1>; 230defm : X86WriteRes<WriteFMaskedLoad, [SKXPort23,SKXPort015], 7, [1,1], 2>; 231defm : X86WriteRes<WriteFMaskedLoadY, [SKXPort23,SKXPort015], 8, [1,1], 2>; 232defm : X86WriteRes<WriteFStore, [SKXPort237,SKXPort4], 1, [1,1], 2>; 233defm : X86WriteRes<WriteFStoreX, [SKXPort237,SKXPort4], 1, [1,1], 2>; 234defm : X86WriteRes<WriteFStoreY, [SKXPort237,SKXPort4], 1, [1,1], 2>; 235defm : X86WriteRes<WriteFStoreNT, [SKXPort237,SKXPort4], 1, [1,1], 2>; 236defm : X86WriteRes<WriteFStoreNTX, [SKXPort237,SKXPort4], 1, [1,1], 2>; 237defm : X86WriteRes<WriteFStoreNTY, [SKXPort237,SKXPort4], 1, [1,1], 2>; 238 239defm : X86WriteRes<WriteFMaskedStore32, [SKXPort237,SKXPort0], 2, [1,1], 2>; 240defm : X86WriteRes<WriteFMaskedStore32Y, [SKXPort237,SKXPort0], 2, [1,1], 2>; 241defm : X86WriteRes<WriteFMaskedStore64, [SKXPort237,SKXPort0], 2, [1,1], 2>; 242defm : X86WriteRes<WriteFMaskedStore64Y, [SKXPort237,SKXPort0], 2, [1,1], 2>; 243 244defm : X86WriteRes<WriteFMove, [SKXPort015], 1, [1], 1>; 245defm : X86WriteRes<WriteFMoveX, [SKXPort015], 1, [1], 1>; 246defm : X86WriteRes<WriteFMoveY, [SKXPort015], 1, [1], 1>; 247defm : X86WriteRes<WriteFMoveZ, [SKXPort05], 1, [1], 1>; 248defm : X86WriteRes<WriteEMMS, [SKXPort05,SKXPort0156], 10, [9,1], 10>; 249 250defm : SKXWriteResPair<WriteFAdd, [SKXPort01], 4, [1], 1, 5>; // Floating point add/sub. 251defm : SKXWriteResPair<WriteFAddX, [SKXPort01], 4, [1], 1, 6>; 252defm : SKXWriteResPair<WriteFAddY, [SKXPort01], 4, [1], 1, 7>; 253defm : SKXWriteResPair<WriteFAddZ, [SKXPort05], 4, [1], 1, 7>; 254defm : SKXWriteResPair<WriteFAdd64, [SKXPort01], 4, [1], 1, 5>; // Floating point double add/sub. 255defm : SKXWriteResPair<WriteFAdd64X, [SKXPort01], 4, [1], 1, 6>; 256defm : SKXWriteResPair<WriteFAdd64Y, [SKXPort01], 4, [1], 1, 7>; 257defm : SKXWriteResPair<WriteFAdd64Z, [SKXPort05], 4, [1], 1, 7>; 258 259defm : SKXWriteResPair<WriteFCmp, [SKXPort01], 4, [1], 1, 5>; // Floating point compare. 260defm : SKXWriteResPair<WriteFCmpX, [SKXPort01], 4, [1], 1, 6>; 261defm : SKXWriteResPair<WriteFCmpY, [SKXPort01], 4, [1], 1, 7>; 262defm : SKXWriteResPair<WriteFCmpZ, [SKXPort05], 4, [1], 1, 7>; 263defm : SKXWriteResPair<WriteFCmp64, [SKXPort01], 4, [1], 1, 5>; // Floating point double compare. 264defm : SKXWriteResPair<WriteFCmp64X, [SKXPort01], 4, [1], 1, 6>; 265defm : SKXWriteResPair<WriteFCmp64Y, [SKXPort01], 4, [1], 1, 7>; 266defm : SKXWriteResPair<WriteFCmp64Z, [SKXPort05], 4, [1], 1, 7>; 267 268defm : SKXWriteResPair<WriteFCom, [SKXPort0], 2>; // Floating point compare to flags (X87). 269defm : SKXWriteResPair<WriteFComX, [SKXPort0], 2>; // Floating point compare to flags (SSE). 270 271defm : SKXWriteResPair<WriteFMul, [SKXPort01], 4, [1], 1, 5>; // Floating point multiplication. 272defm : SKXWriteResPair<WriteFMulX, [SKXPort01], 4, [1], 1, 6>; 273defm : SKXWriteResPair<WriteFMulY, [SKXPort01], 4, [1], 1, 7>; 274defm : SKXWriteResPair<WriteFMulZ, [SKXPort05], 4, [1], 1, 7>; 275defm : SKXWriteResPair<WriteFMul64, [SKXPort01], 4, [1], 1, 5>; // Floating point double multiplication. 276defm : SKXWriteResPair<WriteFMul64X, [SKXPort01], 4, [1], 1, 6>; 277defm : SKXWriteResPair<WriteFMul64Y, [SKXPort01], 4, [1], 1, 7>; 278defm : SKXWriteResPair<WriteFMul64Z, [SKXPort05], 4, [1], 1, 7>; 279 280defm : SKXWriteResPair<WriteFDiv, [SKXPort0,SKXFPDivider], 11, [1,3], 1, 5>; // 10-14 cycles. // Floating point division. 281//defm : SKXWriteResPair<WriteFDivX, [SKXPort0,SKXFPDivider], 11, [1,3], 1, 6>; // 10-14 cycles. 282defm : SKXWriteResPair<WriteFDivY, [SKXPort0,SKXFPDivider], 11, [1,5], 1, 7>; // 10-14 cycles. 283defm : SKXWriteResPair<WriteFDivZ, [SKXPort0,SKXPort5,SKXFPDivider], 18, [2,1,10], 3, 7>; // 10-14 cycles. 284//defm : SKXWriteResPair<WriteFDiv64, [SKXPort0,SKXFPDivider], 14, [1,3], 1, 5>; // 10-14 cycles. // Floating point division. 285//defm : SKXWriteResPair<WriteFDiv64X, [SKXPort0,SKXFPDivider], 14, [1,3], 1, 6>; // 10-14 cycles. 286//defm : SKXWriteResPair<WriteFDiv64Y, [SKXPort0,SKXFPDivider], 14, [1,5], 1, 7>; // 10-14 cycles. 287defm : SKXWriteResPair<WriteFDiv64Z, [SKXPort0,SKXPort5,SKXFPDivider], 23, [2,1,16], 3, 7>; // 10-14 cycles. 288 289defm : SKXWriteResPair<WriteFSqrt, [SKXPort0,SKXFPDivider], 12, [1,3], 1, 5>; // Floating point square root. 290defm : SKXWriteResPair<WriteFSqrtX, [SKXPort0,SKXFPDivider], 12, [1,3], 1, 6>; 291defm : SKXWriteResPair<WriteFSqrtY, [SKXPort0,SKXFPDivider], 12, [1,6], 1, 7>; 292defm : SKXWriteResPair<WriteFSqrtZ, [SKXPort0,SKXPort5,SKXFPDivider], 20, [2,1,12], 3, 7>; 293defm : SKXWriteResPair<WriteFSqrt64, [SKXPort0,SKXFPDivider], 18, [1,6], 1, 5>; // Floating point double square root. 294defm : SKXWriteResPair<WriteFSqrt64X, [SKXPort0,SKXFPDivider], 18, [1,6], 1, 6>; 295defm : SKXWriteResPair<WriteFSqrt64Y, [SKXPort0,SKXFPDivider], 18, [1,12],1, 7>; 296defm : SKXWriteResPair<WriteFSqrt64Z, [SKXPort0,SKXPort5,SKXFPDivider], 32, [2,1,24], 3, 7>; 297defm : SKXWriteResPair<WriteFSqrt80, [SKXPort0,SKXFPDivider], 21, [1,7]>; // Floating point long double square root. 298 299defm : SKXWriteResPair<WriteFRcp, [SKXPort0], 4, [1], 1, 5>; // Floating point reciprocal estimate. 300defm : SKXWriteResPair<WriteFRcpX, [SKXPort0], 4, [1], 1, 6>; 301defm : SKXWriteResPair<WriteFRcpY, [SKXPort0], 4, [1], 1, 7>; 302defm : SKXWriteResPair<WriteFRcpZ, [SKXPort0,SKXPort5], 4, [2,1], 3, 7>; 303 304defm : SKXWriteResPair<WriteFRsqrt, [SKXPort0], 4, [1], 1, 5>; // Floating point reciprocal square root estimate. 305defm : SKXWriteResPair<WriteFRsqrtX,[SKXPort0], 4, [1], 1, 6>; 306defm : SKXWriteResPair<WriteFRsqrtY,[SKXPort0], 4, [1], 1, 7>; 307defm : SKXWriteResPair<WriteFRsqrtZ,[SKXPort0,SKXPort5], 9, [2,1], 3, 7>; 308 309defm : SKXWriteResPair<WriteFMA, [SKXPort01], 4, [1], 1, 5>; // Fused Multiply Add. 310defm : SKXWriteResPair<WriteFMAX, [SKXPort01], 4, [1], 1, 6>; 311defm : SKXWriteResPair<WriteFMAY, [SKXPort01], 4, [1], 1, 7>; 312defm : SKXWriteResPair<WriteFMAZ, [SKXPort05], 4, [1], 1, 7>; 313defm : SKXWriteResPair<WriteDPPD, [SKXPort5,SKXPort015], 9, [1,2], 3, 6>; // Floating point double dot product. 314defm : SKXWriteResPair<WriteDPPS, [SKXPort5,SKXPort015], 13, [1,3], 4, 6>; 315defm : SKXWriteResPair<WriteDPPSY,[SKXPort5,SKXPort015], 13, [1,3], 4, 7>; 316defm : SKXWriteResPair<WriteDPPSZ,[SKXPort5,SKXPort015], 13, [1,3], 4, 7>; 317defm : SKXWriteResPair<WriteFSign, [SKXPort0], 1>; // Floating point fabs/fchs. 318defm : SKXWriteResPair<WriteFRnd, [SKXPort01], 8, [2], 2, 6>; // Floating point rounding. 319defm : SKXWriteResPair<WriteFRndY, [SKXPort01], 8, [2], 2, 7>; 320defm : SKXWriteResPair<WriteFRndZ, [SKXPort05], 8, [2], 2, 7>; 321defm : SKXWriteResPair<WriteFLogic, [SKXPort015], 1, [1], 1, 6>; // Floating point and/or/xor logicals. 322defm : SKXWriteResPair<WriteFLogicY, [SKXPort015], 1, [1], 1, 7>; 323defm : SKXWriteResPair<WriteFLogicZ, [SKXPort05], 1, [1], 1, 7>; 324defm : SKXWriteResPair<WriteFTest, [SKXPort0], 2, [1], 1, 6>; // Floating point TEST instructions. 325defm : SKXWriteResPair<WriteFTestY, [SKXPort0], 2, [1], 1, 7>; 326defm : SKXWriteResPair<WriteFTestZ, [SKXPort0], 2, [1], 1, 7>; 327defm : SKXWriteResPair<WriteFShuffle, [SKXPort5], 1, [1], 1, 6>; // Floating point vector shuffles. 328defm : SKXWriteResPair<WriteFShuffleY, [SKXPort5], 1, [1], 1, 7>; 329defm : SKXWriteResPair<WriteFShuffleZ, [SKXPort5], 1, [1], 1, 7>; 330defm : SKXWriteResPair<WriteFVarShuffle, [SKXPort5], 1, [1], 1, 6>; // Floating point vector variable shuffles. 331defm : SKXWriteResPair<WriteFVarShuffleY, [SKXPort5], 1, [1], 1, 7>; 332defm : SKXWriteResPair<WriteFVarShuffleZ, [SKXPort5], 1, [1], 1, 7>; 333defm : SKXWriteResPair<WriteFBlend, [SKXPort015], 1, [1], 1, 6>; // Floating point vector blends. 334defm : SKXWriteResPair<WriteFBlendY,[SKXPort015], 1, [1], 1, 7>; 335defm : SKXWriteResPair<WriteFBlendZ,[SKXPort015], 1, [1], 1, 7>; 336defm : SKXWriteResPair<WriteFVarBlend, [SKXPort015], 2, [2], 2, 6>; // Fp vector variable blends. 337defm : SKXWriteResPair<WriteFVarBlendY,[SKXPort015], 2, [2], 2, 7>; 338defm : SKXWriteResPair<WriteFVarBlendZ,[SKXPort015], 2, [2], 2, 7>; 339 340// FMA Scheduling helper class. 341// class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; } 342 343// Vector integer operations. 344defm : X86WriteRes<WriteVecLoad, [SKXPort23], 5, [1], 1>; 345defm : X86WriteRes<WriteVecLoadX, [SKXPort23], 6, [1], 1>; 346defm : X86WriteRes<WriteVecLoadY, [SKXPort23], 7, [1], 1>; 347defm : X86WriteRes<WriteVecLoadNT, [SKXPort23], 6, [1], 1>; 348defm : X86WriteRes<WriteVecLoadNTY, [SKXPort23], 7, [1], 1>; 349defm : X86WriteRes<WriteVecMaskedLoad, [SKXPort23,SKXPort015], 7, [1,1], 2>; 350defm : X86WriteRes<WriteVecMaskedLoadY, [SKXPort23,SKXPort015], 8, [1,1], 2>; 351defm : X86WriteRes<WriteVecStore, [SKXPort237,SKXPort4], 1, [1,1], 2>; 352defm : X86WriteRes<WriteVecStoreX, [SKXPort237,SKXPort4], 1, [1,1], 2>; 353defm : X86WriteRes<WriteVecStoreY, [SKXPort237,SKXPort4], 1, [1,1], 2>; 354defm : X86WriteRes<WriteVecStoreNT, [SKXPort237,SKXPort4], 1, [1,1], 2>; 355defm : X86WriteRes<WriteVecStoreNTY, [SKXPort237,SKXPort4], 1, [1,1], 2>; 356defm : X86WriteRes<WriteVecMaskedStore32, [SKXPort237,SKXPort0], 2, [1,1], 2>; 357defm : X86WriteRes<WriteVecMaskedStore32Y, [SKXPort237,SKXPort0], 2, [1,1], 2>; 358defm : X86WriteRes<WriteVecMaskedStore64, [SKXPort237,SKXPort0], 2, [1,1], 2>; 359defm : X86WriteRes<WriteVecMaskedStore64Y, [SKXPort237,SKXPort0], 2, [1,1], 2>; 360defm : X86WriteRes<WriteVecMove, [SKXPort05], 1, [1], 1>; 361defm : X86WriteRes<WriteVecMoveX, [SKXPort015], 1, [1], 1>; 362defm : X86WriteRes<WriteVecMoveY, [SKXPort015], 1, [1], 1>; 363defm : X86WriteRes<WriteVecMoveZ, [SKXPort05], 1, [1], 1>; 364defm : X86WriteRes<WriteVecMoveToGpr, [SKXPort0], 2, [1], 1>; 365defm : X86WriteRes<WriteVecMoveFromGpr, [SKXPort5], 1, [1], 1>; 366 367defm : SKXWriteResPair<WriteVecALU, [SKXPort05], 1, [1], 1, 5>; // Vector integer ALU op, no logicals. 368defm : SKXWriteResPair<WriteVecALUX, [SKXPort01], 1, [1], 1, 6>; 369defm : SKXWriteResPair<WriteVecALUY, [SKXPort01], 1, [1], 1, 7>; 370defm : SKXWriteResPair<WriteVecALUZ, [SKXPort0], 1, [1], 1, 7>; 371defm : SKXWriteResPair<WriteVecLogic, [SKXPort05], 1, [1], 1, 5>; // Vector integer and/or/xor. 372defm : SKXWriteResPair<WriteVecLogicX,[SKXPort015], 1, [1], 1, 6>; 373defm : SKXWriteResPair<WriteVecLogicY,[SKXPort015], 1, [1], 1, 7>; 374defm : SKXWriteResPair<WriteVecLogicZ,[SKXPort05], 1, [1], 1, 7>; 375defm : SKXWriteResPair<WriteVecTest, [SKXPort0,SKXPort5], 3, [1,1], 2, 6>; // Vector integer TEST instructions. 376defm : SKXWriteResPair<WriteVecTestY, [SKXPort0,SKXPort5], 3, [1,1], 2, 7>; 377defm : SKXWriteResPair<WriteVecTestZ, [SKXPort0,SKXPort5], 3, [1,1], 2, 7>; 378defm : SKXWriteResPair<WriteVecIMul, [SKXPort0], 5, [1], 1, 5>; // Vector integer multiply. 379defm : SKXWriteResPair<WriteVecIMulX, [SKXPort01], 5, [1], 1, 6>; 380defm : SKXWriteResPair<WriteVecIMulY, [SKXPort01], 5, [1], 1, 7>; 381defm : SKXWriteResPair<WriteVecIMulZ, [SKXPort05], 5, [1], 1, 7>; 382defm : SKXWriteResPair<WritePMULLD, [SKXPort01], 10, [2], 2, 6>; // Vector PMULLD. 383defm : SKXWriteResPair<WritePMULLDY, [SKXPort01], 10, [2], 2, 7>; 384defm : SKXWriteResPair<WritePMULLDZ, [SKXPort05], 10, [2], 2, 7>; 385defm : SKXWriteResPair<WriteShuffle, [SKXPort5], 1, [1], 1, 5>; // Vector shuffles. 386defm : SKXWriteResPair<WriteShuffleX, [SKXPort5], 1, [1], 1, 6>; 387defm : SKXWriteResPair<WriteShuffleY, [SKXPort5], 1, [1], 1, 7>; 388defm : SKXWriteResPair<WriteShuffleZ, [SKXPort5], 1, [1], 1, 7>; 389defm : SKXWriteResPair<WriteVarShuffle, [SKXPort5], 1, [1], 1, 5>; // Vector variable shuffles. 390defm : SKXWriteResPair<WriteVarShuffleX, [SKXPort5], 1, [1], 1, 6>; 391defm : SKXWriteResPair<WriteVarShuffleY, [SKXPort5], 1, [1], 1, 7>; 392defm : SKXWriteResPair<WriteVarShuffleZ, [SKXPort5], 1, [1], 1, 7>; 393defm : SKXWriteResPair<WriteBlend, [SKXPort5], 1, [1], 1, 6>; // Vector blends. 394defm : SKXWriteResPair<WriteBlendY,[SKXPort5], 1, [1], 1, 7>; 395defm : SKXWriteResPair<WriteBlendZ,[SKXPort5], 1, [1], 1, 7>; 396defm : SKXWriteResPair<WriteVarBlend, [SKXPort015], 2, [2], 2, 6>; // Vector variable blends. 397defm : SKXWriteResPair<WriteVarBlendY,[SKXPort015], 2, [2], 2, 6>; 398defm : SKXWriteResPair<WriteVarBlendZ,[SKXPort05], 2, [1], 1, 6>; 399defm : SKXWriteResPair<WriteMPSAD, [SKXPort5], 4, [2], 2, 6>; // Vector MPSAD. 400defm : SKXWriteResPair<WriteMPSADY, [SKXPort5], 4, [2], 2, 7>; 401defm : SKXWriteResPair<WriteMPSADZ, [SKXPort5], 4, [2], 2, 7>; 402defm : SKXWriteResPair<WritePSADBW, [SKXPort5], 3, [1], 1, 5>; // Vector PSADBW. 403defm : SKXWriteResPair<WritePSADBWX, [SKXPort5], 3, [1], 1, 6>; 404defm : SKXWriteResPair<WritePSADBWY, [SKXPort5], 3, [1], 1, 7>; 405defm : SKXWriteResPair<WritePSADBWZ, [SKXPort5], 3, [1], 1, 7>; 406defm : SKXWriteResPair<WritePHMINPOS, [SKXPort0], 4, [1], 1, 6>; // Vector PHMINPOS. 407 408// Vector integer shifts. 409defm : SKXWriteResPair<WriteVecShift, [SKXPort0], 1, [1], 1, 5>; 410defm : X86WriteRes<WriteVecShiftX, [SKXPort5,SKXPort01], 2, [1,1], 2>; 411defm : X86WriteRes<WriteVecShiftY, [SKXPort5,SKXPort01], 4, [1,1], 2>; 412defm : X86WriteRes<WriteVecShiftZ, [SKXPort5,SKXPort0], 4, [1,1], 2>; 413defm : X86WriteRes<WriteVecShiftXLd, [SKXPort01,SKXPort23], 7, [1,1], 2>; 414defm : X86WriteRes<WriteVecShiftYLd, [SKXPort01,SKXPort23], 8, [1,1], 2>; 415defm : X86WriteRes<WriteVecShiftZLd, [SKXPort0,SKXPort23], 8, [1,1], 2>; 416 417defm : SKXWriteResPair<WriteVecShiftImm, [SKXPort0], 1, [1], 1, 5>; 418defm : SKXWriteResPair<WriteVecShiftImmX, [SKXPort01], 1, [1], 1, 6>; // Vector integer immediate shifts. 419defm : SKXWriteResPair<WriteVecShiftImmY, [SKXPort01], 1, [1], 1, 7>; 420defm : SKXWriteResPair<WriteVecShiftImmZ, [SKXPort0], 1, [1], 1, 7>; 421defm : SKXWriteResPair<WriteVarVecShift, [SKXPort01], 1, [1], 1, 6>; // Variable vector shifts. 422defm : SKXWriteResPair<WriteVarVecShiftY, [SKXPort01], 1, [1], 1, 7>; 423defm : SKXWriteResPair<WriteVarVecShiftZ, [SKXPort0], 1, [1], 1, 7>; 424 425// Vector insert/extract operations. 426def : WriteRes<WriteVecInsert, [SKXPort5]> { 427 let Latency = 2; 428 let NumMicroOps = 2; 429 let ResourceCycles = [2]; 430} 431def : WriteRes<WriteVecInsertLd, [SKXPort5,SKXPort23]> { 432 let Latency = 6; 433 let NumMicroOps = 2; 434} 435def: InstRW<[WriteVecInsertLd], (instregex "(V?)MOV(H|L)(PD|PS)rm")>; 436 437def : WriteRes<WriteVecExtract, [SKXPort0,SKXPort5]> { 438 let Latency = 3; 439 let NumMicroOps = 2; 440} 441def : WriteRes<WriteVecExtractSt, [SKXPort4,SKXPort5,SKXPort237]> { 442 let Latency = 2; 443 let NumMicroOps = 3; 444} 445 446// Conversion between integer and float. 447defm : SKXWriteResPair<WriteCvtSS2I, [SKXPort01], 6, [2], 2>; // Needs more work: DD vs DQ. 448defm : SKXWriteResPair<WriteCvtPS2I, [SKXPort01], 3>; 449defm : SKXWriteResPair<WriteCvtPS2IY, [SKXPort01], 3>; 450defm : SKXWriteResPair<WriteCvtPS2IZ, [SKXPort05], 3>; 451defm : SKXWriteResPair<WriteCvtSD2I, [SKXPort01], 6, [2], 2>; 452defm : SKXWriteResPair<WriteCvtPD2I, [SKXPort01], 3>; 453defm : SKXWriteResPair<WriteCvtPD2IY, [SKXPort01], 3>; 454defm : SKXWriteResPair<WriteCvtPD2IZ, [SKXPort05], 3>; 455 456defm : SKXWriteResPair<WriteCvtI2SS, [SKXPort1], 4>; 457defm : SKXWriteResPair<WriteCvtI2PS, [SKXPort01], 4>; 458defm : SKXWriteResPair<WriteCvtI2PSY, [SKXPort01], 4>; 459defm : SKXWriteResPair<WriteCvtI2PSZ, [SKXPort05], 4>; // Needs more work: DD vs DQ. 460defm : SKXWriteResPair<WriteCvtI2SD, [SKXPort1], 4>; 461defm : SKXWriteResPair<WriteCvtI2PD, [SKXPort01], 4>; 462defm : SKXWriteResPair<WriteCvtI2PDY, [SKXPort01], 4>; 463defm : SKXWriteResPair<WriteCvtI2PDZ, [SKXPort05], 4>; 464 465defm : SKXWriteResPair<WriteCvtSS2SD, [SKXPort1], 3>; 466defm : SKXWriteResPair<WriteCvtPS2PD, [SKXPort1], 3>; 467defm : SKXWriteResPair<WriteCvtPS2PDY, [SKXPort5,SKXPort01], 3, [1,1], 2>; 468defm : SKXWriteResPair<WriteCvtPS2PDZ, [SKXPort05], 3, [2], 2>; 469defm : SKXWriteResPair<WriteCvtSD2SS, [SKXPort1], 3>; 470defm : SKXWriteResPair<WriteCvtPD2PS, [SKXPort1], 3>; 471defm : SKXWriteResPair<WriteCvtPD2PSY, [SKXPort5,SKXPort01], 3, [1,1], 2>; 472defm : SKXWriteResPair<WriteCvtPD2PSZ, [SKXPort05], 3, [2], 2>; 473 474defm : X86WriteRes<WriteCvtPH2PS, [SKXPort5,SKXPort01], 5, [1,1], 2>; 475defm : X86WriteRes<WriteCvtPH2PSY, [SKXPort5,SKXPort01], 7, [1,1], 2>; 476defm : X86WriteRes<WriteCvtPH2PSZ, [SKXPort5,SKXPort0], 7, [1,1], 2>; 477defm : X86WriteRes<WriteCvtPH2PSLd, [SKXPort23,SKXPort01], 9, [1,1], 2>; 478defm : X86WriteRes<WriteCvtPH2PSYLd, [SKXPort23,SKXPort01], 10, [1,1], 2>; 479defm : X86WriteRes<WriteCvtPH2PSZLd, [SKXPort23,SKXPort05], 10, [1,1], 2>; 480 481defm : X86WriteRes<WriteCvtPS2PH, [SKXPort5,SKXPort01], 5, [1,1], 2>; 482defm : X86WriteRes<WriteCvtPS2PHY, [SKXPort5,SKXPort01], 7, [1,1], 2>; 483defm : X86WriteRes<WriteCvtPS2PHZ, [SKXPort5,SKXPort05], 7, [1,1], 2>; 484defm : X86WriteRes<WriteCvtPS2PHSt, [SKXPort4,SKXPort5,SKXPort237,SKXPort01], 6, [1,1,1,1], 4>; 485defm : X86WriteRes<WriteCvtPS2PHYSt, [SKXPort4,SKXPort5,SKXPort237,SKXPort01], 8, [1,1,1,1], 4>; 486defm : X86WriteRes<WriteCvtPS2PHZSt, [SKXPort4,SKXPort5,SKXPort237,SKXPort05], 8, [1,1,1,1], 4>; 487 488// Strings instructions. 489 490// Packed Compare Implicit Length Strings, Return Mask 491def : WriteRes<WritePCmpIStrM, [SKXPort0]> { 492 let Latency = 10; 493 let NumMicroOps = 3; 494 let ResourceCycles = [3]; 495} 496def : WriteRes<WritePCmpIStrMLd, [SKXPort0, SKXPort23]> { 497 let Latency = 16; 498 let NumMicroOps = 4; 499 let ResourceCycles = [3,1]; 500} 501 502// Packed Compare Explicit Length Strings, Return Mask 503def : WriteRes<WritePCmpEStrM, [SKXPort0, SKXPort5, SKXPort015, SKXPort0156]> { 504 let Latency = 19; 505 let NumMicroOps = 9; 506 let ResourceCycles = [4,3,1,1]; 507} 508def : WriteRes<WritePCmpEStrMLd, [SKXPort0, SKXPort5, SKXPort23, SKXPort015, SKXPort0156]> { 509 let Latency = 25; 510 let NumMicroOps = 10; 511 let ResourceCycles = [4,3,1,1,1]; 512} 513 514// Packed Compare Implicit Length Strings, Return Index 515def : WriteRes<WritePCmpIStrI, [SKXPort0]> { 516 let Latency = 10; 517 let NumMicroOps = 3; 518 let ResourceCycles = [3]; 519} 520def : WriteRes<WritePCmpIStrILd, [SKXPort0, SKXPort23]> { 521 let Latency = 16; 522 let NumMicroOps = 4; 523 let ResourceCycles = [3,1]; 524} 525 526// Packed Compare Explicit Length Strings, Return Index 527def : WriteRes<WritePCmpEStrI, [SKXPort0,SKXPort5,SKXPort0156]> { 528 let Latency = 18; 529 let NumMicroOps = 8; 530 let ResourceCycles = [4,3,1]; 531} 532def : WriteRes<WritePCmpEStrILd, [SKXPort0, SKXPort5, SKXPort23, SKXPort0156]> { 533 let Latency = 24; 534 let NumMicroOps = 9; 535 let ResourceCycles = [4,3,1,1]; 536} 537 538// MOVMSK Instructions. 539def : WriteRes<WriteFMOVMSK, [SKXPort0]> { let Latency = 2; } 540def : WriteRes<WriteVecMOVMSK, [SKXPort0]> { let Latency = 2; } 541def : WriteRes<WriteVecMOVMSKY, [SKXPort0]> { let Latency = 2; } 542def : WriteRes<WriteMMXMOVMSK, [SKXPort0]> { let Latency = 2; } 543 544// AES instructions. 545def : WriteRes<WriteAESDecEnc, [SKXPort0]> { // Decryption, encryption. 546 let Latency = 4; 547 let NumMicroOps = 1; 548 let ResourceCycles = [1]; 549} 550def : WriteRes<WriteAESDecEncLd, [SKXPort0, SKXPort23]> { 551 let Latency = 10; 552 let NumMicroOps = 2; 553 let ResourceCycles = [1,1]; 554} 555 556def : WriteRes<WriteAESIMC, [SKXPort0]> { // InvMixColumn. 557 let Latency = 8; 558 let NumMicroOps = 2; 559 let ResourceCycles = [2]; 560} 561def : WriteRes<WriteAESIMCLd, [SKXPort0, SKXPort23]> { 562 let Latency = 14; 563 let NumMicroOps = 3; 564 let ResourceCycles = [2,1]; 565} 566 567def : WriteRes<WriteAESKeyGen, [SKXPort0,SKXPort5,SKXPort015]> { // Key Generation. 568 let Latency = 20; 569 let NumMicroOps = 11; 570 let ResourceCycles = [3,6,2]; 571} 572def : WriteRes<WriteAESKeyGenLd, [SKXPort0,SKXPort5,SKXPort23,SKXPort015]> { 573 let Latency = 25; 574 let NumMicroOps = 11; 575 let ResourceCycles = [3,6,1,1]; 576} 577 578// Carry-less multiplication instructions. 579def : WriteRes<WriteCLMul, [SKXPort5]> { 580 let Latency = 6; 581 let NumMicroOps = 1; 582 let ResourceCycles = [1]; 583} 584def : WriteRes<WriteCLMulLd, [SKXPort5, SKXPort23]> { 585 let Latency = 12; 586 let NumMicroOps = 2; 587 let ResourceCycles = [1,1]; 588} 589 590// Catch-all for expensive system instructions. 591def : WriteRes<WriteSystem, [SKXPort0156]> { let Latency = 100; } // def WriteSystem : SchedWrite; 592 593// AVX2. 594defm : SKXWriteResPair<WriteFShuffle256, [SKXPort5], 3, [1], 1, 7>; // Fp 256-bit width vector shuffles. 595defm : SKXWriteResPair<WriteFVarShuffle256, [SKXPort5], 3, [1], 1, 7>; // Fp 256-bit width vector variable shuffles. 596defm : SKXWriteResPair<WriteShuffle256, [SKXPort5], 3, [1], 1, 7>; // 256-bit width vector shuffles. 597defm : SKXWriteResPair<WriteVPMOV256, [SKXPort5], 3, [1], 1, 7>; // 256-bit width packed vector width-changing move. 598defm : SKXWriteResPair<WriteVarShuffle256, [SKXPort5], 3, [1], 1, 7>; // 256-bit width vector variable shuffles. 599 600// Old microcoded instructions that nobody use. 601def : WriteRes<WriteMicrocoded, [SKXPort0156]> { let Latency = 100; } // def WriteMicrocoded : SchedWrite; 602 603// Fence instructions. 604def : WriteRes<WriteFence, [SKXPort23, SKXPort4]>; 605 606// Load/store MXCSR. 607def : WriteRes<WriteLDMXCSR, [SKXPort0,SKXPort23,SKXPort0156]> { let Latency = 7; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } 608def : WriteRes<WriteSTMXCSR, [SKXPort4,SKXPort5,SKXPort237]> { let Latency = 2; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } 609 610// Nop, not very useful expect it provides a model for nops! 611def : WriteRes<WriteNop, []>; 612 613//////////////////////////////////////////////////////////////////////////////// 614// Horizontal add/sub instructions. 615//////////////////////////////////////////////////////////////////////////////// 616 617defm : SKXWriteResPair<WriteFHAdd, [SKXPort5,SKXPort015], 6, [2,1], 3, 6>; 618defm : SKXWriteResPair<WriteFHAddY, [SKXPort5,SKXPort015], 6, [2,1], 3, 7>; 619defm : SKXWriteResPair<WritePHAdd, [SKXPort5,SKXPort05], 3, [2,1], 3, 5>; 620defm : SKXWriteResPair<WritePHAddX, [SKXPort5,SKXPort015], 3, [2,1], 3, 6>; 621defm : SKXWriteResPair<WritePHAddY, [SKXPort5,SKXPort015], 3, [2,1], 3, 7>; 622 623// Remaining instrs. 624 625def SKXWriteResGroup1 : SchedWriteRes<[SKXPort0]> { 626 let Latency = 1; 627 let NumMicroOps = 1; 628 let ResourceCycles = [1]; 629} 630def: InstRW<[SKXWriteResGroup1], (instregex "KAND(B|D|Q|W)rr", 631 "KANDN(B|D|Q|W)rr", 632 "KMOV(B|D|Q|W)kk", 633 "KNOT(B|D|Q|W)rr", 634 "KOR(B|D|Q|W)rr", 635 "KXNOR(B|D|Q|W)rr", 636 "KXOR(B|D|Q|W)rr", 637 "KSET0(B|D|Q|W)", // Same as KXOR 638 "KSET1(B|D|Q|W)", // Same as KXNOR 639 "MMX_PADDS(B|W)rr", 640 "MMX_PADDUS(B|W)rr", 641 "MMX_PAVG(B|W)rr", 642 "MMX_PCMPEQ(B|D|W)rr", 643 "MMX_PCMPGT(B|D|W)rr", 644 "MMX_P(MAX|MIN)SWrr", 645 "MMX_P(MAX|MIN)UBrr", 646 "MMX_PSUBS(B|W)rr", 647 "MMX_PSUBUS(B|W)rr", 648 "VPMOVB2M(Z|Z128|Z256)rr", 649 "VPMOVD2M(Z|Z128|Z256)rr", 650 "VPMOVQ2M(Z|Z128|Z256)rr", 651 "VPMOVW2M(Z|Z128|Z256)rr")>; 652 653def SKXWriteResGroup3 : SchedWriteRes<[SKXPort5]> { 654 let Latency = 1; 655 let NumMicroOps = 1; 656 let ResourceCycles = [1]; 657} 658def: InstRW<[SKXWriteResGroup3], (instregex "COM(P?)_FST0r", 659 "KMOV(B|D|Q|W)kr", 660 "UCOM_F(P?)r")>; 661 662def SKXWriteResGroup4 : SchedWriteRes<[SKXPort6]> { 663 let Latency = 1; 664 let NumMicroOps = 1; 665 let ResourceCycles = [1]; 666} 667def: InstRW<[SKXWriteResGroup4], (instregex "JMP(16|32|64)r")>; 668 669def SKXWriteResGroup6 : SchedWriteRes<[SKXPort05]> { 670 let Latency = 1; 671 let NumMicroOps = 1; 672 let ResourceCycles = [1]; 673} 674def: InstRW<[SKXWriteResGroup6], (instrs FINCSTP, FNOP)>; 675 676def SKXWriteResGroup7 : SchedWriteRes<[SKXPort06]> { 677 let Latency = 1; 678 let NumMicroOps = 1; 679 let ResourceCycles = [1]; 680} 681def: InstRW<[SKXWriteResGroup7], (instrs CDQ, CQO, CLAC, STAC)>; 682 683def SKXWriteResGroup8 : SchedWriteRes<[SKXPort15]> { 684 let Latency = 1; 685 let NumMicroOps = 1; 686 let ResourceCycles = [1]; 687} 688def: InstRW<[SKXWriteResGroup8], (instregex "ANDN(32|64)rr")>; 689 690def SKXWriteResGroup9 : SchedWriteRes<[SKXPort015]> { 691 let Latency = 1; 692 let NumMicroOps = 1; 693 let ResourceCycles = [1]; 694} 695def: InstRW<[SKXWriteResGroup9], (instregex "VBLENDMPD(Z128|Z256)rr", 696 "VBLENDMPS(Z128|Z256)rr", 697 "VPADD(B|D|Q|W)(Y|Z|Z128|Z256)rr", 698 "(V?)PADD(B|D|Q|W)rr", 699 "VPBLENDD(Y?)rri", 700 "VPBLENDMB(Z128|Z256)rr", 701 "VPBLENDMD(Z128|Z256)rr", 702 "VPBLENDMQ(Z128|Z256)rr", 703 "VPBLENDMW(Z128|Z256)rr", 704 "VPSUB(B|D|Q|W)(Y|Z|Z128|Z256)rrk", 705 "VPTERNLOGD(Z|Z128|Z256)rri", 706 "VPTERNLOGQ(Z|Z128|Z256)rri")>; 707 708def SKXWriteResGroup10 : SchedWriteRes<[SKXPort0156]> { 709 let Latency = 1; 710 let NumMicroOps = 1; 711 let ResourceCycles = [1]; 712} 713def: InstRW<[SKXWriteResGroup10], (instrs CBW, CWDE, CDQE, 714 CMC, STC, 715 SGDT64m, 716 SIDT64m, 717 SMSW16m, 718 STRm, 719 SYSCALL)>; 720 721def SKXWriteResGroup11 : SchedWriteRes<[SKXPort4,SKXPort237]> { 722 let Latency = 1; 723 let NumMicroOps = 2; 724 let ResourceCycles = [1,1]; 725} 726def: InstRW<[SKXWriteResGroup11], (instrs FBSTPm, VMPTRSTm)>; 727def: InstRW<[SKXWriteResGroup11], (instregex "KMOV(B|D|Q|W)mk", 728 "ST_FP(32|64|80)m")>; 729 730def SKXWriteResGroup13 : SchedWriteRes<[SKXPort5]> { 731 let Latency = 2; 732 let NumMicroOps = 2; 733 let ResourceCycles = [2]; 734} 735def: InstRW<[SKXWriteResGroup13], (instrs MMX_MOVQ2DQrr)>; 736 737def SKXWriteResGroup14 : SchedWriteRes<[SKXPort05]> { 738 let Latency = 2; 739 let NumMicroOps = 2; 740 let ResourceCycles = [2]; 741} 742def: InstRW<[SKXWriteResGroup14], (instrs FDECSTP, 743 MMX_MOVDQ2Qrr)>; 744 745def SKXWriteResGroup17 : SchedWriteRes<[SKXPort0156]> { 746 let Latency = 2; 747 let NumMicroOps = 2; 748 let ResourceCycles = [2]; 749} 750def: InstRW<[SKXWriteResGroup17], (instrs LFENCE, 751 WAIT, 752 XGETBV)>; 753 754def SKXWriteResGroup20 : SchedWriteRes<[SKXPort6,SKXPort0156]> { 755 let Latency = 2; 756 let NumMicroOps = 2; 757 let ResourceCycles = [1,1]; 758} 759def: InstRW<[SKXWriteResGroup20], (instregex "CLFLUSH")>; 760 761def SKXWriteResGroup21 : SchedWriteRes<[SKXPort237,SKXPort0156]> { 762 let Latency = 2; 763 let NumMicroOps = 2; 764 let ResourceCycles = [1,1]; 765} 766def: InstRW<[SKXWriteResGroup21], (instrs SFENCE)>; 767 768def SKXWriteResGroup23 : SchedWriteRes<[SKXPort06,SKXPort0156]> { 769 let Latency = 2; 770 let NumMicroOps = 2; 771 let ResourceCycles = [1,1]; 772} 773def: InstRW<[SKXWriteResGroup23], (instrs CWD, 774 JCXZ, JECXZ, JRCXZ, 775 ADC8i8, SBB8i8, 776 ADC16i16, SBB16i16, 777 ADC32i32, SBB32i32, 778 ADC64i32, SBB64i32)>; 779 780def SKXWriteResGroup25 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort237]> { 781 let Latency = 2; 782 let NumMicroOps = 3; 783 let ResourceCycles = [1,1,1]; 784} 785def: InstRW<[SKXWriteResGroup25], (instrs FNSTCW16m)>; 786 787def SKXWriteResGroup27 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort15]> { 788 let Latency = 2; 789 let NumMicroOps = 3; 790 let ResourceCycles = [1,1,1]; 791} 792def: InstRW<[SKXWriteResGroup27], (instregex "MOVBE(16|32|64)mr")>; 793 794def SKXWriteResGroup28 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort0156]> { 795 let Latency = 2; 796 let NumMicroOps = 3; 797 let ResourceCycles = [1,1,1]; 798} 799def: InstRW<[SKXWriteResGroup28], (instrs PUSH16r, PUSH32r, PUSH64r, PUSH64i8, 800 STOSB, STOSL, STOSQ, STOSW)>; 801def: InstRW<[SKXWriteResGroup28], (instregex "PUSH(16|32|64)rmr")>; 802 803def SKXWriteResGroup29 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort15]> { 804 let Latency = 2; 805 let NumMicroOps = 5; 806 let ResourceCycles = [2,2,1]; 807} 808def: InstRW<[SKXWriteResGroup29], (instregex "VMOVDQU8Zmr(b?)")>; 809 810def SKXWriteResGroup30 : SchedWriteRes<[SKXPort0]> { 811 let Latency = 3; 812 let NumMicroOps = 1; 813 let ResourceCycles = [1]; 814} 815def: InstRW<[SKXWriteResGroup30], (instregex "KMOV(B|D|Q|W)rk", 816 "KORTEST(B|D|Q|W)rr", 817 "KTEST(B|D|Q|W)rr")>; 818 819def SKXWriteResGroup31 : SchedWriteRes<[SKXPort1]> { 820 let Latency = 3; 821 let NumMicroOps = 1; 822 let ResourceCycles = [1]; 823} 824def: InstRW<[SKXWriteResGroup31], (instregex "PDEP(32|64)rr", 825 "PEXT(32|64)rr")>; 826 827def SKXWriteResGroup32 : SchedWriteRes<[SKXPort5]> { 828 let Latency = 3; 829 let NumMicroOps = 1; 830 let ResourceCycles = [1]; 831} 832def: InstRW<[SKXWriteResGroup32], (instrs VPSADBWZrr)>; // TODO: 512-bit ops require ports 0/1 to be joined. 833def: InstRW<[SKXWriteResGroup32], (instregex "(ADD|SUB|SUBR)_(FPrST0|FST0r|FrST0)", 834 "VALIGND(Z|Z128|Z256)rri", 835 "VALIGNQ(Z|Z128|Z256)rri", 836 "VDBPSADBWZrri", // TODO: 512-bit ops require ports 0/1 to be joined. 837 "VPBROADCAST(B|W)rr", 838 "VP(MAX|MIN)(S|U)Q(Z|Z128|Z256)rr")>; 839 840def SKXWriteResGroup33 : SchedWriteRes<[SKXPort5]> { 841 let Latency = 4; 842 let NumMicroOps = 1; 843 let ResourceCycles = [1]; 844} 845def: InstRW<[SKXWriteResGroup33], (instregex "KADD(B|D|Q|W)rr", 846 "KSHIFTL(B|D|Q|W)ri", 847 "KSHIFTR(B|D|Q|W)ri", 848 "KUNPCK(BW|DQ|WD)rr", 849 "VCMPPD(Z|Z128|Z256)rri", 850 "VCMPPS(Z|Z128|Z256)rri", 851 "VCMP(SD|SS)Zrr", 852 "VFPCLASS(PD|PS)(Z|Z128|Z256)rr", 853 "VFPCLASS(SD|SS)Zrr", 854 "VPCMPB(Z|Z128|Z256)rri", 855 "VPCMPD(Z|Z128|Z256)rri", 856 "VPCMPEQ(B|D|Q|W)(Z|Z128|Z256)rr", 857 "VPCMPGT(B|D|Q|W)(Z|Z128|Z256)rr", 858 "VPCMPQ(Z|Z128|Z256)rri", 859 "VPCMPU(B|D|Q|W)(Z|Z128|Z256)rri", 860 "VPCMPW(Z|Z128|Z256)rri", 861 "VPTEST(N?)M(B|D|Q|W)(Z|Z128|Z256)rr")>; 862 863def SKXWriteResGroup34 : SchedWriteRes<[SKXPort0,SKXPort0156]> { 864 let Latency = 3; 865 let NumMicroOps = 2; 866 let ResourceCycles = [1,1]; 867} 868def: InstRW<[SKXWriteResGroup34], (instrs FNSTSW16r)>; 869 870def SKXWriteResGroup37 : SchedWriteRes<[SKXPort0,SKXPort5]> { 871 let Latency = 3; 872 let NumMicroOps = 3; 873 let ResourceCycles = [1,2]; 874} 875def: InstRW<[SKXWriteResGroup37], (instregex "MMX_PH(ADD|SUB)SWrr")>; 876 877def SKXWriteResGroup38 : SchedWriteRes<[SKXPort5,SKXPort01]> { 878 let Latency = 3; 879 let NumMicroOps = 3; 880 let ResourceCycles = [2,1]; 881} 882def: InstRW<[SKXWriteResGroup38], (instregex "(V?)PH(ADD|SUB)SW(Y?)rr")>; 883 884def SKXWriteResGroup41 : SchedWriteRes<[SKXPort5,SKXPort0156]> { 885 let Latency = 3; 886 let NumMicroOps = 3; 887 let ResourceCycles = [2,1]; 888} 889def: InstRW<[SKXWriteResGroup41], (instrs MMX_PACKSSDWrr, 890 MMX_PACKSSWBrr, 891 MMX_PACKUSWBrr)>; 892 893def SKXWriteResGroup42 : SchedWriteRes<[SKXPort6,SKXPort0156]> { 894 let Latency = 3; 895 let NumMicroOps = 3; 896 let ResourceCycles = [1,2]; 897} 898def: InstRW<[SKXWriteResGroup42], (instregex "CLD")>; 899 900def SKXWriteResGroup43 : SchedWriteRes<[SKXPort237,SKXPort0156]> { 901 let Latency = 3; 902 let NumMicroOps = 3; 903 let ResourceCycles = [1,2]; 904} 905def: InstRW<[SKXWriteResGroup43], (instrs MFENCE)>; 906 907def SKXWriteResGroup44 : SchedWriteRes<[SKXPort06,SKXPort0156]> { 908 let Latency = 2; 909 let NumMicroOps = 3; 910 let ResourceCycles = [1,2]; 911} 912def: InstRW<[SKXWriteResGroup44], (instrs RCL8r1, RCL16r1, RCL32r1, RCL64r1, 913 RCR8r1, RCR16r1, RCR32r1, RCR64r1)>; 914 915def SKXWriteResGroup44b : SchedWriteRes<[SKXPort1,SKXPort06,SKXPort0156]> { 916 let Latency = 5; 917 let NumMicroOps = 8; 918 let ResourceCycles = [2,4,2]; 919} 920def: InstRW<[SKXWriteResGroup44b], (instrs RCR8ri, RCR16ri, RCR32ri, RCR64ri)>; 921 922def SKXWriteResGroup44c : SchedWriteRes<[SKXPort1,SKXPort06,SKXPort0156]> { 923 let Latency = 6; 924 let NumMicroOps = 8; 925 let ResourceCycles = [2,4,2]; 926} 927def: InstRW<[SKXWriteResGroup44c], (instrs RCL8ri, RCL16ri, RCL32ri, RCL64ri)>; 928 929def SKXWriteResGroup45 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort237]> { 930 let Latency = 3; 931 let NumMicroOps = 3; 932 let ResourceCycles = [1,1,1]; 933} 934def: InstRW<[SKXWriteResGroup45], (instrs FNSTSWm)>; 935 936def SKXWriteResGroup47 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort237,SKXPort0156]> { 937 let Latency = 3; 938 let NumMicroOps = 4; 939 let ResourceCycles = [1,1,1,1]; 940} 941def: InstRW<[SKXWriteResGroup47], (instregex "CALL(16|32|64)r")>; 942 943def SKXWriteResGroup48 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort06,SKXPort0156]> { 944 let Latency = 3; 945 let NumMicroOps = 4; 946 let ResourceCycles = [1,1,1,1]; 947} 948def: InstRW<[SKXWriteResGroup48], (instrs CALL64pcrel32)>; 949 950def SKXWriteResGroup49 : SchedWriteRes<[SKXPort0]> { 951 let Latency = 4; 952 let NumMicroOps = 1; 953 let ResourceCycles = [1]; 954} 955def: InstRW<[SKXWriteResGroup49], (instregex "MUL_(FPrST0|FST0r|FrST0)")>; 956 957def SKXWriteResGroup50 : SchedWriteRes<[SKXPort01]> { 958 let Latency = 4; 959 let NumMicroOps = 1; 960 let ResourceCycles = [1]; 961} 962def: InstRW<[SKXWriteResGroup50], (instregex "VCVTDQ2PS(Y|Z128|Z256)rr", 963 "(V?)CVTDQ2PSrr", 964 "VCVTPD2QQ(Z128|Z256)rr", 965 "VCVTPD2UQQ(Z128|Z256)rr", 966 "VCVTPS2DQ(Y|Z128|Z256)rr", 967 "(V?)CVTPS2DQrr", 968 "VCVTPS2UDQ(Z128|Z256)rr", 969 "VCVTQQ2PD(Z128|Z256)rr", 970 "VCVTTPD2QQ(Z128|Z256)rr", 971 "VCVTTPD2UQQ(Z128|Z256)rr", 972 "VCVTTPS2DQ(Z128|Z256)rr", 973 "(V?)CVTTPS2DQrr", 974 "VCVTTPS2UDQ(Z128|Z256)rr", 975 "VCVTUDQ2PS(Z128|Z256)rr", 976 "VCVTUQQ2PD(Z128|Z256)rr")>; 977 978def SKXWriteResGroup50z : SchedWriteRes<[SKXPort05]> { 979 let Latency = 4; 980 let NumMicroOps = 1; 981 let ResourceCycles = [1]; 982} 983def: InstRW<[SKXWriteResGroup50z], (instrs VCVTDQ2PSZrr, 984 VCVTPD2QQZrr, 985 VCVTPD2UQQZrr, 986 VCVTPS2DQZrr, 987 VCVTPS2UDQZrr, 988 VCVTQQ2PDZrr, 989 VCVTTPD2QQZrr, 990 VCVTTPD2UQQZrr, 991 VCVTTPS2DQZrr, 992 VCVTTPS2UDQZrr, 993 VCVTUDQ2PSZrr, 994 VCVTUQQ2PDZrr)>; 995 996def SKXWriteResGroup51 : SchedWriteRes<[SKXPort5]> { 997 let Latency = 4; 998 let NumMicroOps = 2; 999 let ResourceCycles = [2]; 1000} 1001def: InstRW<[SKXWriteResGroup51], (instregex "VEXPANDPD(Z|Z128|Z256)rr", 1002 "VEXPANDPS(Z|Z128|Z256)rr", 1003 "VPEXPANDD(Z|Z128|Z256)rr", 1004 "VPEXPANDQ(Z|Z128|Z256)rr", 1005 "VPMOVDB(Z|Z128|Z256)rr", 1006 "VPMOVDW(Z|Z128|Z256)rr", 1007 "VPMOVQB(Z|Z128|Z256)rr", 1008 "VPMOVQW(Z|Z128|Z256)rr", 1009 "VPMOVSDB(Z|Z128|Z256)rr", 1010 "VPMOVSDW(Z|Z128|Z256)rr", 1011 "VPMOVSQB(Z|Z128|Z256)rr", 1012 "VPMOVSQD(Z|Z128|Z256)rr", 1013 "VPMOVSQW(Z|Z128|Z256)rr", 1014 "VPMOVSWB(Z|Z128|Z256)rr", 1015 "VPMOVUSDB(Z|Z128|Z256)rr", 1016 "VPMOVUSDW(Z|Z128|Z256)rr", 1017 "VPMOVUSQB(Z|Z128|Z256)rr", 1018 "VPMOVUSQD(Z|Z128|Z256)rr", 1019 "VPMOVUSWB(Z|Z128|Z256)rr", 1020 "VPMOVWB(Z|Z128|Z256)rr")>; 1021 1022def SKXWriteResGroup54 : SchedWriteRes<[SKXPort4,SKXPort5,SKXPort237]> { 1023 let Latency = 4; 1024 let NumMicroOps = 3; 1025 let ResourceCycles = [1,1,1]; 1026} 1027def: InstRW<[SKXWriteResGroup54], (instregex "IST(T?)_FP(16|32|64)m", 1028 "IST_F(16|32)m", 1029 "VPMOVQD(Z|Z128|Z256)mr(b?)")>; 1030 1031def SKXWriteResGroup55 : SchedWriteRes<[SKXPort0156]> { 1032 let Latency = 4; 1033 let NumMicroOps = 4; 1034 let ResourceCycles = [4]; 1035} 1036def: InstRW<[SKXWriteResGroup55], (instrs FNCLEX)>; 1037 1038def SKXWriteResGroup56 : SchedWriteRes<[]> { 1039 let Latency = 0; 1040 let NumMicroOps = 4; 1041 let ResourceCycles = []; 1042} 1043def: InstRW<[SKXWriteResGroup56], (instrs VZEROUPPER)>; 1044 1045def SKXWriteResGroup57 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort0156]> { 1046 let Latency = 4; 1047 let NumMicroOps = 4; 1048 let ResourceCycles = [1,1,2]; 1049} 1050def: InstRW<[SKXWriteResGroup57], (instregex "LAR(16|32|64)rr")>; 1051 1052def SKXWriteResGroup58 : SchedWriteRes<[SKXPort23]> { 1053 let Latency = 5; 1054 let NumMicroOps = 1; 1055 let ResourceCycles = [1]; 1056} 1057def: InstRW<[SKXWriteResGroup58], (instregex "MOVSX(16|32|64)rm(8|16|32)", 1058 "MOVZX(16|32|64)rm(8|16)")>; 1059 1060def SKXWriteResGroup61 : SchedWriteRes<[SKXPort5,SKXPort015]> { 1061 let Latency = 5; 1062 let NumMicroOps = 2; 1063 let ResourceCycles = [1,1]; 1064} 1065def: InstRW<[SKXWriteResGroup61], (instregex "MMX_CVT(T?)PD2PIrr", 1066 "MMX_CVT(T?)PS2PIrr", 1067 "VCVTDQ2PDZ128rr", 1068 "VCVTPD2DQZ128rr", 1069 "(V?)CVT(T?)PD2DQrr", 1070 "VCVTPD2PSZ128rr", 1071 "(V?)CVTPD2PSrr", 1072 "VCVTPD2UDQZ128rr", 1073 "VCVTPS2PDZ128rr", 1074 "(V?)CVTPS2PDrr", 1075 "VCVTPS2QQZ128rr", 1076 "VCVTPS2UQQZ128rr", 1077 "VCVTQQ2PSZ128rr", 1078 "(V?)CVTSD2SS(Z?)rr", 1079 "(V?)CVTSI(64)?2SDrr", 1080 "VCVTSI2SSZrr", 1081 "(V?)CVTSI2SSrr", 1082 "VCVTSI(64)?2SDZrr", 1083 "VCVTSS2SDZrr", 1084 "(V?)CVTSS2SDrr", 1085 "VCVTTPD2DQZ128rr", 1086 "VCVTTPD2UDQZ128rr", 1087 "VCVTTPS2QQZ128rr", 1088 "VCVTTPS2UQQZ128rr", 1089 "VCVTUDQ2PDZ128rr", 1090 "VCVTUQQ2PSZ128rr", 1091 "VCVTUSI2SSZrr", 1092 "VCVTUSI(64)?2SDZrr")>; 1093 1094def SKXWriteResGroup62 : SchedWriteRes<[SKXPort5,SKXPort015]> { 1095 let Latency = 5; 1096 let NumMicroOps = 3; 1097 let ResourceCycles = [2,1]; 1098} 1099def: InstRW<[SKXWriteResGroup62], (instregex "VPCONFLICTQZ128rr")>; 1100 1101def SKXWriteResGroup63 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort06]> { 1102 let Latency = 5; 1103 let NumMicroOps = 3; 1104 let ResourceCycles = [1,1,1]; 1105} 1106def: InstRW<[SKXWriteResGroup63], (instregex "STR(16|32|64)r")>; 1107 1108def SKXWriteResGroup65 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort015]> { 1109 let Latency = 5; 1110 let NumMicroOps = 3; 1111 let ResourceCycles = [1,1,1]; 1112} 1113def: InstRW<[SKXWriteResGroup65], (instregex "VCVTPS2PHZ128mr(b?)", 1114 "VCVTPS2PHZ256mr(b?)", 1115 "VCVTPS2PHZmr(b?)")>; 1116 1117def SKXWriteResGroup66 : SchedWriteRes<[SKXPort4,SKXPort5,SKXPort237]> { 1118 let Latency = 5; 1119 let NumMicroOps = 4; 1120 let ResourceCycles = [1,2,1]; 1121} 1122def: InstRW<[SKXWriteResGroup66], (instregex "VPMOVDB(Z|Z128|Z256)mr(b?)", 1123 "VPMOVDW(Z|Z128|Z256)mr(b?)", 1124 "VPMOVQB(Z|Z128|Z256)mr(b?)", 1125 "VPMOVQW(Z|Z128|Z256)mr(b?)", 1126 "VPMOVSDB(Z|Z128|Z256)mr(b?)", 1127 "VPMOVSDW(Z|Z128|Z256)mr(b?)", 1128 "VPMOVSQB(Z|Z128|Z256)mr(b?)", 1129 "VPMOVSQD(Z|Z128|Z256)mr(b?)", 1130 "VPMOVSQW(Z|Z128|Z256)mr(b?)", 1131 "VPMOVSWB(Z|Z128|Z256)mr(b?)", 1132 "VPMOVUSDB(Z|Z128|Z256)mr(b?)", 1133 "VPMOVUSDW(Z|Z128|Z256)mr(b?)", 1134 "VPMOVUSQB(Z|Z128|Z256)mr(b?)", 1135 "VPMOVUSQD(Z|Z128|Z256)mr(b?)", 1136 "VPMOVUSQW(Z|Z128|Z256)mr(b?)", 1137 "VPMOVUSWB(Z|Z128|Z256)mr(b?)", 1138 "VPMOVWB(Z|Z128|Z256)mr(b?)")>; 1139 1140def SKXWriteResGroup67 : SchedWriteRes<[SKXPort06,SKXPort0156]> { 1141 let Latency = 5; 1142 let NumMicroOps = 5; 1143 let ResourceCycles = [1,4]; 1144} 1145def: InstRW<[SKXWriteResGroup67], (instrs XSETBV)>; 1146 1147def SKXWriteResGroup69 : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort0156]> { 1148 let Latency = 5; 1149 let NumMicroOps = 6; 1150 let ResourceCycles = [1,1,4]; 1151} 1152def: InstRW<[SKXWriteResGroup69], (instregex "PUSHF(16|64)")>; 1153 1154def SKXWriteResGroup71 : SchedWriteRes<[SKXPort23]> { 1155 let Latency = 6; 1156 let NumMicroOps = 1; 1157 let ResourceCycles = [1]; 1158} 1159def: InstRW<[SKXWriteResGroup71], (instrs VBROADCASTSSrm, 1160 VPBROADCASTDrm, 1161 VPBROADCASTQrm)>; 1162def: InstRW<[SKXWriteResGroup71], (instregex "(V?)MOVSHDUPrm", 1163 "(V?)MOVSLDUPrm", 1164 "(V?)MOVDDUPrm")>; 1165 1166def SKXWriteResGroup72 : SchedWriteRes<[SKXPort5]> { 1167 let Latency = 6; 1168 let NumMicroOps = 2; 1169 let ResourceCycles = [2]; 1170} 1171def: InstRW<[SKXWriteResGroup72], (instrs MMX_CVTPI2PSrr)>; 1172def: InstRW<[SKXWriteResGroup72], (instregex "VCOMPRESSPD(Z|Z128|Z256)rr", 1173 "VCOMPRESSPS(Z|Z128|Z256)rr", 1174 "VPCOMPRESSD(Z|Z128|Z256)rr", 1175 "VPCOMPRESSQ(Z|Z128|Z256)rr", 1176 "VPERMW(Z|Z128|Z256)rr")>; 1177 1178def SKXWriteResGroup73 : SchedWriteRes<[SKXPort0,SKXPort23]> { 1179 let Latency = 6; 1180 let NumMicroOps = 2; 1181 let ResourceCycles = [1,1]; 1182} 1183def: InstRW<[SKXWriteResGroup73], (instrs MMX_PADDSBrm, 1184 MMX_PADDSWrm, 1185 MMX_PADDUSBrm, 1186 MMX_PADDUSWrm, 1187 MMX_PAVGBrm, 1188 MMX_PAVGWrm, 1189 MMX_PCMPEQBrm, 1190 MMX_PCMPEQDrm, 1191 MMX_PCMPEQWrm, 1192 MMX_PCMPGTBrm, 1193 MMX_PCMPGTDrm, 1194 MMX_PCMPGTWrm, 1195 MMX_PMAXSWrm, 1196 MMX_PMAXUBrm, 1197 MMX_PMINSWrm, 1198 MMX_PMINUBrm, 1199 MMX_PSUBSBrm, 1200 MMX_PSUBSWrm, 1201 MMX_PSUBUSBrm, 1202 MMX_PSUBUSWrm)>; 1203 1204def SKXWriteResGroup76 : SchedWriteRes<[SKXPort6,SKXPort23]> { 1205 let Latency = 6; 1206 let NumMicroOps = 2; 1207 let ResourceCycles = [1,1]; 1208} 1209def: InstRW<[SKXWriteResGroup76], (instrs FARJMP64m)>; 1210def: InstRW<[SKXWriteResGroup76], (instregex "JMP(16|32|64)m")>; 1211 1212def SKXWriteResGroup79 : SchedWriteRes<[SKXPort23,SKXPort15]> { 1213 let Latency = 6; 1214 let NumMicroOps = 2; 1215 let ResourceCycles = [1,1]; 1216} 1217def: InstRW<[SKXWriteResGroup79], (instregex "ANDN(32|64)rm", 1218 "MOVBE(16|32|64)rm")>; 1219 1220def SKXWriteResGroup80 : SchedWriteRes<[SKXPort23,SKXPort015]> { 1221 let Latency = 6; 1222 let NumMicroOps = 2; 1223 let ResourceCycles = [1,1]; 1224} 1225def: InstRW<[SKXWriteResGroup80], (instregex "VMOV(64to|QI2)PQIZrm(b?)")>; 1226def: InstRW<[SKXWriteResGroup80], (instrs VMOVDI2PDIZrm)>; 1227 1228def SKXWriteResGroup81 : SchedWriteRes<[SKXPort23,SKXPort0156]> { 1229 let Latency = 6; 1230 let NumMicroOps = 2; 1231 let ResourceCycles = [1,1]; 1232} 1233def: InstRW<[SKXWriteResGroup81], (instrs POP16r, POP32r, POP64r)>; 1234def: InstRW<[SKXWriteResGroup81], (instregex "POP(16|32|64)rmr")>; 1235 1236def SKXWriteResGroup82 : SchedWriteRes<[SKXPort5,SKXPort015]> { 1237 let Latency = 6; 1238 let NumMicroOps = 3; 1239 let ResourceCycles = [2,1]; 1240} 1241def: InstRW<[SKXWriteResGroup82], (instregex "(V?)CVTSI642SSrr", 1242 "VCVTSI642SSZrr", 1243 "VCVTUSI642SSZrr")>; 1244 1245def SKXWriteResGroup84 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort06,SKXPort0156]> { 1246 let Latency = 6; 1247 let NumMicroOps = 4; 1248 let ResourceCycles = [1,1,1,1]; 1249} 1250def: InstRW<[SKXWriteResGroup84], (instregex "SLDT(16|32|64)r")>; 1251 1252def SKXWriteResGroup86 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06]> { 1253 let Latency = 6; 1254 let NumMicroOps = 4; 1255 let ResourceCycles = [1,1,1,1]; 1256} 1257def: InstRW<[SKXWriteResGroup86], (instregex "SAR(8|16|32|64)m(1|i)", 1258 "SHL(8|16|32|64)m(1|i)", 1259 "SHR(8|16|32|64)m(1|i)")>; 1260 1261def SKXWriteResGroup87 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort0156]> { 1262 let Latency = 6; 1263 let NumMicroOps = 4; 1264 let ResourceCycles = [1,1,1,1]; 1265} 1266def: InstRW<[SKXWriteResGroup87], (instregex "POP(16|32|64)rmm", 1267 "PUSH(16|32|64)rmm")>; 1268 1269def SKXWriteResGroup88 : SchedWriteRes<[SKXPort6,SKXPort0156]> { 1270 let Latency = 6; 1271 let NumMicroOps = 6; 1272 let ResourceCycles = [1,5]; 1273} 1274def: InstRW<[SKXWriteResGroup88], (instrs STD)>; 1275 1276def SKXWriteResGroup89 : SchedWriteRes<[SKXPort23]> { 1277 let Latency = 7; 1278 let NumMicroOps = 1; 1279 let ResourceCycles = [1]; 1280} 1281def: InstRW<[SKXWriteResGroup89], (instregex "LD_F(32|64|80)m")>; 1282def: InstRW<[SKXWriteResGroup89], (instrs VBROADCASTF128, 1283 VBROADCASTI128, 1284 VBROADCASTSDYrm, 1285 VBROADCASTSSYrm, 1286 VMOVDDUPYrm, 1287 VMOVSHDUPYrm, 1288 VMOVSLDUPYrm, 1289 VPBROADCASTDYrm, 1290 VPBROADCASTQYrm)>; 1291 1292def SKXWriteResGroup90 : SchedWriteRes<[SKXPort01,SKXPort5]> { 1293 let Latency = 7; 1294 let NumMicroOps = 2; 1295 let ResourceCycles = [1,1]; 1296} 1297def: InstRW<[SKXWriteResGroup90], (instrs VCVTDQ2PDYrr)>; 1298 1299def SKXWriteResGroup92 : SchedWriteRes<[SKXPort5,SKXPort23]> { 1300 let Latency = 7; 1301 let NumMicroOps = 2; 1302 let ResourceCycles = [1,1]; 1303} 1304def: InstRW<[SKXWriteResGroup92], (instregex "VMOVSDZrm(b?)", 1305 "VMOVSSZrm(b?)")>; 1306 1307def SKXWriteResGroup92a : SchedWriteRes<[SKXPort5,SKXPort23]> { 1308 let Latency = 6; 1309 let NumMicroOps = 2; 1310 let ResourceCycles = [1,1]; 1311} 1312def: InstRW<[SKXWriteResGroup92a], (instregex "(V?)PMOV(SX|ZX)BDrm", 1313 "(V?)PMOV(SX|ZX)BQrm", 1314 "(V?)PMOV(SX|ZX)BWrm", 1315 "(V?)PMOV(SX|ZX)DQrm", 1316 "(V?)PMOV(SX|ZX)WDrm", 1317 "(V?)PMOV(SX|ZX)WQrm")>; 1318 1319def SKXWriteResGroup93 : SchedWriteRes<[SKXPort5,SKXPort015]> { 1320 let Latency = 7; 1321 let NumMicroOps = 2; 1322 let ResourceCycles = [1,1]; 1323} 1324def: InstRW<[SKXWriteResGroup93], (instregex "VCVTDQ2PDZ256rr", 1325 "VCVTPD2DQ(Y|Z256)rr", 1326 "VCVTPD2PS(Y|Z256)rr", 1327 "VCVTPD2UDQZ256rr", 1328 "VCVTPS2PD(Y|Z256)rr", 1329 "VCVTPS2QQZ256rr", 1330 "VCVTPS2UQQZ256rr", 1331 "VCVTQQ2PSZ256rr", 1332 "VCVTTPD2DQ(Y|Z256)rr", 1333 "VCVTTPD2UDQZ256rr", 1334 "VCVTTPS2QQZ256rr", 1335 "VCVTTPS2UQQZ256rr", 1336 "VCVTUDQ2PDZ256rr", 1337 "VCVTUQQ2PSZ256rr")>; 1338 1339def SKXWriteResGroup93z : SchedWriteRes<[SKXPort5,SKXPort05]> { 1340 let Latency = 7; 1341 let NumMicroOps = 2; 1342 let ResourceCycles = [1,1]; 1343} 1344def: InstRW<[SKXWriteResGroup93z], (instrs VCVTDQ2PDZrr, 1345 VCVTPD2DQZrr, 1346 VCVTPD2PSZrr, 1347 VCVTPD2UDQZrr, 1348 VCVTPS2PDZrr, 1349 VCVTPS2QQZrr, 1350 VCVTPS2UQQZrr, 1351 VCVTQQ2PSZrr, 1352 VCVTTPD2DQZrr, 1353 VCVTTPD2UDQZrr, 1354 VCVTTPS2QQZrr, 1355 VCVTTPS2UQQZrr, 1356 VCVTUDQ2PDZrr, 1357 VCVTUQQ2PSZrr)>; 1358 1359def SKXWriteResGroup95 : SchedWriteRes<[SKXPort23,SKXPort015]> { 1360 let Latency = 7; 1361 let NumMicroOps = 2; 1362 let ResourceCycles = [1,1]; 1363} 1364def: InstRW<[SKXWriteResGroup95], (instrs VMOVNTDQAZ128rm, 1365 VPBLENDDrmi)>; 1366def: InstRW<[SKXWriteResGroup95, ReadAfterVecXLd], 1367 (instregex "VBLENDMPDZ128rm(b?)", 1368 "VBLENDMPSZ128rm(b?)", 1369 "VBROADCASTI32X2Z128rm(b?)", 1370 "VBROADCASTSSZ128rm(b?)", 1371 "VINSERT(F|I)128rm", 1372 "VMOVAPDZ128rm(b?)", 1373 "VMOVAPSZ128rm(b?)", 1374 "VMOVDDUPZ128rm(b?)", 1375 "VMOVDQA32Z128rm(b?)", 1376 "VMOVDQA64Z128rm(b?)", 1377 "VMOVDQU16Z128rm(b?)", 1378 "VMOVDQU32Z128rm(b?)", 1379 "VMOVDQU64Z128rm(b?)", 1380 "VMOVDQU8Z128rm(b?)", 1381 "VMOVSHDUPZ128rm(b?)", 1382 "VMOVSLDUPZ128rm(b?)", 1383 "VMOVUPDZ128rm(b?)", 1384 "VMOVUPSZ128rm(b?)", 1385 "VPADD(B|D|Q|W)Z128rm(b?)", 1386 "(V?)PADD(B|D|Q|W)rm", 1387 "VPBLENDM(B|D|Q|W)Z128rm(b?)", 1388 "VPBROADCASTDZ128rm(b?)", 1389 "VPBROADCASTQZ128rm(b?)", 1390 "VPSUB(B|D|Q|W)Z128rm(b?)", 1391 "(V?)PSUB(B|D|Q|W)rm", 1392 "VPTERNLOGDZ128rm(b?)i", 1393 "VPTERNLOGQZ128rm(b?)i")>; 1394 1395def SKXWriteResGroup96 : SchedWriteRes<[SKXPort5,SKXPort23]> { 1396 let Latency = 7; 1397 let NumMicroOps = 3; 1398 let ResourceCycles = [2,1]; 1399} 1400def: InstRW<[SKXWriteResGroup96], (instrs MMX_PACKSSDWrm, 1401 MMX_PACKSSWBrm, 1402 MMX_PACKUSWBrm)>; 1403 1404def SKXWriteResGroup97 : SchedWriteRes<[SKXPort5,SKXPort015]> { 1405 let Latency = 7; 1406 let NumMicroOps = 3; 1407 let ResourceCycles = [2,1]; 1408} 1409def: InstRW<[SKXWriteResGroup97], (instregex "VPERMI2W128rr", 1410 "VPERMI2W256rr", 1411 "VPERMI2Wrr", 1412 "VPERMT2W128rr", 1413 "VPERMT2W256rr", 1414 "VPERMT2Wrr")>; 1415 1416def SKXWriteResGroup99 : SchedWriteRes<[SKXPort23,SKXPort0156]> { 1417 let Latency = 7; 1418 let NumMicroOps = 3; 1419 let ResourceCycles = [1,2]; 1420} 1421def: InstRW<[SKXWriteResGroup99], (instrs LEAVE, LEAVE64, 1422 SCASB, SCASL, SCASQ, SCASW)>; 1423 1424def SKXWriteResGroup100 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort015]> { 1425 let Latency = 7; 1426 let NumMicroOps = 3; 1427 let ResourceCycles = [1,1,1]; 1428} 1429def: InstRW<[SKXWriteResGroup100], (instregex "VCVTSS2USI64Zrr", 1430 "(V?)CVTSS2SI64(Z?)rr", 1431 "(V?)CVTTSS2SI64(Z?)rr", 1432 "VCVTTSS2USI64Zrr")>; 1433 1434def SKXWriteResGroup101 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort05]> { 1435 let Latency = 7; 1436 let NumMicroOps = 3; 1437 let ResourceCycles = [1,1,1]; 1438} 1439def: InstRW<[SKXWriteResGroup101], (instrs FLDCW16m)>; 1440 1441def SKXWriteResGroup103 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort0156]> { 1442 let Latency = 7; 1443 let NumMicroOps = 3; 1444 let ResourceCycles = [1,1,1]; 1445} 1446def: InstRW<[SKXWriteResGroup103], (instregex "KMOV(B|D|Q|W)km")>; 1447 1448def SKXWriteResGroup104 : SchedWriteRes<[SKXPort6,SKXPort23,SKXPort0156]> { 1449 let Latency = 7; 1450 let NumMicroOps = 3; 1451 let ResourceCycles = [1,1,1]; 1452} 1453def: InstRW<[SKXWriteResGroup104], (instrs LRET64, RET64)>; 1454 1455def SKXWriteResGroup106 : SchedWriteRes<[SKXPort4,SKXPort5,SKXPort237]> { 1456 let Latency = 7; 1457 let NumMicroOps = 4; 1458 let ResourceCycles = [1,2,1]; 1459} 1460def: InstRW<[SKXWriteResGroup106], (instregex "VCOMPRESSPD(Z|Z128|Z256)mr(b?)", 1461 "VCOMPRESSPS(Z|Z128|Z256)mr(b?)", 1462 "VPCOMPRESSD(Z|Z128|Z256)mr(b?)", 1463 "VPCOMPRESSQ(Z|Z128|Z256)mr(b?)")>; 1464 1465def SKXWriteResGroup107 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06]> { 1466 let Latency = 7; 1467 let NumMicroOps = 5; 1468 let ResourceCycles = [1,1,1,2]; 1469} 1470def: InstRW<[SKXWriteResGroup107], (instregex "ROL(8|16|32|64)m(1|i)", 1471 "ROR(8|16|32|64)m(1|i)")>; 1472 1473def SKXWriteResGroup107_1 : SchedWriteRes<[SKXPort06]> { 1474 let Latency = 2; 1475 let NumMicroOps = 2; 1476 let ResourceCycles = [2]; 1477} 1478def: InstRW<[SKXWriteResGroup107_1], (instrs ROL8r1, ROL16r1, ROL32r1, ROL64r1, 1479 ROR8r1, ROR16r1, ROR32r1, ROR64r1)>; 1480 1481def SKXWriteResGroup108 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort0156]> { 1482 let Latency = 7; 1483 let NumMicroOps = 5; 1484 let ResourceCycles = [1,1,1,2]; 1485} 1486def: InstRW<[SKXWriteResGroup108], (instregex "XADD(8|16|32|64)rm")>; 1487 1488def SKXWriteResGroup109 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort23,SKXPort237,SKXPort0156]> { 1489 let Latency = 7; 1490 let NumMicroOps = 5; 1491 let ResourceCycles = [1,1,1,1,1]; 1492} 1493def: InstRW<[SKXWriteResGroup109], (instregex "CALL(16|32|64)m")>; 1494def: InstRW<[SKXWriteResGroup109], (instrs FARCALL64m)>; 1495 1496def SKXWriteResGroup110 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort237,SKXPort0156]> { 1497 let Latency = 7; 1498 let NumMicroOps = 7; 1499 let ResourceCycles = [1,2,2,2]; 1500} 1501def: InstRW<[SKXWriteResGroup110], (instrs VPSCATTERDQZ128mr, 1502 VPSCATTERQQZ128mr, 1503 VSCATTERDPDZ128mr, 1504 VSCATTERQPDZ128mr)>; 1505 1506def SKXWriteResGroup111 : SchedWriteRes<[SKXPort6,SKXPort06,SKXPort15,SKXPort0156]> { 1507 let Latency = 7; 1508 let NumMicroOps = 7; 1509 let ResourceCycles = [1,3,1,2]; 1510} 1511def: InstRW<[SKXWriteResGroup111], (instrs LOOP)>; 1512 1513def SKXWriteResGroup112 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort237,SKXPort0156]> { 1514 let Latency = 7; 1515 let NumMicroOps = 11; 1516 let ResourceCycles = [1,4,4,2]; 1517} 1518def: InstRW<[SKXWriteResGroup112], (instrs VPSCATTERDQZ256mr, 1519 VPSCATTERQQZ256mr, 1520 VSCATTERDPDZ256mr, 1521 VSCATTERQPDZ256mr)>; 1522 1523def SKXWriteResGroup113 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort237,SKXPort0156]> { 1524 let Latency = 7; 1525 let NumMicroOps = 19; 1526 let ResourceCycles = [1,8,8,2]; 1527} 1528def: InstRW<[SKXWriteResGroup113], (instrs VPSCATTERDQZmr, 1529 VPSCATTERQQZmr, 1530 VSCATTERDPDZmr, 1531 VSCATTERQPDZmr)>; 1532 1533def SKXWriteResGroup114 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> { 1534 let Latency = 7; 1535 let NumMicroOps = 36; 1536 let ResourceCycles = [1,16,1,16,2]; 1537} 1538def: InstRW<[SKXWriteResGroup114], (instrs VSCATTERDPSZmr)>; 1539 1540def SKXWriteResGroup118 : SchedWriteRes<[SKXPort1,SKXPort23]> { 1541 let Latency = 8; 1542 let NumMicroOps = 2; 1543 let ResourceCycles = [1,1]; 1544} 1545def: InstRW<[SKXWriteResGroup118], (instregex "PDEP(32|64)rm", 1546 "PEXT(32|64)rm")>; 1547 1548def SKXWriteResGroup119 : SchedWriteRes<[SKXPort5,SKXPort23]> { 1549 let Latency = 8; 1550 let NumMicroOps = 2; 1551 let ResourceCycles = [1,1]; 1552} 1553def: InstRW<[SKXWriteResGroup119], (instregex "FCOM(P?)(32|64)m", 1554 "VPBROADCASTB(Z|Z256)rm(b?)", 1555 "VPBROADCASTW(Z|Z256)rm(b?)")>; 1556def: InstRW<[SKXWriteResGroup119], (instrs VPBROADCASTBYrm, 1557 VPBROADCASTWYrm, 1558 VPMOVSXBDYrm, 1559 VPMOVSXBQYrm, 1560 VPMOVSXWQYrm)>; 1561 1562def SKXWriteResGroup121 : SchedWriteRes<[SKXPort23,SKXPort015]> { 1563 let Latency = 8; 1564 let NumMicroOps = 2; 1565 let ResourceCycles = [1,1]; 1566} 1567def: InstRW<[SKXWriteResGroup121], (instrs VMOVNTDQAZ256rm, 1568 VPBLENDDYrmi)>; 1569def: InstRW<[SKXWriteResGroup121, ReadAfterVecYLd], 1570 (instregex "VBLENDMPD(Z|Z256)rm(b?)", 1571 "VBLENDMPS(Z|Z256)rm(b?)", 1572 "VBROADCASTF32X2Z256rm(b?)", 1573 "VBROADCASTF32X2Zrm(b?)", 1574 "VBROADCASTF32X4Z256rm(b?)", 1575 "VBROADCASTF32X4rm(b?)", 1576 "VBROADCASTF32X8rm(b?)", 1577 "VBROADCASTF64X2Z128rm(b?)", 1578 "VBROADCASTF64X2rm(b?)", 1579 "VBROADCASTF64X4rm(b?)", 1580 "VBROADCASTI32X2Z256rm(b?)", 1581 "VBROADCASTI32X2Zrm(b?)", 1582 "VBROADCASTI32X4Z256rm(b?)", 1583 "VBROADCASTI32X4rm(b?)", 1584 "VBROADCASTI32X8rm(b?)", 1585 "VBROADCASTI64X2Z128rm(b?)", 1586 "VBROADCASTI64X2rm(b?)", 1587 "VBROADCASTI64X4rm(b?)", 1588 "VBROADCASTSD(Z|Z256)rm(b?)", 1589 "VBROADCASTSS(Z|Z256)rm(b?)", 1590 "VINSERTF32x4(Z|Z256)rm(b?)", 1591 "VINSERTF32x8Zrm(b?)", 1592 "VINSERTF64x2(Z|Z256)rm(b?)", 1593 "VINSERTF64x4Zrm(b?)", 1594 "VINSERTI32x4(Z|Z256)rm(b?)", 1595 "VINSERTI32x8Zrm(b?)", 1596 "VINSERTI64x2(Z|Z256)rm(b?)", 1597 "VINSERTI64x4Zrm(b?)", 1598 "VMOVAPD(Z|Z256)rm(b?)", 1599 "VMOVAPS(Z|Z256)rm(b?)", 1600 "VMOVDDUP(Z|Z256)rm(b?)", 1601 "VMOVDQA32(Z|Z256)rm(b?)", 1602 "VMOVDQA64(Z|Z256)rm(b?)", 1603 "VMOVDQU16(Z|Z256)rm(b?)", 1604 "VMOVDQU32(Z|Z256)rm(b?)", 1605 "VMOVDQU64(Z|Z256)rm(b?)", 1606 "VMOVDQU8(Z|Z256)rm(b?)", 1607 "VMOVSHDUP(Z|Z256)rm(b?)", 1608 "VMOVSLDUP(Z|Z256)rm(b?)", 1609 "VMOVUPD(Z|Z256)rm(b?)", 1610 "VMOVUPS(Z|Z256)rm(b?)", 1611 "VPADD(B|D|Q|W)Yrm", 1612 "VPADD(B|D|Q|W)(Z|Z256)rm(b?)", 1613 "VPBLENDM(B|D|Q|W)(Z|Z256)rm(b?)", 1614 "VPBROADCASTD(Z|Z256)rm(b?)", 1615 "VPBROADCASTQ(Z|Z256)rm(b?)", 1616 "VPSUB(B|D|Q|W)Yrm", 1617 "VPSUB(B|D|Q|W)(Z|Z256)rm(b?)", 1618 "VPTERNLOGD(Z|Z256)rm(b?)i", 1619 "VPTERNLOGQ(Z|Z256)rm(b?)i")>; 1620 1621def SKXWriteResGroup123 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> { 1622 let Latency = 8; 1623 let NumMicroOps = 4; 1624 let ResourceCycles = [1,2,1]; 1625} 1626def: InstRW<[SKXWriteResGroup123], (instregex "MMX_PH(ADD|SUB)SWrm")>; 1627 1628def SKXWriteResGroup127 : SchedWriteRes<[SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> { 1629 let Latency = 8; 1630 let NumMicroOps = 5; 1631 let ResourceCycles = [1,1,1,2]; 1632} 1633def: InstRW<[SKXWriteResGroup127], (instregex "RCL(8|16|32|64)m(1|i)", 1634 "RCR(8|16|32|64)m(1|i)")>; 1635 1636def SKXWriteResGroup128 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06]> { 1637 let Latency = 8; 1638 let NumMicroOps = 6; 1639 let ResourceCycles = [1,1,1,3]; 1640} 1641def: InstRW<[SKXWriteResGroup128], (instregex "ROL(8|16|32|64)mCL", 1642 "ROR(8|16|32|64)mCL", 1643 "SAR(8|16|32|64)mCL", 1644 "SHL(8|16|32|64)mCL", 1645 "SHR(8|16|32|64)mCL")>; 1646 1647def SKXWriteResGroup130 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> { 1648 let Latency = 8; 1649 let NumMicroOps = 6; 1650 let ResourceCycles = [1,1,1,2,1]; 1651} 1652def: SchedAlias<WriteADCRMW, SKXWriteResGroup130>; 1653 1654def SKXWriteResGroup131 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> { 1655 let Latency = 8; 1656 let NumMicroOps = 8; 1657 let ResourceCycles = [1,2,1,2,2]; 1658} 1659def: InstRW<[SKXWriteResGroup131], (instrs VPSCATTERQDZ128mr, 1660 VPSCATTERQDZ256mr, 1661 VSCATTERQPSZ128mr, 1662 VSCATTERQPSZ256mr)>; 1663 1664def SKXWriteResGroup132 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> { 1665 let Latency = 8; 1666 let NumMicroOps = 12; 1667 let ResourceCycles = [1,4,1,4,2]; 1668} 1669def: InstRW<[SKXWriteResGroup132], (instrs VPSCATTERDDZ128mr, 1670 VSCATTERDPSZ128mr)>; 1671 1672def SKXWriteResGroup133 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> { 1673 let Latency = 8; 1674 let NumMicroOps = 20; 1675 let ResourceCycles = [1,8,1,8,2]; 1676} 1677def: InstRW<[SKXWriteResGroup133], (instrs VPSCATTERDDZ256mr, 1678 VSCATTERDPSZ256mr)>; 1679 1680def SKXWriteResGroup134 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort237,SKXPort0156]> { 1681 let Latency = 8; 1682 let NumMicroOps = 36; 1683 let ResourceCycles = [1,16,1,16,2]; 1684} 1685def: InstRW<[SKXWriteResGroup134], (instrs VPSCATTERDDZmr)>; 1686 1687def SKXWriteResGroup135 : SchedWriteRes<[SKXPort0,SKXPort23]> { 1688 let Latency = 9; 1689 let NumMicroOps = 2; 1690 let ResourceCycles = [1,1]; 1691} 1692def: InstRW<[SKXWriteResGroup135], (instrs MMX_CVTPI2PSrm)>; 1693 1694def SKXWriteResGroup136 : SchedWriteRes<[SKXPort5,SKXPort23]> { 1695 let Latency = 9; 1696 let NumMicroOps = 2; 1697 let ResourceCycles = [1,1]; 1698} 1699def: InstRW<[SKXWriteResGroup136], (instrs VPMOVSXBWYrm, 1700 VPMOVSXDQYrm, 1701 VPMOVSXWDYrm, 1702 VPMOVZXWDYrm)>; 1703def: InstRW<[SKXWriteResGroup136], (instregex "VALIGN(D|Q)Z128rm(b?)i", 1704 "VFPCLASSSDZrm(b?)", 1705 "VFPCLASSSSZrm(b?)", 1706 "(V?)PCMPGTQrm", 1707 "VPERMI2D128rm(b?)", 1708 "VPERMI2PD128rm(b?)", 1709 "VPERMI2PS128rm(b?)", 1710 "VPERMI2Q128rm(b?)", 1711 "VPERMT2D128rm(b?)", 1712 "VPERMT2PD128rm(b?)", 1713 "VPERMT2PS128rm(b?)", 1714 "VPERMT2Q128rm(b?)", 1715 "VPMAXSQZ128rm(b?)", 1716 "VPMAXUQZ128rm(b?)", 1717 "VPMINSQZ128rm(b?)", 1718 "VPMINUQZ128rm(b?)")>; 1719 1720def SKXWriteResGroup136_2 : SchedWriteRes<[SKXPort5,SKXPort23]> { 1721 let Latency = 10; 1722 let NumMicroOps = 2; 1723 let ResourceCycles = [1,1]; 1724} 1725def: InstRW<[SKXWriteResGroup136_2], (instregex "VCMP(PD|PS)Z128rm(b?)i", 1726 "VCMP(SD|SS)Zrm", 1727 "VFPCLASSPDZ128rm(b?)", 1728 "VFPCLASSPSZ128rm(b?)", 1729 "VPCMPBZ128rmi(b?)", 1730 "VPCMPDZ128rmi(b?)", 1731 "VPCMPEQ(B|D|Q|W)Z128rm(b?)", 1732 "VPCMPGT(B|D|Q|W)Z128rm(b?)", 1733 "VPCMPQZ128rmi(b?)", 1734 "VPCMPU(B|D|Q|W)Z128rmi(b?)", 1735 "VPCMPWZ128rmi(b?)", 1736 "VPTESTMBZ128rm(b?)", 1737 "VPTESTMDZ128rm(b?)", 1738 "VPTESTMQZ128rm(b?)", 1739 "VPTESTMWZ128rm(b?)", 1740 "VPTESTNMBZ128rm(b?)", 1741 "VPTESTNMDZ128rm(b?)", 1742 "VPTESTNMQZ128rm(b?)", 1743 "VPTESTNMWZ128rm(b?)")>; 1744 1745def SKXWriteResGroup137 : SchedWriteRes<[SKXPort23,SKXPort015]> { 1746 let Latency = 9; 1747 let NumMicroOps = 2; 1748 let ResourceCycles = [1,1]; 1749} 1750def: InstRW<[SKXWriteResGroup137], (instregex "MMX_CVT(T?)PS2PIrm", 1751 "(V?)CVTPS2PDrm")>; 1752 1753def SKXWriteResGroup143 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23]> { 1754 let Latency = 9; 1755 let NumMicroOps = 4; 1756 let ResourceCycles = [2,1,1]; 1757} 1758def: InstRW<[SKXWriteResGroup143], (instregex "(V?)PHADDSWrm", 1759 "(V?)PHSUBSWrm")>; 1760 1761def SKXWriteResGroup146 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort23,SKXPort0156]> { 1762 let Latency = 9; 1763 let NumMicroOps = 5; 1764 let ResourceCycles = [1,2,1,1]; 1765} 1766def: InstRW<[SKXWriteResGroup146], (instregex "LAR(16|32|64)rm", 1767 "LSL(16|32|64)rm")>; 1768 1769def SKXWriteResGroup148 : SchedWriteRes<[SKXPort5,SKXPort23]> { 1770 let Latency = 10; 1771 let NumMicroOps = 2; 1772 let ResourceCycles = [1,1]; 1773} 1774def: InstRW<[SKXWriteResGroup148], (instrs VPCMPGTQYrm)>; 1775def: InstRW<[SKXWriteResGroup148], (instregex "(ADD|SUB|SUBR)_F(32|64)m", 1776 "ILD_F(16|32|64)m", 1777 "VALIGND(Z|Z256)rm(b?)i", 1778 "VALIGNQ(Z|Z256)rm(b?)i", 1779 "VPMAXSQ(Z|Z256)rm(b?)", 1780 "VPMAXUQ(Z|Z256)rm(b?)", 1781 "VPMINSQ(Z|Z256)rm(b?)", 1782 "VPMINUQ(Z|Z256)rm(b?)")>; 1783 1784def SKXWriteResGroup148_2 : SchedWriteRes<[SKXPort5,SKXPort23]> { 1785 let Latency = 11; 1786 let NumMicroOps = 2; 1787 let ResourceCycles = [1,1]; 1788} 1789def: InstRW<[SKXWriteResGroup148_2], (instregex "VCMPPD(Z|Z256)rm(b?)i", 1790 "VCMPPS(Z|Z256)rm(b?)i", 1791 "VFPCLASSPD(Z|Z256)rm(b?)", 1792 "VFPCLASSPS(Z|Z256)rm(b?)", 1793 "VPCMPB(Z|Z256)rmi(b?)", 1794 "VPCMPD(Z|Z256)rmi(b?)", 1795 "VPCMPEQB(Z|Z256)rm(b?)", 1796 "VPCMPEQD(Z|Z256)rm(b?)", 1797 "VPCMPEQQ(Z|Z256)rm(b?)", 1798 "VPCMPEQW(Z|Z256)rm(b?)", 1799 "VPCMPGTB(Z|Z256)rm(b?)", 1800 "VPCMPGTD(Z|Z256)rm(b?)", 1801 "VPCMPGTQ(Z|Z256)rm(b?)", 1802 "VPCMPGTW(Z|Z256)rm(b?)", 1803 "VPCMPQ(Z|Z256)rmi(b?)", 1804 "VPCMPU(B|D|Q|W)Z256rmi(b?)", 1805 "VPCMPU(B|D|Q|W)Zrmi(b?)", 1806 "VPCMPW(Z|Z256)rmi(b?)", 1807 "VPTESTM(B|D|Q|W)Z256rm(b?)", 1808 "VPTESTM(B|D|Q|W)Zrm(b?)", 1809 "VPTESTNM(B|D|Q|W)Z256rm(b?)", 1810 "VPTESTNM(B|D|Q|W)Zrm(b?)")>; 1811 1812def SKXWriteResGroup149 : SchedWriteRes<[SKXPort23,SKXPort015]> { 1813 let Latency = 10; 1814 let NumMicroOps = 2; 1815 let ResourceCycles = [1,1]; 1816} 1817def: InstRW<[SKXWriteResGroup149], (instregex "VCVTDQ2PDZ128rm(b?)", 1818 "VCVTDQ2PSZ128rm(b?)", 1819 "(V?)CVTDQ2PSrm", 1820 "VCVTPD2QQZ128rm(b?)", 1821 "VCVTPD2UQQZ128rm(b?)", 1822 "VCVTPH2PSZ128rm(b?)", 1823 "VCVTPS2DQZ128rm(b?)", 1824 "(V?)CVTPS2DQrm", 1825 "VCVTPS2PDZ128rm(b?)", 1826 "VCVTPS2QQZ128rm(b?)", 1827 "VCVTPS2UDQZ128rm(b?)", 1828 "VCVTPS2UQQZ128rm(b?)", 1829 "VCVTQQ2PDZ128rm(b?)", 1830 "VCVTQQ2PSZ128rm(b?)", 1831 "VCVTSS2SDZrm", 1832 "(V?)CVTSS2SDrm", 1833 "VCVTTPD2QQZ128rm(b?)", 1834 "VCVTTPD2UQQZ128rm(b?)", 1835 "VCVTTPS2DQZ128rm(b?)", 1836 "(V?)CVTTPS2DQrm", 1837 "VCVTTPS2QQZ128rm(b?)", 1838 "VCVTTPS2UDQZ128rm(b?)", 1839 "VCVTTPS2UQQZ128rm(b?)", 1840 "VCVTUDQ2PDZ128rm(b?)", 1841 "VCVTUDQ2PSZ128rm(b?)", 1842 "VCVTUQQ2PDZ128rm(b?)", 1843 "VCVTUQQ2PSZ128rm(b?)")>; 1844 1845def SKXWriteResGroup151 : SchedWriteRes<[SKXPort5,SKXPort23]> { 1846 let Latency = 10; 1847 let NumMicroOps = 3; 1848 let ResourceCycles = [2,1]; 1849} 1850def: InstRW<[SKXWriteResGroup151], (instregex "VEXPANDPDZ128rm(b?)", 1851 "VEXPANDPSZ128rm(b?)", 1852 "VPEXPANDDZ128rm(b?)", 1853 "VPEXPANDQZ128rm(b?)")>; 1854 1855def SKXWriteResGroup153 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> { 1856 let Latency = 10; 1857 let NumMicroOps = 3; 1858 let ResourceCycles = [1,1,1]; 1859} 1860def: InstRW<[SKXWriteResGroup153], (instregex "(V?)CVTSD2SSrm")>; 1861 1862def SKXWriteResGroup154 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23]> { 1863 let Latency = 10; 1864 let NumMicroOps = 4; 1865 let ResourceCycles = [2,1,1]; 1866} 1867def: InstRW<[SKXWriteResGroup154], (instrs VPHADDSWYrm, 1868 VPHSUBSWYrm)>; 1869 1870def SKXWriteResGroup157 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> { 1871 let Latency = 10; 1872 let NumMicroOps = 8; 1873 let ResourceCycles = [1,1,1,1,1,3]; 1874} 1875def: InstRW<[SKXWriteResGroup157], (instregex "XCHG(8|16|32|64)rm")>; 1876 1877def SKXWriteResGroup159 : SchedWriteRes<[SKXPort0,SKXFPDivider]> { 1878 let Latency = 11; 1879 let NumMicroOps = 1; 1880 let ResourceCycles = [1,3]; 1881} 1882def : SchedAlias<WriteFDivX, SKXWriteResGroup159>; // TODO - convert to ZnWriteResFpuPair 1883 1884def SKXWriteResGroup160 : SchedWriteRes<[SKXPort0,SKXPort23]> { 1885 let Latency = 11; 1886 let NumMicroOps = 2; 1887 let ResourceCycles = [1,1]; 1888} 1889def: InstRW<[SKXWriteResGroup160], (instregex "MUL_F(32|64)m")>; 1890 1891def SKXWriteResGroup161 : SchedWriteRes<[SKXPort23,SKXPort015]> { 1892 let Latency = 11; 1893 let NumMicroOps = 2; 1894 let ResourceCycles = [1,1]; 1895} 1896def: InstRW<[SKXWriteResGroup161], (instrs VCVTDQ2PSYrm, 1897 VCVTPS2PDYrm)>; 1898def: InstRW<[SKXWriteResGroup161], (instregex "VCVTDQ2(PD|PS)(Z|Z256)rm(b?)", 1899 "VCVTPH2PS(Z|Z256)rm(b?)", 1900 "VCVTPS2PD(Z|Z256)rm(b?)", 1901 "VCVTQQ2PD(Z|Z256)rm(b?)", 1902 "VCVTQQ2PSZ256rm(b?)", 1903 "VCVT(T?)PD2QQ(Z|Z256)rm(b?)", 1904 "VCVT(T?)PD2UQQ(Z|Z256)rm(b?)", 1905 "VCVT(T?)PS2DQYrm", 1906 "VCVT(T?)PS2DQ(Z|Z256)rm(b?)", 1907 "VCVT(T?)PS2QQZ256rm(b?)", 1908 "VCVT(T?)PS2UDQ(Z|Z256)rm(b?)", 1909 "VCVT(T?)PS2UQQZ256rm(b?)", 1910 "VCVTUDQ2(PD|PS)(Z|Z256)rm(b?)", 1911 "VCVTUQQ2PD(Z|Z256)rm(b?)", 1912 "VCVTUQQ2PSZ256rm(b?)")>; 1913 1914def SKXWriteResGroup162 : SchedWriteRes<[SKXPort5,SKXPort23]> { 1915 let Latency = 11; 1916 let NumMicroOps = 3; 1917 let ResourceCycles = [2,1]; 1918} 1919def: InstRW<[SKXWriteResGroup162], (instregex "FICOM(P?)(16|32)m", 1920 "VEXPANDPD(Z|Z256)rm(b?)", 1921 "VEXPANDPS(Z|Z256)rm(b?)", 1922 "VPEXPANDD(Z|Z256)rm(b?)", 1923 "VPEXPANDQ(Z|Z256)rm(b?)")>; 1924 1925def SKXWriteResGroup163 : SchedWriteRes<[SKXPort23,SKXPort015]> { 1926 let Latency = 11; 1927 let NumMicroOps = 3; 1928 let ResourceCycles = [1,2]; 1929} 1930def: InstRW<[SKXWriteResGroup163], (instregex "VCVTSD2SSZrm")>; 1931 1932def SKXWriteResGroup164 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> { 1933 let Latency = 11; 1934 let NumMicroOps = 3; 1935 let ResourceCycles = [1,1,1]; 1936} 1937def: InstRW<[SKXWriteResGroup164], (instregex "(V?)CVTDQ2PDrm")>; 1938 1939def SKXWriteResGroup166 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> { 1940 let Latency = 11; 1941 let NumMicroOps = 3; 1942 let ResourceCycles = [1,1,1]; 1943} 1944def: InstRW<[SKXWriteResGroup166], (instrs CVTPD2PSrm, 1945 CVTPD2DQrm, 1946 CVTTPD2DQrm, 1947 MMX_CVTPD2PIrm, 1948 MMX_CVTTPD2PIrm)>; 1949 1950def SKXWriteResGroup167 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> { 1951 let Latency = 11; 1952 let NumMicroOps = 4; 1953 let ResourceCycles = [2,1,1]; 1954} 1955def: InstRW<[SKXWriteResGroup167], (instregex "VPCONFLICTQZ128rm(b?)")>; 1956 1957def SKXWriteResGroup169 : SchedWriteRes<[SKXPort1,SKXPort06,SKXPort0156]> { 1958 let Latency = 11; 1959 let NumMicroOps = 7; 1960 let ResourceCycles = [2,3,2]; 1961} 1962def: InstRW<[SKXWriteResGroup169], (instregex "RCL(16|32|64)rCL", 1963 "RCR(16|32|64)rCL")>; 1964 1965def SKXWriteResGroup170 : SchedWriteRes<[SKXPort1,SKXPort06,SKXPort15,SKXPort0156]> { 1966 let Latency = 11; 1967 let NumMicroOps = 9; 1968 let ResourceCycles = [1,5,1,2]; 1969} 1970def: InstRW<[SKXWriteResGroup170], (instrs RCL8rCL)>; 1971 1972def SKXWriteResGroup171 : SchedWriteRes<[SKXPort06,SKXPort0156]> { 1973 let Latency = 11; 1974 let NumMicroOps = 11; 1975 let ResourceCycles = [2,9]; 1976} 1977def: InstRW<[SKXWriteResGroup171], (instrs LOOPE, LOOPNE)>; 1978 1979def SKXWriteResGroup174 : SchedWriteRes<[SKXPort01]> { 1980 let Latency = 15; 1981 let NumMicroOps = 3; 1982 let ResourceCycles = [3]; 1983} 1984def: InstRW<[SKXWriteResGroup174], (instregex "VPMULLQ(Z128|Z256)rr")>; 1985 1986def SKXWriteResGroup174z : SchedWriteRes<[SKXPort05]> { 1987 let Latency = 15; 1988 let NumMicroOps = 3; 1989 let ResourceCycles = [3]; 1990} 1991def: InstRW<[SKXWriteResGroup174z], (instregex "VPMULLQZrr")>; 1992 1993def SKXWriteResGroup175 : SchedWriteRes<[SKXPort5,SKXPort23]> { 1994 let Latency = 12; 1995 let NumMicroOps = 3; 1996 let ResourceCycles = [2,1]; 1997} 1998def: InstRW<[SKXWriteResGroup175], (instregex "VPERMWZ128rm(b?)")>; 1999 2000def SKXWriteResGroup176 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015]> { 2001 let Latency = 12; 2002 let NumMicroOps = 3; 2003 let ResourceCycles = [1,1,1]; 2004} 2005def: InstRW<[SKXWriteResGroup176], (instregex "VCVT(T?)SD2USIZrm(b?)", 2006 "VCVT(T?)SS2USI64Zrm(b?)")>; 2007 2008def SKXWriteResGroup177 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> { 2009 let Latency = 12; 2010 let NumMicroOps = 3; 2011 let ResourceCycles = [1,1,1]; 2012} 2013def: InstRW<[SKXWriteResGroup177], (instregex "VCVT(T?)PS2QQZrm(b?)", 2014 "VCVT(T?)PS2UQQZrm(b?)")>; 2015 2016def SKXWriteResGroup179 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23,SKXPort015]> { 2017 let Latency = 12; 2018 let NumMicroOps = 4; 2019 let ResourceCycles = [1,1,1,1]; 2020} 2021def: InstRW<[SKXWriteResGroup179], (instregex "CVTTSS2SI64rm")>; 2022 2023def SKXWriteResGroup180 : SchedWriteRes<[SKXPort5,SKXPort23]> { 2024 let Latency = 13; 2025 let NumMicroOps = 3; 2026 let ResourceCycles = [2,1]; 2027} 2028def: InstRW<[SKXWriteResGroup180], (instregex "(ADD|SUB|SUBR)_FI(16|32)m", 2029 "VPERMWZ256rm(b?)", 2030 "VPERMWZrm(b?)")>; 2031 2032def SKXWriteResGroup181 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> { 2033 let Latency = 13; 2034 let NumMicroOps = 3; 2035 let ResourceCycles = [1,1,1]; 2036} 2037def: InstRW<[SKXWriteResGroup181], (instrs VCVTDQ2PDYrm)>; 2038 2039def SKXWriteResGroup183 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> { 2040 let Latency = 13; 2041 let NumMicroOps = 4; 2042 let ResourceCycles = [2,1,1]; 2043} 2044def: InstRW<[SKXWriteResGroup183], (instregex "VPERMI2W128rm(b?)", 2045 "VPERMT2W128rm(b?)")>; 2046 2047def SKXWriteResGroup184 : SchedWriteRes<[SKXPort0,SKXFPDivider]> { 2048 let Latency = 14; 2049 let NumMicroOps = 1; 2050 let ResourceCycles = [1,3]; 2051} 2052def : SchedAlias<WriteFDiv64, SKXWriteResGroup184>; // TODO - convert to ZnWriteResFpuPair 2053def : SchedAlias<WriteFDiv64X, SKXWriteResGroup184>; // TODO - convert to ZnWriteResFpuPair 2054 2055def SKXWriteResGroup184_1 : SchedWriteRes<[SKXPort0,SKXFPDivider]> { 2056 let Latency = 14; 2057 let NumMicroOps = 1; 2058 let ResourceCycles = [1,5]; 2059} 2060def : SchedAlias<WriteFDiv64Y, SKXWriteResGroup184_1>; // TODO - convert to ZnWriteResFpuPair 2061 2062def SKXWriteResGroup187 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> { 2063 let Latency = 14; 2064 let NumMicroOps = 3; 2065 let ResourceCycles = [1,1,1]; 2066} 2067def: InstRW<[SKXWriteResGroup187], (instregex "MUL_FI(16|32)m")>; 2068 2069def SKXWriteResGroup188 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> { 2070 let Latency = 14; 2071 let NumMicroOps = 3; 2072 let ResourceCycles = [1,1,1]; 2073} 2074def: InstRW<[SKXWriteResGroup188], (instregex "VCVTPD2DQZrm(b?)", 2075 "VCVTPD2PSZrm(b?)", 2076 "VCVTPD2UDQZrm(b?)", 2077 "VCVTQQ2PSZrm(b?)", 2078 "VCVTTPD2DQZrm(b?)", 2079 "VCVTTPD2UDQZrm(b?)", 2080 "VCVTUQQ2PSZrm(b?)")>; 2081 2082def SKXWriteResGroup189 : SchedWriteRes<[SKXPort5,SKXPort23,SKXPort015]> { 2083 let Latency = 14; 2084 let NumMicroOps = 4; 2085 let ResourceCycles = [2,1,1]; 2086} 2087def: InstRW<[SKXWriteResGroup189], (instregex "VPERMI2W256rm(b?)", 2088 "VPERMI2Wrm(b?)", 2089 "VPERMT2W256rm(b?)", 2090 "VPERMT2Wrm(b?)")>; 2091 2092def SKXWriteResGroup190 : SchedWriteRes<[SKXPort1,SKXPort06,SKXPort15,SKXPort0156]> { 2093 let Latency = 14; 2094 let NumMicroOps = 10; 2095 let ResourceCycles = [2,4,1,3]; 2096} 2097def: InstRW<[SKXWriteResGroup190], (instrs RCR8rCL)>; 2098 2099def SKXWriteResGroup191 : SchedWriteRes<[SKXPort0]> { 2100 let Latency = 15; 2101 let NumMicroOps = 1; 2102 let ResourceCycles = [1]; 2103} 2104def: InstRW<[SKXWriteResGroup191], (instregex "DIVR_(FPrST0|FST0r|FrST0)")>; 2105 2106def SKXWriteResGroup194 : SchedWriteRes<[SKXPort1,SKXPort5,SKXPort01,SKXPort23,SKXPort015]> { 2107 let Latency = 15; 2108 let NumMicroOps = 8; 2109 let ResourceCycles = [1,2,2,1,2]; 2110} 2111def: InstRW<[SKXWriteResGroup194], (instregex "VPCONFLICTDZ128rm(b?)")>; 2112 2113def SKXWriteResGroup195 : SchedWriteRes<[SKXPort1,SKXPort23,SKXPort237,SKXPort06,SKXPort15,SKXPort0156]> { 2114 let Latency = 15; 2115 let NumMicroOps = 10; 2116 let ResourceCycles = [1,1,1,5,1,1]; 2117} 2118def: InstRW<[SKXWriteResGroup195], (instregex "RCL(8|16|32|64)mCL")>; 2119 2120def SKXWriteResGroup199 : SchedWriteRes<[SKXPort4,SKXPort23,SKXPort237,SKXPort06,SKXPort15,SKXPort0156]> { 2121 let Latency = 16; 2122 let NumMicroOps = 14; 2123 let ResourceCycles = [1,1,1,4,2,5]; 2124} 2125def: InstRW<[SKXWriteResGroup199], (instrs CMPXCHG8B)>; 2126 2127def SKXWriteResGroup200 : SchedWriteRes<[SKXPort1, SKXPort05, SKXPort6]> { 2128 let Latency = 12; 2129 let NumMicroOps = 34; 2130 let ResourceCycles = [1, 4, 5]; 2131} 2132def: InstRW<[SKXWriteResGroup200], (instrs VZEROALL)>; 2133 2134def SKXWriteResGroup201 : SchedWriteRes<[SKXPort0,SKXPort23,SKXFPDivider]> { 2135 let Latency = 17; 2136 let NumMicroOps = 2; 2137 let ResourceCycles = [1,1,5]; 2138} 2139def : SchedAlias<WriteFDivXLd, SKXWriteResGroup201>; // TODO - convert to ZnWriteResFpuPair 2140 2141def SKXWriteResGroup202 : SchedWriteRes<[SKXPort0,SKXPort1,SKXPort5,SKXPort6,SKXPort05,SKXPort0156]> { 2142 let Latency = 17; 2143 let NumMicroOps = 15; 2144 let ResourceCycles = [2,1,2,4,2,4]; 2145} 2146def: InstRW<[SKXWriteResGroup202], (instrs XCH_F)>; 2147 2148def SKXWriteResGroup205 : SchedWriteRes<[SKXPort23,SKXPort01]> { 2149 let Latency = 21; 2150 let NumMicroOps = 4; 2151 let ResourceCycles = [1,3]; 2152} 2153def: InstRW<[SKXWriteResGroup205], (instregex "VPMULLQZ128rm(b?)")>; 2154 2155def SKXWriteResGroup207 : SchedWriteRes<[SKXPort5,SKXPort6,SKXPort06,SKXPort0156]> { 2156 let Latency = 18; 2157 let NumMicroOps = 8; 2158 let ResourceCycles = [1,1,1,5]; 2159} 2160def: InstRW<[SKXWriteResGroup207], (instrs CPUID, RDTSC)>; 2161 2162def SKXWriteResGroup208 : SchedWriteRes<[SKXPort1,SKXPort23,SKXPort237,SKXPort06,SKXPort15,SKXPort0156]> { 2163 let Latency = 18; 2164 let NumMicroOps = 11; 2165 let ResourceCycles = [2,1,1,4,1,2]; 2166} 2167def: InstRW<[SKXWriteResGroup208], (instregex "RCR(8|16|32|64)mCL")>; 2168 2169def SKXWriteResGroup209 : SchedWriteRes<[SKXPort0,SKXPort23,SKXFPDivider]> { 2170 let Latency = 19; 2171 let NumMicroOps = 2; 2172 let ResourceCycles = [1,1,4]; 2173} 2174def : SchedAlias<WriteFDiv64Ld, SKXWriteResGroup209>; // TODO - convert to ZnWriteResFpuPair 2175 2176def SKXWriteResGroup211 : SchedWriteRes<[SKXPort23,SKXPort01]> { 2177 let Latency = 22; 2178 let NumMicroOps = 4; 2179 let ResourceCycles = [1,3]; 2180} 2181def: InstRW<[SKXWriteResGroup211], (instregex "VPMULLQZ256rm(b?)")>; 2182 2183def SKXWriteResGroup211_1 : SchedWriteRes<[SKXPort23,SKXPort05]> { 2184 let Latency = 22; 2185 let NumMicroOps = 4; 2186 let ResourceCycles = [1,3]; 2187} 2188def: InstRW<[SKXWriteResGroup211_1], (instregex "VPMULLQZrm(b?)")>; 2189 2190def SKXWriteResGroup215 : SchedWriteRes<[SKXPort0]> { 2191 let Latency = 20; 2192 let NumMicroOps = 1; 2193 let ResourceCycles = [1]; 2194} 2195def: InstRW<[SKXWriteResGroup215], (instregex "DIV_(FPrST0|FST0r|FrST0)")>; 2196 2197def SKXWriteResGroup216 : SchedWriteRes<[SKXPort0,SKXPort23,SKXFPDivider]> { 2198 let Latency = 20; 2199 let NumMicroOps = 2; 2200 let ResourceCycles = [1,1,4]; 2201} 2202def : SchedAlias<WriteFDiv64XLd, SKXWriteResGroup216>; // TODO - convert to ZnWriteResFpuPair 2203 2204def SKXWriteGatherEVEX2 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> { 2205 let Latency = 17; 2206 let NumMicroOps = 5; // 2 uops perform multiple loads 2207 let ResourceCycles = [1,2,1,1]; 2208} 2209def: InstRW<[SKXWriteGatherEVEX2], (instrs VGATHERQPSZ128rm, VPGATHERQDZ128rm, 2210 VGATHERDPDZ128rm, VPGATHERDQZ128rm, 2211 VGATHERQPDZ128rm, VPGATHERQQZ128rm)>; 2212 2213def SKXWriteGatherEVEX4 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> { 2214 let Latency = 19; 2215 let NumMicroOps = 5; // 2 uops perform multiple loads 2216 let ResourceCycles = [1,4,1,1]; 2217} 2218def: InstRW<[SKXWriteGatherEVEX4], (instrs VGATHERQPSZ256rm, VPGATHERQDZ256rm, 2219 VGATHERQPDZ256rm, VPGATHERQQZ256rm, 2220 VGATHERDPSZ128rm, VPGATHERDDZ128rm, 2221 VGATHERDPDZ256rm, VPGATHERDQZ256rm)>; 2222 2223def SKXWriteGatherEVEX8 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> { 2224 let Latency = 21; 2225 let NumMicroOps = 5; // 2 uops perform multiple loads 2226 let ResourceCycles = [1,8,1,1]; 2227} 2228def: InstRW<[SKXWriteGatherEVEX8], (instrs VGATHERDPSZ256rm, VPGATHERDDZ256rm, 2229 VGATHERDPDZrm, VPGATHERDQZrm, 2230 VGATHERQPDZrm, VPGATHERQQZrm, 2231 VGATHERQPSZrm, VPGATHERQDZrm)>; 2232 2233def SKXWriteGatherEVEX16 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort015,SKXPort0156]> { 2234 let Latency = 25; 2235 let NumMicroOps = 5; // 2 uops perform multiple loads 2236 let ResourceCycles = [1,16,1,1]; 2237} 2238def: InstRW<[SKXWriteGatherEVEX16], (instrs VGATHERDPSZrm, VPGATHERDDZrm)>; 2239 2240def SKXWriteResGroup219 : SchedWriteRes<[SKXPort4,SKXPort5,SKXPort6,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> { 2241 let Latency = 20; 2242 let NumMicroOps = 8; 2243 let ResourceCycles = [1,1,1,1,1,1,2]; 2244} 2245def: InstRW<[SKXWriteResGroup219], (instrs INSB, INSL, INSW)>; 2246 2247def SKXWriteResGroup220 : SchedWriteRes<[SKXPort5,SKXPort6,SKXPort0156]> { 2248 let Latency = 20; 2249 let NumMicroOps = 10; 2250 let ResourceCycles = [1,2,7]; 2251} 2252def: InstRW<[SKXWriteResGroup220], (instrs MWAITrr)>; 2253 2254def SKXWriteResGroup222 : SchedWriteRes<[SKXPort0,SKXPort23,SKXFPDivider]> { 2255 let Latency = 21; 2256 let NumMicroOps = 2; 2257 let ResourceCycles = [1,1,8]; 2258} 2259def : SchedAlias<WriteFDiv64YLd, SKXWriteResGroup222>; // TODO - convert to ZnWriteResFpuPair 2260 2261def SKXWriteResGroup223 : SchedWriteRes<[SKXPort0,SKXPort23]> { 2262 let Latency = 22; 2263 let NumMicroOps = 2; 2264 let ResourceCycles = [1,1]; 2265} 2266def: InstRW<[SKXWriteResGroup223], (instregex "DIV_F(32|64)m")>; 2267 2268def SKXWriteResGroupVEX2 : SchedWriteRes<[SKXPort0, SKXPort23, SKXPort5, SKXPort015]> { 2269 let Latency = 18; 2270 let NumMicroOps = 5; // 2 uops perform multiple loads 2271 let ResourceCycles = [1,2,1,1]; 2272} 2273def: InstRW<[SKXWriteResGroupVEX2], (instrs VGATHERDPDrm, VPGATHERDQrm, 2274 VGATHERQPDrm, VPGATHERQQrm, 2275 VGATHERQPSrm, VPGATHERQDrm)>; 2276 2277def SKXWriteResGroupVEX4 : SchedWriteRes<[SKXPort0, SKXPort23, SKXPort5, SKXPort015]> { 2278 let Latency = 20; 2279 let NumMicroOps = 5; // 2 uops peform multiple loads 2280 let ResourceCycles = [1,4,1,1]; 2281} 2282def: InstRW<[SKXWriteResGroupVEX4], (instrs VGATHERDPDYrm, VPGATHERDQYrm, 2283 VGATHERDPSrm, VPGATHERDDrm, 2284 VGATHERQPDYrm, VPGATHERQQYrm, 2285 VGATHERQPSYrm, VPGATHERQDYrm)>; 2286 2287def SKXWriteResGroupVEX8 : SchedWriteRes<[SKXPort0, SKXPort23, SKXPort5, SKXPort015]> { 2288 let Latency = 22; 2289 let NumMicroOps = 5; // 2 uops perform multiple loads 2290 let ResourceCycles = [1,8,1,1]; 2291} 2292def: InstRW<[SKXWriteResGroupVEX8], (instrs VGATHERDPSYrm, VPGATHERDDYrm)>; 2293 2294def SKXWriteResGroup225 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort015]> { 2295 let Latency = 22; 2296 let NumMicroOps = 14; 2297 let ResourceCycles = [5,5,4]; 2298} 2299def: InstRW<[SKXWriteResGroup225], (instregex "VPCONFLICTDZ128rr", 2300 "VPCONFLICTQZ256rr")>; 2301 2302def SKXWriteResGroup228 : SchedWriteRes<[SKXPort0,SKXPort4,SKXPort5,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> { 2303 let Latency = 23; 2304 let NumMicroOps = 19; 2305 let ResourceCycles = [2,1,4,1,1,4,6]; 2306} 2307def: InstRW<[SKXWriteResGroup228], (instrs CMPXCHG16B)>; 2308 2309def SKXWriteResGroup233 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> { 2310 let Latency = 25; 2311 let NumMicroOps = 3; 2312 let ResourceCycles = [1,1,1]; 2313} 2314def: InstRW<[SKXWriteResGroup233], (instregex "DIV_FI(16|32)m")>; 2315 2316def SKXWriteResGroup239 : SchedWriteRes<[SKXPort0,SKXPort23]> { 2317 let Latency = 27; 2318 let NumMicroOps = 2; 2319 let ResourceCycles = [1,1]; 2320} 2321def: InstRW<[SKXWriteResGroup239], (instregex "DIVR_F(32|64)m")>; 2322 2323def SKXWriteResGroup242 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23,SKXPort015]> { 2324 let Latency = 29; 2325 let NumMicroOps = 15; 2326 let ResourceCycles = [5,5,1,4]; 2327} 2328def: InstRW<[SKXWriteResGroup242], (instregex "VPCONFLICTQZ256rm(b?)")>; 2329 2330def SKXWriteResGroup243 : SchedWriteRes<[SKXPort0,SKXPort5,SKXPort23]> { 2331 let Latency = 30; 2332 let NumMicroOps = 3; 2333 let ResourceCycles = [1,1,1]; 2334} 2335def: InstRW<[SKXWriteResGroup243], (instregex "DIVR_FI(16|32)m")>; 2336 2337def SKXWriteResGroup247 : SchedWriteRes<[SKXPort5,SKXPort6,SKXPort23,SKXPort06,SKXPort0156]> { 2338 let Latency = 35; 2339 let NumMicroOps = 23; 2340 let ResourceCycles = [1,5,3,4,10]; 2341} 2342def: InstRW<[SKXWriteResGroup247], (instregex "IN(8|16|32)ri", 2343 "IN(8|16|32)rr")>; 2344 2345def SKXWriteResGroup248 : SchedWriteRes<[SKXPort5,SKXPort6,SKXPort23,SKXPort237,SKXPort06,SKXPort0156]> { 2346 let Latency = 35; 2347 let NumMicroOps = 23; 2348 let ResourceCycles = [1,5,2,1,4,10]; 2349} 2350def: InstRW<[SKXWriteResGroup248], (instregex "OUT(8|16|32)ir", 2351 "OUT(8|16|32)rr")>; 2352 2353def SKXWriteResGroup249 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort015]> { 2354 let Latency = 37; 2355 let NumMicroOps = 21; 2356 let ResourceCycles = [9,7,5]; 2357} 2358def: InstRW<[SKXWriteResGroup249], (instregex "VPCONFLICTDZ256rr", 2359 "VPCONFLICTQZrr")>; 2360 2361def SKXWriteResGroup250 : SchedWriteRes<[SKXPort1,SKXPort6,SKXPort23,SKXPort0156]> { 2362 let Latency = 37; 2363 let NumMicroOps = 31; 2364 let ResourceCycles = [1,8,1,21]; 2365} 2366def: InstRW<[SKXWriteResGroup250], (instregex "XRSTOR(64)?")>; 2367 2368def SKXWriteResGroup252 : SchedWriteRes<[SKXPort1,SKXPort4,SKXPort5,SKXPort6,SKXPort23,SKXPort237,SKXPort15,SKXPort0156]> { 2369 let Latency = 40; 2370 let NumMicroOps = 18; 2371 let ResourceCycles = [1,1,2,3,1,1,1,8]; 2372} 2373def: InstRW<[SKXWriteResGroup252], (instrs VMCLEARm)>; 2374 2375def SKXWriteResGroup253 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort23,SKXPort237,SKXPort0156]> { 2376 let Latency = 41; 2377 let NumMicroOps = 39; 2378 let ResourceCycles = [1,10,1,1,26]; 2379} 2380def: InstRW<[SKXWriteResGroup253], (instrs XSAVE64)>; 2381 2382def SKXWriteResGroup254 : SchedWriteRes<[SKXPort5,SKXPort0156]> { 2383 let Latency = 42; 2384 let NumMicroOps = 22; 2385 let ResourceCycles = [2,20]; 2386} 2387def: InstRW<[SKXWriteResGroup254], (instrs RDTSCP)>; 2388 2389def SKXWriteResGroup255 : SchedWriteRes<[SKXPort4,SKXPort6,SKXPort23,SKXPort237,SKXPort0156]> { 2390 let Latency = 42; 2391 let NumMicroOps = 40; 2392 let ResourceCycles = [1,11,1,1,26]; 2393} 2394def: InstRW<[SKXWriteResGroup255], (instrs XSAVE)>; 2395def: InstRW<[SKXWriteResGroup255], (instregex "XSAVEC", "XSAVES", "XSAVEOPT")>; 2396 2397def SKXWriteResGroup256 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23,SKXPort015]> { 2398 let Latency = 44; 2399 let NumMicroOps = 22; 2400 let ResourceCycles = [9,7,1,5]; 2401} 2402def: InstRW<[SKXWriteResGroup256], (instregex "VPCONFLICTDZ256rm(b?)", 2403 "VPCONFLICTQZrm(b?)")>; 2404 2405def SKXWriteResGroup258 : SchedWriteRes<[SKXPort0,SKXPort23,SKXPort05,SKXPort06,SKXPort0156]> { 2406 let Latency = 62; 2407 let NumMicroOps = 64; 2408 let ResourceCycles = [2,8,5,10,39]; 2409} 2410def: InstRW<[SKXWriteResGroup258], (instrs FLDENVm)>; 2411 2412def SKXWriteResGroup259 : SchedWriteRes<[SKXPort0,SKXPort6,SKXPort23,SKXPort05,SKXPort06,SKXPort15,SKXPort0156]> { 2413 let Latency = 63; 2414 let NumMicroOps = 88; 2415 let ResourceCycles = [4,4,31,1,2,1,45]; 2416} 2417def: InstRW<[SKXWriteResGroup259], (instrs FXRSTOR64)>; 2418 2419def SKXWriteResGroup260 : SchedWriteRes<[SKXPort0,SKXPort6,SKXPort23,SKXPort05,SKXPort06,SKXPort15,SKXPort0156]> { 2420 let Latency = 63; 2421 let NumMicroOps = 90; 2422 let ResourceCycles = [4,2,33,1,2,1,47]; 2423} 2424def: InstRW<[SKXWriteResGroup260], (instrs FXRSTOR)>; 2425 2426def SKXWriteResGroup261 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort015]> { 2427 let Latency = 67; 2428 let NumMicroOps = 35; 2429 let ResourceCycles = [17,11,7]; 2430} 2431def: InstRW<[SKXWriteResGroup261], (instregex "VPCONFLICTDZrr")>; 2432 2433def SKXWriteResGroup262 : SchedWriteRes<[SKXPort5,SKXPort01,SKXPort23,SKXPort015]> { 2434 let Latency = 74; 2435 let NumMicroOps = 36; 2436 let ResourceCycles = [17,11,1,7]; 2437} 2438def: InstRW<[SKXWriteResGroup262], (instregex "VPCONFLICTDZrm(b?)")>; 2439 2440def SKXWriteResGroup263 : SchedWriteRes<[SKXPort5,SKXPort05,SKXPort0156]> { 2441 let Latency = 75; 2442 let NumMicroOps = 15; 2443 let ResourceCycles = [6,3,6]; 2444} 2445def: InstRW<[SKXWriteResGroup263], (instrs FNINIT)>; 2446 2447def SKXWriteResGroup266 : SchedWriteRes<[SKXPort0,SKXPort1,SKXPort4,SKXPort5,SKXPort6,SKXPort237,SKXPort06,SKXPort0156]> { 2448 let Latency = 106; 2449 let NumMicroOps = 100; 2450 let ResourceCycles = [9,1,11,16,1,11,21,30]; 2451} 2452def: InstRW<[SKXWriteResGroup266], (instrs FSTENVm)>; 2453 2454def SKXWriteResGroup267 : SchedWriteRes<[SKXPort6,SKXPort0156]> { 2455 let Latency = 140; 2456 let NumMicroOps = 4; 2457 let ResourceCycles = [1,3]; 2458} 2459def: InstRW<[SKXWriteResGroup267], (instrs PAUSE)>; 2460 2461def: InstRW<[WriteZero], (instrs CLC)>; 2462 2463 2464// Instruction variants handled by the renamer. These might not need execution 2465// ports in certain conditions. 2466// See Agner's Fog "The microarchitecture of Intel, AMD and VIA CPUs", 2467// section "Skylake Pipeline" > "Register allocation and renaming". 2468// These can be investigated with llvm-exegesis, e.g. 2469// echo 'pxor %mm0, %mm0' | /tmp/llvm-exegesis -mode=uops -snippets-file=- 2470// echo 'vxorpd %xmm0, %xmm0, %xmm1' | /tmp/llvm-exegesis -mode=uops -snippets-file=- 2471 2472def SKXWriteZeroLatency : SchedWriteRes<[]> { 2473 let Latency = 0; 2474} 2475 2476def SKXWriteZeroIdiom : SchedWriteVariant<[ 2477 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>, 2478 SchedVar<NoSchedPred, [WriteALU]> 2479]>; 2480def : InstRW<[SKXWriteZeroIdiom], (instrs SUB32rr, SUB64rr, 2481 XOR32rr, XOR64rr)>; 2482 2483def SKXWriteFZeroIdiom : SchedWriteVariant<[ 2484 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>, 2485 SchedVar<NoSchedPred, [WriteFLogic]> 2486]>; 2487def : InstRW<[SKXWriteFZeroIdiom], (instrs XORPSrr, VXORPSrr, 2488 XORPDrr, VXORPDrr, 2489 VXORPSZ128rr, 2490 VXORPDZ128rr)>; 2491 2492def SKXWriteFZeroIdiomY : SchedWriteVariant<[ 2493 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>, 2494 SchedVar<NoSchedPred, [WriteFLogicY]> 2495]>; 2496def : InstRW<[SKXWriteFZeroIdiomY], (instrs VXORPSYrr, VXORPDYrr, 2497 VXORPSZ256rr, VXORPDZ256rr)>; 2498 2499def SKXWriteFZeroIdiomZ : SchedWriteVariant<[ 2500 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>, 2501 SchedVar<NoSchedPred, [WriteFLogicZ]> 2502]>; 2503def : InstRW<[SKXWriteFZeroIdiomZ], (instrs VXORPSZrr, VXORPDZrr)>; 2504 2505def SKXWriteVZeroIdiomLogicX : SchedWriteVariant<[ 2506 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>, 2507 SchedVar<NoSchedPred, [WriteVecLogicX]> 2508]>; 2509def : InstRW<[SKXWriteVZeroIdiomLogicX], (instrs PXORrr, VPXORrr, 2510 VPXORDZ128rr, VPXORQZ128rr)>; 2511 2512def SKXWriteVZeroIdiomLogicY : SchedWriteVariant<[ 2513 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>, 2514 SchedVar<NoSchedPred, [WriteVecLogicY]> 2515]>; 2516def : InstRW<[SKXWriteVZeroIdiomLogicY], (instrs VPXORYrr, 2517 VPXORDZ256rr, VPXORQZ256rr)>; 2518 2519def SKXWriteVZeroIdiomLogicZ : SchedWriteVariant<[ 2520 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>, 2521 SchedVar<NoSchedPred, [WriteVecLogicZ]> 2522]>; 2523def : InstRW<[SKXWriteVZeroIdiomLogicZ], (instrs VPXORDZrr, VPXORQZrr)>; 2524 2525def SKXWriteVZeroIdiomALUX : SchedWriteVariant<[ 2526 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>, 2527 SchedVar<NoSchedPred, [WriteVecALUX]> 2528]>; 2529def : InstRW<[SKXWriteVZeroIdiomALUX], (instrs PCMPGTBrr, VPCMPGTBrr, 2530 PCMPGTDrr, VPCMPGTDrr, 2531 PCMPGTWrr, VPCMPGTWrr)>; 2532 2533def SKXWriteVZeroIdiomALUY : SchedWriteVariant<[ 2534 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>, 2535 SchedVar<NoSchedPred, [WriteVecALUY]> 2536]>; 2537def : InstRW<[SKXWriteVZeroIdiomALUY], (instrs VPCMPGTBYrr, 2538 VPCMPGTDYrr, 2539 VPCMPGTWYrr)>; 2540 2541def SKXWritePSUB : SchedWriteRes<[SKXPort015]> { 2542 let Latency = 1; 2543 let NumMicroOps = 1; 2544 let ResourceCycles = [1]; 2545} 2546 2547def SKXWriteVZeroIdiomPSUB : SchedWriteVariant<[ 2548 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>, 2549 SchedVar<NoSchedPred, [SKXWritePSUB]> 2550]>; 2551 2552def : InstRW<[SKXWriteVZeroIdiomPSUB], (instrs PSUBBrr, VPSUBBrr, VPSUBBZ128rr, 2553 PSUBDrr, VPSUBDrr, VPSUBDZ128rr, 2554 PSUBQrr, VPSUBQrr, VPSUBQZ128rr, 2555 PSUBWrr, VPSUBWrr, VPSUBWZ128rr, 2556 VPSUBBYrr, VPSUBBZ256rr, 2557 VPSUBDYrr, VPSUBDZ256rr, 2558 VPSUBQYrr, VPSUBQZ256rr, 2559 VPSUBWYrr, VPSUBWZ256rr, 2560 VPSUBBZrr, 2561 VPSUBDZrr, 2562 VPSUBQZrr, 2563 VPSUBWZrr)>; 2564def SKXWritePCMPGTQ : SchedWriteRes<[SKXPort5]> { 2565 let Latency = 3; 2566 let NumMicroOps = 1; 2567 let ResourceCycles = [1]; 2568} 2569 2570def SKXWriteVZeroIdiomPCMPGTQ : SchedWriteVariant<[ 2571 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKXWriteZeroLatency]>, 2572 SchedVar<NoSchedPred, [SKXWritePCMPGTQ]> 2573]>; 2574def : InstRW<[SKXWriteVZeroIdiomPCMPGTQ], (instrs PCMPGTQrr, VPCMPGTQrr, 2575 VPCMPGTQYrr)>; 2576 2577 2578// CMOVs that use both Z and C flag require an extra uop. 2579def SKXWriteCMOVA_CMOVBErr : SchedWriteRes<[SKXPort06]> { 2580 let Latency = 2; 2581 let ResourceCycles = [2]; 2582 let NumMicroOps = 2; 2583} 2584 2585def SKXWriteCMOVA_CMOVBErm : SchedWriteRes<[SKXPort23,SKXPort06]> { 2586 let Latency = 7; 2587 let ResourceCycles = [1,2]; 2588 let NumMicroOps = 3; 2589} 2590 2591def SKXCMOVA_CMOVBErr : SchedWriteVariant<[ 2592 SchedVar<MCSchedPredicate<IsCMOVArr_Or_CMOVBErr>, [SKXWriteCMOVA_CMOVBErr]>, 2593 SchedVar<NoSchedPred, [WriteCMOV]> 2594]>; 2595 2596def SKXCMOVA_CMOVBErm : SchedWriteVariant<[ 2597 SchedVar<MCSchedPredicate<IsCMOVArm_Or_CMOVBErm>, [SKXWriteCMOVA_CMOVBErm]>, 2598 SchedVar<NoSchedPred, [WriteCMOV.Folded]> 2599]>; 2600 2601def : InstRW<[SKXCMOVA_CMOVBErr], (instrs CMOV16rr, CMOV32rr, CMOV64rr)>; 2602def : InstRW<[SKXCMOVA_CMOVBErm], (instrs CMOV16rm, CMOV32rm, CMOV64rm)>; 2603 2604// SETCCs that use both Z and C flag require an extra uop. 2605def SKXWriteSETA_SETBEr : SchedWriteRes<[SKXPort06]> { 2606 let Latency = 2; 2607 let ResourceCycles = [2]; 2608 let NumMicroOps = 2; 2609} 2610 2611def SKXWriteSETA_SETBEm : SchedWriteRes<[SKXPort4,SKXPort237,SKXPort06]> { 2612 let Latency = 3; 2613 let ResourceCycles = [1,1,2]; 2614 let NumMicroOps = 4; 2615} 2616 2617def SKXSETA_SETBErr : SchedWriteVariant<[ 2618 SchedVar<MCSchedPredicate<IsSETAr_Or_SETBEr>, [SKXWriteSETA_SETBEr]>, 2619 SchedVar<NoSchedPred, [WriteSETCC]> 2620]>; 2621 2622def SKXSETA_SETBErm : SchedWriteVariant<[ 2623 SchedVar<MCSchedPredicate<IsSETAm_Or_SETBEm>, [SKXWriteSETA_SETBEm]>, 2624 SchedVar<NoSchedPred, [WriteSETCCStore]> 2625]>; 2626 2627def : InstRW<[SKXSETA_SETBErr], (instrs SETCCr)>; 2628def : InstRW<[SKXSETA_SETBErm], (instrs SETCCm)>; 2629 2630/////////////////////////////////////////////////////////////////////////////// 2631// Dependency breaking instructions. 2632/////////////////////////////////////////////////////////////////////////////// 2633 2634def : IsZeroIdiomFunction<[ 2635 // GPR Zero-idioms. 2636 DepBreakingClass<[ SUB32rr, SUB64rr, XOR32rr, XOR64rr ], ZeroIdiomPredicate>, 2637 2638 // SSE Zero-idioms. 2639 DepBreakingClass<[ 2640 // fp variants. 2641 XORPSrr, XORPDrr, 2642 2643 // int variants. 2644 PXORrr, 2645 PSUBBrr, PSUBWrr, PSUBDrr, PSUBQrr, 2646 PCMPGTBrr, PCMPGTDrr, PCMPGTQrr, PCMPGTWrr 2647 ], ZeroIdiomPredicate>, 2648 2649 // AVX Zero-idioms. 2650 DepBreakingClass<[ 2651 // xmm fp variants. 2652 VXORPSrr, VXORPDrr, 2653 2654 // xmm int variants. 2655 VPXORrr, 2656 VPSUBBrr, VPSUBWrr, VPSUBDrr, VPSUBQrr, 2657 VPCMPGTBrr, VPCMPGTWrr, VPCMPGTDrr, VPCMPGTQrr, 2658 2659 // ymm variants. 2660 VXORPSYrr, VXORPDYrr, VPXORYrr, 2661 VPSUBBYrr, VPSUBWYrr, VPSUBDYrr, VPSUBQYrr, 2662 VPCMPGTBYrr, VPCMPGTWYrr, VPCMPGTDYrr, VPCMPGTQYrr, 2663 2664 // zmm variants. 2665 VXORPSZrr, VXORPDZrr, VPXORDZrr, VPXORQZrr, 2666 VXORPSZ128rr, VXORPDZ128rr, VPXORDZ128rr, VPXORQZ128rr, 2667 VXORPSZ256rr, VXORPDZ256rr, VPXORDZ256rr, VPXORQZ256rr, 2668 VPSUBBZrr, VPSUBWZrr, VPSUBDZrr, VPSUBQZrr, 2669 VPSUBBZ128rr, VPSUBWZ128rr, VPSUBDZ128rr, VPSUBQZ128rr, 2670 VPSUBBZ256rr, VPSUBWZ256rr, VPSUBDZ256rr, VPSUBQZ256rr, 2671 ], ZeroIdiomPredicate>, 2672]>; 2673 2674} // SchedModel 2675