1//=- X86SchedSkylake.td - X86 Skylake Client Scheduling ------*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the machine model for Skylake Client to support 10// instruction scheduling and other instruction cost heuristics. 11// 12//===----------------------------------------------------------------------===// 13 14def SkylakeClientModel : SchedMachineModel { 15 // All x86 instructions are modeled as a single micro-op, and SKylake can 16 // decode 6 instructions per cycle. 17 let IssueWidth = 6; 18 let MicroOpBufferSize = 224; // Based on the reorder buffer. 19 let LoadLatency = 5; 20 let MispredictPenalty = 14; 21 22 // Based on the LSD (loop-stream detector) queue size and benchmarking data. 23 let LoopMicroOpBufferSize = 50; 24 25 // This flag is set to allow the scheduler to assign a default model to 26 // unrecognized opcodes. 27 let CompleteModel = 0; 28} 29 30let SchedModel = SkylakeClientModel in { 31 32// Skylake Client can issue micro-ops to 8 different ports in one cycle. 33 34// Ports 0, 1, 5, and 6 handle all computation. 35// Port 4 gets the data half of stores. Store data can be available later than 36// the store address, but since we don't model the latency of stores, we can 37// ignore that. 38// Ports 2 and 3 are identical. They handle loads and the address half of 39// stores. Port 7 can handle address calculations. 40def SKLPort0 : ProcResource<1>; 41def SKLPort1 : ProcResource<1>; 42def SKLPort2 : ProcResource<1>; 43def SKLPort3 : ProcResource<1>; 44def SKLPort4 : ProcResource<1>; 45def SKLPort5 : ProcResource<1>; 46def SKLPort6 : ProcResource<1>; 47def SKLPort7 : ProcResource<1>; 48 49// Many micro-ops are capable of issuing on multiple ports. 50def SKLPort01 : ProcResGroup<[SKLPort0, SKLPort1]>; 51def SKLPort23 : ProcResGroup<[SKLPort2, SKLPort3]>; 52def SKLPort237 : ProcResGroup<[SKLPort2, SKLPort3, SKLPort7]>; 53def SKLPort04 : ProcResGroup<[SKLPort0, SKLPort4]>; 54def SKLPort05 : ProcResGroup<[SKLPort0, SKLPort5]>; 55def SKLPort06 : ProcResGroup<[SKLPort0, SKLPort6]>; 56def SKLPort15 : ProcResGroup<[SKLPort1, SKLPort5]>; 57def SKLPort16 : ProcResGroup<[SKLPort1, SKLPort6]>; 58def SKLPort56 : ProcResGroup<[SKLPort5, SKLPort6]>; 59def SKLPort015 : ProcResGroup<[SKLPort0, SKLPort1, SKLPort5]>; 60def SKLPort056 : ProcResGroup<[SKLPort0, SKLPort5, SKLPort6]>; 61def SKLPort0156: ProcResGroup<[SKLPort0, SKLPort1, SKLPort5, SKLPort6]>; 62 63def SKLDivider : ProcResource<1>; // Integer division issued on port 0. 64// FP division and sqrt on port 0. 65def SKLFPDivider : ProcResource<1>; 66 67// 60 Entry Unified Scheduler 68def SKLPortAny : ProcResGroup<[SKLPort0, SKLPort1, SKLPort2, SKLPort3, SKLPort4, 69 SKLPort5, SKLPort6, SKLPort7]> { 70 let BufferSize=60; 71} 72 73// Integer loads are 5 cycles, so ReadAfterLd registers needn't be available until 5 74// cycles after the memory operand. 75def : ReadAdvance<ReadAfterLd, 5>; 76 77// Vector loads are 5/6/7 cycles, so ReadAfterVec*Ld registers needn't be available 78// until 5/6/7 cycles after the memory operand. 79def : ReadAdvance<ReadAfterVecLd, 5>; 80def : ReadAdvance<ReadAfterVecXLd, 6>; 81def : ReadAdvance<ReadAfterVecYLd, 7>; 82 83def : ReadAdvance<ReadInt2Fpu, 0>; 84 85// Many SchedWrites are defined in pairs with and without a folded load. 86// Instructions with folded loads are usually micro-fused, so they only appear 87// as two micro-ops when queued in the reservation station. 88// This multiclass defines the resource usage for variants with and without 89// folded loads. 90multiclass SKLWriteResPair<X86FoldableSchedWrite SchedRW, 91 list<ProcResourceKind> ExePorts, 92 int Lat, list<int> Res = [1], int UOps = 1, 93 int LoadLat = 5> { 94 // Register variant is using a single cycle on ExePort. 95 def : WriteRes<SchedRW, ExePorts> { 96 let Latency = Lat; 97 let ResourceCycles = Res; 98 let NumMicroOps = UOps; 99 } 100 101 // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to 102 // the latency (default = 5). 103 def : WriteRes<SchedRW.Folded, !listconcat([SKLPort23], ExePorts)> { 104 let Latency = !add(Lat, LoadLat); 105 let ResourceCycles = !listconcat([1], Res); 106 let NumMicroOps = !add(UOps, 1); 107 } 108} 109 110// A folded store needs a cycle on port 4 for the store data, and an extra port 111// 2/3/7 cycle to recompute the address. 112def : WriteRes<WriteRMW, [SKLPort237,SKLPort4]>; 113 114// Arithmetic. 115defm : SKLWriteResPair<WriteALU, [SKLPort0156], 1>; // Simple integer ALU op. 116defm : SKLWriteResPair<WriteADC, [SKLPort06], 1>; // Integer ALU + flags op. 117 118// Integer multiplication. 119defm : SKLWriteResPair<WriteIMul8, [SKLPort1], 3>; 120defm : SKLWriteResPair<WriteIMul16, [SKLPort1,SKLPort06,SKLPort0156], 4, [1,1,2], 4>; 121defm : X86WriteRes<WriteIMul16Imm, [SKLPort1,SKLPort0156], 4, [1,1], 2>; 122defm : X86WriteRes<WriteIMul16ImmLd, [SKLPort1,SKLPort0156,SKLPort23], 8, [1,1,1], 3>; 123defm : SKLWriteResPair<WriteIMul16Reg, [SKLPort1], 3>; 124defm : SKLWriteResPair<WriteIMul32, [SKLPort1,SKLPort06,SKLPort0156], 4, [1,1,1], 3>; 125defm : SKLWriteResPair<WriteIMul32Imm, [SKLPort1], 3>; 126defm : SKLWriteResPair<WriteIMul32Reg, [SKLPort1], 3>; 127defm : SKLWriteResPair<WriteIMul64, [SKLPort1,SKLPort5], 4, [1,1], 2>; 128defm : SKLWriteResPair<WriteIMul64Imm, [SKLPort1], 3>; 129defm : SKLWriteResPair<WriteIMul64Reg, [SKLPort1], 3>; 130def : WriteRes<WriteIMulH, []> { let Latency = 3; } 131 132defm : X86WriteRes<WriteBSWAP32, [SKLPort15], 1, [1], 1>; 133defm : X86WriteRes<WriteBSWAP64, [SKLPort06, SKLPort15], 2, [1,1], 2>; 134defm : X86WriteRes<WriteCMPXCHG,[SKLPort06, SKLPort0156], 5, [2,3], 5>; 135defm : X86WriteRes<WriteCMPXCHGRMW,[SKLPort23,SKLPort06,SKLPort0156,SKLPort237,SKLPort4], 8, [1,2,1,1,1], 6>; 136defm : X86WriteRes<WriteXCHG, [SKLPort0156], 2, [3], 3>; 137 138// TODO: Why isn't the SKLDivider used? 139defm : SKLWriteResPair<WriteDiv8, [SKLPort0,SKLDivider], 25, [1,10], 1, 4>; 140defm : X86WriteRes<WriteDiv16, [SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort05,SKLPort0156], 76, [7,2,8,3,1,11], 32>; 141defm : X86WriteRes<WriteDiv32, [SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort05,SKLPort0156], 76, [7,2,8,3,1,11], 32>; 142defm : X86WriteRes<WriteDiv64, [SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort05,SKLPort0156], 76, [7,2,8,3,1,11], 32>; 143defm : X86WriteRes<WriteDiv16Ld, [SKLPort0,SKLPort23,SKLDivider], 29, [1,1,10], 2>; 144defm : X86WriteRes<WriteDiv32Ld, [SKLPort0,SKLPort23,SKLDivider], 29, [1,1,10], 2>; 145defm : X86WriteRes<WriteDiv64Ld, [SKLPort0,SKLPort23,SKLDivider], 29, [1,1,10], 2>; 146 147defm : X86WriteRes<WriteIDiv8, [SKLPort0,SKLDivider], 25, [1,10], 1>; 148defm : X86WriteRes<WriteIDiv16, [SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort06,SKLPort0156], 102, [4,2,4,8,14,34], 66>; 149defm : X86WriteRes<WriteIDiv32, [SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort06,SKLPort0156], 102, [4,2,4,8,14,34], 66>; 150defm : X86WriteRes<WriteIDiv64, [SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort06,SKLPort0156], 102, [4,2,4,8,14,34], 66>; 151defm : X86WriteRes<WriteIDiv8Ld, [SKLPort0,SKLPort5,SKLPort23,SKLPort0156], 28, [2,4,1,1], 8>; 152defm : X86WriteRes<WriteIDiv16Ld, [SKLPort0,SKLPort5,SKLPort23,SKLPort0156], 28, [2,4,1,1], 8>; 153defm : X86WriteRes<WriteIDiv32Ld, [SKLPort0,SKLPort5,SKLPort23,SKLPort0156], 28, [2,4,1,1], 8>; 154defm : X86WriteRes<WriteIDiv64Ld, [SKLPort0,SKLPort5,SKLPort23,SKLPort0156], 28, [2,4,1,1], 8>; 155 156defm : SKLWriteResPair<WriteCRC32, [SKLPort1], 3>; 157 158def : WriteRes<WriteLEA, [SKLPort15]>; // LEA instructions can't fold loads. 159 160defm : SKLWriteResPair<WriteCMOV, [SKLPort06], 1, [1], 1>; // Conditional move. 161defm : X86WriteRes<WriteFCMOV, [SKLPort1], 3, [1], 1>; // x87 conditional move. 162def : WriteRes<WriteSETCC, [SKLPort06]>; // Setcc. 163def : WriteRes<WriteSETCCStore, [SKLPort06,SKLPort4,SKLPort237]> { 164 let Latency = 2; 165 let NumMicroOps = 3; 166} 167 168defm : X86WriteRes<WriteLAHFSAHF, [SKLPort06], 1, [1], 1>; 169defm : X86WriteRes<WriteBitTest, [SKLPort06], 1, [1], 1>; 170defm : X86WriteRes<WriteBitTestImmLd, [SKLPort06,SKLPort23], 6, [1,1], 2>; 171defm : X86WriteRes<WriteBitTestRegLd, [SKLPort0156,SKLPort23], 6, [1,1], 2>; 172defm : X86WriteRes<WriteBitTestSet, [SKLPort06], 1, [1], 1>; 173defm : X86WriteRes<WriteBitTestSetImmLd, [SKLPort06,SKLPort23], 5, [1,1], 3>; 174defm : X86WriteRes<WriteBitTestSetRegLd, [SKLPort0156,SKLPort23], 5, [1,1], 2>; 175 176// Bit counts. 177defm : SKLWriteResPair<WriteBSF, [SKLPort1], 3>; 178defm : SKLWriteResPair<WriteBSR, [SKLPort1], 3>; 179defm : SKLWriteResPair<WriteLZCNT, [SKLPort1], 3>; 180defm : SKLWriteResPair<WriteTZCNT, [SKLPort1], 3>; 181defm : SKLWriteResPair<WritePOPCNT, [SKLPort1], 3>; 182 183// Integer shifts and rotates. 184defm : SKLWriteResPair<WriteShift, [SKLPort06], 1>; 185defm : SKLWriteResPair<WriteShiftCL, [SKLPort06], 3, [3], 3>; 186defm : SKLWriteResPair<WriteRotate, [SKLPort06], 1, [1], 1>; 187defm : SKLWriteResPair<WriteRotateCL, [SKLPort06], 3, [3], 3>; 188 189// SHLD/SHRD. 190defm : X86WriteRes<WriteSHDrri, [SKLPort1], 3, [1], 1>; 191defm : X86WriteRes<WriteSHDrrcl,[SKLPort1,SKLPort06,SKLPort0156], 6, [1, 2, 1], 4>; 192defm : X86WriteRes<WriteSHDmri, [SKLPort1,SKLPort23,SKLPort237,SKLPort0156], 9, [1, 1, 1, 1], 4>; 193defm : X86WriteRes<WriteSHDmrcl,[SKLPort1,SKLPort23,SKLPort237,SKLPort06,SKLPort0156], 11, [1, 1, 1, 2, 1], 6>; 194 195// BMI1 BEXTR/BLS, BMI2 BZHI 196defm : SKLWriteResPair<WriteBEXTR, [SKLPort06,SKLPort15], 2, [1,1], 2>; 197defm : SKLWriteResPair<WriteBLS, [SKLPort15], 1>; 198defm : SKLWriteResPair<WriteBZHI, [SKLPort15], 1>; 199 200// Loads, stores, and moves, not folded with other operations. 201defm : X86WriteRes<WriteLoad, [SKLPort23], 5, [1], 1>; 202defm : X86WriteRes<WriteStore, [SKLPort237, SKLPort4], 1, [1,1], 1>; 203defm : X86WriteRes<WriteStoreNT, [SKLPort237, SKLPort4], 1, [1,1], 2>; 204defm : X86WriteRes<WriteMove, [SKLPort0156], 1, [1], 1>; 205 206// Idioms that clear a register, like xorps %xmm0, %xmm0. 207// These can often bypass execution ports completely. 208def : WriteRes<WriteZero, []>; 209 210// Branches don't produce values, so they have no latency, but they still 211// consume resources. Indirect branches can fold loads. 212defm : SKLWriteResPair<WriteJump, [SKLPort06], 1>; 213 214// Floating point. This covers both scalar and vector operations. 215defm : X86WriteRes<WriteFLD0, [SKLPort05], 1, [1], 1>; 216defm : X86WriteRes<WriteFLD1, [SKLPort05], 1, [2], 2>; 217defm : X86WriteRes<WriteFLDC, [SKLPort05], 1, [2], 2>; 218defm : X86WriteRes<WriteFLoad, [SKLPort23], 5, [1], 1>; 219defm : X86WriteRes<WriteFLoadX, [SKLPort23], 6, [1], 1>; 220defm : X86WriteRes<WriteFLoadY, [SKLPort23], 7, [1], 1>; 221defm : X86WriteRes<WriteFMaskedLoad, [SKLPort23,SKLPort015], 7, [1,1], 2>; 222defm : X86WriteRes<WriteFMaskedLoadY, [SKLPort23,SKLPort015], 8, [1,1], 2>; 223defm : X86WriteRes<WriteFStore, [SKLPort237,SKLPort4], 1, [1,1], 2>; 224defm : X86WriteRes<WriteFStoreX, [SKLPort237,SKLPort4], 1, [1,1], 2>; 225defm : X86WriteRes<WriteFStoreY, [SKLPort237,SKLPort4], 1, [1,1], 2>; 226defm : X86WriteRes<WriteFStoreNT, [SKLPort237,SKLPort4], 1, [1,1], 2>; 227defm : X86WriteRes<WriteFStoreNTX, [SKLPort237,SKLPort4], 1, [1,1], 2>; 228defm : X86WriteRes<WriteFStoreNTY, [SKLPort237,SKLPort4], 1, [1,1], 2>; 229 230defm : X86WriteRes<WriteFMaskedStore32, [SKLPort237,SKLPort0], 2, [1,1], 2>; 231defm : X86WriteRes<WriteFMaskedStore32Y, [SKLPort237,SKLPort0], 2, [1,1], 2>; 232defm : X86WriteRes<WriteFMaskedStore64, [SKLPort237,SKLPort0], 2, [1,1], 2>; 233defm : X86WriteRes<WriteFMaskedStore64Y, [SKLPort237,SKLPort0], 2, [1,1], 2>; 234 235defm : X86WriteRes<WriteFMove, [SKLPort015], 1, [1], 1>; 236defm : X86WriteRes<WriteFMoveX, [SKLPort015], 1, [1], 1>; 237defm : X86WriteRes<WriteFMoveY, [SKLPort015], 1, [1], 1>; 238defm : X86WriteRes<WriteEMMS, [SKLPort05,SKLPort0156], 10, [9,1], 10>; 239 240defm : SKLWriteResPair<WriteFAdd, [SKLPort01], 4, [1], 1, 5>; // Floating point add/sub. 241defm : SKLWriteResPair<WriteFAddX, [SKLPort01], 4, [1], 1, 6>; 242defm : SKLWriteResPair<WriteFAddY, [SKLPort01], 4, [1], 1, 7>; 243defm : X86WriteResPairUnsupported<WriteFAddZ>; 244defm : SKLWriteResPair<WriteFAdd64, [SKLPort01], 4, [1], 1, 5>; // Floating point double add/sub. 245defm : SKLWriteResPair<WriteFAdd64X, [SKLPort01], 4, [1], 1, 6>; 246defm : SKLWriteResPair<WriteFAdd64Y, [SKLPort01], 4, [1], 1, 7>; 247defm : X86WriteResPairUnsupported<WriteFAdd64Z>; 248 249defm : SKLWriteResPair<WriteFCmp, [SKLPort01], 4, [1], 1, 5>; // Floating point compare. 250defm : SKLWriteResPair<WriteFCmpX, [SKLPort01], 4, [1], 1, 6>; 251defm : SKLWriteResPair<WriteFCmpY, [SKLPort01], 4, [1], 1, 7>; 252defm : X86WriteResPairUnsupported<WriteFCmpZ>; 253defm : SKLWriteResPair<WriteFCmp64, [SKLPort01], 4, [1], 1, 5>; // Floating point double compare. 254defm : SKLWriteResPair<WriteFCmp64X, [SKLPort01], 4, [1], 1, 6>; 255defm : SKLWriteResPair<WriteFCmp64Y, [SKLPort01], 4, [1], 1, 7>; 256defm : X86WriteResPairUnsupported<WriteFCmp64Z>; 257 258defm : SKLWriteResPair<WriteFCom, [SKLPort0], 2>; // Floating point compare to flags. 259 260defm : SKLWriteResPair<WriteFMul, [SKLPort01], 4, [1], 1, 5>; // Floating point multiplication. 261defm : SKLWriteResPair<WriteFMulX, [SKLPort01], 4, [1], 1, 6>; 262defm : SKLWriteResPair<WriteFMulY, [SKLPort01], 4, [1], 1, 7>; 263defm : X86WriteResPairUnsupported<WriteFMulZ>; 264defm : SKLWriteResPair<WriteFMul64, [SKLPort01], 4, [1], 1, 5>; // Floating point double multiplication. 265defm : SKLWriteResPair<WriteFMul64X, [SKLPort01], 4, [1], 1, 6>; 266defm : SKLWriteResPair<WriteFMul64Y, [SKLPort01], 4, [1], 1, 7>; 267defm : X86WriteResPairUnsupported<WriteFMul64Z>; 268 269defm : SKLWriteResPair<WriteFDiv, [SKLPort0,SKLFPDivider], 11, [1,3], 1, 5>; // Floating point division. 270//defm : SKLWriteResPair<WriteFDivX, [SKLPort0,SKLFPDivider], 11, [1,3], 1, 6>; 271defm : SKLWriteResPair<WriteFDivY, [SKLPort0,SKLFPDivider], 11, [1,5], 1, 7>; 272defm : X86WriteResPairUnsupported<WriteFDivZ>; 273//defm : SKLWriteResPair<WriteFDiv64, [SKLPort0,SKLFPDivider], 14, [1,3], 1, 5>; // Floating point double division. 274//defm : SKLWriteResPair<WriteFDiv64X, [SKLPort0,SKLFPDivider], 14, [1,3], 1, 6>; 275//defm : SKLWriteResPair<WriteFDiv64Y, [SKLPort0,SKLFPDivider], 14, [1,5], 1, 7>; 276defm : X86WriteResPairUnsupported<WriteFDiv64Z>; 277 278defm : SKLWriteResPair<WriteFSqrt, [SKLPort0,SKLFPDivider], 12, [1,3], 1, 5>; // Floating point square root. 279defm : SKLWriteResPair<WriteFSqrtX, [SKLPort0,SKLFPDivider], 12, [1,3], 1, 6>; 280defm : SKLWriteResPair<WriteFSqrtY, [SKLPort0,SKLFPDivider], 12, [1,6], 1, 7>; 281defm : X86WriteResPairUnsupported<WriteFSqrtZ>; 282defm : SKLWriteResPair<WriteFSqrt64, [SKLPort0,SKLFPDivider], 18, [1,6], 1, 5>; // Floating point double square root. 283defm : SKLWriteResPair<WriteFSqrt64X, [SKLPort0,SKLFPDivider], 18, [1,6], 1, 6>; 284defm : SKLWriteResPair<WriteFSqrt64Y, [SKLPort0,SKLFPDivider], 18, [1,12],1, 7>; 285defm : X86WriteResPairUnsupported<WriteFSqrt64Z>; 286defm : SKLWriteResPair<WriteFSqrt80, [SKLPort0,SKLFPDivider], 21, [1,7]>; // Floating point long double square root. 287 288defm : SKLWriteResPair<WriteFRcp, [SKLPort0], 4, [1], 1, 5>; // Floating point reciprocal estimate. 289defm : SKLWriteResPair<WriteFRcpX, [SKLPort0], 4, [1], 1, 6>; 290defm : SKLWriteResPair<WriteFRcpY, [SKLPort0], 4, [1], 1, 7>; 291defm : X86WriteResPairUnsupported<WriteFRcpZ>; 292 293defm : SKLWriteResPair<WriteFRsqrt, [SKLPort0], 4, [1], 1, 5>; // Floating point reciprocal square root estimate. 294defm : SKLWriteResPair<WriteFRsqrtX,[SKLPort0], 4, [1], 1, 6>; 295defm : SKLWriteResPair<WriteFRsqrtY,[SKLPort0], 4, [1], 1, 7>; 296defm : X86WriteResPairUnsupported<WriteFRsqrtZ>; 297 298defm : SKLWriteResPair<WriteFMA, [SKLPort01], 4, [1], 1, 5>; // Fused Multiply Add. 299defm : SKLWriteResPair<WriteFMAX, [SKLPort01], 4, [1], 1, 6>; 300defm : SKLWriteResPair<WriteFMAY, [SKLPort01], 4, [1], 1, 7>; 301defm : X86WriteResPairUnsupported<WriteFMAZ>; 302defm : SKLWriteResPair<WriteDPPD, [SKLPort5,SKLPort01], 9, [1,2], 3, 6>; // Floating point double dot product. 303defm : SKLWriteResPair<WriteDPPS, [SKLPort5,SKLPort01], 13, [1,3], 4, 6>; 304defm : SKLWriteResPair<WriteDPPSY, [SKLPort5,SKLPort01], 13, [1,3], 4, 7>; 305defm : X86WriteResPairUnsupported<WriteDPPSZ>; 306defm : SKLWriteResPair<WriteFSign, [SKLPort0], 1>; // Floating point fabs/fchs. 307defm : SKLWriteResPair<WriteFRnd, [SKLPort01], 8, [2], 2, 6>; // Floating point rounding. 308defm : SKLWriteResPair<WriteFRndY, [SKLPort01], 8, [2], 2, 7>; 309defm : X86WriteResPairUnsupported<WriteFRndZ>; 310defm : SKLWriteResPair<WriteFLogic, [SKLPort015], 1, [1], 1, 6>; // Floating point and/or/xor logicals. 311defm : SKLWriteResPair<WriteFLogicY, [SKLPort015], 1, [1], 1, 7>; 312defm : X86WriteResPairUnsupported<WriteFLogicZ>; 313defm : SKLWriteResPair<WriteFTest, [SKLPort0], 2, [1], 1, 6>; // Floating point TEST instructions. 314defm : SKLWriteResPair<WriteFTestY, [SKLPort0], 2, [1], 1, 7>; 315defm : X86WriteResPairUnsupported<WriteFTestZ>; 316defm : SKLWriteResPair<WriteFShuffle, [SKLPort5], 1, [1], 1, 6>; // Floating point vector shuffles. 317defm : SKLWriteResPair<WriteFShuffleY, [SKLPort5], 1, [1], 1, 7>; 318defm : X86WriteResPairUnsupported<WriteFShuffleZ>; 319defm : SKLWriteResPair<WriteFVarShuffle, [SKLPort5], 1, [1], 1, 6>; // Floating point vector shuffles. 320defm : SKLWriteResPair<WriteFVarShuffleY, [SKLPort5], 1, [1], 1, 7>; 321defm : X86WriteResPairUnsupported<WriteFVarShuffleZ>; 322defm : SKLWriteResPair<WriteFBlend, [SKLPort015], 1, [1], 1, 6>; // Floating point vector blends. 323defm : SKLWriteResPair<WriteFBlendY, [SKLPort015], 1, [1], 1, 7>; 324defm : X86WriteResPairUnsupported<WriteFBlendZ>; 325defm : SKLWriteResPair<WriteFVarBlend, [SKLPort015], 2, [2], 2, 6>; // Fp vector variable blends. 326defm : SKLWriteResPair<WriteFVarBlendY,[SKLPort015], 2, [2], 2, 7>; 327defm : X86WriteResPairUnsupported<WriteFVarBlendZ>; 328 329// FMA Scheduling helper class. 330// class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; } 331 332// Vector integer operations. 333defm : X86WriteRes<WriteVecLoad, [SKLPort23], 5, [1], 1>; 334defm : X86WriteRes<WriteVecLoadX, [SKLPort23], 6, [1], 1>; 335defm : X86WriteRes<WriteVecLoadY, [SKLPort23], 7, [1], 1>; 336defm : X86WriteRes<WriteVecLoadNT, [SKLPort23], 6, [1], 1>; 337defm : X86WriteRes<WriteVecLoadNTY, [SKLPort23], 7, [1], 1>; 338defm : X86WriteRes<WriteVecMaskedLoad, [SKLPort23,SKLPort015], 7, [1,1], 2>; 339defm : X86WriteRes<WriteVecMaskedLoadY, [SKLPort23,SKLPort015], 8, [1,1], 2>; 340defm : X86WriteRes<WriteVecStore, [SKLPort237,SKLPort4], 1, [1,1], 2>; 341defm : X86WriteRes<WriteVecStoreX, [SKLPort237,SKLPort4], 1, [1,1], 2>; 342defm : X86WriteRes<WriteVecStoreY, [SKLPort237,SKLPort4], 1, [1,1], 2>; 343defm : X86WriteRes<WriteVecStoreNT, [SKLPort237,SKLPort4], 1, [1,1], 2>; 344defm : X86WriteRes<WriteVecStoreNTY, [SKLPort237,SKLPort4], 1, [1,1], 2>; 345defm : X86WriteRes<WriteVecMaskedStore, [SKLPort237,SKLPort0], 2, [1,1], 2>; 346defm : X86WriteRes<WriteVecMaskedStoreY, [SKLPort237,SKLPort0], 2, [1,1], 2>; 347defm : X86WriteRes<WriteVecMove, [SKLPort05], 1, [1], 1>; 348defm : X86WriteRes<WriteVecMoveX, [SKLPort015], 1, [1], 1>; 349defm : X86WriteRes<WriteVecMoveY, [SKLPort015], 1, [1], 1>; 350defm : X86WriteRes<WriteVecMoveToGpr, [SKLPort0], 2, [1], 1>; 351defm : X86WriteRes<WriteVecMoveFromGpr, [SKLPort5], 1, [1], 1>; 352 353defm : SKLWriteResPair<WriteVecALU, [SKLPort05], 1, [1], 1, 5>; // Vector integer ALU op, no logicals. 354defm : SKLWriteResPair<WriteVecALUX, [SKLPort01], 1, [1], 1, 6>; 355defm : SKLWriteResPair<WriteVecALUY, [SKLPort01], 1, [1], 1, 7>; 356defm : X86WriteResPairUnsupported<WriteVecALUZ>; 357defm : SKLWriteResPair<WriteVecLogic, [SKLPort05], 1, [1], 1, 5>; // Vector integer and/or/xor. 358defm : SKLWriteResPair<WriteVecLogicX,[SKLPort015], 1, [1], 1, 6>; 359defm : SKLWriteResPair<WriteVecLogicY,[SKLPort015], 1, [1], 1, 7>; 360defm : X86WriteResPairUnsupported<WriteVecLogicZ>; 361defm : SKLWriteResPair<WriteVecTest, [SKLPort0,SKLPort5], 3, [1,1], 2, 6>; // Vector integer TEST instructions. 362defm : SKLWriteResPair<WriteVecTestY, [SKLPort0,SKLPort5], 3, [1,1], 2, 7>; 363defm : X86WriteResPairUnsupported<WriteVecTestZ>; 364defm : SKLWriteResPair<WriteVecIMul, [SKLPort0] , 4, [1], 1, 5>; // Vector integer multiply. 365defm : SKLWriteResPair<WriteVecIMulX, [SKLPort01], 4, [1], 1, 6>; 366defm : SKLWriteResPair<WriteVecIMulY, [SKLPort01], 4, [1], 1, 7>; 367defm : X86WriteResPairUnsupported<WriteVecIMulZ>; 368defm : SKLWriteResPair<WritePMULLD, [SKLPort01], 10, [2], 2, 6>; // Vector PMULLD. 369defm : SKLWriteResPair<WritePMULLDY, [SKLPort01], 10, [2], 2, 7>; 370defm : X86WriteResPairUnsupported<WritePMULLDZ>; 371defm : SKLWriteResPair<WriteShuffle, [SKLPort5], 1, [1], 1, 5>; // Vector shuffles. 372defm : SKLWriteResPair<WriteShuffleX, [SKLPort5], 1, [1], 1, 6>; 373defm : SKLWriteResPair<WriteShuffleY, [SKLPort5], 1, [1], 1, 7>; 374defm : X86WriteResPairUnsupported<WriteShuffleZ>; 375defm : SKLWriteResPair<WriteVarShuffle, [SKLPort5], 1, [1], 1, 5>; // Vector shuffles. 376defm : SKLWriteResPair<WriteVarShuffleX, [SKLPort5], 1, [1], 1, 6>; 377defm : SKLWriteResPair<WriteVarShuffleY, [SKLPort5], 1, [1], 1, 7>; 378defm : X86WriteResPairUnsupported<WriteVarShuffleZ>; 379defm : SKLWriteResPair<WriteBlend, [SKLPort5], 1, [1], 1, 6>; // Vector blends. 380defm : SKLWriteResPair<WriteBlendY, [SKLPort5], 1, [1], 1, 7>; 381defm : X86WriteResPairUnsupported<WriteBlendZ>; 382defm : SKLWriteResPair<WriteVarBlend, [SKLPort015], 2, [2], 2, 6>; // Vector variable blends. 383defm : SKLWriteResPair<WriteVarBlendY, [SKLPort015], 2, [2], 2, 6>; 384defm : X86WriteResPairUnsupported<WriteVarBlendZ>; 385defm : SKLWriteResPair<WriteMPSAD, [SKLPort5], 4, [2], 2, 6>; // Vector MPSAD. 386defm : SKLWriteResPair<WriteMPSADY, [SKLPort5], 4, [2], 2, 7>; 387defm : X86WriteResPairUnsupported<WriteMPSADZ>; 388defm : SKLWriteResPair<WritePSADBW, [SKLPort5], 3, [1], 1, 5>; // Vector PSADBW. 389defm : SKLWriteResPair<WritePSADBWX, [SKLPort5], 3, [1], 1, 6>; 390defm : SKLWriteResPair<WritePSADBWY, [SKLPort5], 3, [1], 1, 7>; 391defm : X86WriteResPairUnsupported<WritePSADBWZ>; 392defm : SKLWriteResPair<WritePHMINPOS, [SKLPort01], 4, [1], 1, 6>; // Vector PHMINPOS. 393 394// Vector integer shifts. 395defm : SKLWriteResPair<WriteVecShift, [SKLPort0], 1, [1], 1, 5>; 396defm : X86WriteRes<WriteVecShiftX, [SKLPort5,SKLPort01], 2, [1,1], 2>; 397defm : X86WriteRes<WriteVecShiftY, [SKLPort5,SKLPort01], 4, [1,1], 2>; 398defm : X86WriteRes<WriteVecShiftXLd, [SKLPort01,SKLPort23], 7, [1,1], 2>; 399defm : X86WriteRes<WriteVecShiftYLd, [SKLPort01,SKLPort23], 8, [1,1], 2>; 400defm : X86WriteResPairUnsupported<WriteVecShiftZ>; 401 402defm : SKLWriteResPair<WriteVecShiftImm, [SKLPort0], 1, [1], 1, 5>; // Vector integer immediate shifts. 403defm : SKLWriteResPair<WriteVecShiftImmX, [SKLPort01], 1, [1], 1, 6>; 404defm : SKLWriteResPair<WriteVecShiftImmY, [SKLPort01], 1, [1], 1, 7>; 405defm : X86WriteResPairUnsupported<WriteVecShiftImmZ>; 406defm : SKLWriteResPair<WriteVarVecShift, [SKLPort01], 1, [1], 1, 6>; // Variable vector shifts. 407defm : SKLWriteResPair<WriteVarVecShiftY, [SKLPort01], 1, [1], 1, 7>; 408defm : X86WriteResPairUnsupported<WriteVarVecShiftZ>; 409 410// Vector insert/extract operations. 411def : WriteRes<WriteVecInsert, [SKLPort5]> { 412 let Latency = 2; 413 let NumMicroOps = 2; 414 let ResourceCycles = [2]; 415} 416def : WriteRes<WriteVecInsertLd, [SKLPort5,SKLPort23]> { 417 let Latency = 6; 418 let NumMicroOps = 2; 419} 420def: InstRW<[WriteVecInsertLd], (instregex "(V?)MOV(H|L)(PD|PS)rm")>; 421 422def : WriteRes<WriteVecExtract, [SKLPort0,SKLPort5]> { 423 let Latency = 3; 424 let NumMicroOps = 2; 425} 426def : WriteRes<WriteVecExtractSt, [SKLPort4,SKLPort5,SKLPort237]> { 427 let Latency = 2; 428 let NumMicroOps = 3; 429} 430 431// Conversion between integer and float. 432defm : SKLWriteResPair<WriteCvtSS2I, [SKLPort1], 3>; 433defm : SKLWriteResPair<WriteCvtPS2I, [SKLPort1], 3>; 434defm : SKLWriteResPair<WriteCvtPS2IY, [SKLPort1], 3>; 435defm : X86WriteResPairUnsupported<WriteCvtPS2IZ>; 436defm : SKLWriteResPair<WriteCvtSD2I, [SKLPort1], 3>; 437defm : SKLWriteResPair<WriteCvtPD2I, [SKLPort1], 3>; 438defm : SKLWriteResPair<WriteCvtPD2IY, [SKLPort1], 3>; 439defm : X86WriteResPairUnsupported<WriteCvtPD2IZ>; 440 441defm : SKLWriteResPair<WriteCvtI2SS, [SKLPort1], 4>; 442defm : SKLWriteResPair<WriteCvtI2PS, [SKLPort1], 4>; 443defm : SKLWriteResPair<WriteCvtI2PSY, [SKLPort1], 4>; 444defm : X86WriteResPairUnsupported<WriteCvtI2PSZ>; 445defm : SKLWriteResPair<WriteCvtI2SD, [SKLPort1], 4>; 446defm : SKLWriteResPair<WriteCvtI2PD, [SKLPort1], 4>; 447defm : SKLWriteResPair<WriteCvtI2PDY, [SKLPort1], 4>; 448defm : X86WriteResPairUnsupported<WriteCvtI2PDZ>; 449 450defm : SKLWriteResPair<WriteCvtSS2SD, [SKLPort1], 3>; 451defm : SKLWriteResPair<WriteCvtPS2PD, [SKLPort1], 3>; 452defm : SKLWriteResPair<WriteCvtPS2PDY, [SKLPort1], 3>; 453defm : X86WriteResPairUnsupported<WriteCvtPS2PDZ>; 454defm : SKLWriteResPair<WriteCvtSD2SS, [SKLPort1], 3>; 455defm : SKLWriteResPair<WriteCvtPD2PS, [SKLPort1], 3>; 456defm : SKLWriteResPair<WriteCvtPD2PSY, [SKLPort1], 3>; 457defm : X86WriteResPairUnsupported<WriteCvtPD2PSZ>; 458 459defm : X86WriteRes<WriteCvtPH2PS, [SKLPort5,SKLPort015], 5, [1,1], 2>; 460defm : X86WriteRes<WriteCvtPH2PSY, [SKLPort5,SKLPort01], 7, [1,1], 2>; 461defm : X86WriteResUnsupported<WriteCvtPH2PSZ>; 462defm : X86WriteRes<WriteCvtPH2PSLd, [SKLPort23,SKLPort01], 9, [1,1], 2>; 463defm : X86WriteRes<WriteCvtPH2PSYLd, [SKLPort23,SKLPort01], 10, [1,1], 2>; 464defm : X86WriteResUnsupported<WriteCvtPH2PSZLd>; 465 466defm : X86WriteRes<WriteCvtPS2PH, [SKLPort5,SKLPort015], 5, [1,1], 2>; 467defm : X86WriteRes<WriteCvtPS2PHY, [SKLPort5,SKLPort01], 7, [1,1], 2>; 468defm : X86WriteResUnsupported<WriteCvtPS2PHZ>; 469defm : X86WriteRes<WriteCvtPS2PHSt, [SKLPort4,SKLPort5,SKLPort237,SKLPort01], 6, [1,1,1,1], 4>; 470defm : X86WriteRes<WriteCvtPS2PHYSt, [SKLPort4,SKLPort5,SKLPort237,SKLPort01], 8, [1,1,1,1], 4>; 471defm : X86WriteResUnsupported<WriteCvtPS2PHZSt>; 472 473// Strings instructions. 474 475// Packed Compare Implicit Length Strings, Return Mask 476def : WriteRes<WritePCmpIStrM, [SKLPort0]> { 477 let Latency = 10; 478 let NumMicroOps = 3; 479 let ResourceCycles = [3]; 480} 481def : WriteRes<WritePCmpIStrMLd, [SKLPort0, SKLPort23]> { 482 let Latency = 16; 483 let NumMicroOps = 4; 484 let ResourceCycles = [3,1]; 485} 486 487// Packed Compare Explicit Length Strings, Return Mask 488def : WriteRes<WritePCmpEStrM, [SKLPort0, SKLPort5, SKLPort015, SKLPort0156]> { 489 let Latency = 19; 490 let NumMicroOps = 9; 491 let ResourceCycles = [4,3,1,1]; 492} 493def : WriteRes<WritePCmpEStrMLd, [SKLPort0, SKLPort5,SKLPort23, SKLPort015, SKLPort0156]> { 494 let Latency = 25; 495 let NumMicroOps = 10; 496 let ResourceCycles = [4,3,1,1,1]; 497} 498 499// Packed Compare Implicit Length Strings, Return Index 500def : WriteRes<WritePCmpIStrI, [SKLPort0]> { 501 let Latency = 10; 502 let NumMicroOps = 3; 503 let ResourceCycles = [3]; 504} 505def : WriteRes<WritePCmpIStrILd, [SKLPort0, SKLPort23]> { 506 let Latency = 16; 507 let NumMicroOps = 4; 508 let ResourceCycles = [3,1]; 509} 510 511// Packed Compare Explicit Length Strings, Return Index 512def : WriteRes<WritePCmpEStrI, [SKLPort0, SKLPort5, SKLPort0156]> { 513 let Latency = 18; 514 let NumMicroOps = 8; 515 let ResourceCycles = [4,3,1]; 516} 517def : WriteRes<WritePCmpEStrILd, [SKLPort0, SKLPort5, SKLPort23, SKLPort0156]> { 518 let Latency = 24; 519 let NumMicroOps = 9; 520 let ResourceCycles = [4,3,1,1]; 521} 522 523// MOVMSK Instructions. 524def : WriteRes<WriteFMOVMSK, [SKLPort0]> { let Latency = 2; } 525def : WriteRes<WriteVecMOVMSK, [SKLPort0]> { let Latency = 2; } 526def : WriteRes<WriteVecMOVMSKY, [SKLPort0]> { let Latency = 2; } 527def : WriteRes<WriteMMXMOVMSK, [SKLPort0]> { let Latency = 2; } 528 529// AES instructions. 530def : WriteRes<WriteAESDecEnc, [SKLPort0]> { // Decryption, encryption. 531 let Latency = 4; 532 let NumMicroOps = 1; 533 let ResourceCycles = [1]; 534} 535def : WriteRes<WriteAESDecEncLd, [SKLPort0, SKLPort23]> { 536 let Latency = 10; 537 let NumMicroOps = 2; 538 let ResourceCycles = [1,1]; 539} 540 541def : WriteRes<WriteAESIMC, [SKLPort0]> { // InvMixColumn. 542 let Latency = 8; 543 let NumMicroOps = 2; 544 let ResourceCycles = [2]; 545} 546def : WriteRes<WriteAESIMCLd, [SKLPort0, SKLPort23]> { 547 let Latency = 14; 548 let NumMicroOps = 3; 549 let ResourceCycles = [2,1]; 550} 551 552def : WriteRes<WriteAESKeyGen, [SKLPort0, SKLPort5, SKLPort015]> { // Key Generation. 553 let Latency = 20; 554 let NumMicroOps = 11; 555 let ResourceCycles = [3,6,2]; 556} 557def : WriteRes<WriteAESKeyGenLd, [SKLPort0, SKLPort5, SKLPort23, SKLPort015]> { 558 let Latency = 25; 559 let NumMicroOps = 11; 560 let ResourceCycles = [3,6,1,1]; 561} 562 563// Carry-less multiplication instructions. 564def : WriteRes<WriteCLMul, [SKLPort5]> { 565 let Latency = 6; 566 let NumMicroOps = 1; 567 let ResourceCycles = [1]; 568} 569def : WriteRes<WriteCLMulLd, [SKLPort5, SKLPort23]> { 570 let Latency = 12; 571 let NumMicroOps = 2; 572 let ResourceCycles = [1,1]; 573} 574 575// Catch-all for expensive system instructions. 576def : WriteRes<WriteSystem, [SKLPort0156]> { let Latency = 100; } // def WriteSystem : SchedWrite; 577 578// AVX2. 579defm : SKLWriteResPair<WriteFShuffle256, [SKLPort5], 3, [1], 1, 7>; // Fp 256-bit width vector shuffles. 580defm : SKLWriteResPair<WriteFVarShuffle256, [SKLPort5], 3, [1], 1, 7>; // Fp 256-bit width vector variable shuffles. 581defm : SKLWriteResPair<WriteShuffle256, [SKLPort5], 3, [1], 1, 7>; // 256-bit width vector shuffles. 582defm : SKLWriteResPair<WriteVarShuffle256, [SKLPort5], 3, [1], 1, 7>; // 256-bit width vector variable shuffles. 583 584// Old microcoded instructions that nobody use. 585def : WriteRes<WriteMicrocoded, [SKLPort0156]> { let Latency = 100; } // def WriteMicrocoded : SchedWrite; 586 587// Fence instructions. 588def : WriteRes<WriteFence, [SKLPort23, SKLPort4]>; 589 590// Load/store MXCSR. 591def : WriteRes<WriteLDMXCSR, [SKLPort0,SKLPort23,SKLPort0156]> { let Latency = 7; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } 592def : WriteRes<WriteSTMXCSR, [SKLPort4,SKLPort5,SKLPort237]> { let Latency = 2; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } 593 594// Nop, not very useful expect it provides a model for nops! 595def : WriteRes<WriteNop, []>; 596 597//////////////////////////////////////////////////////////////////////////////// 598// Horizontal add/sub instructions. 599//////////////////////////////////////////////////////////////////////////////// 600 601defm : SKLWriteResPair<WriteFHAdd, [SKLPort5,SKLPort01], 6, [2,1], 3, 6>; 602defm : SKLWriteResPair<WriteFHAddY, [SKLPort5,SKLPort01], 6, [2,1], 3, 7>; 603defm : SKLWriteResPair<WritePHAdd, [SKLPort5,SKLPort05], 3, [2,1], 3, 5>; 604defm : SKLWriteResPair<WritePHAddX, [SKLPort5,SKLPort015], 3, [2,1], 3, 6>; 605defm : SKLWriteResPair<WritePHAddY, [SKLPort5,SKLPort015], 3, [2,1], 3, 7>; 606 607// Remaining instrs. 608 609def SKLWriteResGroup1 : SchedWriteRes<[SKLPort0]> { 610 let Latency = 1; 611 let NumMicroOps = 1; 612 let ResourceCycles = [1]; 613} 614def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PADDS(B|W)irr", 615 "MMX_PADDUS(B|W)irr", 616 "MMX_PAVG(B|W)irr", 617 "MMX_PCMPEQ(B|D|W)irr", 618 "MMX_PCMPGT(B|D|W)irr", 619 "MMX_P(MAX|MIN)SWirr", 620 "MMX_P(MAX|MIN)UBirr", 621 "MMX_PSUBS(B|W)irr", 622 "MMX_PSUBUS(B|W)irr")>; 623 624def SKLWriteResGroup3 : SchedWriteRes<[SKLPort5]> { 625 let Latency = 1; 626 let NumMicroOps = 1; 627 let ResourceCycles = [1]; 628} 629def: InstRW<[SKLWriteResGroup3], (instregex "COM(P?)_FST0r", 630 "UCOM_F(P?)r")>; 631 632def SKLWriteResGroup4 : SchedWriteRes<[SKLPort6]> { 633 let Latency = 1; 634 let NumMicroOps = 1; 635 let ResourceCycles = [1]; 636} 637def: InstRW<[SKLWriteResGroup4], (instregex "JMP(16|32|64)r")>; 638 639def SKLWriteResGroup6 : SchedWriteRes<[SKLPort05]> { 640 let Latency = 1; 641 let NumMicroOps = 1; 642 let ResourceCycles = [1]; 643} 644def: InstRW<[SKLWriteResGroup6], (instrs FINCSTP, FNOP)>; 645 646def SKLWriteResGroup7 : SchedWriteRes<[SKLPort06]> { 647 let Latency = 1; 648 let NumMicroOps = 1; 649 let ResourceCycles = [1]; 650} 651def: InstRW<[SKLWriteResGroup7], (instrs CDQ, CQO, CLAC, STAC)>; 652 653def SKLWriteResGroup8 : SchedWriteRes<[SKLPort15]> { 654 let Latency = 1; 655 let NumMicroOps = 1; 656 let ResourceCycles = [1]; 657} 658def: InstRW<[SKLWriteResGroup8], (instregex "ANDN(32|64)rr")>; 659 660def SKLWriteResGroup9 : SchedWriteRes<[SKLPort015]> { 661 let Latency = 1; 662 let NumMicroOps = 1; 663 let ResourceCycles = [1]; 664} 665def: InstRW<[SKLWriteResGroup9], (instregex "(V?)PADD(B|D|Q|W)(Y?)rr", 666 "VPBLENDD(Y?)rri")>; 667 668def SKLWriteResGroup10 : SchedWriteRes<[SKLPort0156]> { 669 let Latency = 1; 670 let NumMicroOps = 1; 671 let ResourceCycles = [1]; 672} 673def: InstRW<[SKLWriteResGroup10], (instrs CBW, CWDE, CDQE, 674 CMC, STC, 675 SGDT64m, 676 SIDT64m, 677 SMSW16m, 678 STRm, 679 SYSCALL)>; 680 681def SKLWriteResGroup11 : SchedWriteRes<[SKLPort4,SKLPort237]> { 682 let Latency = 1; 683 let NumMicroOps = 2; 684 let ResourceCycles = [1,1]; 685} 686def: InstRW<[SKLWriteResGroup11], (instrs FBSTPm, VMPTRSTm)>; 687def: InstRW<[SKLWriteResGroup11], (instregex "ST_FP(32|64|80)m")>; 688 689def SKLWriteResGroup13 : SchedWriteRes<[SKLPort5]> { 690 let Latency = 2; 691 let NumMicroOps = 2; 692 let ResourceCycles = [2]; 693} 694def: InstRW<[SKLWriteResGroup13], (instrs MMX_MOVQ2DQrr)>; 695 696def SKLWriteResGroup14 : SchedWriteRes<[SKLPort05]> { 697 let Latency = 2; 698 let NumMicroOps = 2; 699 let ResourceCycles = [2]; 700} 701def: InstRW<[SKLWriteResGroup14], (instrs FDECSTP, 702 MMX_MOVDQ2Qrr)>; 703 704def SKLWriteResGroup17 : SchedWriteRes<[SKLPort0156]> { 705 let Latency = 2; 706 let NumMicroOps = 2; 707 let ResourceCycles = [2]; 708} 709def: InstRW<[SKLWriteResGroup17], (instrs LFENCE, 710 WAIT, 711 XGETBV)>; 712 713def SKLWriteResGroup20 : SchedWriteRes<[SKLPort6,SKLPort0156]> { 714 let Latency = 2; 715 let NumMicroOps = 2; 716 let ResourceCycles = [1,1]; 717} 718def: InstRW<[SKLWriteResGroup20], (instregex "CLFLUSH")>; 719 720def SKLWriteResGroup21 : SchedWriteRes<[SKLPort237,SKLPort0156]> { 721 let Latency = 2; 722 let NumMicroOps = 2; 723 let ResourceCycles = [1,1]; 724} 725def: InstRW<[SKLWriteResGroup21], (instrs SFENCE)>; 726 727def SKLWriteResGroup23 : SchedWriteRes<[SKLPort06,SKLPort0156]> { 728 let Latency = 2; 729 let NumMicroOps = 2; 730 let ResourceCycles = [1,1]; 731} 732def: InstRW<[SKLWriteResGroup23], (instrs CWD, 733 JCXZ, JECXZ, JRCXZ, 734 ADC8i8, SBB8i8, 735 ADC16i16, SBB16i16, 736 ADC32i32, SBB32i32, 737 ADC64i32, SBB64i32)>; 738 739def SKLWriteResGroup25 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort237]> { 740 let Latency = 2; 741 let NumMicroOps = 3; 742 let ResourceCycles = [1,1,1]; 743} 744def: InstRW<[SKLWriteResGroup25], (instrs FNSTCW16m)>; 745 746def SKLWriteResGroup27 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort15]> { 747 let Latency = 2; 748 let NumMicroOps = 3; 749 let ResourceCycles = [1,1,1]; 750} 751def: InstRW<[SKLWriteResGroup27], (instregex "MOVBE(16|32|64)mr")>; 752 753def SKLWriteResGroup28 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort0156]> { 754 let Latency = 2; 755 let NumMicroOps = 3; 756 let ResourceCycles = [1,1,1]; 757} 758def: InstRW<[SKLWriteResGroup28], (instrs PUSH16r, PUSH32r, PUSH64r, PUSH64i8, 759 STOSB, STOSL, STOSQ, STOSW)>; 760def: InstRW<[SKLWriteResGroup28], (instregex "PUSH(16|32|64)rmr")>; 761 762def SKLWriteResGroup29 : SchedWriteRes<[SKLPort1]> { 763 let Latency = 3; 764 let NumMicroOps = 1; 765 let ResourceCycles = [1]; 766} 767def: InstRW<[SKLWriteResGroup29], (instregex "PDEP(32|64)rr", 768 "PEXT(32|64)rr")>; 769 770def SKLWriteResGroup30 : SchedWriteRes<[SKLPort5]> { 771 let Latency = 3; 772 let NumMicroOps = 1; 773 let ResourceCycles = [1]; 774} 775def: InstRW<[SKLWriteResGroup30], (instregex "(ADD|SUB|SUBR)_(FPrST0|FST0r|FrST0)", 776 "VPBROADCAST(B|W)rr")>; 777 778def SKLWriteResGroup32 : SchedWriteRes<[SKLPort0,SKLPort0156]> { 779 let Latency = 3; 780 let NumMicroOps = 2; 781 let ResourceCycles = [1,1]; 782} 783def: InstRW<[SKLWriteResGroup32], (instrs FNSTSW16r)>; 784 785def SKLWriteResGroup35 : SchedWriteRes<[SKLPort0,SKLPort5]> { 786 let Latency = 3; 787 let NumMicroOps = 3; 788 let ResourceCycles = [1,2]; 789} 790def: InstRW<[SKLWriteResGroup35], (instregex "MMX_PH(ADD|SUB)SWrr")>; 791 792def SKLWriteResGroup36 : SchedWriteRes<[SKLPort5,SKLPort01]> { 793 let Latency = 3; 794 let NumMicroOps = 3; 795 let ResourceCycles = [2,1]; 796} 797def: InstRW<[SKLWriteResGroup36], (instregex "(V?)PHADDSW(Y?)rr", 798 "(V?)PHSUBSW(Y?)rr")>; 799 800def SKLWriteResGroup39 : SchedWriteRes<[SKLPort5,SKLPort0156]> { 801 let Latency = 3; 802 let NumMicroOps = 3; 803 let ResourceCycles = [2,1]; 804} 805def: InstRW<[SKLWriteResGroup39], (instrs MMX_PACKSSDWirr, 806 MMX_PACKSSWBirr, 807 MMX_PACKUSWBirr)>; 808 809def SKLWriteResGroup40 : SchedWriteRes<[SKLPort6,SKLPort0156]> { 810 let Latency = 3; 811 let NumMicroOps = 3; 812 let ResourceCycles = [1,2]; 813} 814def: InstRW<[SKLWriteResGroup40], (instregex "CLD")>; 815 816def SKLWriteResGroup41 : SchedWriteRes<[SKLPort237,SKLPort0156]> { 817 let Latency = 3; 818 let NumMicroOps = 3; 819 let ResourceCycles = [1,2]; 820} 821def: InstRW<[SKLWriteResGroup41], (instrs MFENCE)>; 822 823def SKLWriteResGroup42 : SchedWriteRes<[SKLPort06,SKLPort0156]> { 824 let Latency = 3; 825 let NumMicroOps = 3; 826 let ResourceCycles = [1,2]; 827} 828def: InstRW<[SKLWriteResGroup42], (instregex "RCL(8|16|32|64)r(1|i)", 829 "RCR(8|16|32|64)r(1|i)")>; 830 831def SKLWriteResGroup43 : SchedWriteRes<[SKLPort0,SKLPort4,SKLPort237]> { 832 let Latency = 3; 833 let NumMicroOps = 3; 834 let ResourceCycles = [1,1,1]; 835} 836def: InstRW<[SKLWriteResGroup43], (instrs FNSTSWm)>; 837 838def SKLWriteResGroup45 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort237,SKLPort0156]> { 839 let Latency = 3; 840 let NumMicroOps = 4; 841 let ResourceCycles = [1,1,1,1]; 842} 843def: InstRW<[SKLWriteResGroup45], (instregex "CALL(16|32|64)r")>; 844 845def SKLWriteResGroup46 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort06,SKLPort0156]> { 846 let Latency = 3; 847 let NumMicroOps = 4; 848 let ResourceCycles = [1,1,1,1]; 849} 850def: InstRW<[SKLWriteResGroup46], (instrs CALL64pcrel32)>; 851 852def SKLWriteResGroup47 : SchedWriteRes<[SKLPort0]> { 853 let Latency = 4; 854 let NumMicroOps = 1; 855 let ResourceCycles = [1]; 856} 857def: InstRW<[SKLWriteResGroup47], (instregex "MUL_(FPrST0|FST0r|FrST0)")>; 858 859def SKLWriteResGroup48 : SchedWriteRes<[SKLPort01]> { 860 let Latency = 4; 861 let NumMicroOps = 1; 862 let ResourceCycles = [1]; 863} 864def: InstRW<[SKLWriteResGroup48], (instregex "(V?)CVTDQ2PS(Y?)rr", 865 "(V?)CVT(T?)PS2DQ(Y?)rr")>; 866 867def SKLWriteResGroup53 : SchedWriteRes<[SKLPort4,SKLPort5,SKLPort237]> { 868 let Latency = 4; 869 let NumMicroOps = 3; 870 let ResourceCycles = [1,1,1]; 871} 872def: InstRW<[SKLWriteResGroup53], (instregex "IST(T?)_FP(16|32|64)m", 873 "IST_F(16|32)m")>; 874 875def SKLWriteResGroup54 : SchedWriteRes<[SKLPort0156]> { 876 let Latency = 4; 877 let NumMicroOps = 4; 878 let ResourceCycles = [4]; 879} 880def: InstRW<[SKLWriteResGroup54], (instrs FNCLEX)>; 881 882def SKLWriteResGroup55 : SchedWriteRes<[SKLPort6,SKLPort0156]> { 883 let Latency = 4; 884 let NumMicroOps = 4; 885 let ResourceCycles = [1,3]; 886} 887def: InstRW<[SKLWriteResGroup55], (instrs PAUSE)>; 888 889def SKLWriteResGroup56 : SchedWriteRes<[]> { 890 let Latency = 0; 891 let NumMicroOps = 4; 892 let ResourceCycles = []; 893} 894def: InstRW<[SKLWriteResGroup56], (instrs VZEROUPPER)>; 895 896def SKLWriteResGroup57 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort0156]> { 897 let Latency = 4; 898 let NumMicroOps = 4; 899 let ResourceCycles = [1,1,2]; 900} 901def: InstRW<[SKLWriteResGroup57], (instregex "LAR(16|32|64)rr")>; 902 903def SKLWriteResGroup58 : SchedWriteRes<[SKLPort23]> { 904 let Latency = 5; 905 let NumMicroOps = 1; 906 let ResourceCycles = [1]; 907} 908def: InstRW<[SKLWriteResGroup58], (instregex "MOVSX(16|32|64)rm(8|16|32)", 909 "MOVZX(16|32|64)rm(8|16)", 910 "(V?)MOVDDUPrm")>; // TODO: Should this be SKLWriteResGroup67? 911 912def SKLWriteResGroup59 : SchedWriteRes<[SKLPort0,SKLPort5]> { 913 let Latency = 5; 914 let NumMicroOps = 2; 915 let ResourceCycles = [1,1]; 916} 917def: InstRW<[SKLWriteResGroup59], (instrs MMX_CVTPI2PDirr, 918 CVTDQ2PDrr, 919 VCVTDQ2PDrr)>; 920 921def SKLWriteResGroup60 : SchedWriteRes<[SKLPort5,SKLPort015]> { 922 let Latency = 5; 923 let NumMicroOps = 2; 924 let ResourceCycles = [1,1]; 925} 926def: InstRW<[SKLWriteResGroup60], (instregex "MMX_CVT(T?)PD2PIirr", 927 "MMX_CVT(T?)PS2PIirr", 928 "(V?)CVT(T?)PD2DQrr", 929 "(V?)CVTPD2PSrr", 930 "(V?)CVTPS2PDrr", 931 "(V?)CVTSD2SSrr", 932 "(V?)CVTSI642SDrr", 933 "(V?)CVTSI2SDrr", 934 "(V?)CVTSI2SSrr", 935 "(V?)CVTSS2SDrr")>; 936 937def SKLWriteResGroup61 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort06]> { 938 let Latency = 5; 939 let NumMicroOps = 3; 940 let ResourceCycles = [1,1,1]; 941} 942def: InstRW<[SKLWriteResGroup61], (instregex "STR(16|32|64)r")>; 943 944def SKLWriteResGroup63 : SchedWriteRes<[SKLPort06,SKLPort0156]> { 945 let Latency = 5; 946 let NumMicroOps = 5; 947 let ResourceCycles = [1,4]; 948} 949def: InstRW<[SKLWriteResGroup63], (instrs XSETBV)>; 950 951def SKLWriteResGroup65 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort0156]> { 952 let Latency = 5; 953 let NumMicroOps = 6; 954 let ResourceCycles = [1,1,4]; 955} 956def: InstRW<[SKLWriteResGroup65], (instregex "PUSHF(16|64)")>; 957 958def SKLWriteResGroup67 : SchedWriteRes<[SKLPort23]> { 959 let Latency = 6; 960 let NumMicroOps = 1; 961 let ResourceCycles = [1]; 962} 963def: InstRW<[SKLWriteResGroup67], (instrs VBROADCASTSSrm, 964 VPBROADCASTDrm, 965 VPBROADCASTQrm)>; 966def: InstRW<[SKLWriteResGroup67], (instregex "(V?)MOVSHDUPrm", 967 "(V?)MOVSLDUPrm")>; 968 969def SKLWriteResGroup68 : SchedWriteRes<[SKLPort0]> { 970 let Latency = 6; 971 let NumMicroOps = 2; 972 let ResourceCycles = [2]; 973} 974def: InstRW<[SKLWriteResGroup68], (instrs MMX_CVTPI2PSirr)>; 975 976def SKLWriteResGroup69 : SchedWriteRes<[SKLPort0,SKLPort23]> { 977 let Latency = 6; 978 let NumMicroOps = 2; 979 let ResourceCycles = [1,1]; 980} 981def: InstRW<[SKLWriteResGroup69], (instrs MMX_PADDSBirm, 982 MMX_PADDSWirm, 983 MMX_PADDUSBirm, 984 MMX_PADDUSWirm, 985 MMX_PAVGBirm, 986 MMX_PAVGWirm, 987 MMX_PCMPEQBirm, 988 MMX_PCMPEQDirm, 989 MMX_PCMPEQWirm, 990 MMX_PCMPGTBirm, 991 MMX_PCMPGTDirm, 992 MMX_PCMPGTWirm, 993 MMX_PMAXSWirm, 994 MMX_PMAXUBirm, 995 MMX_PMINSWirm, 996 MMX_PMINUBirm, 997 MMX_PSUBSBirm, 998 MMX_PSUBSWirm, 999 MMX_PSUBUSBirm, 1000 MMX_PSUBUSWirm)>; 1001 1002def SKLWriteResGroup70 : SchedWriteRes<[SKLPort0,SKLPort01]> { 1003 let Latency = 6; 1004 let NumMicroOps = 2; 1005 let ResourceCycles = [1,1]; 1006} 1007def: InstRW<[SKLWriteResGroup70], (instregex "(V?)CVTSS2SI(64)?rr", 1008 "(V?)CVT(T?)SD2SI(64)?rr")>; 1009 1010def SKLWriteResGroup72 : SchedWriteRes<[SKLPort6,SKLPort23]> { 1011 let Latency = 6; 1012 let NumMicroOps = 2; 1013 let ResourceCycles = [1,1]; 1014} 1015def: InstRW<[SKLWriteResGroup72], (instrs FARJMP64)>; 1016def: InstRW<[SKLWriteResGroup72], (instregex "JMP(16|32|64)m")>; 1017 1018def SKLWriteResGroup75 : SchedWriteRes<[SKLPort23,SKLPort15]> { 1019 let Latency = 6; 1020 let NumMicroOps = 2; 1021 let ResourceCycles = [1,1]; 1022} 1023def: InstRW<[SKLWriteResGroup75], (instregex "ANDN(32|64)rm", 1024 "MOVBE(16|32|64)rm")>; 1025 1026def SKLWriteResGroup76 : SchedWriteRes<[SKLPort23,SKLPort0156]> { 1027 let Latency = 6; 1028 let NumMicroOps = 2; 1029 let ResourceCycles = [1,1]; 1030} 1031def: InstRW<[SKLWriteResGroup76], (instrs POP16r, POP32r, POP64r)>; 1032def: InstRW<[SKLWriteResGroup76], (instregex "POP(16|32|64)rmr")>; 1033 1034def SKLWriteResGroup78 : SchedWriteRes<[SKLPort5,SKLPort01]> { 1035 let Latency = 6; 1036 let NumMicroOps = 3; 1037 let ResourceCycles = [2,1]; 1038} 1039def: InstRW<[SKLWriteResGroup78], (instregex "(V?)CVTSI642SSrr")>; 1040 1041def SKLWriteResGroup80 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort06,SKLPort0156]> { 1042 let Latency = 6; 1043 let NumMicroOps = 4; 1044 let ResourceCycles = [1,1,1,1]; 1045} 1046def: InstRW<[SKLWriteResGroup80], (instregex "SLDT(16|32|64)r")>; 1047 1048def SKLWriteResGroup82 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> { 1049 let Latency = 6; 1050 let NumMicroOps = 4; 1051 let ResourceCycles = [1,1,1,1]; 1052} 1053def: InstRW<[SKLWriteResGroup82], (instregex "SAR(8|16|32|64)m(1|i)", 1054 "SHL(8|16|32|64)m(1|i)", 1055 "SHR(8|16|32|64)m(1|i)")>; 1056 1057def SKLWriteResGroup83 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort0156]> { 1058 let Latency = 6; 1059 let NumMicroOps = 4; 1060 let ResourceCycles = [1,1,1,1]; 1061} 1062def: InstRW<[SKLWriteResGroup83], (instregex "POP(16|32|64)rmm", 1063 "PUSH(16|32|64)rmm")>; 1064 1065def SKLWriteResGroup84 : SchedWriteRes<[SKLPort6,SKLPort0156]> { 1066 let Latency = 6; 1067 let NumMicroOps = 6; 1068 let ResourceCycles = [1,5]; 1069} 1070def: InstRW<[SKLWriteResGroup84], (instrs STD)>; 1071 1072def SKLWriteResGroup85 : SchedWriteRes<[SKLPort23]> { 1073 let Latency = 7; 1074 let NumMicroOps = 1; 1075 let ResourceCycles = [1]; 1076} 1077def: InstRW<[SKLWriteResGroup85], (instregex "LD_F(32|64|80)m")>; 1078def: InstRW<[SKLWriteResGroup85], (instrs VBROADCASTF128, 1079 VBROADCASTI128, 1080 VBROADCASTSDYrm, 1081 VBROADCASTSSYrm, 1082 VMOVDDUPYrm, 1083 VMOVSHDUPYrm, 1084 VMOVSLDUPYrm, 1085 VPBROADCASTDYrm, 1086 VPBROADCASTQYrm)>; 1087 1088def SKLWriteResGroup86 : SchedWriteRes<[SKLPort0,SKLPort5]> { 1089 let Latency = 7; 1090 let NumMicroOps = 2; 1091 let ResourceCycles = [1,1]; 1092} 1093def: InstRW<[SKLWriteResGroup86], (instrs VCVTDQ2PDYrr)>; 1094 1095def SKLWriteResGroup88 : SchedWriteRes<[SKLPort5,SKLPort23]> { 1096 let Latency = 6; 1097 let NumMicroOps = 2; 1098 let ResourceCycles = [1,1]; 1099} 1100def: InstRW<[SKLWriteResGroup88], (instregex "(V?)PMOV(SX|ZX)BDrm", 1101 "(V?)PMOV(SX|ZX)BQrm", 1102 "(V?)PMOV(SX|ZX)BWrm", 1103 "(V?)PMOV(SX|ZX)DQrm", 1104 "(V?)PMOV(SX|ZX)WDrm", 1105 "(V?)PMOV(SX|ZX)WQrm")>; 1106 1107def SKLWriteResGroup89 : SchedWriteRes<[SKLPort5,SKLPort01]> { 1108 let Latency = 7; 1109 let NumMicroOps = 2; 1110 let ResourceCycles = [1,1]; 1111} 1112def: InstRW<[SKLWriteResGroup89], (instrs VCVTPD2PSYrr, 1113 VCVTPS2PDYrr, 1114 VCVTPD2DQYrr, 1115 VCVTTPD2DQYrr)>; 1116 1117def SKLWriteResGroup91 : SchedWriteRes<[SKLPort23,SKLPort015]> { 1118 let Latency = 7; 1119 let NumMicroOps = 2; 1120 let ResourceCycles = [1,1]; 1121} 1122def: InstRW<[SKLWriteResGroup91], (instrs VINSERTF128rm, 1123 VINSERTI128rm, 1124 VPBLENDDrmi)>; 1125def: InstRW<[SKLWriteResGroup91, ReadAfterVecXLd], 1126 (instregex "(V?)PADD(B|D|Q|W)rm", 1127 "(V?)PSUB(B|D|Q|W)rm")>; 1128 1129def SKLWriteResGroup92 : SchedWriteRes<[SKLPort5,SKLPort23]> { 1130 let Latency = 7; 1131 let NumMicroOps = 3; 1132 let ResourceCycles = [2,1]; 1133} 1134def: InstRW<[SKLWriteResGroup92], (instrs MMX_PACKSSDWirm, 1135 MMX_PACKSSWBirm, 1136 MMX_PACKUSWBirm)>; 1137 1138def SKLWriteResGroup94 : SchedWriteRes<[SKLPort23,SKLPort0156]> { 1139 let Latency = 7; 1140 let NumMicroOps = 3; 1141 let ResourceCycles = [1,2]; 1142} 1143def: InstRW<[SKLWriteResGroup94], (instrs LEAVE, LEAVE64, 1144 SCASB, SCASL, SCASQ, SCASW)>; 1145 1146def SKLWriteResGroup95 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort01]> { 1147 let Latency = 7; 1148 let NumMicroOps = 3; 1149 let ResourceCycles = [1,1,1]; 1150} 1151def: InstRW<[SKLWriteResGroup95], (instregex "(V?)CVTTSS2SI(64)?rr")>; 1152 1153def SKLWriteResGroup96 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort05]> { 1154 let Latency = 7; 1155 let NumMicroOps = 3; 1156 let ResourceCycles = [1,1,1]; 1157} 1158def: InstRW<[SKLWriteResGroup96], (instrs FLDCW16m)>; 1159 1160def SKLWriteResGroup98 : SchedWriteRes<[SKLPort6,SKLPort23,SKLPort0156]> { 1161 let Latency = 7; 1162 let NumMicroOps = 3; 1163 let ResourceCycles = [1,1,1]; 1164} 1165def: InstRW<[SKLWriteResGroup98], (instrs LRETQ, RETQ)>; 1166 1167def SKLWriteResGroup100 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> { 1168 let Latency = 7; 1169 let NumMicroOps = 5; 1170 let ResourceCycles = [1,1,1,2]; 1171} 1172def: InstRW<[SKLWriteResGroup100], (instregex "ROL(8|16|32|64)m(1|i)", 1173 "ROR(8|16|32|64)m(1|i)")>; 1174 1175def SKLWriteResGroup100_1 : SchedWriteRes<[SKLPort06]> { 1176 let Latency = 2; 1177 let NumMicroOps = 2; 1178 let ResourceCycles = [2]; 1179} 1180def: InstRW<[SKLWriteResGroup100_1], (instrs ROL8r1, ROL16r1, ROL32r1, ROL64r1, 1181 ROR8r1, ROR16r1, ROR32r1, ROR64r1)>; 1182 1183def SKLWriteResGroup101 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort0156]> { 1184 let Latency = 7; 1185 let NumMicroOps = 5; 1186 let ResourceCycles = [1,1,1,2]; 1187} 1188def: InstRW<[SKLWriteResGroup101], (instregex "XADD(8|16|32|64)rm")>; 1189 1190def SKLWriteResGroup102 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> { 1191 let Latency = 7; 1192 let NumMicroOps = 5; 1193 let ResourceCycles = [1,1,1,1,1]; 1194} 1195def: InstRW<[SKLWriteResGroup102], (instregex "CALL(16|32|64)m")>; 1196def: InstRW<[SKLWriteResGroup102], (instrs FARCALL64)>; 1197 1198def SKLWriteResGroup103 : SchedWriteRes<[SKLPort6,SKLPort06,SKLPort15,SKLPort0156]> { 1199 let Latency = 7; 1200 let NumMicroOps = 7; 1201 let ResourceCycles = [1,3,1,2]; 1202} 1203def: InstRW<[SKLWriteResGroup103], (instrs LOOP)>; 1204 1205def SKLWriteResGroup107 : SchedWriteRes<[SKLPort1,SKLPort23]> { 1206 let Latency = 8; 1207 let NumMicroOps = 2; 1208 let ResourceCycles = [1,1]; 1209} 1210def: InstRW<[SKLWriteResGroup107], (instregex "PDEP(32|64)rm", 1211 "PEXT(32|64)rm")>; 1212 1213def SKLWriteResGroup108 : SchedWriteRes<[SKLPort5,SKLPort23]> { 1214 let Latency = 8; 1215 let NumMicroOps = 2; 1216 let ResourceCycles = [1,1]; 1217} 1218def: InstRW<[SKLWriteResGroup108], (instregex "FCOM(P?)(32|64)m")>; 1219def: InstRW<[SKLWriteResGroup108], (instrs VPBROADCASTBYrm, 1220 VPBROADCASTWYrm, 1221 VPMOVSXBDYrm, 1222 VPMOVSXBQYrm, 1223 VPMOVSXWQYrm)>; 1224 1225def SKLWriteResGroup110 : SchedWriteRes<[SKLPort23,SKLPort015]> { 1226 let Latency = 8; 1227 let NumMicroOps = 2; 1228 let ResourceCycles = [1,1]; 1229} 1230def: InstRW<[SKLWriteResGroup110], (instrs VPBLENDDYrmi)>; 1231def: InstRW<[SKLWriteResGroup110, ReadAfterVecYLd], 1232 (instregex "VPADD(B|D|Q|W)Yrm", 1233 "VPSUB(B|D|Q|W)Yrm")>; 1234 1235def SKLWriteResGroup112 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> { 1236 let Latency = 8; 1237 let NumMicroOps = 4; 1238 let ResourceCycles = [1,2,1]; 1239} 1240def: InstRW<[SKLWriteResGroup112], (instregex "MMX_PH(ADD|SUB)SWrm")>; 1241 1242def SKLWriteResGroup116 : SchedWriteRes<[SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> { 1243 let Latency = 8; 1244 let NumMicroOps = 5; 1245 let ResourceCycles = [1,1,1,2]; 1246} 1247def: InstRW<[SKLWriteResGroup116], (instregex "RCL(8|16|32|64)m(1|i)", 1248 "RCR(8|16|32|64)m(1|i)")>; 1249 1250def SKLWriteResGroup117 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> { 1251 let Latency = 8; 1252 let NumMicroOps = 6; 1253 let ResourceCycles = [1,1,1,3]; 1254} 1255def: InstRW<[SKLWriteResGroup117], (instregex "ROL(8|16|32|64)mCL", 1256 "ROR(8|16|32|64)mCL", 1257 "SAR(8|16|32|64)mCL", 1258 "SHL(8|16|32|64)mCL", 1259 "SHR(8|16|32|64)mCL")>; 1260 1261def SKLWriteResGroup119 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> { 1262 let Latency = 8; 1263 let NumMicroOps = 6; 1264 let ResourceCycles = [1,1,1,2,1]; 1265} 1266def: SchedAlias<WriteADCRMW, SKLWriteResGroup119>; 1267 1268def SKLWriteResGroup120 : SchedWriteRes<[SKLPort0,SKLPort23]> { 1269 let Latency = 9; 1270 let NumMicroOps = 2; 1271 let ResourceCycles = [1,1]; 1272} 1273def: InstRW<[SKLWriteResGroup120], (instrs MMX_CVTPI2PSirm)>; 1274 1275def SKLWriteResGroup121 : SchedWriteRes<[SKLPort5,SKLPort23]> { 1276 let Latency = 9; 1277 let NumMicroOps = 2; 1278 let ResourceCycles = [1,1]; 1279} 1280def: InstRW<[SKLWriteResGroup121], (instrs PCMPGTQrm, 1281 VPCMPGTQrm, 1282 VPMOVSXBWYrm, 1283 VPMOVSXDQYrm, 1284 VPMOVSXWDYrm, 1285 VPMOVZXWDYrm)>; 1286 1287def SKLWriteResGroup123 : SchedWriteRes<[SKLPort23,SKLPort01]> { 1288 let Latency = 9; 1289 let NumMicroOps = 2; 1290 let ResourceCycles = [1,1]; 1291} 1292def: InstRW<[SKLWriteResGroup123], (instregex "MMX_CVT(T?)PS2PIirm", 1293 "(V?)CVTPS2PDrm")>; 1294 1295def SKLWriteResGroup128 : SchedWriteRes<[SKLPort5,SKLPort01,SKLPort23]> { 1296 let Latency = 9; 1297 let NumMicroOps = 4; 1298 let ResourceCycles = [2,1,1]; 1299} 1300def: InstRW<[SKLWriteResGroup128], (instregex "(V?)PHADDSWrm", 1301 "(V?)PHSUBSWrm")>; 1302 1303def SKLWriteResGroup131 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort23,SKLPort0156]> { 1304 let Latency = 9; 1305 let NumMicroOps = 5; 1306 let ResourceCycles = [1,2,1,1]; 1307} 1308def: InstRW<[SKLWriteResGroup131], (instregex "LAR(16|32|64)rm", 1309 "LSL(16|32|64)rm")>; 1310 1311def SKLWriteResGroup133 : SchedWriteRes<[SKLPort5,SKLPort23]> { 1312 let Latency = 10; 1313 let NumMicroOps = 2; 1314 let ResourceCycles = [1,1]; 1315} 1316def: InstRW<[SKLWriteResGroup133], (instregex "(ADD|SUB|SUBR)_F(32|64)m", 1317 "ILD_F(16|32|64)m")>; 1318def: InstRW<[SKLWriteResGroup133], (instrs VPCMPGTQYrm)>; 1319 1320def SKLWriteResGroup134 : SchedWriteRes<[SKLPort01,SKLPort23]> { 1321 let Latency = 10; 1322 let NumMicroOps = 2; 1323 let ResourceCycles = [1,1]; 1324} 1325def: InstRW<[SKLWriteResGroup134], (instregex "(V?)CVTDQ2PSrm", 1326 "(V?)CVTPS2DQrm", 1327 "(V?)CVTSS2SDrm", 1328 "(V?)CVTTPS2DQrm")>; 1329 1330def SKLWriteResGroup138 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> { 1331 let Latency = 10; 1332 let NumMicroOps = 3; 1333 let ResourceCycles = [1,1,1]; 1334} 1335def: InstRW<[SKLWriteResGroup138], (instrs MMX_CVTPI2PDirm)>; 1336 1337def SKLWriteResGroup139 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort01]> { 1338 let Latency = 10; 1339 let NumMicroOps = 3; 1340 let ResourceCycles = [1,1,1]; 1341} 1342def: InstRW<[SKLWriteResGroup139], (instregex "(V?)CVTSD2SSrm")>; 1343 1344def SKLWriteResGroup140 : SchedWriteRes<[SKLPort5,SKLPort01,SKLPort23]> { 1345 let Latency = 10; 1346 let NumMicroOps = 4; 1347 let ResourceCycles = [2,1,1]; 1348} 1349def: InstRW<[SKLWriteResGroup140], (instrs VPHADDSWYrm, 1350 VPHSUBSWYrm)>; 1351 1352def SKLWriteResGroup143 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> { 1353 let Latency = 10; 1354 let NumMicroOps = 8; 1355 let ResourceCycles = [1,1,1,1,1,3]; 1356} 1357def: InstRW<[SKLWriteResGroup143], (instregex "XCHG(8|16|32|64)rm")>; 1358 1359def SKLWriteResGroup145 : SchedWriteRes<[SKLPort0,SKLFPDivider]> { 1360 let Latency = 11; 1361 let NumMicroOps = 1; 1362 let ResourceCycles = [1,3]; 1363} 1364def : SchedAlias<WriteFDivX, SKLWriteResGroup145>; // TODO - convert to ZnWriteResFpuPair 1365 1366def SKLWriteResGroup146 : SchedWriteRes<[SKLPort0,SKLPort23]> { 1367 let Latency = 11; 1368 let NumMicroOps = 2; 1369 let ResourceCycles = [1,1]; 1370} 1371def: InstRW<[SKLWriteResGroup146], (instregex "MUL_F(32|64)m")>; 1372 1373def SKLWriteResGroup147 : SchedWriteRes<[SKLPort01,SKLPort23]> { 1374 let Latency = 11; 1375 let NumMicroOps = 2; 1376 let ResourceCycles = [1,1]; 1377} 1378def: InstRW<[SKLWriteResGroup147], (instrs VCVTDQ2PSYrm, 1379 VCVTPS2PDYrm, 1380 VCVTPS2DQYrm, 1381 VCVTTPS2DQYrm)>; 1382 1383def SKLWriteResGroup149 : SchedWriteRes<[SKLPort5,SKLPort23]> { 1384 let Latency = 11; 1385 let NumMicroOps = 3; 1386 let ResourceCycles = [2,1]; 1387} 1388def: InstRW<[SKLWriteResGroup149], (instregex "FICOM(P?)(16|32)m")>; 1389 1390def SKLWriteResGroup150 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> { 1391 let Latency = 11; 1392 let NumMicroOps = 3; 1393 let ResourceCycles = [1,1,1]; 1394} 1395def: InstRW<[SKLWriteResGroup150], (instregex "(V?)CVTDQ2PDrm")>; 1396 1397def SKLWriteResGroup151 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort01]> { 1398 let Latency = 11; 1399 let NumMicroOps = 3; 1400 let ResourceCycles = [1,1,1]; 1401} 1402def: InstRW<[SKLWriteResGroup151], (instregex "(V?)CVTSS2SI64rm", 1403 "(V?)CVT(T?)SD2SI(64)?rm", 1404 "VCVTTSS2SI64rm", 1405 "(V?)CVT(T?)SS2SIrm")>; 1406 1407def SKLWriteResGroup152 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort01]> { 1408 let Latency = 11; 1409 let NumMicroOps = 3; 1410 let ResourceCycles = [1,1,1]; 1411} 1412def: InstRW<[SKLWriteResGroup152], (instrs CVTPD2PSrm, 1413 CVTPD2DQrm, 1414 CVTTPD2DQrm, 1415 MMX_CVTPD2PIirm, 1416 MMX_CVTTPD2PIirm)>; 1417 1418def SKLWriteResGroup154 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort0156]> { 1419 let Latency = 11; 1420 let NumMicroOps = 7; 1421 let ResourceCycles = [2,3,2]; 1422} 1423def: InstRW<[SKLWriteResGroup154], (instregex "RCL(16|32|64)rCL", 1424 "RCR(16|32|64)rCL")>; 1425 1426def SKLWriteResGroup155 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort15,SKLPort0156]> { 1427 let Latency = 11; 1428 let NumMicroOps = 9; 1429 let ResourceCycles = [1,5,1,2]; 1430} 1431def: InstRW<[SKLWriteResGroup155], (instrs RCL8rCL)>; 1432 1433def SKLWriteResGroup156 : SchedWriteRes<[SKLPort06,SKLPort0156]> { 1434 let Latency = 11; 1435 let NumMicroOps = 11; 1436 let ResourceCycles = [2,9]; 1437} 1438def: InstRW<[SKLWriteResGroup156], (instrs LOOPE, LOOPNE)>; 1439 1440def SKLWriteResGroup160 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23,SKLPort01]> { 1441 let Latency = 12; 1442 let NumMicroOps = 4; 1443 let ResourceCycles = [1,1,1,1]; 1444} 1445def: InstRW<[SKLWriteResGroup160], (instregex "CVTTSS2SI64rm")>; 1446 1447def SKLWriteResGroup162 : SchedWriteRes<[SKLPort5,SKLPort23]> { 1448 let Latency = 13; 1449 let NumMicroOps = 3; 1450 let ResourceCycles = [2,1]; 1451} 1452def: InstRW<[SKLWriteResGroup162], (instregex "(ADD|SUB|SUBR)_FI(16|32)m")>; 1453 1454def SKLWriteResGroup163 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> { 1455 let Latency = 13; 1456 let NumMicroOps = 3; 1457 let ResourceCycles = [1,1,1]; 1458} 1459def: InstRW<[SKLWriteResGroup163], (instrs VCVTDQ2PDYrm)>; 1460 1461def SKLWriteResGroup166 : SchedWriteRes<[SKLPort0,SKLFPDivider]> { 1462 let Latency = 14; 1463 let NumMicroOps = 1; 1464 let ResourceCycles = [1,3]; 1465} 1466def : SchedAlias<WriteFDiv64, SKLWriteResGroup166>; // TODO - convert to ZnWriteResFpuPair 1467def : SchedAlias<WriteFDiv64X, SKLWriteResGroup166>; // TODO - convert to ZnWriteResFpuPair 1468 1469def SKLWriteResGroup166_1 : SchedWriteRes<[SKLPort0,SKLFPDivider]> { 1470 let Latency = 14; 1471 let NumMicroOps = 1; 1472 let ResourceCycles = [1,5]; 1473} 1474def : SchedAlias<WriteFDiv64Y, SKLWriteResGroup166_1>; // TODO - convert to ZnWriteResFpuPair 1475 1476def SKLWriteResGroup169 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> { 1477 let Latency = 14; 1478 let NumMicroOps = 3; 1479 let ResourceCycles = [1,1,1]; 1480} 1481def: InstRW<[SKLWriteResGroup169], (instregex "MUL_FI(16|32)m")>; 1482 1483def SKLWriteResGroup170 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort15,SKLPort0156]> { 1484 let Latency = 14; 1485 let NumMicroOps = 10; 1486 let ResourceCycles = [2,4,1,3]; 1487} 1488def: InstRW<[SKLWriteResGroup170], (instrs RCR8rCL)>; 1489 1490def SKLWriteResGroup171 : SchedWriteRes<[SKLPort0]> { 1491 let Latency = 15; 1492 let NumMicroOps = 1; 1493 let ResourceCycles = [1]; 1494} 1495def: InstRW<[SKLWriteResGroup171], (instregex "DIVR_(FPrST0|FST0r|FrST0)")>; 1496 1497def SKLWriteResGroup174 : SchedWriteRes<[SKLPort1,SKLPort23,SKLPort237,SKLPort06,SKLPort15,SKLPort0156]> { 1498 let Latency = 15; 1499 let NumMicroOps = 10; 1500 let ResourceCycles = [1,1,1,5,1,1]; 1501} 1502def: InstRW<[SKLWriteResGroup174], (instregex "RCL(8|16|32|64)mCL")>; 1503 1504def SKLWriteResGroup177 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06,SKLPort15,SKLPort0156]> { 1505 let Latency = 16; 1506 let NumMicroOps = 14; 1507 let ResourceCycles = [1,1,1,4,2,5]; 1508} 1509def: InstRW<[SKLWriteResGroup177], (instrs CMPXCHG8B)>; 1510 1511def SKLWriteResGroup178 : SchedWriteRes<[SKLPort0156]> { 1512 let Latency = 16; 1513 let NumMicroOps = 16; 1514 let ResourceCycles = [16]; 1515} 1516def: InstRW<[SKLWriteResGroup178], (instrs VZEROALL)>; 1517 1518def SKLWriteResGroup179 : SchedWriteRes<[SKLPort0,SKLPort23,SKLFPDivider]> { 1519 let Latency = 17; 1520 let NumMicroOps = 2; 1521 let ResourceCycles = [1,1,5]; 1522} 1523def : SchedAlias<WriteFDivXLd, SKLWriteResGroup179>; // TODO - convert to ZnWriteResFpuPair 1524 1525def SKLWriteResGroup180 : SchedWriteRes<[SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort05,SKLPort0156]> { 1526 let Latency = 17; 1527 let NumMicroOps = 15; 1528 let ResourceCycles = [2,1,2,4,2,4]; 1529} 1530def: InstRW<[SKLWriteResGroup180], (instrs XCH_F)>; 1531 1532def SKLWriteResGroup184 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort06,SKLPort0156]> { 1533 let Latency = 18; 1534 let NumMicroOps = 8; 1535 let ResourceCycles = [1,1,1,5]; 1536} 1537def: InstRW<[SKLWriteResGroup184], (instrs CPUID, RDTSC)>; 1538 1539def SKLWriteResGroup185 : SchedWriteRes<[SKLPort1,SKLPort23,SKLPort237,SKLPort06,SKLPort15,SKLPort0156]> { 1540 let Latency = 18; 1541 let NumMicroOps = 11; 1542 let ResourceCycles = [2,1,1,4,1,2]; 1543} 1544def: InstRW<[SKLWriteResGroup185], (instregex "RCR(8|16|32|64)mCL")>; 1545 1546def SKLWriteResGroup186 : SchedWriteRes<[SKLPort0,SKLPort23,SKLFPDivider]> { 1547 let Latency = 19; 1548 let NumMicroOps = 2; 1549 let ResourceCycles = [1,1,4]; 1550} 1551def : SchedAlias<WriteFDiv64Ld, SKLWriteResGroup186>; // TODO - convert to ZnWriteResFpuPair 1552 1553def SKLWriteResGroup189 : SchedWriteRes<[SKLPort0]> { 1554 let Latency = 20; 1555 let NumMicroOps = 1; 1556 let ResourceCycles = [1]; 1557} 1558def: InstRW<[SKLWriteResGroup189], (instregex "DIV_(FPrST0|FST0r|FrST0)")>; 1559 1560def SKLWriteResGroup190 : SchedWriteRes<[SKLPort0,SKLPort23,SKLFPDivider]> { 1561 let Latency = 20; 1562 let NumMicroOps = 2; 1563 let ResourceCycles = [1,1,4]; 1564} 1565def : SchedAlias<WriteFDiv64XLd, SKLWriteResGroup190>; // TODO - convert to ZnWriteResFpuPair 1566 1567def SKLWriteResGroup192 : SchedWriteRes<[SKLPort4,SKLPort5,SKLPort6,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> { 1568 let Latency = 20; 1569 let NumMicroOps = 8; 1570 let ResourceCycles = [1,1,1,1,1,1,2]; 1571} 1572def: InstRW<[SKLWriteResGroup192], (instrs INSB, INSL, INSW)>; 1573 1574def SKLWriteResGroup193 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort0156]> { 1575 let Latency = 20; 1576 let NumMicroOps = 10; 1577 let ResourceCycles = [1,2,7]; 1578} 1579def: InstRW<[SKLWriteResGroup193], (instrs MWAITrr)>; 1580 1581def SKLWriteResGroup195 : SchedWriteRes<[SKLPort0,SKLPort23,SKLFPDivider]> { 1582 let Latency = 21; 1583 let NumMicroOps = 2; 1584 let ResourceCycles = [1,1,8]; 1585} 1586def : SchedAlias<WriteFDiv64YLd, SKLWriteResGroup195>; // TODO - convert to ZnWriteResFpuPair 1587 1588def SKLWriteResGroup196 : SchedWriteRes<[SKLPort0,SKLPort23]> { 1589 let Latency = 22; 1590 let NumMicroOps = 2; 1591 let ResourceCycles = [1,1]; 1592} 1593def: InstRW<[SKLWriteResGroup196], (instregex "DIV_F(32|64)m")>; 1594 1595def SKLWriteResGroup196_1 : SchedWriteRes<[SKLPort0, SKLPort23, SKLPort5, SKLPort015]> { 1596 let Latency = 22; 1597 let NumMicroOps = 5; 1598 let ResourceCycles = [1,2,1,1]; 1599} 1600def: InstRW<[SKLWriteResGroup196_1], (instrs VGATHERDPSrm, 1601 VGATHERDPDrm, 1602 VGATHERQPDrm, 1603 VGATHERQPSrm, 1604 VPGATHERDDrm, 1605 VPGATHERDQrm, 1606 VPGATHERQDrm, 1607 VPGATHERQQrm)>; 1608 1609def SKLWriteResGroup196_2 : SchedWriteRes<[SKLPort0, SKLPort23, SKLPort5, SKLPort015]> { 1610 let Latency = 25; 1611 let NumMicroOps = 5; 1612 let ResourceCycles = [1,2,1,1]; 1613} 1614def: InstRW<[SKLWriteResGroup196_2], (instrs VGATHERDPSYrm, 1615 VGATHERQPDYrm, 1616 VGATHERQPSYrm, 1617 VPGATHERDDYrm, 1618 VPGATHERDQYrm, 1619 VPGATHERQDYrm, 1620 VPGATHERQQYrm, 1621 VGATHERDPDYrm)>; 1622 1623def SKLWriteResGroup198 : SchedWriteRes<[SKLPort0,SKLPort4,SKLPort5,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> { 1624 let Latency = 23; 1625 let NumMicroOps = 19; 1626 let ResourceCycles = [2,1,4,1,1,4,6]; 1627} 1628def: InstRW<[SKLWriteResGroup198], (instrs CMPXCHG16B)>; 1629 1630def SKLWriteResGroup202 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> { 1631 let Latency = 25; 1632 let NumMicroOps = 3; 1633 let ResourceCycles = [1,1,1]; 1634} 1635def: InstRW<[SKLWriteResGroup202], (instregex "DIV_FI(16|32)m")>; 1636 1637def SKLWriteResGroup206 : SchedWriteRes<[SKLPort0,SKLPort23]> { 1638 let Latency = 27; 1639 let NumMicroOps = 2; 1640 let ResourceCycles = [1,1]; 1641} 1642def: InstRW<[SKLWriteResGroup206], (instregex "DIVR_F(32|64)m")>; 1643 1644def SKLWriteResGroup208 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> { 1645 let Latency = 30; 1646 let NumMicroOps = 3; 1647 let ResourceCycles = [1,1,1]; 1648} 1649def: InstRW<[SKLWriteResGroup208], (instregex "DIVR_FI(16|32)m")>; 1650 1651def SKLWriteResGroup209 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort23,SKLPort06,SKLPort0156]> { 1652 let Latency = 35; 1653 let NumMicroOps = 23; 1654 let ResourceCycles = [1,5,3,4,10]; 1655} 1656def: InstRW<[SKLWriteResGroup209], (instregex "IN(8|16|32)ri", 1657 "IN(8|16|32)rr")>; 1658 1659def SKLWriteResGroup210 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> { 1660 let Latency = 35; 1661 let NumMicroOps = 23; 1662 let ResourceCycles = [1,5,2,1,4,10]; 1663} 1664def: InstRW<[SKLWriteResGroup210], (instregex "OUT(8|16|32)ir", 1665 "OUT(8|16|32)rr")>; 1666 1667def SKLWriteResGroup211 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort23,SKLPort0156]> { 1668 let Latency = 37; 1669 let NumMicroOps = 31; 1670 let ResourceCycles = [1,8,1,21]; 1671} 1672def: InstRW<[SKLWriteResGroup211], (instregex "XRSTOR(64)?")>; 1673 1674def SKLWriteResGroup212 : SchedWriteRes<[SKLPort1,SKLPort4,SKLPort5,SKLPort6,SKLPort23,SKLPort237,SKLPort15,SKLPort0156]> { 1675 let Latency = 40; 1676 let NumMicroOps = 18; 1677 let ResourceCycles = [1,1,2,3,1,1,1,8]; 1678} 1679def: InstRW<[SKLWriteResGroup212], (instrs VMCLEARm)>; 1680 1681def SKLWriteResGroup213 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> { 1682 let Latency = 41; 1683 let NumMicroOps = 39; 1684 let ResourceCycles = [1,10,1,1,26]; 1685} 1686def: InstRW<[SKLWriteResGroup213], (instrs XSAVE64)>; 1687 1688def SKLWriteResGroup214 : SchedWriteRes<[SKLPort5,SKLPort0156]> { 1689 let Latency = 42; 1690 let NumMicroOps = 22; 1691 let ResourceCycles = [2,20]; 1692} 1693def: InstRW<[SKLWriteResGroup214], (instrs RDTSCP)>; 1694 1695def SKLWriteResGroup215 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> { 1696 let Latency = 42; 1697 let NumMicroOps = 40; 1698 let ResourceCycles = [1,11,1,1,26]; 1699} 1700def: InstRW<[SKLWriteResGroup215], (instrs XSAVE)>; 1701def: InstRW<[SKLWriteResGroup215], (instregex "XSAVEC", "XSAVES")>; 1702 1703def SKLWriteResGroup216 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> { 1704 let Latency = 46; 1705 let NumMicroOps = 44; 1706 let ResourceCycles = [1,11,1,1,30]; 1707} 1708def: InstRW<[SKLWriteResGroup216], (instregex "XSAVEOPT")>; 1709 1710def SKLWriteResGroup217 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort05,SKLPort06,SKLPort0156]> { 1711 let Latency = 62; 1712 let NumMicroOps = 64; 1713 let ResourceCycles = [2,8,5,10,39]; 1714} 1715def: InstRW<[SKLWriteResGroup217], (instrs FLDENVm)>; 1716 1717def SKLWriteResGroup218 : SchedWriteRes<[SKLPort0,SKLPort6,SKLPort23,SKLPort05,SKLPort06,SKLPort15,SKLPort0156]> { 1718 let Latency = 63; 1719 let NumMicroOps = 88; 1720 let ResourceCycles = [4,4,31,1,2,1,45]; 1721} 1722def: InstRW<[SKLWriteResGroup218], (instrs FXRSTOR64)>; 1723 1724def SKLWriteResGroup219 : SchedWriteRes<[SKLPort0,SKLPort6,SKLPort23,SKLPort05,SKLPort06,SKLPort15,SKLPort0156]> { 1725 let Latency = 63; 1726 let NumMicroOps = 90; 1727 let ResourceCycles = [4,2,33,1,2,1,47]; 1728} 1729def: InstRW<[SKLWriteResGroup219], (instrs FXRSTOR)>; 1730 1731def SKLWriteResGroup220 : SchedWriteRes<[SKLPort5,SKLPort05,SKLPort0156]> { 1732 let Latency = 75; 1733 let NumMicroOps = 15; 1734 let ResourceCycles = [6,3,6]; 1735} 1736def: InstRW<[SKLWriteResGroup220], (instrs FNINIT)>; 1737 1738def SKLWriteResGroup223 : SchedWriteRes<[SKLPort0,SKLPort1,SKLPort4,SKLPort5,SKLPort6,SKLPort237,SKLPort06,SKLPort0156]> { 1739 let Latency = 106; 1740 let NumMicroOps = 100; 1741 let ResourceCycles = [9,1,11,16,1,11,21,30]; 1742} 1743def: InstRW<[SKLWriteResGroup223], (instrs FSTENVm)>; 1744 1745def: InstRW<[WriteZero], (instrs CLC)>; 1746 1747 1748// Intruction variants handled by the renamer. These might not need execution 1749// ports in certain conditions. 1750// See Agner's Fog "The microarchitecture of Intel, AMD and VIA CPUs", 1751// section "Skylake Pipeline" > "Register allocation and renaming". 1752// These can be investigated with llvm-exegesis, e.g. 1753// echo 'pxor %mm0, %mm0' | /tmp/llvm-exegesis -mode=uops -snippets-file=- 1754// echo 'vxorpd %xmm0, %xmm0, %xmm1' | /tmp/llvm-exegesis -mode=uops -snippets-file=- 1755 1756def SKLWriteZeroLatency : SchedWriteRes<[]> { 1757 let Latency = 0; 1758} 1759 1760def SKLWriteZeroIdiom : SchedWriteVariant<[ 1761 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>, 1762 SchedVar<NoSchedPred, [WriteALU]> 1763]>; 1764def : InstRW<[SKLWriteZeroIdiom], (instrs SUB32rr, SUB64rr, 1765 XOR32rr, XOR64rr)>; 1766 1767def SKLWriteFZeroIdiom : SchedWriteVariant<[ 1768 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>, 1769 SchedVar<NoSchedPred, [WriteFLogic]> 1770]>; 1771def : InstRW<[SKLWriteFZeroIdiom], (instrs XORPSrr, VXORPSrr, XORPDrr, 1772 VXORPDrr)>; 1773 1774def SKLWriteFZeroIdiomY : SchedWriteVariant<[ 1775 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>, 1776 SchedVar<NoSchedPred, [WriteFLogicY]> 1777]>; 1778def : InstRW<[SKLWriteFZeroIdiomY], (instrs VXORPSYrr, VXORPDYrr)>; 1779 1780def SKLWriteVZeroIdiomLogicX : SchedWriteVariant<[ 1781 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>, 1782 SchedVar<NoSchedPred, [WriteVecLogicX]> 1783]>; 1784def : InstRW<[SKLWriteVZeroIdiomLogicX], (instrs PXORrr, VPXORrr)>; 1785 1786def SKLWriteVZeroIdiomLogicY : SchedWriteVariant<[ 1787 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>, 1788 SchedVar<NoSchedPred, [WriteVecLogicY]> 1789]>; 1790def : InstRW<[SKLWriteVZeroIdiomLogicY], (instrs VPXORYrr)>; 1791 1792def SKLWriteVZeroIdiomALUX : SchedWriteVariant<[ 1793 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>, 1794 SchedVar<NoSchedPred, [WriteVecALUX]> 1795]>; 1796def : InstRW<[SKLWriteVZeroIdiomALUX], (instrs PCMPGTBrr, VPCMPGTBrr, 1797 PCMPGTDrr, VPCMPGTDrr, 1798 PCMPGTWrr, VPCMPGTWrr)>; 1799 1800def SKLWriteVZeroIdiomALUY : SchedWriteVariant<[ 1801 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>, 1802 SchedVar<NoSchedPred, [WriteVecALUY]> 1803]>; 1804def : InstRW<[SKLWriteVZeroIdiomALUY], (instrs VPCMPGTBYrr, 1805 VPCMPGTDYrr, 1806 VPCMPGTWYrr)>; 1807 1808def SKLWritePSUB : SchedWriteRes<[SKLPort015]> { 1809 let Latency = 1; 1810 let NumMicroOps = 1; 1811 let ResourceCycles = [1]; 1812} 1813 1814def SKLWriteVZeroIdiomPSUB : SchedWriteVariant<[ 1815 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>, 1816 SchedVar<NoSchedPred, [SKLWritePSUB]> 1817]>; 1818def : InstRW<[SKLWriteVZeroIdiomPSUB], (instrs PSUBBrr, VPSUBBrr, 1819 PSUBDrr, VPSUBDrr, 1820 PSUBQrr, VPSUBQrr, 1821 PSUBWrr, VPSUBWrr, 1822 VPSUBBYrr, 1823 VPSUBDYrr, 1824 VPSUBQYrr, 1825 VPSUBWYrr)>; 1826 1827def SKLWritePCMPGTQ : SchedWriteRes<[SKLPort5]> { 1828 let Latency = 3; 1829 let NumMicroOps = 1; 1830 let ResourceCycles = [1]; 1831} 1832 1833def SKLWriteVZeroIdiomPCMPGTQ : SchedWriteVariant<[ 1834 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>, 1835 SchedVar<NoSchedPred, [SKLWritePCMPGTQ]> 1836]>; 1837def : InstRW<[SKLWriteVZeroIdiomPCMPGTQ], (instrs PCMPGTQrr, VPCMPGTQrr, 1838 VPCMPGTQYrr)>; 1839 1840 1841// CMOVs that use both Z and C flag require an extra uop. 1842def SKLWriteCMOVA_CMOVBErr : SchedWriteRes<[SKLPort06]> { 1843 let Latency = 2; 1844 let ResourceCycles = [2]; 1845 let NumMicroOps = 2; 1846} 1847 1848def SKLWriteCMOVA_CMOVBErm : SchedWriteRes<[SKLPort23,SKLPort06]> { 1849 let Latency = 7; 1850 let ResourceCycles = [1,2]; 1851 let NumMicroOps = 3; 1852} 1853 1854def SKLCMOVA_CMOVBErr : SchedWriteVariant<[ 1855 SchedVar<MCSchedPredicate<IsCMOVArr_Or_CMOVBErr>, [SKLWriteCMOVA_CMOVBErr]>, 1856 SchedVar<NoSchedPred, [WriteCMOV]> 1857]>; 1858 1859def SKLCMOVA_CMOVBErm : SchedWriteVariant<[ 1860 SchedVar<MCSchedPredicate<IsCMOVArm_Or_CMOVBErm>, [SKLWriteCMOVA_CMOVBErm]>, 1861 SchedVar<NoSchedPred, [WriteCMOV.Folded]> 1862]>; 1863 1864def : InstRW<[SKLCMOVA_CMOVBErr], (instrs CMOV16rr, CMOV32rr, CMOV64rr)>; 1865def : InstRW<[SKLCMOVA_CMOVBErm], (instrs CMOV16rm, CMOV32rm, CMOV64rm)>; 1866 1867// SETCCs that use both Z and C flag require an extra uop. 1868def SKLWriteSETA_SETBEr : SchedWriteRes<[SKLPort06]> { 1869 let Latency = 2; 1870 let ResourceCycles = [2]; 1871 let NumMicroOps = 2; 1872} 1873 1874def SKLWriteSETA_SETBEm : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort06]> { 1875 let Latency = 3; 1876 let ResourceCycles = [1,1,2]; 1877 let NumMicroOps = 4; 1878} 1879 1880def SKLSETA_SETBErr : SchedWriteVariant<[ 1881 SchedVar<MCSchedPredicate<IsSETAr_Or_SETBEr>, [SKLWriteSETA_SETBEr]>, 1882 SchedVar<NoSchedPred, [WriteSETCC]> 1883]>; 1884 1885def SKLSETA_SETBErm : SchedWriteVariant<[ 1886 SchedVar<MCSchedPredicate<IsSETAm_Or_SETBEm>, [SKLWriteSETA_SETBEm]>, 1887 SchedVar<NoSchedPred, [WriteSETCCStore]> 1888]>; 1889 1890def : InstRW<[SKLSETA_SETBErr], (instrs SETCCr)>; 1891def : InstRW<[SKLSETA_SETBErm], (instrs SETCCm)>; 1892 1893} // SchedModel 1894