xref: /freebsd/contrib/llvm-project/llvm/lib/Target/X86/X86SchedSkylakeClient.td (revision e32fecd0c2c3ee37c47ee100f169e7eb0282a873) 
1//=- X86SchedSkylake.td - X86 Skylake Client Scheduling ------*- tablegen -*-=//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the machine model for Skylake Client to support
10// instruction scheduling and other instruction cost heuristics.
11//
12//===----------------------------------------------------------------------===//
13
14def SkylakeClientModel : SchedMachineModel {
15  // All x86 instructions are modeled as a single micro-op, and SKylake can
16  // decode 6 instructions per cycle.
17  let IssueWidth = 6;
18  let MicroOpBufferSize = 224; // Based on the reorder buffer.
19  let LoadLatency = 5;
20  let MispredictPenalty = 14;
21
22  // Based on the LSD (loop-stream detector) queue size and benchmarking data.
23  let LoopMicroOpBufferSize = 50;
24
25  // This flag is set to allow the scheduler to assign a default model to
26  // unrecognized opcodes.
27  let CompleteModel = 0;
28}
29
30let SchedModel = SkylakeClientModel in {
31
32// Skylake Client can issue micro-ops to 8 different ports in one cycle.
33
34// Ports 0, 1, 5, and 6 handle all computation.
35// Port 4 gets the data half of stores. Store data can be available later than
36// the store address, but since we don't model the latency of stores, we can
37// ignore that.
38// Ports 2 and 3 are identical. They handle loads and the address half of
39// stores. Port 7 can handle address calculations.
40def SKLPort0 : ProcResource<1>;
41def SKLPort1 : ProcResource<1>;
42def SKLPort2 : ProcResource<1>;
43def SKLPort3 : ProcResource<1>;
44def SKLPort4 : ProcResource<1>;
45def SKLPort5 : ProcResource<1>;
46def SKLPort6 : ProcResource<1>;
47def SKLPort7 : ProcResource<1>;
48
49// Many micro-ops are capable of issuing on multiple ports.
50def SKLPort01  : ProcResGroup<[SKLPort0, SKLPort1]>;
51def SKLPort23  : ProcResGroup<[SKLPort2, SKLPort3]>;
52def SKLPort237 : ProcResGroup<[SKLPort2, SKLPort3, SKLPort7]>;
53def SKLPort04  : ProcResGroup<[SKLPort0, SKLPort4]>;
54def SKLPort05  : ProcResGroup<[SKLPort0, SKLPort5]>;
55def SKLPort06  : ProcResGroup<[SKLPort0, SKLPort6]>;
56def SKLPort15  : ProcResGroup<[SKLPort1, SKLPort5]>;
57def SKLPort16  : ProcResGroup<[SKLPort1, SKLPort6]>;
58def SKLPort56  : ProcResGroup<[SKLPort5, SKLPort6]>;
59def SKLPort015 : ProcResGroup<[SKLPort0, SKLPort1, SKLPort5]>;
60def SKLPort056 : ProcResGroup<[SKLPort0, SKLPort5, SKLPort6]>;
61def SKLPort0156: ProcResGroup<[SKLPort0, SKLPort1, SKLPort5, SKLPort6]>;
62
63def SKLDivider : ProcResource<1>; // Integer division issued on port 0.
64// FP division and sqrt on port 0.
65def SKLFPDivider : ProcResource<1>;
66
67// 60 Entry Unified Scheduler
68def SKLPortAny : ProcResGroup<[SKLPort0, SKLPort1, SKLPort2, SKLPort3, SKLPort4,
69                              SKLPort5, SKLPort6, SKLPort7]> {
70  let BufferSize=60;
71}
72
73// Integer loads are 5 cycles, so ReadAfterLd registers needn't be available until 5
74// cycles after the memory operand.
75def : ReadAdvance<ReadAfterLd, 5>;
76
77// Vector loads are 5/6/7 cycles, so ReadAfterVec*Ld registers needn't be available
78// until 5/6/7 cycles after the memory operand.
79def : ReadAdvance<ReadAfterVecLd, 5>;
80def : ReadAdvance<ReadAfterVecXLd, 6>;
81def : ReadAdvance<ReadAfterVecYLd, 7>;
82
83def : ReadAdvance<ReadInt2Fpu, 0>;
84
85// Many SchedWrites are defined in pairs with and without a folded load.
86// Instructions with folded loads are usually micro-fused, so they only appear
87// as two micro-ops when queued in the reservation station.
88// This multiclass defines the resource usage for variants with and without
89// folded loads.
90multiclass SKLWriteResPair<X86FoldableSchedWrite SchedRW,
91                          list<ProcResourceKind> ExePorts,
92                          int Lat, list<int> Res = [1], int UOps = 1,
93                          int LoadLat = 5> {
94  // Register variant is using a single cycle on ExePort.
95  def : WriteRes<SchedRW, ExePorts> {
96    let Latency = Lat;
97    let ResourceCycles = Res;
98    let NumMicroOps = UOps;
99  }
100
101  // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to
102  // the latency (default = 5).
103  def : WriteRes<SchedRW.Folded, !listconcat([SKLPort23], ExePorts)> {
104    let Latency = !add(Lat, LoadLat);
105    let ResourceCycles = !listconcat([1], Res);
106    let NumMicroOps = !add(UOps, 1);
107  }
108}
109
110// A folded store needs a cycle on port 4 for the store data, and an extra port
111// 2/3/7 cycle to recompute the address.
112def : WriteRes<WriteRMW, [SKLPort237,SKLPort4]>;
113
114// Arithmetic.
115defm : SKLWriteResPair<WriteALU,    [SKLPort0156], 1>; // Simple integer ALU op.
116defm : SKLWriteResPair<WriteADC,    [SKLPort06],   1>; // Integer ALU + flags op.
117
118// Integer multiplication.
119defm : SKLWriteResPair<WriteIMul8,     [SKLPort1],   3>;
120defm : SKLWriteResPair<WriteIMul16,    [SKLPort1,SKLPort06,SKLPort0156], 4, [1,1,2], 4>;
121defm : X86WriteRes<WriteIMul16Imm,     [SKLPort1,SKLPort0156], 4, [1,1], 2>;
122defm : X86WriteRes<WriteIMul16ImmLd,   [SKLPort1,SKLPort0156,SKLPort23], 8, [1,1,1], 3>;
123defm : SKLWriteResPair<WriteIMul16Reg, [SKLPort1],   3>;
124defm : SKLWriteResPair<WriteIMul32,    [SKLPort1,SKLPort06,SKLPort0156], 4, [1,1,1], 3>;
125defm : SKLWriteResPair<WriteMULX32,    [SKLPort1,SKLPort06,SKLPort0156], 3, [1,1,1], 3>;
126defm : SKLWriteResPair<WriteIMul32Imm, [SKLPort1],   3>;
127defm : SKLWriteResPair<WriteIMul32Reg, [SKLPort1],   3>;
128defm : SKLWriteResPair<WriteIMul64,    [SKLPort1,SKLPort5], 4, [1,1], 2>;
129defm : SKLWriteResPair<WriteMULX64,    [SKLPort1,SKLPort5], 3, [1,1], 2>;
130defm : SKLWriteResPair<WriteIMul64Imm, [SKLPort1],   3>;
131defm : SKLWriteResPair<WriteIMul64Reg, [SKLPort1],   3>;
132def SKLWriteIMulH : WriteRes<WriteIMulH, []> { let Latency = 4; }
133def  : WriteRes<WriteIMulHLd, []> {
134  let Latency = !add(SKLWriteIMulH.Latency, SkylakeClientModel.LoadLatency);
135}
136
137defm : X86WriteRes<WriteBSWAP32,    [SKLPort15], 1, [1], 1>;
138defm : X86WriteRes<WriteBSWAP64,    [SKLPort06, SKLPort15], 2, [1,1], 2>;
139defm : X86WriteRes<WriteCMPXCHG,[SKLPort06, SKLPort0156], 5, [2,3], 5>;
140defm : X86WriteRes<WriteCMPXCHGRMW,[SKLPort23,SKLPort06,SKLPort0156,SKLPort237,SKLPort4], 8, [1,2,1,1,1], 6>;
141defm : X86WriteRes<WriteXCHG, [SKLPort0156], 2, [3], 3>;
142
143// TODO: Why isn't the SKLDivider used?
144defm : SKLWriteResPair<WriteDiv8,   [SKLPort0,SKLDivider], 25, [1,10], 1, 4>;
145defm : X86WriteRes<WriteDiv16,      [SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort05,SKLPort0156], 76, [7,2,8,3,1,11], 32>;
146defm : X86WriteRes<WriteDiv32,      [SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort05,SKLPort0156], 76, [7,2,8,3,1,11], 32>;
147defm : X86WriteRes<WriteDiv64,      [SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort05,SKLPort0156], 76, [7,2,8,3,1,11], 32>;
148defm : X86WriteRes<WriteDiv16Ld,    [SKLPort0,SKLPort23,SKLDivider], 29, [1,1,10], 2>;
149defm : X86WriteRes<WriteDiv32Ld,    [SKLPort0,SKLPort23,SKLDivider], 29, [1,1,10], 2>;
150defm : X86WriteRes<WriteDiv64Ld,    [SKLPort0,SKLPort23,SKLDivider], 29, [1,1,10], 2>;
151
152defm : X86WriteRes<WriteIDiv8,    [SKLPort0,SKLDivider], 25, [1,10], 1>;
153defm : X86WriteRes<WriteIDiv16,   [SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort06,SKLPort0156], 102, [4,2,4,8,14,34], 66>;
154defm : X86WriteRes<WriteIDiv32,   [SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort06,SKLPort0156], 102, [4,2,4,8,14,34], 66>;
155defm : X86WriteRes<WriteIDiv64,   [SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort06,SKLPort0156], 102, [4,2,4,8,14,34], 66>;
156defm : X86WriteRes<WriteIDiv8Ld,  [SKLPort0,SKLPort5,SKLPort23,SKLPort0156], 28, [2,4,1,1], 8>;
157defm : X86WriteRes<WriteIDiv16Ld, [SKLPort0,SKLPort5,SKLPort23,SKLPort0156], 28, [2,4,1,1], 8>;
158defm : X86WriteRes<WriteIDiv32Ld, [SKLPort0,SKLPort5,SKLPort23,SKLPort0156], 28, [2,4,1,1], 8>;
159defm : X86WriteRes<WriteIDiv64Ld, [SKLPort0,SKLPort5,SKLPort23,SKLPort0156], 28, [2,4,1,1], 8>;
160
161defm : SKLWriteResPair<WriteCRC32, [SKLPort1], 3>;
162
163def : WriteRes<WriteLEA, [SKLPort15]>; // LEA instructions can't fold loads.
164
165defm : SKLWriteResPair<WriteCMOV,  [SKLPort06], 1, [1], 1>; // Conditional move.
166defm : X86WriteRes<WriteFCMOV, [SKLPort1], 3, [1], 1>; // x87 conditional move.
167def  : WriteRes<WriteSETCC, [SKLPort06]>; // Setcc.
168def  : WriteRes<WriteSETCCStore, [SKLPort06,SKLPort4,SKLPort237]> {
169  let Latency = 2;
170  let NumMicroOps = 3;
171}
172
173defm : X86WriteRes<WriteLAHFSAHF,        [SKLPort06], 1, [1], 1>;
174defm : X86WriteRes<WriteBitTest,         [SKLPort06], 1, [1], 1>;
175defm : X86WriteRes<WriteBitTestImmLd,    [SKLPort06,SKLPort23], 6, [1,1], 2>;
176defm : X86WriteRes<WriteBitTestRegLd,    [SKLPort0156,SKLPort23], 6, [1,1], 2>;
177defm : X86WriteRes<WriteBitTestSet,      [SKLPort06], 1, [1], 1>;
178defm : X86WriteRes<WriteBitTestSetImmLd, [SKLPort06,SKLPort23], 5, [1,1], 3>;
179defm : X86WriteRes<WriteBitTestSetRegLd, [SKLPort0156,SKLPort23], 5, [1,1], 2>;
180
181// Bit counts.
182defm : SKLWriteResPair<WriteBSF, [SKLPort1], 3>;
183defm : SKLWriteResPair<WriteBSR, [SKLPort1], 3>;
184defm : SKLWriteResPair<WriteLZCNT,          [SKLPort1], 3>;
185defm : SKLWriteResPair<WriteTZCNT,          [SKLPort1], 3>;
186defm : SKLWriteResPair<WritePOPCNT,         [SKLPort1], 3>;
187
188// Integer shifts and rotates.
189defm : SKLWriteResPair<WriteShift,    [SKLPort06],  1>;
190defm : SKLWriteResPair<WriteShiftCL,  [SKLPort06],  3, [3], 3>;
191defm : SKLWriteResPair<WriteRotate,   [SKLPort06],  1, [1], 1>;
192defm : SKLWriteResPair<WriteRotateCL, [SKLPort06],  3, [3], 3>;
193
194// SHLD/SHRD.
195defm : X86WriteRes<WriteSHDrri, [SKLPort1], 3, [1], 1>;
196defm : X86WriteRes<WriteSHDrrcl,[SKLPort1,SKLPort06,SKLPort0156], 6, [1, 2, 1], 4>;
197defm : X86WriteRes<WriteSHDmri, [SKLPort1,SKLPort23,SKLPort237,SKLPort0156], 9, [1, 1, 1, 1], 4>;
198defm : X86WriteRes<WriteSHDmrcl,[SKLPort1,SKLPort23,SKLPort237,SKLPort06,SKLPort0156], 11, [1, 1, 1, 2, 1], 6>;
199
200// BMI1 BEXTR/BLS, BMI2 BZHI
201defm : SKLWriteResPair<WriteBEXTR, [SKLPort06,SKLPort15], 2, [1,1], 2>;
202defm : SKLWriteResPair<WriteBLS,   [SKLPort15], 1>;
203defm : SKLWriteResPair<WriteBZHI,  [SKLPort15], 1>;
204
205// Loads, stores, and moves, not folded with other operations.
206defm : X86WriteRes<WriteLoad,    [SKLPort23], 5, [1], 1>;
207defm : X86WriteRes<WriteStore,   [SKLPort237, SKLPort4], 1, [1,1], 1>;
208defm : X86WriteRes<WriteStoreNT, [SKLPort237, SKLPort4], 1, [1,1], 2>;
209defm : X86WriteRes<WriteMove,    [SKLPort0156], 1, [1], 1>;
210
211// Model the effect of clobbering the read-write mask operand of the GATHER operation.
212// Does not cost anything by itself, only has latency, matching that of the WriteLoad,
213defm : X86WriteRes<WriteVecMaskedGatherWriteback, [], 5, [], 0>;
214
215// Idioms that clear a register, like xorps %xmm0, %xmm0.
216// These can often bypass execution ports completely.
217def : WriteRes<WriteZero,  []>;
218
219// Branches don't produce values, so they have no latency, but they still
220// consume resources. Indirect branches can fold loads.
221defm : SKLWriteResPair<WriteJump,  [SKLPort06],   1>;
222
223// Floating point. This covers both scalar and vector operations.
224defm : X86WriteRes<WriteFLD0,          [SKLPort05], 1, [1], 1>;
225defm : X86WriteRes<WriteFLD1,          [SKLPort05], 1, [2], 2>;
226defm : X86WriteRes<WriteFLDC,          [SKLPort05], 1, [2], 2>;
227defm : X86WriteRes<WriteFLoad,         [SKLPort23], 5, [1], 1>;
228defm : X86WriteRes<WriteFLoadX,        [SKLPort23], 6, [1], 1>;
229defm : X86WriteRes<WriteFLoadY,        [SKLPort23], 7, [1], 1>;
230defm : X86WriteRes<WriteFMaskedLoad,   [SKLPort23,SKLPort015], 7, [1,1], 2>;
231defm : X86WriteRes<WriteFMaskedLoadY,  [SKLPort23,SKLPort015], 8, [1,1], 2>;
232defm : X86WriteRes<WriteFStore,        [SKLPort237,SKLPort4], 1, [1,1], 2>;
233defm : X86WriteRes<WriteFStoreX,       [SKLPort237,SKLPort4], 1, [1,1], 2>;
234defm : X86WriteRes<WriteFStoreY,       [SKLPort237,SKLPort4], 1, [1,1], 2>;
235defm : X86WriteRes<WriteFStoreNT,      [SKLPort237,SKLPort4], 1, [1,1], 2>;
236defm : X86WriteRes<WriteFStoreNTX,     [SKLPort237,SKLPort4], 1, [1,1], 2>;
237defm : X86WriteRes<WriteFStoreNTY,     [SKLPort237,SKLPort4], 1, [1,1], 2>;
238
239defm : X86WriteRes<WriteFMaskedStore32,  [SKLPort237,SKLPort0], 2, [1,1], 2>;
240defm : X86WriteRes<WriteFMaskedStore32Y, [SKLPort237,SKLPort0], 2, [1,1], 2>;
241defm : X86WriteRes<WriteFMaskedStore64,  [SKLPort237,SKLPort0], 2, [1,1], 2>;
242defm : X86WriteRes<WriteFMaskedStore64Y, [SKLPort237,SKLPort0], 2, [1,1], 2>;
243
244defm : X86WriteRes<WriteFMove,         [SKLPort015], 1, [1], 1>;
245defm : X86WriteRes<WriteFMoveX,        [SKLPort015], 1, [1], 1>;
246defm : X86WriteRes<WriteFMoveY,        [SKLPort015], 1, [1], 1>;
247defm : X86WriteResUnsupported<WriteFMoveZ>;
248defm : X86WriteRes<WriteEMMS,          [SKLPort05,SKLPort0156], 10, [9,1], 10>;
249
250defm : SKLWriteResPair<WriteFAdd,     [SKLPort01],  4, [1], 1, 5>; // Floating point add/sub.
251defm : SKLWriteResPair<WriteFAddX,    [SKLPort01],  4, [1], 1, 6>;
252defm : SKLWriteResPair<WriteFAddY,    [SKLPort01],  4, [1], 1, 7>;
253defm : X86WriteResPairUnsupported<WriteFAddZ>;
254defm : SKLWriteResPair<WriteFAdd64,   [SKLPort01],  4, [1], 1, 5>; // Floating point double add/sub.
255defm : SKLWriteResPair<WriteFAdd64X,  [SKLPort01],  4, [1], 1, 6>;
256defm : SKLWriteResPair<WriteFAdd64Y,  [SKLPort01],  4, [1], 1, 7>;
257defm : X86WriteResPairUnsupported<WriteFAdd64Z>;
258
259defm : SKLWriteResPair<WriteFCmp,     [SKLPort01],  4, [1], 1, 5>; // Floating point compare.
260defm : SKLWriteResPair<WriteFCmpX,    [SKLPort01],  4, [1], 1, 6>;
261defm : SKLWriteResPair<WriteFCmpY,    [SKLPort01],  4, [1], 1, 7>;
262defm : X86WriteResPairUnsupported<WriteFCmpZ>;
263defm : SKLWriteResPair<WriteFCmp64,   [SKLPort01],  4, [1], 1, 5>; // Floating point double compare.
264defm : SKLWriteResPair<WriteFCmp64X,  [SKLPort01],  4, [1], 1, 6>;
265defm : SKLWriteResPair<WriteFCmp64Y,  [SKLPort01],  4, [1], 1, 7>;
266defm : X86WriteResPairUnsupported<WriteFCmp64Z>;
267
268defm : SKLWriteResPair<WriteFCom,      [SKLPort0],  2>; // Floating point compare to flags (X87).
269defm : SKLWriteResPair<WriteFComX,     [SKLPort0],  2>; // Floating point compare to flags (SSE).
270
271defm : SKLWriteResPair<WriteFMul,     [SKLPort01],  4, [1], 1, 5>; // Floating point multiplication.
272defm : SKLWriteResPair<WriteFMulX,    [SKLPort01],  4, [1], 1, 6>;
273defm : SKLWriteResPair<WriteFMulY,    [SKLPort01],  4, [1], 1, 7>;
274defm : X86WriteResPairUnsupported<WriteFMulZ>;
275defm : SKLWriteResPair<WriteFMul64,   [SKLPort01],  4, [1], 1, 5>; // Floating point double multiplication.
276defm : SKLWriteResPair<WriteFMul64X,  [SKLPort01],  4, [1], 1, 6>;
277defm : SKLWriteResPair<WriteFMul64Y,  [SKLPort01],  4, [1], 1, 7>;
278defm : X86WriteResPairUnsupported<WriteFMul64Z>;
279
280defm : SKLWriteResPair<WriteFDiv,     [SKLPort0,SKLFPDivider], 11, [1,3], 1, 5>; // Floating point division.
281//defm : SKLWriteResPair<WriteFDivX,    [SKLPort0,SKLFPDivider], 11, [1,3], 1, 6>;
282defm : SKLWriteResPair<WriteFDivY,    [SKLPort0,SKLFPDivider], 11, [1,5], 1, 7>;
283defm : X86WriteResPairUnsupported<WriteFDivZ>;
284//defm : SKLWriteResPair<WriteFDiv64,   [SKLPort0,SKLFPDivider], 14, [1,3], 1, 5>; // Floating point double division.
285//defm : SKLWriteResPair<WriteFDiv64X,  [SKLPort0,SKLFPDivider], 14, [1,3], 1, 6>;
286//defm : SKLWriteResPair<WriteFDiv64Y,  [SKLPort0,SKLFPDivider], 14, [1,5], 1, 7>;
287defm : X86WriteResPairUnsupported<WriteFDiv64Z>;
288
289defm : SKLWriteResPair<WriteFSqrt,    [SKLPort0,SKLFPDivider], 12, [1,3], 1, 5>; // Floating point square root.
290defm : SKLWriteResPair<WriteFSqrtX,   [SKLPort0,SKLFPDivider], 12, [1,3], 1, 6>;
291defm : SKLWriteResPair<WriteFSqrtY,   [SKLPort0,SKLFPDivider], 12, [1,6], 1, 7>;
292defm : X86WriteResPairUnsupported<WriteFSqrtZ>;
293defm : SKLWriteResPair<WriteFSqrt64,  [SKLPort0,SKLFPDivider], 18, [1,6], 1, 5>; // Floating point double square root.
294defm : SKLWriteResPair<WriteFSqrt64X, [SKLPort0,SKLFPDivider], 18, [1,6], 1, 6>;
295defm : SKLWriteResPair<WriteFSqrt64Y, [SKLPort0,SKLFPDivider], 18, [1,12],1, 7>;
296defm : X86WriteResPairUnsupported<WriteFSqrt64Z>;
297defm : SKLWriteResPair<WriteFSqrt80,  [SKLPort0,SKLFPDivider], 21, [1,7]>; // Floating point long double square root.
298
299defm : SKLWriteResPair<WriteFRcp,   [SKLPort0], 4, [1], 1, 5>; // Floating point reciprocal estimate.
300defm : SKLWriteResPair<WriteFRcpX,  [SKLPort0], 4, [1], 1, 6>;
301defm : SKLWriteResPair<WriteFRcpY,  [SKLPort0], 4, [1], 1, 7>;
302defm : X86WriteResPairUnsupported<WriteFRcpZ>;
303
304defm : SKLWriteResPair<WriteFRsqrt, [SKLPort0], 4, [1], 1, 5>; // Floating point reciprocal square root estimate.
305defm : SKLWriteResPair<WriteFRsqrtX,[SKLPort0], 4, [1], 1, 6>;
306defm : SKLWriteResPair<WriteFRsqrtY,[SKLPort0], 4, [1], 1, 7>;
307defm : X86WriteResPairUnsupported<WriteFRsqrtZ>;
308
309defm : SKLWriteResPair<WriteFMA,    [SKLPort01], 4, [1], 1, 5>; // Fused Multiply Add.
310defm : SKLWriteResPair<WriteFMAX,   [SKLPort01], 4, [1], 1, 6>;
311defm : SKLWriteResPair<WriteFMAY,   [SKLPort01], 4, [1], 1, 7>;
312defm : X86WriteResPairUnsupported<WriteFMAZ>;
313defm : SKLWriteResPair<WriteDPPD,   [SKLPort5,SKLPort01],  9, [1,2], 3, 6>; // Floating point double dot product.
314defm : SKLWriteResPair<WriteDPPS,   [SKLPort5,SKLPort01], 13, [1,3], 4, 6>;
315defm : SKLWriteResPair<WriteDPPSY,  [SKLPort5,SKLPort01], 13, [1,3], 4, 7>;
316defm : X86WriteResPairUnsupported<WriteDPPSZ>;
317defm : SKLWriteResPair<WriteFSign,   [SKLPort0], 1>; // Floating point fabs/fchs.
318defm : SKLWriteResPair<WriteFRnd,     [SKLPort01], 8, [2], 2, 6>; // Floating point rounding.
319defm : SKLWriteResPair<WriteFRndY,    [SKLPort01], 8, [2], 2, 7>;
320defm : X86WriteResPairUnsupported<WriteFRndZ>;
321defm : SKLWriteResPair<WriteFLogic,  [SKLPort015], 1, [1], 1, 6>; // Floating point and/or/xor logicals.
322defm : SKLWriteResPair<WriteFLogicY, [SKLPort015], 1, [1], 1, 7>;
323defm : X86WriteResPairUnsupported<WriteFLogicZ>;
324defm : SKLWriteResPair<WriteFTest,   [SKLPort0], 2, [1], 1, 6>; // Floating point TEST instructions.
325defm : SKLWriteResPair<WriteFTestY,  [SKLPort0], 2, [1], 1, 7>;
326defm : X86WriteResPairUnsupported<WriteFTestZ>;
327defm : SKLWriteResPair<WriteFShuffle,  [SKLPort5], 1, [1], 1, 6>; // Floating point vector shuffles.
328defm : SKLWriteResPair<WriteFShuffleY, [SKLPort5], 1, [1], 1, 7>;
329defm : X86WriteResPairUnsupported<WriteFShuffleZ>;
330defm : SKLWriteResPair<WriteFVarShuffle,  [SKLPort5], 1, [1], 1, 6>; // Floating point vector shuffles.
331defm : SKLWriteResPair<WriteFVarShuffleY, [SKLPort5], 1, [1], 1, 7>;
332defm : X86WriteResPairUnsupported<WriteFVarShuffleZ>;
333defm : SKLWriteResPair<WriteFBlend,  [SKLPort015], 1, [1], 1, 6>; // Floating point vector blends.
334defm : SKLWriteResPair<WriteFBlendY, [SKLPort015], 1, [1], 1, 7>;
335defm : X86WriteResPairUnsupported<WriteFBlendZ>;
336defm : SKLWriteResPair<WriteFVarBlend, [SKLPort015], 2, [2], 2, 6>; // Fp vector variable blends.
337defm : SKLWriteResPair<WriteFVarBlendY,[SKLPort015], 2, [2], 2, 7>;
338defm : X86WriteResPairUnsupported<WriteFVarBlendZ>;
339
340// FMA Scheduling helper class.
341// class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; }
342
343// Vector integer operations.
344defm : X86WriteRes<WriteVecLoad,         [SKLPort23], 5, [1], 1>;
345defm : X86WriteRes<WriteVecLoadX,        [SKLPort23], 6, [1], 1>;
346defm : X86WriteRes<WriteVecLoadY,        [SKLPort23], 7, [1], 1>;
347defm : X86WriteRes<WriteVecLoadNT,       [SKLPort23], 6, [1], 1>;
348defm : X86WriteRes<WriteVecLoadNTY,      [SKLPort23], 7, [1], 1>;
349defm : X86WriteRes<WriteVecMaskedLoad,   [SKLPort23,SKLPort015], 7, [1,1], 2>;
350defm : X86WriteRes<WriteVecMaskedLoadY,  [SKLPort23,SKLPort015], 8, [1,1], 2>;
351defm : X86WriteRes<WriteVecStore,        [SKLPort237,SKLPort4], 1, [1,1], 2>;
352defm : X86WriteRes<WriteVecStoreX,       [SKLPort237,SKLPort4], 1, [1,1], 2>;
353defm : X86WriteRes<WriteVecStoreY,       [SKLPort237,SKLPort4], 1, [1,1], 2>;
354defm : X86WriteRes<WriteVecStoreNT,      [SKLPort237,SKLPort4], 1, [1,1], 2>;
355defm : X86WriteRes<WriteVecStoreNTY,     [SKLPort237,SKLPort4], 1, [1,1], 2>;
356defm : X86WriteRes<WriteVecMaskedStore32,  [SKLPort237,SKLPort0], 2, [1,1], 2>;
357defm : X86WriteRes<WriteVecMaskedStore32Y, [SKLPort237,SKLPort0], 2, [1,1], 2>;
358defm : X86WriteRes<WriteVecMaskedStore64,  [SKLPort237,SKLPort0], 2, [1,1], 2>;
359defm : X86WriteRes<WriteVecMaskedStore64Y, [SKLPort237,SKLPort0], 2, [1,1], 2>;
360defm : X86WriteRes<WriteVecMove,         [SKLPort05],  1, [1], 1>;
361defm : X86WriteRes<WriteVecMoveX,        [SKLPort015], 1, [1], 1>;
362defm : X86WriteRes<WriteVecMoveY,        [SKLPort015], 1, [1], 1>;
363defm : X86WriteResUnsupported<WriteVecMoveZ>;
364defm : X86WriteRes<WriteVecMoveToGpr,    [SKLPort0], 2, [1], 1>;
365defm : X86WriteRes<WriteVecMoveFromGpr,  [SKLPort5], 1, [1], 1>;
366
367defm : SKLWriteResPair<WriteVecALU,   [SKLPort05], 1, [1], 1, 5>; // Vector integer ALU op, no logicals.
368defm : SKLWriteResPair<WriteVecALUX,  [SKLPort01], 1, [1], 1, 6>;
369defm : SKLWriteResPair<WriteVecALUY,  [SKLPort01], 1, [1], 1, 7>;
370defm : X86WriteResPairUnsupported<WriteVecALUZ>;
371defm : SKLWriteResPair<WriteVecLogic, [SKLPort05],  1, [1], 1, 5>; // Vector integer and/or/xor.
372defm : SKLWriteResPair<WriteVecLogicX,[SKLPort015], 1, [1], 1, 6>;
373defm : SKLWriteResPair<WriteVecLogicY,[SKLPort015], 1, [1], 1, 7>;
374defm : X86WriteResPairUnsupported<WriteVecLogicZ>;
375defm : SKLWriteResPair<WriteVecTest,  [SKLPort0,SKLPort5], 3, [1,1], 2, 6>; // Vector integer TEST instructions.
376defm : SKLWriteResPair<WriteVecTestY, [SKLPort0,SKLPort5], 3, [1,1], 2, 7>;
377defm : X86WriteResPairUnsupported<WriteVecTestZ>;
378defm : SKLWriteResPair<WriteVecIMul,  [SKLPort0] ,  5, [1], 1, 5>; // Vector integer multiply.
379defm : SKLWriteResPair<WriteVecIMulX, [SKLPort01],  5, [1], 1, 6>;
380defm : SKLWriteResPair<WriteVecIMulY, [SKLPort01],  5, [1], 1, 7>;
381defm : X86WriteResPairUnsupported<WriteVecIMulZ>;
382defm : SKLWriteResPair<WritePMULLD,   [SKLPort01], 10, [2], 2, 6>; // Vector PMULLD.
383defm : SKLWriteResPair<WritePMULLDY,  [SKLPort01], 10, [2], 2, 7>;
384defm : X86WriteResPairUnsupported<WritePMULLDZ>;
385defm : SKLWriteResPair<WriteShuffle,  [SKLPort5], 1, [1], 1, 5>; // Vector shuffles.
386defm : SKLWriteResPair<WriteShuffleX, [SKLPort5], 1, [1], 1, 6>;
387defm : SKLWriteResPair<WriteShuffleY, [SKLPort5], 1, [1], 1, 7>;
388defm : X86WriteResPairUnsupported<WriteShuffleZ>;
389defm : SKLWriteResPair<WriteVarShuffle,  [SKLPort5], 1, [1], 1, 5>; // Vector shuffles.
390defm : SKLWriteResPair<WriteVarShuffleX, [SKLPort5], 1, [1], 1, 6>;
391defm : SKLWriteResPair<WriteVarShuffleY, [SKLPort5], 1, [1], 1, 7>;
392defm : X86WriteResPairUnsupported<WriteVarShuffleZ>;
393defm : SKLWriteResPair<WriteBlend,  [SKLPort5], 1, [1], 1, 6>; // Vector blends.
394defm : SKLWriteResPair<WriteBlendY, [SKLPort5], 1, [1], 1, 7>;
395defm : X86WriteResPairUnsupported<WriteBlendZ>;
396defm : SKLWriteResPair<WriteVarBlend,  [SKLPort015], 2, [2], 2, 6>; // Vector variable blends.
397defm : SKLWriteResPair<WriteVarBlendY, [SKLPort015], 2, [2], 2, 6>;
398defm : X86WriteResPairUnsupported<WriteVarBlendZ>;
399defm : SKLWriteResPair<WriteMPSAD,  [SKLPort5], 4, [2], 2, 6>; // Vector MPSAD.
400defm : SKLWriteResPair<WriteMPSADY, [SKLPort5], 4, [2], 2, 7>;
401defm : X86WriteResPairUnsupported<WriteMPSADZ>;
402defm : SKLWriteResPair<WritePSADBW,  [SKLPort5], 3, [1], 1, 5>; // Vector PSADBW.
403defm : SKLWriteResPair<WritePSADBWX, [SKLPort5], 3, [1], 1, 6>;
404defm : SKLWriteResPair<WritePSADBWY, [SKLPort5], 3, [1], 1, 7>;
405defm : X86WriteResPairUnsupported<WritePSADBWZ>;
406defm : SKLWriteResPair<WritePHMINPOS, [SKLPort01], 4, [1], 1, 6>; // Vector PHMINPOS.
407
408// Vector integer shifts.
409defm : SKLWriteResPair<WriteVecShift,     [SKLPort0], 1, [1], 1, 5>;
410defm : X86WriteRes<WriteVecShiftX,        [SKLPort5,SKLPort01],  2, [1,1], 2>;
411defm : X86WriteRes<WriteVecShiftY,        [SKLPort5,SKLPort01],  4, [1,1], 2>;
412defm : X86WriteRes<WriteVecShiftXLd,      [SKLPort01,SKLPort23], 7, [1,1], 2>;
413defm : X86WriteRes<WriteVecShiftYLd,      [SKLPort01,SKLPort23], 8, [1,1], 2>;
414defm : X86WriteResPairUnsupported<WriteVecShiftZ>;
415
416defm : SKLWriteResPair<WriteVecShiftImm,  [SKLPort0],  1, [1], 1, 5>; // Vector integer immediate shifts.
417defm : SKLWriteResPair<WriteVecShiftImmX, [SKLPort01], 1, [1], 1, 6>;
418defm : SKLWriteResPair<WriteVecShiftImmY, [SKLPort01], 1, [1], 1, 7>;
419defm : X86WriteResPairUnsupported<WriteVecShiftImmZ>;
420defm : SKLWriteResPair<WriteVarVecShift,  [SKLPort01], 1, [1], 1, 6>; // Variable vector shifts.
421defm : SKLWriteResPair<WriteVarVecShiftY, [SKLPort01], 1, [1], 1, 7>;
422defm : X86WriteResPairUnsupported<WriteVarVecShiftZ>;
423
424// Vector insert/extract operations.
425def : WriteRes<WriteVecInsert, [SKLPort5]> {
426  let Latency = 2;
427  let NumMicroOps = 2;
428  let ResourceCycles = [2];
429}
430def : WriteRes<WriteVecInsertLd, [SKLPort5,SKLPort23]> {
431  let Latency = 6;
432  let NumMicroOps = 2;
433}
434def: InstRW<[WriteVecInsertLd], (instregex "(V?)MOV(H|L)(PD|PS)rm")>;
435
436def : WriteRes<WriteVecExtract, [SKLPort0,SKLPort5]> {
437  let Latency = 3;
438  let NumMicroOps = 2;
439}
440def : WriteRes<WriteVecExtractSt, [SKLPort4,SKLPort5,SKLPort237]> {
441  let Latency = 2;
442  let NumMicroOps = 3;
443}
444
445// Conversion between integer and float.
446defm : SKLWriteResPair<WriteCvtSS2I,   [SKLPort1], 3>;
447defm : SKLWriteResPair<WriteCvtPS2I,   [SKLPort1], 3>;
448defm : SKLWriteResPair<WriteCvtPS2IY,  [SKLPort1], 3>;
449defm : X86WriteResPairUnsupported<WriteCvtPS2IZ>;
450defm : SKLWriteResPair<WriteCvtSD2I,   [SKLPort1], 3>;
451defm : SKLWriteResPair<WriteCvtPD2I,   [SKLPort1], 3>;
452defm : SKLWriteResPair<WriteCvtPD2IY,  [SKLPort1], 3>;
453defm : X86WriteResPairUnsupported<WriteCvtPD2IZ>;
454
455defm : SKLWriteResPair<WriteCvtI2SS,   [SKLPort1], 4>;
456defm : SKLWriteResPair<WriteCvtI2PS,   [SKLPort1], 4>;
457defm : SKLWriteResPair<WriteCvtI2PSY,  [SKLPort1], 4>;
458defm : X86WriteResPairUnsupported<WriteCvtI2PSZ>;
459defm : SKLWriteResPair<WriteCvtI2SD,   [SKLPort1], 4>;
460defm : SKLWriteResPair<WriteCvtI2PD,   [SKLPort1], 4>;
461defm : SKLWriteResPair<WriteCvtI2PDY,  [SKLPort1], 4>;
462defm : X86WriteResPairUnsupported<WriteCvtI2PDZ>;
463
464defm : SKLWriteResPair<WriteCvtSS2SD,  [SKLPort1], 3>;
465defm : SKLWriteResPair<WriteCvtPS2PD,  [SKLPort1], 3>;
466defm : SKLWriteResPair<WriteCvtPS2PDY, [SKLPort1], 3>;
467defm : X86WriteResPairUnsupported<WriteCvtPS2PDZ>;
468defm : SKLWriteResPair<WriteCvtSD2SS,  [SKLPort1], 3>;
469defm : SKLWriteResPair<WriteCvtPD2PS,  [SKLPort1], 3>;
470defm : SKLWriteResPair<WriteCvtPD2PSY, [SKLPort1], 3>;
471defm : X86WriteResPairUnsupported<WriteCvtPD2PSZ>;
472
473defm : X86WriteRes<WriteCvtPH2PS,    [SKLPort5,SKLPort015],  5, [1,1], 2>;
474defm : X86WriteRes<WriteCvtPH2PSY,    [SKLPort5,SKLPort01],  7, [1,1], 2>;
475defm : X86WriteResUnsupported<WriteCvtPH2PSZ>;
476defm : X86WriteRes<WriteCvtPH2PSLd,  [SKLPort23,SKLPort01],  9, [1,1], 2>;
477defm : X86WriteRes<WriteCvtPH2PSYLd, [SKLPort23,SKLPort01], 10, [1,1], 2>;
478defm : X86WriteResUnsupported<WriteCvtPH2PSZLd>;
479
480defm : X86WriteRes<WriteCvtPS2PH,                       [SKLPort5,SKLPort015], 5, [1,1], 2>;
481defm : X86WriteRes<WriteCvtPS2PHY,                       [SKLPort5,SKLPort01], 7, [1,1], 2>;
482defm : X86WriteResUnsupported<WriteCvtPS2PHZ>;
483defm : X86WriteRes<WriteCvtPS2PHSt,  [SKLPort4,SKLPort5,SKLPort237,SKLPort01], 6, [1,1,1,1], 4>;
484defm : X86WriteRes<WriteCvtPS2PHYSt, [SKLPort4,SKLPort5,SKLPort237,SKLPort01], 8, [1,1,1,1], 4>;
485defm : X86WriteResUnsupported<WriteCvtPS2PHZSt>;
486
487// Strings instructions.
488
489// Packed Compare Implicit Length Strings, Return Mask
490def : WriteRes<WritePCmpIStrM, [SKLPort0]> {
491  let Latency = 10;
492  let NumMicroOps = 3;
493  let ResourceCycles = [3];
494}
495def : WriteRes<WritePCmpIStrMLd, [SKLPort0, SKLPort23]> {
496  let Latency = 16;
497  let NumMicroOps = 4;
498  let ResourceCycles = [3,1];
499}
500
501// Packed Compare Explicit Length Strings, Return Mask
502def : WriteRes<WritePCmpEStrM, [SKLPort0, SKLPort5, SKLPort015, SKLPort0156]> {
503  let Latency = 19;
504  let NumMicroOps = 9;
505  let ResourceCycles = [4,3,1,1];
506}
507def : WriteRes<WritePCmpEStrMLd, [SKLPort0, SKLPort5,SKLPort23, SKLPort015, SKLPort0156]> {
508  let Latency = 25;
509  let NumMicroOps = 10;
510  let ResourceCycles = [4,3,1,1,1];
511}
512
513// Packed Compare Implicit Length Strings, Return Index
514def : WriteRes<WritePCmpIStrI, [SKLPort0]> {
515  let Latency = 10;
516  let NumMicroOps = 3;
517  let ResourceCycles = [3];
518}
519def : WriteRes<WritePCmpIStrILd, [SKLPort0, SKLPort23]> {
520  let Latency = 16;
521  let NumMicroOps = 4;
522  let ResourceCycles = [3,1];
523}
524
525// Packed Compare Explicit Length Strings, Return Index
526def : WriteRes<WritePCmpEStrI, [SKLPort0, SKLPort5, SKLPort0156]> {
527  let Latency = 18;
528  let NumMicroOps = 8;
529  let ResourceCycles = [4,3,1];
530}
531def : WriteRes<WritePCmpEStrILd, [SKLPort0, SKLPort5, SKLPort23, SKLPort0156]> {
532  let Latency = 24;
533  let NumMicroOps = 9;
534  let ResourceCycles = [4,3,1,1];
535}
536
537// MOVMSK Instructions.
538def : WriteRes<WriteFMOVMSK,    [SKLPort0]> { let Latency = 2; }
539def : WriteRes<WriteVecMOVMSK,  [SKLPort0]> { let Latency = 2; }
540def : WriteRes<WriteVecMOVMSKY, [SKLPort0]> { let Latency = 2; }
541def : WriteRes<WriteMMXMOVMSK,  [SKLPort0]> { let Latency = 2; }
542
543// AES instructions.
544def : WriteRes<WriteAESDecEnc, [SKLPort0]> { // Decryption, encryption.
545  let Latency = 4;
546  let NumMicroOps = 1;
547  let ResourceCycles = [1];
548}
549def : WriteRes<WriteAESDecEncLd, [SKLPort0, SKLPort23]> {
550  let Latency = 10;
551  let NumMicroOps = 2;
552  let ResourceCycles = [1,1];
553}
554
555def : WriteRes<WriteAESIMC, [SKLPort0]> { // InvMixColumn.
556  let Latency = 8;
557  let NumMicroOps = 2;
558  let ResourceCycles = [2];
559}
560def : WriteRes<WriteAESIMCLd, [SKLPort0, SKLPort23]> {
561  let Latency = 14;
562  let NumMicroOps = 3;
563  let ResourceCycles = [2,1];
564}
565
566def : WriteRes<WriteAESKeyGen, [SKLPort0, SKLPort5, SKLPort015]> { // Key Generation.
567  let Latency = 20;
568  let NumMicroOps = 11;
569  let ResourceCycles = [3,6,2];
570}
571def : WriteRes<WriteAESKeyGenLd, [SKLPort0, SKLPort5, SKLPort23, SKLPort015]> {
572  let Latency = 25;
573  let NumMicroOps = 11;
574  let ResourceCycles = [3,6,1,1];
575}
576
577// Carry-less multiplication instructions.
578def : WriteRes<WriteCLMul, [SKLPort5]> {
579  let Latency = 6;
580  let NumMicroOps = 1;
581  let ResourceCycles = [1];
582}
583def : WriteRes<WriteCLMulLd, [SKLPort5, SKLPort23]> {
584  let Latency = 12;
585  let NumMicroOps = 2;
586  let ResourceCycles = [1,1];
587}
588
589// Catch-all for expensive system instructions.
590def : WriteRes<WriteSystem,     [SKLPort0156]> { let Latency = 100; } // def WriteSystem : SchedWrite;
591
592// AVX2.
593defm : SKLWriteResPair<WriteFShuffle256, [SKLPort5], 3, [1], 1, 7>; // Fp 256-bit width vector shuffles.
594defm : SKLWriteResPair<WriteFVarShuffle256, [SKLPort5], 3, [1], 1, 7>; // Fp 256-bit width vector variable shuffles.
595defm : SKLWriteResPair<WriteShuffle256, [SKLPort5], 3, [1], 1, 7>;  // 256-bit width vector shuffles.
596defm : SKLWriteResPair<WriteVPMOV256, [SKLPort5], 3, [1], 1, 7>;  // 256-bit width packed vector width-changing move.
597defm : SKLWriteResPair<WriteVarShuffle256, [SKLPort5], 3, [1], 1, 7>;  // 256-bit width vector variable shuffles.
598
599// Old microcoded instructions that nobody use.
600def : WriteRes<WriteMicrocoded, [SKLPort0156]> { let Latency = 100; } // def WriteMicrocoded : SchedWrite;
601
602// Fence instructions.
603def : WriteRes<WriteFence,  [SKLPort23, SKLPort4]>;
604
605// Load/store MXCSR.
606def : WriteRes<WriteLDMXCSR, [SKLPort0,SKLPort23,SKLPort0156]> { let Latency = 7; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; }
607def : WriteRes<WriteSTMXCSR, [SKLPort4,SKLPort5,SKLPort237]> { let Latency = 2; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; }
608
609// Nop, not very useful expect it provides a model for nops!
610def : WriteRes<WriteNop, []>;
611
612////////////////////////////////////////////////////////////////////////////////
613// Horizontal add/sub  instructions.
614////////////////////////////////////////////////////////////////////////////////
615
616defm : SKLWriteResPair<WriteFHAdd,  [SKLPort5,SKLPort01], 6, [2,1], 3, 6>;
617defm : SKLWriteResPair<WriteFHAddY, [SKLPort5,SKLPort01], 6, [2,1], 3, 7>;
618defm : SKLWriteResPair<WritePHAdd,  [SKLPort5,SKLPort05],  3, [2,1], 3, 5>;
619defm : SKLWriteResPair<WritePHAddX, [SKLPort5,SKLPort015], 3, [2,1], 3, 6>;
620defm : SKLWriteResPair<WritePHAddY, [SKLPort5,SKLPort015], 3, [2,1], 3, 7>;
621
622// Remaining instrs.
623
624def SKLWriteResGroup1 : SchedWriteRes<[SKLPort0]> {
625  let Latency = 1;
626  let NumMicroOps = 1;
627  let ResourceCycles = [1];
628}
629def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PADDS(B|W)rr",
630                                            "MMX_PADDUS(B|W)rr",
631                                            "MMX_PAVG(B|W)rr",
632                                            "MMX_PCMPEQ(B|D|W)rr",
633                                            "MMX_PCMPGT(B|D|W)rr",
634                                            "MMX_P(MAX|MIN)SWrr",
635                                            "MMX_P(MAX|MIN)UBrr",
636                                            "MMX_PSUBS(B|W)rr",
637                                            "MMX_PSUBUS(B|W)rr")>;
638
639def SKLWriteResGroup3 : SchedWriteRes<[SKLPort5]> {
640  let Latency = 1;
641  let NumMicroOps = 1;
642  let ResourceCycles = [1];
643}
644def: InstRW<[SKLWriteResGroup3], (instregex "COM(P?)_FST0r",
645                                            "UCOM_F(P?)r")>;
646
647def SKLWriteResGroup4 : SchedWriteRes<[SKLPort6]> {
648  let Latency = 1;
649  let NumMicroOps = 1;
650  let ResourceCycles = [1];
651}
652def: InstRW<[SKLWriteResGroup4], (instregex "JMP(16|32|64)r")>;
653
654def SKLWriteResGroup6 : SchedWriteRes<[SKLPort05]> {
655  let Latency = 1;
656  let NumMicroOps = 1;
657  let ResourceCycles = [1];
658}
659def: InstRW<[SKLWriteResGroup6], (instrs FINCSTP, FNOP)>;
660
661def SKLWriteResGroup7 : SchedWriteRes<[SKLPort06]> {
662  let Latency = 1;
663  let NumMicroOps = 1;
664  let ResourceCycles = [1];
665}
666def: InstRW<[SKLWriteResGroup7], (instrs CDQ, CQO, CLAC, STAC)>;
667
668def SKLWriteResGroup8 : SchedWriteRes<[SKLPort15]> {
669  let Latency = 1;
670  let NumMicroOps = 1;
671  let ResourceCycles = [1];
672}
673def: InstRW<[SKLWriteResGroup8], (instregex "ANDN(32|64)rr")>;
674
675def SKLWriteResGroup9 : SchedWriteRes<[SKLPort015]> {
676  let Latency = 1;
677  let NumMicroOps = 1;
678  let ResourceCycles = [1];
679}
680def: InstRW<[SKLWriteResGroup9], (instregex "(V?)PADD(B|D|Q|W)(Y?)rr",
681                                            "VPBLENDD(Y?)rri")>;
682
683def SKLWriteResGroup10 : SchedWriteRes<[SKLPort0156]> {
684  let Latency = 1;
685  let NumMicroOps = 1;
686  let ResourceCycles = [1];
687}
688def: InstRW<[SKLWriteResGroup10], (instrs CBW, CWDE, CDQE,
689                                          CMC, STC,
690                                          SGDT64m,
691                                          SIDT64m,
692                                          SMSW16m,
693                                          STRm,
694                                          SYSCALL)>;
695
696def SKLWriteResGroup11 : SchedWriteRes<[SKLPort4,SKLPort237]> {
697  let Latency = 1;
698  let NumMicroOps = 2;
699  let ResourceCycles = [1,1];
700}
701def: InstRW<[SKLWriteResGroup11], (instrs FBSTPm, VMPTRSTm)>;
702def: InstRW<[SKLWriteResGroup11], (instregex "ST_FP(32|64|80)m")>;
703
704def SKLWriteResGroup13 : SchedWriteRes<[SKLPort5]> {
705  let Latency = 2;
706  let NumMicroOps = 2;
707  let ResourceCycles = [2];
708}
709def: InstRW<[SKLWriteResGroup13], (instrs MMX_MOVQ2DQrr)>;
710
711def SKLWriteResGroup14 : SchedWriteRes<[SKLPort05]> {
712  let Latency = 2;
713  let NumMicroOps = 2;
714  let ResourceCycles = [2];
715}
716def: InstRW<[SKLWriteResGroup14], (instrs FDECSTP,
717                                          MMX_MOVDQ2Qrr)>;
718
719def SKLWriteResGroup17 : SchedWriteRes<[SKLPort0156]> {
720  let Latency = 2;
721  let NumMicroOps = 2;
722  let ResourceCycles = [2];
723}
724def: InstRW<[SKLWriteResGroup17], (instrs LFENCE,
725                                          WAIT,
726                                          XGETBV)>;
727
728def SKLWriteResGroup20 : SchedWriteRes<[SKLPort6,SKLPort0156]> {
729  let Latency = 2;
730  let NumMicroOps = 2;
731  let ResourceCycles = [1,1];
732}
733def: InstRW<[SKLWriteResGroup20], (instregex "CLFLUSH")>;
734
735def SKLWriteResGroup21 : SchedWriteRes<[SKLPort237,SKLPort0156]> {
736  let Latency = 2;
737  let NumMicroOps = 2;
738  let ResourceCycles = [1,1];
739}
740def: InstRW<[SKLWriteResGroup21], (instrs SFENCE)>;
741
742def SKLWriteResGroup23 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
743  let Latency = 2;
744  let NumMicroOps = 2;
745  let ResourceCycles = [1,1];
746}
747def: InstRW<[SKLWriteResGroup23], (instrs CWD,
748                                          JCXZ, JECXZ, JRCXZ,
749                                          ADC8i8, SBB8i8,
750                                          ADC16i16, SBB16i16,
751                                          ADC32i32, SBB32i32,
752                                          ADC64i32, SBB64i32)>;
753
754def SKLWriteResGroup25 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort237]> {
755  let Latency = 2;
756  let NumMicroOps = 3;
757  let ResourceCycles = [1,1,1];
758}
759def: InstRW<[SKLWriteResGroup25], (instrs FNSTCW16m)>;
760
761def SKLWriteResGroup27 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort15]> {
762  let Latency = 2;
763  let NumMicroOps = 3;
764  let ResourceCycles = [1,1,1];
765}
766def: InstRW<[SKLWriteResGroup27], (instregex "MOVBE(16|32|64)mr")>;
767
768def SKLWriteResGroup28 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort0156]> {
769  let Latency = 2;
770  let NumMicroOps = 3;
771  let ResourceCycles = [1,1,1];
772}
773def: InstRW<[SKLWriteResGroup28], (instrs PUSH16r, PUSH32r, PUSH64r, PUSH64i8,
774                                          STOSB, STOSL, STOSQ, STOSW)>;
775def: InstRW<[SKLWriteResGroup28], (instregex "PUSH(16|32|64)rmr")>;
776
777def SKLWriteResGroup29 : SchedWriteRes<[SKLPort1]> {
778  let Latency = 3;
779  let NumMicroOps = 1;
780  let ResourceCycles = [1];
781}
782def: InstRW<[SKLWriteResGroup29], (instregex "PDEP(32|64)rr",
783                                             "PEXT(32|64)rr")>;
784
785def SKLWriteResGroup30 : SchedWriteRes<[SKLPort5]> {
786  let Latency = 3;
787  let NumMicroOps = 1;
788  let ResourceCycles = [1];
789}
790def: InstRW<[SKLWriteResGroup30], (instregex "(ADD|SUB|SUBR)_(FPrST0|FST0r|FrST0)",
791                                             "VPBROADCAST(B|W)rr")>;
792
793def SKLWriteResGroup32 : SchedWriteRes<[SKLPort0,SKLPort0156]> {
794  let Latency = 3;
795  let NumMicroOps = 2;
796  let ResourceCycles = [1,1];
797}
798def: InstRW<[SKLWriteResGroup32], (instrs FNSTSW16r)>;
799
800def SKLWriteResGroup35 : SchedWriteRes<[SKLPort0,SKLPort5]> {
801  let Latency = 3;
802  let NumMicroOps = 3;
803  let ResourceCycles = [1,2];
804}
805def: InstRW<[SKLWriteResGroup35], (instregex "MMX_PH(ADD|SUB)SWrr")>;
806
807def SKLWriteResGroup36 : SchedWriteRes<[SKLPort5,SKLPort01]> {
808  let Latency = 3;
809  let NumMicroOps = 3;
810  let ResourceCycles = [2,1];
811}
812def: InstRW<[SKLWriteResGroup36], (instregex "(V?)PHADDSW(Y?)rr",
813                                             "(V?)PHSUBSW(Y?)rr")>;
814
815def SKLWriteResGroup39 : SchedWriteRes<[SKLPort5,SKLPort0156]> {
816  let Latency = 3;
817  let NumMicroOps = 3;
818  let ResourceCycles = [2,1];
819}
820def: InstRW<[SKLWriteResGroup39], (instrs MMX_PACKSSDWrr,
821                                          MMX_PACKSSWBrr,
822                                          MMX_PACKUSWBrr)>;
823
824def SKLWriteResGroup40 : SchedWriteRes<[SKLPort6,SKLPort0156]> {
825  let Latency = 3;
826  let NumMicroOps = 3;
827  let ResourceCycles = [1,2];
828}
829def: InstRW<[SKLWriteResGroup40], (instregex "CLD")>;
830
831def SKLWriteResGroup41 : SchedWriteRes<[SKLPort237,SKLPort0156]> {
832  let Latency = 3;
833  let NumMicroOps = 3;
834  let ResourceCycles = [1,2];
835}
836def: InstRW<[SKLWriteResGroup41], (instrs MFENCE)>;
837
838def SKLWriteResGroup42 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
839  let Latency = 2;
840  let NumMicroOps = 3;
841  let ResourceCycles = [1,2];
842}
843def: InstRW<[SKLWriteResGroup42], (instrs RCL8r1, RCL16r1, RCL32r1, RCL64r1,
844                                          RCR8r1, RCR16r1, RCR32r1, RCR64r1)>;
845
846def SKLWriteResGroup42b : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort0156]> {
847  let Latency = 5;
848  let NumMicroOps = 8;
849  let ResourceCycles = [2,4,2];
850}
851def: InstRW<[SKLWriteResGroup42b], (instrs RCR8ri, RCR16ri, RCR32ri, RCR64ri)>;
852
853def SKLWriteResGroup42c : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort0156]> {
854  let Latency = 6;
855  let NumMicroOps = 8;
856  let ResourceCycles = [2,4,2];
857}
858def: InstRW<[SKLWriteResGroup42c], (instrs RCL8ri, RCL16ri, RCL32ri, RCL64ri)>;
859
860def SKLWriteResGroup43 : SchedWriteRes<[SKLPort0,SKLPort4,SKLPort237]> {
861  let Latency = 3;
862  let NumMicroOps = 3;
863  let ResourceCycles = [1,1,1];
864}
865def: InstRW<[SKLWriteResGroup43], (instrs FNSTSWm)>;
866
867def SKLWriteResGroup45 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort237,SKLPort0156]> {
868  let Latency = 3;
869  let NumMicroOps = 4;
870  let ResourceCycles = [1,1,1,1];
871}
872def: InstRW<[SKLWriteResGroup45], (instregex "CALL(16|32|64)r")>;
873
874def SKLWriteResGroup46 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort06,SKLPort0156]> {
875  let Latency = 3;
876  let NumMicroOps = 4;
877  let ResourceCycles = [1,1,1,1];
878}
879def: InstRW<[SKLWriteResGroup46], (instrs CALL64pcrel32)>;
880
881def SKLWriteResGroup47 : SchedWriteRes<[SKLPort0]> {
882  let Latency = 4;
883  let NumMicroOps = 1;
884  let ResourceCycles = [1];
885}
886def: InstRW<[SKLWriteResGroup47], (instregex "MUL_(FPrST0|FST0r|FrST0)")>;
887
888def SKLWriteResGroup48 : SchedWriteRes<[SKLPort01]> {
889  let Latency = 4;
890  let NumMicroOps = 1;
891  let ResourceCycles = [1];
892}
893def: InstRW<[SKLWriteResGroup48], (instregex "(V?)CVTDQ2PS(Y?)rr",
894                                             "(V?)CVT(T?)PS2DQ(Y?)rr")>;
895
896def SKLWriteResGroup53 : SchedWriteRes<[SKLPort4,SKLPort5,SKLPort237]> {
897  let Latency = 4;
898  let NumMicroOps = 3;
899  let ResourceCycles = [1,1,1];
900}
901def: InstRW<[SKLWriteResGroup53], (instregex "IST(T?)_FP(16|32|64)m",
902                                             "IST_F(16|32)m")>;
903
904def SKLWriteResGroup54 : SchedWriteRes<[SKLPort0156]> {
905  let Latency = 4;
906  let NumMicroOps = 4;
907  let ResourceCycles = [4];
908}
909def: InstRW<[SKLWriteResGroup54], (instrs FNCLEX)>;
910
911def SKLWriteResGroup55 : SchedWriteRes<[SKLPort6,SKLPort0156]> {
912  let Latency = 4;
913  let NumMicroOps = 4;
914  let ResourceCycles = [1,3];
915}
916def: InstRW<[SKLWriteResGroup55], (instrs PAUSE)>;
917
918def SKLWriteResGroup56 : SchedWriteRes<[]> {
919  let Latency = 0;
920  let NumMicroOps = 4;
921  let ResourceCycles = [];
922}
923def: InstRW<[SKLWriteResGroup56], (instrs VZEROUPPER)>;
924
925def SKLWriteResGroup57 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort0156]> {
926  let Latency = 4;
927  let NumMicroOps = 4;
928  let ResourceCycles = [1,1,2];
929}
930def: InstRW<[SKLWriteResGroup57], (instregex "LAR(16|32|64)rr")>;
931
932def SKLWriteResGroup58 : SchedWriteRes<[SKLPort23]> {
933  let Latency = 5;
934  let NumMicroOps = 1;
935  let ResourceCycles = [1];
936}
937def: InstRW<[SKLWriteResGroup58], (instregex "MOVSX(16|32|64)rm(8|16|32)",
938                                             "MOVZX(16|32|64)rm(8|16)")>;
939
940def SKLWriteResGroup59 : SchedWriteRes<[SKLPort0,SKLPort5]> {
941  let Latency = 5;
942  let NumMicroOps = 2;
943  let ResourceCycles = [1,1];
944}
945def: InstRW<[SKLWriteResGroup59], (instrs MMX_CVTPI2PDrr,
946                                          CVTDQ2PDrr,
947                                          VCVTDQ2PDrr)>;
948
949def SKLWriteResGroup60 : SchedWriteRes<[SKLPort5,SKLPort015]> {
950  let Latency = 5;
951  let NumMicroOps = 2;
952  let ResourceCycles = [1,1];
953}
954def: InstRW<[SKLWriteResGroup60], (instregex "MMX_CVT(T?)PD2PIrr",
955                                             "MMX_CVT(T?)PS2PIrr",
956                                             "(V?)CVT(T?)PD2DQrr",
957                                             "(V?)CVTPD2PSrr",
958                                             "(V?)CVTPS2PDrr",
959                                             "(V?)CVTSD2SSrr",
960                                             "(V?)CVTSI642SDrr",
961                                             "(V?)CVTSI2SDrr",
962                                             "(V?)CVTSI2SSrr",
963                                             "(V?)CVTSS2SDrr")>;
964
965def SKLWriteResGroup61 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort06]> {
966  let Latency = 5;
967  let NumMicroOps = 3;
968  let ResourceCycles = [1,1,1];
969}
970def: InstRW<[SKLWriteResGroup61], (instregex "STR(16|32|64)r")>;
971
972def SKLWriteResGroup63 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
973  let Latency = 5;
974  let NumMicroOps = 5;
975  let ResourceCycles = [1,4];
976}
977def: InstRW<[SKLWriteResGroup63], (instrs XSETBV)>;
978
979def SKLWriteResGroup65 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort0156]> {
980  let Latency = 5;
981  let NumMicroOps = 6;
982  let ResourceCycles = [1,1,4];
983}
984def: InstRW<[SKLWriteResGroup65], (instregex "PUSHF(16|64)")>;
985
986def SKLWriteResGroup67 : SchedWriteRes<[SKLPort23]> {
987  let Latency = 6;
988  let NumMicroOps = 1;
989  let ResourceCycles = [1];
990}
991def: InstRW<[SKLWriteResGroup67], (instrs VBROADCASTSSrm,
992                                          VPBROADCASTDrm,
993                                          VPBROADCASTQrm)>;
994def: InstRW<[SKLWriteResGroup67], (instregex "(V?)MOVSHDUPrm",
995                                             "(V?)MOVSLDUPrm",
996                                             "(V?)MOVDDUPrm")>;
997
998def SKLWriteResGroup68 : SchedWriteRes<[SKLPort0]> {
999  let Latency = 6;
1000  let NumMicroOps = 2;
1001  let ResourceCycles = [2];
1002}
1003def: InstRW<[SKLWriteResGroup68], (instrs MMX_CVTPI2PSrr)>;
1004
1005def SKLWriteResGroup69 : SchedWriteRes<[SKLPort0,SKLPort23]> {
1006  let Latency = 6;
1007  let NumMicroOps = 2;
1008  let ResourceCycles = [1,1];
1009}
1010def: InstRW<[SKLWriteResGroup69], (instrs MMX_PADDSBrm,
1011                                          MMX_PADDSWrm,
1012                                          MMX_PADDUSBrm,
1013                                          MMX_PADDUSWrm,
1014                                          MMX_PAVGBrm,
1015                                          MMX_PAVGWrm,
1016                                          MMX_PCMPEQBrm,
1017                                          MMX_PCMPEQDrm,
1018                                          MMX_PCMPEQWrm,
1019                                          MMX_PCMPGTBrm,
1020                                          MMX_PCMPGTDrm,
1021                                          MMX_PCMPGTWrm,
1022                                          MMX_PMAXSWrm,
1023                                          MMX_PMAXUBrm,
1024                                          MMX_PMINSWrm,
1025                                          MMX_PMINUBrm,
1026                                          MMX_PSUBSBrm,
1027                                          MMX_PSUBSWrm,
1028                                          MMX_PSUBUSBrm,
1029                                          MMX_PSUBUSWrm)>;
1030
1031def SKLWriteResGroup70 : SchedWriteRes<[SKLPort0,SKLPort01]> {
1032  let Latency = 6;
1033  let NumMicroOps = 2;
1034  let ResourceCycles = [1,1];
1035}
1036def: InstRW<[SKLWriteResGroup70], (instregex "(V?)CVTSS2SI(64)?rr",
1037                                             "(V?)CVT(T?)SD2SI(64)?rr")>;
1038
1039def SKLWriteResGroup72 : SchedWriteRes<[SKLPort6,SKLPort23]> {
1040  let Latency = 6;
1041  let NumMicroOps = 2;
1042  let ResourceCycles = [1,1];
1043}
1044def: InstRW<[SKLWriteResGroup72], (instrs FARJMP64m)>;
1045def: InstRW<[SKLWriteResGroup72], (instregex "JMP(16|32|64)m")>;
1046
1047def SKLWriteResGroup75 : SchedWriteRes<[SKLPort23,SKLPort15]> {
1048  let Latency = 6;
1049  let NumMicroOps = 2;
1050  let ResourceCycles = [1,1];
1051}
1052def: InstRW<[SKLWriteResGroup75], (instregex "ANDN(32|64)rm",
1053                                             "MOVBE(16|32|64)rm")>;
1054
1055def SKLWriteResGroup76 : SchedWriteRes<[SKLPort23,SKLPort0156]> {
1056  let Latency = 6;
1057  let NumMicroOps = 2;
1058  let ResourceCycles = [1,1];
1059}
1060def: InstRW<[SKLWriteResGroup76], (instrs POP16r, POP32r, POP64r)>;
1061def: InstRW<[SKLWriteResGroup76], (instregex "POP(16|32|64)rmr")>;
1062
1063def SKLWriteResGroup78 : SchedWriteRes<[SKLPort5,SKLPort01]> {
1064  let Latency = 6;
1065  let NumMicroOps = 3;
1066  let ResourceCycles = [2,1];
1067}
1068def: InstRW<[SKLWriteResGroup78], (instregex "(V?)CVTSI642SSrr")>;
1069
1070def SKLWriteResGroup80 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort06,SKLPort0156]> {
1071  let Latency = 6;
1072  let NumMicroOps = 4;
1073  let ResourceCycles = [1,1,1,1];
1074}
1075def: InstRW<[SKLWriteResGroup80], (instregex "SLDT(16|32|64)r")>;
1076
1077def SKLWriteResGroup82 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> {
1078  let Latency = 6;
1079  let NumMicroOps = 4;
1080  let ResourceCycles = [1,1,1,1];
1081}
1082def: InstRW<[SKLWriteResGroup82], (instregex "SAR(8|16|32|64)m(1|i)",
1083                                             "SHL(8|16|32|64)m(1|i)",
1084                                             "SHR(8|16|32|64)m(1|i)")>;
1085
1086def SKLWriteResGroup83 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort0156]> {
1087  let Latency = 6;
1088  let NumMicroOps = 4;
1089  let ResourceCycles = [1,1,1,1];
1090}
1091def: InstRW<[SKLWriteResGroup83], (instregex "POP(16|32|64)rmm",
1092                                             "PUSH(16|32|64)rmm")>;
1093
1094def SKLWriteResGroup84 : SchedWriteRes<[SKLPort6,SKLPort0156]> {
1095  let Latency = 6;
1096  let NumMicroOps = 6;
1097  let ResourceCycles = [1,5];
1098}
1099def: InstRW<[SKLWriteResGroup84], (instrs STD)>;
1100
1101def SKLWriteResGroup85 : SchedWriteRes<[SKLPort23]> {
1102  let Latency = 7;
1103  let NumMicroOps = 1;
1104  let ResourceCycles = [1];
1105}
1106def: InstRW<[SKLWriteResGroup85], (instregex "LD_F(32|64|80)m")>;
1107def: InstRW<[SKLWriteResGroup85], (instrs VBROADCASTF128,
1108                                          VBROADCASTI128,
1109                                          VBROADCASTSDYrm,
1110                                          VBROADCASTSSYrm,
1111                                          VMOVDDUPYrm,
1112                                          VMOVSHDUPYrm,
1113                                          VMOVSLDUPYrm,
1114                                          VPBROADCASTDYrm,
1115                                          VPBROADCASTQYrm)>;
1116
1117def SKLWriteResGroup86 : SchedWriteRes<[SKLPort0,SKLPort5]> {
1118  let Latency = 7;
1119  let NumMicroOps = 2;
1120  let ResourceCycles = [1,1];
1121}
1122def: InstRW<[SKLWriteResGroup86], (instrs VCVTDQ2PDYrr)>;
1123
1124def SKLWriteResGroup88 : SchedWriteRes<[SKLPort5,SKLPort23]> {
1125  let Latency = 6;
1126  let NumMicroOps = 2;
1127  let ResourceCycles = [1,1];
1128}
1129def: InstRW<[SKLWriteResGroup88], (instregex "(V?)PMOV(SX|ZX)BDrm",
1130                                             "(V?)PMOV(SX|ZX)BQrm",
1131                                             "(V?)PMOV(SX|ZX)BWrm",
1132                                             "(V?)PMOV(SX|ZX)DQrm",
1133                                             "(V?)PMOV(SX|ZX)WDrm",
1134                                             "(V?)PMOV(SX|ZX)WQrm")>;
1135
1136def SKLWriteResGroup89 : SchedWriteRes<[SKLPort5,SKLPort01]> {
1137  let Latency = 7;
1138  let NumMicroOps = 2;
1139  let ResourceCycles = [1,1];
1140}
1141def: InstRW<[SKLWriteResGroup89], (instrs VCVTPD2PSYrr,
1142                                          VCVTPS2PDYrr,
1143                                          VCVTPD2DQYrr,
1144                                          VCVTTPD2DQYrr)>;
1145
1146def SKLWriteResGroup91 : SchedWriteRes<[SKLPort23,SKLPort015]> {
1147  let Latency = 7;
1148  let NumMicroOps = 2;
1149  let ResourceCycles = [1,1];
1150}
1151def: InstRW<[SKLWriteResGroup91], (instrs VINSERTF128rm,
1152                                          VINSERTI128rm,
1153                                          VPBLENDDrmi)>;
1154def: InstRW<[SKLWriteResGroup91, ReadAfterVecXLd],
1155                                  (instregex "(V?)PADD(B|D|Q|W)rm",
1156                                             "(V?)PSUB(B|D|Q|W)rm")>;
1157
1158def SKLWriteResGroup92 : SchedWriteRes<[SKLPort5,SKLPort23]> {
1159  let Latency = 7;
1160  let NumMicroOps = 3;
1161  let ResourceCycles = [2,1];
1162}
1163def: InstRW<[SKLWriteResGroup92], (instrs MMX_PACKSSDWrm,
1164                                          MMX_PACKSSWBrm,
1165                                          MMX_PACKUSWBrm)>;
1166
1167def SKLWriteResGroup94 : SchedWriteRes<[SKLPort23,SKLPort0156]> {
1168  let Latency = 7;
1169  let NumMicroOps = 3;
1170  let ResourceCycles = [1,2];
1171}
1172def: InstRW<[SKLWriteResGroup94], (instrs LEAVE, LEAVE64,
1173                                          SCASB, SCASL, SCASQ, SCASW)>;
1174
1175def SKLWriteResGroup95 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort01]> {
1176  let Latency = 7;
1177  let NumMicroOps = 3;
1178  let ResourceCycles = [1,1,1];
1179}
1180def: InstRW<[SKLWriteResGroup95], (instregex "(V?)CVTTSS2SI(64)?rr")>;
1181
1182def SKLWriteResGroup96 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort05]> {
1183  let Latency = 7;
1184  let NumMicroOps = 3;
1185  let ResourceCycles = [1,1,1];
1186}
1187def: InstRW<[SKLWriteResGroup96], (instrs FLDCW16m)>;
1188
1189def SKLWriteResGroup98 : SchedWriteRes<[SKLPort6,SKLPort23,SKLPort0156]> {
1190  let Latency = 7;
1191  let NumMicroOps = 3;
1192  let ResourceCycles = [1,1,1];
1193}
1194def: InstRW<[SKLWriteResGroup98], (instrs LRET64, RET64)>;
1195
1196def SKLWriteResGroup100 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> {
1197  let Latency = 7;
1198  let NumMicroOps = 5;
1199  let ResourceCycles = [1,1,1,2];
1200}
1201def: InstRW<[SKLWriteResGroup100], (instregex "ROL(8|16|32|64)m(1|i)",
1202                                              "ROR(8|16|32|64)m(1|i)")>;
1203
1204def SKLWriteResGroup100_1 : SchedWriteRes<[SKLPort06]> {
1205  let Latency = 2;
1206  let NumMicroOps = 2;
1207  let ResourceCycles = [2];
1208}
1209def: InstRW<[SKLWriteResGroup100_1], (instrs ROL8r1, ROL16r1, ROL32r1, ROL64r1,
1210                                             ROR8r1, ROR16r1, ROR32r1, ROR64r1)>;
1211
1212def SKLWriteResGroup101 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort0156]> {
1213  let Latency = 7;
1214  let NumMicroOps = 5;
1215  let ResourceCycles = [1,1,1,2];
1216}
1217def: InstRW<[SKLWriteResGroup101], (instregex "XADD(8|16|32|64)rm")>;
1218
1219def SKLWriteResGroup102 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> {
1220  let Latency = 7;
1221  let NumMicroOps = 5;
1222  let ResourceCycles = [1,1,1,1,1];
1223}
1224def: InstRW<[SKLWriteResGroup102], (instregex "CALL(16|32|64)m")>;
1225def: InstRW<[SKLWriteResGroup102], (instrs FARCALL64m)>;
1226
1227def SKLWriteResGroup103 : SchedWriteRes<[SKLPort6,SKLPort06,SKLPort15,SKLPort0156]> {
1228  let Latency = 7;
1229  let NumMicroOps = 7;
1230  let ResourceCycles = [1,3,1,2];
1231}
1232def: InstRW<[SKLWriteResGroup103], (instrs LOOP)>;
1233
1234def SKLWriteResGroup107 : SchedWriteRes<[SKLPort1,SKLPort23]> {
1235  let Latency = 8;
1236  let NumMicroOps = 2;
1237  let ResourceCycles = [1,1];
1238}
1239def: InstRW<[SKLWriteResGroup107], (instregex "PDEP(32|64)rm",
1240                                              "PEXT(32|64)rm")>;
1241
1242def SKLWriteResGroup108 : SchedWriteRes<[SKLPort5,SKLPort23]> {
1243  let Latency = 8;
1244  let NumMicroOps = 2;
1245  let ResourceCycles = [1,1];
1246}
1247def: InstRW<[SKLWriteResGroup108], (instregex "FCOM(P?)(32|64)m")>;
1248def: InstRW<[SKLWriteResGroup108], (instrs VPBROADCASTBYrm,
1249                                           VPBROADCASTWYrm,
1250                                           VPMOVSXBDYrm,
1251                                           VPMOVSXBQYrm,
1252                                           VPMOVSXWQYrm)>;
1253
1254def SKLWriteResGroup110 : SchedWriteRes<[SKLPort23,SKLPort015]> {
1255  let Latency = 8;
1256  let NumMicroOps = 2;
1257  let ResourceCycles = [1,1];
1258}
1259def: InstRW<[SKLWriteResGroup110], (instrs VPBLENDDYrmi)>;
1260def: InstRW<[SKLWriteResGroup110, ReadAfterVecYLd],
1261                                   (instregex "VPADD(B|D|Q|W)Yrm",
1262                                              "VPSUB(B|D|Q|W)Yrm")>;
1263
1264def SKLWriteResGroup112 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
1265  let Latency = 8;
1266  let NumMicroOps = 4;
1267  let ResourceCycles = [1,2,1];
1268}
1269def: InstRW<[SKLWriteResGroup112], (instregex "MMX_PH(ADD|SUB)SWrm")>;
1270
1271def SKLWriteResGroup116 : SchedWriteRes<[SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
1272  let Latency = 8;
1273  let NumMicroOps = 5;
1274  let ResourceCycles = [1,1,1,2];
1275}
1276def: InstRW<[SKLWriteResGroup116], (instregex "RCL(8|16|32|64)m(1|i)",
1277                                              "RCR(8|16|32|64)m(1|i)")>;
1278
1279def SKLWriteResGroup117 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> {
1280  let Latency = 8;
1281  let NumMicroOps = 6;
1282  let ResourceCycles = [1,1,1,3];
1283}
1284def: InstRW<[SKLWriteResGroup117], (instregex "ROL(8|16|32|64)mCL",
1285                                              "ROR(8|16|32|64)mCL",
1286                                              "SAR(8|16|32|64)mCL",
1287                                              "SHL(8|16|32|64)mCL",
1288                                              "SHR(8|16|32|64)mCL")>;
1289
1290def SKLWriteResGroup119 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
1291  let Latency = 8;
1292  let NumMicroOps = 6;
1293  let ResourceCycles = [1,1,1,2,1];
1294}
1295def: SchedAlias<WriteADCRMW, SKLWriteResGroup119>;
1296
1297def SKLWriteResGroup120 : SchedWriteRes<[SKLPort0,SKLPort23]> {
1298  let Latency = 9;
1299  let NumMicroOps = 2;
1300  let ResourceCycles = [1,1];
1301}
1302def: InstRW<[SKLWriteResGroup120], (instrs MMX_CVTPI2PSrm)>;
1303
1304def SKLWriteResGroup121 : SchedWriteRes<[SKLPort5,SKLPort23]> {
1305  let Latency = 9;
1306  let NumMicroOps = 2;
1307  let ResourceCycles = [1,1];
1308}
1309def: InstRW<[SKLWriteResGroup121], (instrs PCMPGTQrm,
1310                                           VPCMPGTQrm,
1311                                           VPMOVSXBWYrm,
1312                                           VPMOVSXDQYrm,
1313                                           VPMOVSXWDYrm,
1314                                           VPMOVZXWDYrm)>;
1315
1316def SKLWriteResGroup123 : SchedWriteRes<[SKLPort23,SKLPort01]> {
1317  let Latency = 9;
1318  let NumMicroOps = 2;
1319  let ResourceCycles = [1,1];
1320}
1321def: InstRW<[SKLWriteResGroup123], (instregex "MMX_CVT(T?)PS2PIrm",
1322                                              "(V?)CVTPS2PDrm")>;
1323
1324def SKLWriteResGroup128 : SchedWriteRes<[SKLPort5,SKLPort01,SKLPort23]> {
1325  let Latency = 9;
1326  let NumMicroOps = 4;
1327  let ResourceCycles = [2,1,1];
1328}
1329def: InstRW<[SKLWriteResGroup128], (instregex "(V?)PHADDSWrm",
1330                                              "(V?)PHSUBSWrm")>;
1331
1332def SKLWriteResGroup131 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort23,SKLPort0156]> {
1333  let Latency = 9;
1334  let NumMicroOps = 5;
1335  let ResourceCycles = [1,2,1,1];
1336}
1337def: InstRW<[SKLWriteResGroup131], (instregex "LAR(16|32|64)rm",
1338                                              "LSL(16|32|64)rm")>;
1339
1340def SKLWriteResGroup133 : SchedWriteRes<[SKLPort5,SKLPort23]> {
1341  let Latency = 10;
1342  let NumMicroOps = 2;
1343  let ResourceCycles = [1,1];
1344}
1345def: InstRW<[SKLWriteResGroup133], (instregex "(ADD|SUB|SUBR)_F(32|64)m",
1346                                              "ILD_F(16|32|64)m")>;
1347def: InstRW<[SKLWriteResGroup133], (instrs VPCMPGTQYrm)>;
1348
1349def SKLWriteResGroup134 : SchedWriteRes<[SKLPort01,SKLPort23]> {
1350  let Latency = 10;
1351  let NumMicroOps = 2;
1352  let ResourceCycles = [1,1];
1353}
1354def: InstRW<[SKLWriteResGroup134], (instregex "(V?)CVTDQ2PSrm",
1355                                              "(V?)CVTPS2DQrm",
1356                                              "(V?)CVTSS2SDrm",
1357                                              "(V?)CVTTPS2DQrm")>;
1358
1359def SKLWriteResGroup138 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
1360  let Latency = 10;
1361  let NumMicroOps = 3;
1362  let ResourceCycles = [1,1,1];
1363}
1364def: InstRW<[SKLWriteResGroup138], (instrs MMX_CVTPI2PDrm)>;
1365
1366def SKLWriteResGroup139 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort01]> {
1367  let Latency = 10;
1368  let NumMicroOps = 3;
1369  let ResourceCycles = [1,1,1];
1370}
1371def: InstRW<[SKLWriteResGroup139], (instregex "(V?)CVTSD2SSrm")>;
1372
1373def SKLWriteResGroup140 : SchedWriteRes<[SKLPort5,SKLPort01,SKLPort23]> {
1374  let Latency = 10;
1375  let NumMicroOps = 4;
1376  let ResourceCycles = [2,1,1];
1377}
1378def: InstRW<[SKLWriteResGroup140], (instrs VPHADDSWYrm,
1379                                           VPHSUBSWYrm)>;
1380
1381def SKLWriteResGroup143 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
1382  let Latency = 10;
1383  let NumMicroOps = 8;
1384  let ResourceCycles = [1,1,1,1,1,3];
1385}
1386def: InstRW<[SKLWriteResGroup143], (instregex "XCHG(8|16|32|64)rm")>;
1387
1388def SKLWriteResGroup145 : SchedWriteRes<[SKLPort0,SKLFPDivider]> {
1389  let Latency = 11;
1390  let NumMicroOps = 1;
1391  let ResourceCycles = [1,3];
1392}
1393def : SchedAlias<WriteFDivX, SKLWriteResGroup145>; // TODO - convert to ZnWriteResFpuPair
1394
1395def SKLWriteResGroup146 : SchedWriteRes<[SKLPort0,SKLPort23]> {
1396  let Latency = 11;
1397  let NumMicroOps = 2;
1398  let ResourceCycles = [1,1];
1399}
1400def: InstRW<[SKLWriteResGroup146], (instregex "MUL_F(32|64)m")>;
1401
1402def SKLWriteResGroup147 : SchedWriteRes<[SKLPort01,SKLPort23]> {
1403  let Latency = 11;
1404  let NumMicroOps = 2;
1405  let ResourceCycles = [1,1];
1406}
1407def: InstRW<[SKLWriteResGroup147], (instrs VCVTDQ2PSYrm,
1408                                           VCVTPS2PDYrm,
1409                                           VCVTPS2DQYrm,
1410                                           VCVTTPS2DQYrm)>;
1411
1412def SKLWriteResGroup149 : SchedWriteRes<[SKLPort5,SKLPort23]> {
1413  let Latency = 11;
1414  let NumMicroOps = 3;
1415  let ResourceCycles = [2,1];
1416}
1417def: InstRW<[SKLWriteResGroup149], (instregex "FICOM(P?)(16|32)m")>;
1418
1419def SKLWriteResGroup150 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
1420  let Latency = 11;
1421  let NumMicroOps = 3;
1422  let ResourceCycles = [1,1,1];
1423}
1424def: InstRW<[SKLWriteResGroup150], (instregex "(V?)CVTDQ2PDrm")>;
1425
1426def SKLWriteResGroup151 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort01]> {
1427  let Latency = 11;
1428  let NumMicroOps = 3;
1429  let ResourceCycles = [1,1,1];
1430}
1431def: InstRW<[SKLWriteResGroup151], (instregex "(V?)CVTSS2SI64rm",
1432                                              "(V?)CVT(T?)SD2SI(64)?rm",
1433                                              "VCVTTSS2SI64rm",
1434                                              "(V?)CVT(T?)SS2SIrm")>;
1435
1436def SKLWriteResGroup152 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort01]> {
1437  let Latency = 11;
1438  let NumMicroOps = 3;
1439  let ResourceCycles = [1,1,1];
1440}
1441def: InstRW<[SKLWriteResGroup152], (instrs CVTPD2PSrm,
1442                                           CVTPD2DQrm,
1443                                           CVTTPD2DQrm,
1444                                           MMX_CVTPD2PIrm,
1445                                           MMX_CVTTPD2PIrm)>;
1446
1447def SKLWriteResGroup154 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort0156]> {
1448  let Latency = 11;
1449  let NumMicroOps = 7;
1450  let ResourceCycles = [2,3,2];
1451}
1452def: InstRW<[SKLWriteResGroup154], (instregex "RCL(16|32|64)rCL",
1453                                              "RCR(16|32|64)rCL")>;
1454
1455def SKLWriteResGroup155 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort15,SKLPort0156]> {
1456  let Latency = 11;
1457  let NumMicroOps = 9;
1458  let ResourceCycles = [1,5,1,2];
1459}
1460def: InstRW<[SKLWriteResGroup155], (instrs RCL8rCL)>;
1461
1462def SKLWriteResGroup156 : SchedWriteRes<[SKLPort06,SKLPort0156]> {
1463  let Latency = 11;
1464  let NumMicroOps = 11;
1465  let ResourceCycles = [2,9];
1466}
1467def: InstRW<[SKLWriteResGroup156], (instrs LOOPE, LOOPNE)>;
1468
1469def SKLWriteResGroup160 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23,SKLPort01]> {
1470  let Latency = 12;
1471  let NumMicroOps = 4;
1472  let ResourceCycles = [1,1,1,1];
1473}
1474def: InstRW<[SKLWriteResGroup160], (instregex "CVTTSS2SI64rm")>;
1475
1476def SKLWriteResGroup162 : SchedWriteRes<[SKLPort5,SKLPort23]> {
1477  let Latency = 13;
1478  let NumMicroOps = 3;
1479  let ResourceCycles = [2,1];
1480}
1481def: InstRW<[SKLWriteResGroup162], (instregex "(ADD|SUB|SUBR)_FI(16|32)m")>;
1482
1483def SKLWriteResGroup163 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
1484  let Latency = 13;
1485  let NumMicroOps = 3;
1486  let ResourceCycles = [1,1,1];
1487}
1488def: InstRW<[SKLWriteResGroup163], (instrs VCVTDQ2PDYrm)>;
1489
1490def SKLWriteResGroup166 : SchedWriteRes<[SKLPort0,SKLFPDivider]> {
1491  let Latency = 14;
1492  let NumMicroOps = 1;
1493  let ResourceCycles = [1,3];
1494}
1495def : SchedAlias<WriteFDiv64,  SKLWriteResGroup166>; // TODO - convert to ZnWriteResFpuPair
1496def : SchedAlias<WriteFDiv64X, SKLWriteResGroup166>; // TODO - convert to ZnWriteResFpuPair
1497
1498def SKLWriteResGroup166_1 : SchedWriteRes<[SKLPort0,SKLFPDivider]> {
1499  let Latency = 14;
1500  let NumMicroOps = 1;
1501  let ResourceCycles = [1,5];
1502}
1503def : SchedAlias<WriteFDiv64Y, SKLWriteResGroup166_1>; // TODO - convert to ZnWriteResFpuPair
1504
1505def SKLWriteResGroup169 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
1506  let Latency = 14;
1507  let NumMicroOps = 3;
1508  let ResourceCycles = [1,1,1];
1509}
1510def: InstRW<[SKLWriteResGroup169], (instregex "MUL_FI(16|32)m")>;
1511
1512def SKLWriteResGroup170 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort15,SKLPort0156]> {
1513  let Latency = 14;
1514  let NumMicroOps = 10;
1515  let ResourceCycles = [2,4,1,3];
1516}
1517def: InstRW<[SKLWriteResGroup170], (instrs RCR8rCL)>;
1518
1519def SKLWriteResGroup171 : SchedWriteRes<[SKLPort0]> {
1520  let Latency = 15;
1521  let NumMicroOps = 1;
1522  let ResourceCycles = [1];
1523}
1524def: InstRW<[SKLWriteResGroup171], (instregex "DIVR_(FPrST0|FST0r|FrST0)")>;
1525
1526def SKLWriteResGroup174 : SchedWriteRes<[SKLPort1,SKLPort23,SKLPort237,SKLPort06,SKLPort15,SKLPort0156]> {
1527  let Latency = 15;
1528  let NumMicroOps = 10;
1529  let ResourceCycles = [1,1,1,5,1,1];
1530}
1531def: InstRW<[SKLWriteResGroup174], (instregex "RCL(8|16|32|64)mCL")>;
1532
1533def SKLWriteResGroup177 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06,SKLPort15,SKLPort0156]> {
1534  let Latency = 16;
1535  let NumMicroOps = 14;
1536  let ResourceCycles = [1,1,1,4,2,5];
1537}
1538def: InstRW<[SKLWriteResGroup177], (instrs CMPXCHG8B)>;
1539
1540def SKLWriteResGroup178 : SchedWriteRes<[SKLPort0156]> {
1541  let Latency = 16;
1542  let NumMicroOps = 16;
1543  let ResourceCycles = [16];
1544}
1545def: InstRW<[SKLWriteResGroup178], (instrs VZEROALL)>;
1546
1547def SKLWriteResGroup179 : SchedWriteRes<[SKLPort0,SKLPort23,SKLFPDivider]> {
1548  let Latency = 17;
1549  let NumMicroOps = 2;
1550  let ResourceCycles = [1,1,5];
1551}
1552def : SchedAlias<WriteFDivXLd, SKLWriteResGroup179>; // TODO - convert to ZnWriteResFpuPair
1553
1554def SKLWriteResGroup180 : SchedWriteRes<[SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort05,SKLPort0156]> {
1555  let Latency = 17;
1556  let NumMicroOps = 15;
1557  let ResourceCycles = [2,1,2,4,2,4];
1558}
1559def: InstRW<[SKLWriteResGroup180], (instrs XCH_F)>;
1560
1561def SKLWriteResGroup184 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort06,SKLPort0156]> {
1562  let Latency = 18;
1563  let NumMicroOps = 8;
1564  let ResourceCycles = [1,1,1,5];
1565}
1566def: InstRW<[SKLWriteResGroup184], (instrs CPUID, RDTSC)>;
1567
1568def SKLWriteResGroup185 : SchedWriteRes<[SKLPort1,SKLPort23,SKLPort237,SKLPort06,SKLPort15,SKLPort0156]> {
1569  let Latency = 18;
1570  let NumMicroOps = 11;
1571  let ResourceCycles = [2,1,1,4,1,2];
1572}
1573def: InstRW<[SKLWriteResGroup185], (instregex "RCR(8|16|32|64)mCL")>;
1574
1575def SKLWriteResGroup186 : SchedWriteRes<[SKLPort0,SKLPort23,SKLFPDivider]> {
1576  let Latency = 19;
1577  let NumMicroOps = 2;
1578  let ResourceCycles = [1,1,4];
1579}
1580def : SchedAlias<WriteFDiv64Ld,  SKLWriteResGroup186>; // TODO - convert to ZnWriteResFpuPair
1581
1582def SKLWriteResGroup189 : SchedWriteRes<[SKLPort0]> {
1583  let Latency = 20;
1584  let NumMicroOps = 1;
1585  let ResourceCycles = [1];
1586}
1587def: InstRW<[SKLWriteResGroup189], (instregex "DIV_(FPrST0|FST0r|FrST0)")>;
1588
1589def SKLWriteResGroup190 : SchedWriteRes<[SKLPort0,SKLPort23,SKLFPDivider]> {
1590  let Latency = 20;
1591  let NumMicroOps = 2;
1592  let ResourceCycles = [1,1,4];
1593}
1594def : SchedAlias<WriteFDiv64XLd, SKLWriteResGroup190>; // TODO - convert to ZnWriteResFpuPair
1595
1596def SKLWriteResGroup192 : SchedWriteRes<[SKLPort4,SKLPort5,SKLPort6,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
1597  let Latency = 20;
1598  let NumMicroOps = 8;
1599  let ResourceCycles = [1,1,1,1,1,1,2];
1600}
1601def: InstRW<[SKLWriteResGroup192], (instrs INSB, INSL, INSW)>;
1602
1603def SKLWriteResGroup193 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort0156]> {
1604  let Latency = 20;
1605  let NumMicroOps = 10;
1606  let ResourceCycles = [1,2,7];
1607}
1608def: InstRW<[SKLWriteResGroup193], (instrs MWAITrr)>;
1609
1610def SKLWriteResGroup195 : SchedWriteRes<[SKLPort0,SKLPort23,SKLFPDivider]> {
1611  let Latency = 21;
1612  let NumMicroOps = 2;
1613  let ResourceCycles = [1,1,8];
1614}
1615def : SchedAlias<WriteFDiv64YLd, SKLWriteResGroup195>; // TODO - convert to ZnWriteResFpuPair
1616
1617def SKLWriteResGroup196 : SchedWriteRes<[SKLPort0,SKLPort23]> {
1618  let Latency = 22;
1619  let NumMicroOps = 2;
1620  let ResourceCycles = [1,1];
1621}
1622def: InstRW<[SKLWriteResGroup196], (instregex "DIV_F(32|64)m")>;
1623
1624def SKLWriteResGroupVEX2 : SchedWriteRes<[SKLPort0, SKLPort23, SKLPort5, SKLPort015]> {
1625  let Latency = 18;
1626  let NumMicroOps = 5; // 2 uops perform multiple loads
1627  let ResourceCycles = [1,2,1,1];
1628}
1629def: InstRW<[SKLWriteResGroupVEX2], (instrs VGATHERDPDrm, VPGATHERDQrm,
1630                                            VGATHERQPDrm, VPGATHERQQrm,
1631                                            VGATHERQPSrm, VPGATHERQDrm)>;
1632
1633def SKLWriteResGroupVEX4 : SchedWriteRes<[SKLPort0, SKLPort23, SKLPort5, SKLPort015]> {
1634  let Latency = 20;
1635  let NumMicroOps = 5; // 2 uops peform multiple loads
1636  let ResourceCycles = [1,4,1,1];
1637}
1638def: InstRW<[SKLWriteResGroupVEX4], (instrs VGATHERDPDYrm, VPGATHERDQYrm,
1639                                            VGATHERDPSrm,  VPGATHERDDrm,
1640                                            VGATHERQPDYrm, VPGATHERQQYrm,
1641                                            VGATHERQPSYrm,  VPGATHERQDYrm)>;
1642
1643def SKLWriteResGroupVEX8 : SchedWriteRes<[SKLPort0, SKLPort23, SKLPort5, SKLPort015]> {
1644  let Latency = 22;
1645  let NumMicroOps = 5; // 2 uops perform multiple loads
1646  let ResourceCycles = [1,8,1,1];
1647}
1648def: InstRW<[SKLWriteResGroupVEX8], (instrs VGATHERDPSYrm,  VPGATHERDDYrm)>;
1649
1650def SKLWriteResGroup198 : SchedWriteRes<[SKLPort0,SKLPort4,SKLPort5,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
1651  let Latency = 23;
1652  let NumMicroOps = 19;
1653  let ResourceCycles = [2,1,4,1,1,4,6];
1654}
1655def: InstRW<[SKLWriteResGroup198], (instrs CMPXCHG16B)>;
1656
1657def SKLWriteResGroup202 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
1658  let Latency = 25;
1659  let NumMicroOps = 3;
1660  let ResourceCycles = [1,1,1];
1661}
1662def: InstRW<[SKLWriteResGroup202], (instregex "DIV_FI(16|32)m")>;
1663
1664def SKLWriteResGroup206 : SchedWriteRes<[SKLPort0,SKLPort23]> {
1665  let Latency = 27;
1666  let NumMicroOps = 2;
1667  let ResourceCycles = [1,1];
1668}
1669def: InstRW<[SKLWriteResGroup206], (instregex "DIVR_F(32|64)m")>;
1670
1671def SKLWriteResGroup208 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> {
1672  let Latency = 30;
1673  let NumMicroOps = 3;
1674  let ResourceCycles = [1,1,1];
1675}
1676def: InstRW<[SKLWriteResGroup208], (instregex "DIVR_FI(16|32)m")>;
1677
1678def SKLWriteResGroup209 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort23,SKLPort06,SKLPort0156]> {
1679  let Latency = 35;
1680  let NumMicroOps = 23;
1681  let ResourceCycles = [1,5,3,4,10];
1682}
1683def: InstRW<[SKLWriteResGroup209], (instregex "IN(8|16|32)ri",
1684                                              "IN(8|16|32)rr")>;
1685
1686def SKLWriteResGroup210 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> {
1687  let Latency = 35;
1688  let NumMicroOps = 23;
1689  let ResourceCycles = [1,5,2,1,4,10];
1690}
1691def: InstRW<[SKLWriteResGroup210], (instregex "OUT(8|16|32)ir",
1692                                              "OUT(8|16|32)rr")>;
1693
1694def SKLWriteResGroup211 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort23,SKLPort0156]> {
1695  let Latency = 37;
1696  let NumMicroOps = 31;
1697  let ResourceCycles = [1,8,1,21];
1698}
1699def: InstRW<[SKLWriteResGroup211], (instregex "XRSTOR(64)?")>;
1700
1701def SKLWriteResGroup212 : SchedWriteRes<[SKLPort1,SKLPort4,SKLPort5,SKLPort6,SKLPort23,SKLPort237,SKLPort15,SKLPort0156]> {
1702  let Latency = 40;
1703  let NumMicroOps = 18;
1704  let ResourceCycles = [1,1,2,3,1,1,1,8];
1705}
1706def: InstRW<[SKLWriteResGroup212], (instrs VMCLEARm)>;
1707
1708def SKLWriteResGroup213 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> {
1709  let Latency = 41;
1710  let NumMicroOps = 39;
1711  let ResourceCycles = [1,10,1,1,26];
1712}
1713def: InstRW<[SKLWriteResGroup213], (instrs XSAVE64)>;
1714
1715def SKLWriteResGroup214 : SchedWriteRes<[SKLPort5,SKLPort0156]> {
1716  let Latency = 42;
1717  let NumMicroOps = 22;
1718  let ResourceCycles = [2,20];
1719}
1720def: InstRW<[SKLWriteResGroup214], (instrs RDTSCP)>;
1721
1722def SKLWriteResGroup215 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> {
1723  let Latency = 42;
1724  let NumMicroOps = 40;
1725  let ResourceCycles = [1,11,1,1,26];
1726}
1727def: InstRW<[SKLWriteResGroup215], (instrs XSAVE)>;
1728def: InstRW<[SKLWriteResGroup215], (instregex "XSAVEC", "XSAVES")>;
1729
1730def SKLWriteResGroup216 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> {
1731  let Latency = 46;
1732  let NumMicroOps = 44;
1733  let ResourceCycles = [1,11,1,1,30];
1734}
1735def: InstRW<[SKLWriteResGroup216], (instregex "XSAVEOPT")>;
1736
1737def SKLWriteResGroup217 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort05,SKLPort06,SKLPort0156]> {
1738  let Latency = 62;
1739  let NumMicroOps = 64;
1740  let ResourceCycles = [2,8,5,10,39];
1741}
1742def: InstRW<[SKLWriteResGroup217], (instrs FLDENVm)>;
1743
1744def SKLWriteResGroup218 : SchedWriteRes<[SKLPort0,SKLPort6,SKLPort23,SKLPort05,SKLPort06,SKLPort15,SKLPort0156]> {
1745  let Latency = 63;
1746  let NumMicroOps = 88;
1747  let ResourceCycles = [4,4,31,1,2,1,45];
1748}
1749def: InstRW<[SKLWriteResGroup218], (instrs FXRSTOR64)>;
1750
1751def SKLWriteResGroup219 : SchedWriteRes<[SKLPort0,SKLPort6,SKLPort23,SKLPort05,SKLPort06,SKLPort15,SKLPort0156]> {
1752  let Latency = 63;
1753  let NumMicroOps = 90;
1754  let ResourceCycles = [4,2,33,1,2,1,47];
1755}
1756def: InstRW<[SKLWriteResGroup219], (instrs FXRSTOR)>;
1757
1758def SKLWriteResGroup220 : SchedWriteRes<[SKLPort5,SKLPort05,SKLPort0156]> {
1759  let Latency = 75;
1760  let NumMicroOps = 15;
1761  let ResourceCycles = [6,3,6];
1762}
1763def: InstRW<[SKLWriteResGroup220], (instrs FNINIT)>;
1764
1765def SKLWriteResGroup223 : SchedWriteRes<[SKLPort0,SKLPort1,SKLPort4,SKLPort5,SKLPort6,SKLPort237,SKLPort06,SKLPort0156]> {
1766  let Latency = 106;
1767  let NumMicroOps = 100;
1768  let ResourceCycles = [9,1,11,16,1,11,21,30];
1769}
1770def: InstRW<[SKLWriteResGroup223], (instrs FSTENVm)>;
1771
1772def: InstRW<[WriteZero], (instrs CLC)>;
1773
1774
1775// Instruction variants handled by the renamer. These might not need execution
1776// ports in certain conditions.
1777// See Agner's Fog "The microarchitecture of Intel, AMD and VIA CPUs",
1778// section "Skylake Pipeline" > "Register allocation and renaming".
1779// These can be investigated with llvm-exegesis, e.g.
1780// echo 'pxor %mm0, %mm0' | /tmp/llvm-exegesis -mode=uops -snippets-file=-
1781// echo 'vxorpd %xmm0, %xmm0, %xmm1' | /tmp/llvm-exegesis -mode=uops -snippets-file=-
1782
1783def SKLWriteZeroLatency : SchedWriteRes<[]> {
1784  let Latency = 0;
1785}
1786
1787def SKLWriteZeroIdiom : SchedWriteVariant<[
1788    SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>,
1789    SchedVar<NoSchedPred,                          [WriteALU]>
1790]>;
1791def : InstRW<[SKLWriteZeroIdiom], (instrs SUB32rr, SUB64rr,
1792                                          XOR32rr, XOR64rr)>;
1793
1794def SKLWriteFZeroIdiom : SchedWriteVariant<[
1795    SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>,
1796    SchedVar<NoSchedPred,                          [WriteFLogic]>
1797]>;
1798def : InstRW<[SKLWriteFZeroIdiom], (instrs XORPSrr, VXORPSrr, XORPDrr,
1799                                           VXORPDrr)>;
1800
1801def SKLWriteFZeroIdiomY : SchedWriteVariant<[
1802    SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>,
1803    SchedVar<NoSchedPred,                          [WriteFLogicY]>
1804]>;
1805def : InstRW<[SKLWriteFZeroIdiomY], (instrs VXORPSYrr, VXORPDYrr)>;
1806
1807def SKLWriteVZeroIdiomLogicX : SchedWriteVariant<[
1808    SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>,
1809    SchedVar<NoSchedPred,                          [WriteVecLogicX]>
1810]>;
1811def : InstRW<[SKLWriteVZeroIdiomLogicX], (instrs PXORrr, VPXORrr)>;
1812
1813def SKLWriteVZeroIdiomLogicY : SchedWriteVariant<[
1814    SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>,
1815    SchedVar<NoSchedPred,                          [WriteVecLogicY]>
1816]>;
1817def : InstRW<[SKLWriteVZeroIdiomLogicY], (instrs VPXORYrr)>;
1818
1819def SKLWriteVZeroIdiomALUX : SchedWriteVariant<[
1820    SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>,
1821    SchedVar<NoSchedPred,                          [WriteVecALUX]>
1822]>;
1823def : InstRW<[SKLWriteVZeroIdiomALUX], (instrs PCMPGTBrr, VPCMPGTBrr,
1824                                               PCMPGTDrr, VPCMPGTDrr,
1825                                               PCMPGTWrr, VPCMPGTWrr)>;
1826
1827def SKLWriteVZeroIdiomALUY : SchedWriteVariant<[
1828    SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>,
1829    SchedVar<NoSchedPred,                          [WriteVecALUY]>
1830]>;
1831def : InstRW<[SKLWriteVZeroIdiomALUY], (instrs VPCMPGTBYrr,
1832                                               VPCMPGTDYrr,
1833                                               VPCMPGTWYrr)>;
1834
1835def SKLWritePSUB : SchedWriteRes<[SKLPort015]> {
1836  let Latency = 1;
1837  let NumMicroOps = 1;
1838  let ResourceCycles = [1];
1839}
1840
1841def SKLWriteVZeroIdiomPSUB : SchedWriteVariant<[
1842    SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>,
1843    SchedVar<NoSchedPred,                          [SKLWritePSUB]>
1844]>;
1845def : InstRW<[SKLWriteVZeroIdiomPSUB], (instrs PSUBBrr, VPSUBBrr,
1846                                               PSUBDrr, VPSUBDrr,
1847                                               PSUBQrr, VPSUBQrr,
1848                                               PSUBWrr, VPSUBWrr,
1849                                               VPSUBBYrr,
1850                                               VPSUBDYrr,
1851                                               VPSUBQYrr,
1852                                               VPSUBWYrr)>;
1853
1854def SKLWritePCMPGTQ : SchedWriteRes<[SKLPort5]> {
1855  let Latency = 3;
1856  let NumMicroOps = 1;
1857  let ResourceCycles = [1];
1858}
1859
1860def SKLWriteVZeroIdiomPCMPGTQ : SchedWriteVariant<[
1861    SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>,
1862    SchedVar<NoSchedPred,                          [SKLWritePCMPGTQ]>
1863]>;
1864def : InstRW<[SKLWriteVZeroIdiomPCMPGTQ], (instrs PCMPGTQrr, VPCMPGTQrr,
1865                                                  VPCMPGTQYrr)>;
1866
1867
1868// CMOVs that use both Z and C flag require an extra uop.
1869def SKLWriteCMOVA_CMOVBErr : SchedWriteRes<[SKLPort06]> {
1870  let Latency = 2;
1871  let ResourceCycles = [2];
1872  let NumMicroOps = 2;
1873}
1874
1875def SKLWriteCMOVA_CMOVBErm : SchedWriteRes<[SKLPort23,SKLPort06]> {
1876  let Latency = 7;
1877  let ResourceCycles = [1,2];
1878  let NumMicroOps = 3;
1879}
1880
1881def SKLCMOVA_CMOVBErr :  SchedWriteVariant<[
1882  SchedVar<MCSchedPredicate<IsCMOVArr_Or_CMOVBErr>, [SKLWriteCMOVA_CMOVBErr]>,
1883  SchedVar<NoSchedPred,                             [WriteCMOV]>
1884]>;
1885
1886def SKLCMOVA_CMOVBErm :  SchedWriteVariant<[
1887  SchedVar<MCSchedPredicate<IsCMOVArm_Or_CMOVBErm>, [SKLWriteCMOVA_CMOVBErm]>,
1888  SchedVar<NoSchedPred,                             [WriteCMOV.Folded]>
1889]>;
1890
1891def : InstRW<[SKLCMOVA_CMOVBErr], (instrs CMOV16rr, CMOV32rr, CMOV64rr)>;
1892def : InstRW<[SKLCMOVA_CMOVBErm], (instrs CMOV16rm, CMOV32rm, CMOV64rm)>;
1893
1894// SETCCs that use both Z and C flag require an extra uop.
1895def SKLWriteSETA_SETBEr : SchedWriteRes<[SKLPort06]> {
1896  let Latency = 2;
1897  let ResourceCycles = [2];
1898  let NumMicroOps = 2;
1899}
1900
1901def SKLWriteSETA_SETBEm : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort06]> {
1902  let Latency = 3;
1903  let ResourceCycles = [1,1,2];
1904  let NumMicroOps = 4;
1905}
1906
1907def SKLSETA_SETBErr :  SchedWriteVariant<[
1908  SchedVar<MCSchedPredicate<IsSETAr_Or_SETBEr>, [SKLWriteSETA_SETBEr]>,
1909  SchedVar<NoSchedPred,                         [WriteSETCC]>
1910]>;
1911
1912def SKLSETA_SETBErm :  SchedWriteVariant<[
1913  SchedVar<MCSchedPredicate<IsSETAm_Or_SETBEm>, [SKLWriteSETA_SETBEm]>,
1914  SchedVar<NoSchedPred,                         [WriteSETCCStore]>
1915]>;
1916
1917def : InstRW<[SKLSETA_SETBErr], (instrs SETCCr)>;
1918def : InstRW<[SKLSETA_SETBErm], (instrs SETCCm)>;
1919
1920///////////////////////////////////////////////////////////////////////////////
1921// Dependency breaking instructions.
1922///////////////////////////////////////////////////////////////////////////////
1923
1924def : IsZeroIdiomFunction<[
1925  // GPR Zero-idioms.
1926  DepBreakingClass<[ SUB32rr, SUB64rr, XOR32rr, XOR64rr ], ZeroIdiomPredicate>,
1927
1928  // SSE Zero-idioms.
1929  DepBreakingClass<[
1930    // fp variants.
1931    XORPSrr, XORPDrr,
1932
1933    // int variants.
1934    PXORrr,
1935    PSUBBrr, PSUBWrr, PSUBDrr, PSUBQrr,
1936    PCMPGTBrr, PCMPGTDrr, PCMPGTQrr, PCMPGTWrr
1937  ], ZeroIdiomPredicate>,
1938
1939  // AVX Zero-idioms.
1940  DepBreakingClass<[
1941    // xmm fp variants.
1942    VXORPSrr, VXORPDrr,
1943
1944    // xmm int variants.
1945    VPXORrr,
1946    VPSUBBrr, VPSUBWrr, VPSUBDrr, VPSUBQrr,
1947    VPCMPGTBrr, VPCMPGTWrr, VPCMPGTDrr, VPCMPGTQrr,
1948
1949    // ymm variants.
1950    VXORPSYrr, VXORPDYrr, VPXORYrr,
1951    VPSUBBYrr, VPSUBWYrr, VPSUBDYrr, VPSUBQYrr,
1952    VPCMPGTBYrr, VPCMPGTWYrr, VPCMPGTDYrr, VPCMPGTQYrr
1953  ], ZeroIdiomPredicate>,
1954]>;
1955
1956} // SchedModel
1957