1//=- X86SchedSkylake.td - X86 Skylake Client Scheduling ------*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the machine model for Skylake Client to support 10// instruction scheduling and other instruction cost heuristics. 11// 12//===----------------------------------------------------------------------===// 13 14def SkylakeClientModel : SchedMachineModel { 15 // All x86 instructions are modeled as a single micro-op, and SKylake can 16 // decode 6 instructions per cycle. 17 let IssueWidth = 6; 18 let MicroOpBufferSize = 224; // Based on the reorder buffer. 19 let LoadLatency = 5; 20 let MispredictPenalty = 14; 21 22 // Based on the LSD (loop-stream detector) queue size and benchmarking data. 23 let LoopMicroOpBufferSize = 50; 24 25 // This flag is set to allow the scheduler to assign a default model to 26 // unrecognized opcodes. 27 let CompleteModel = 0; 28} 29 30let SchedModel = SkylakeClientModel in { 31 32// Skylake Client can issue micro-ops to 8 different ports in one cycle. 33 34// Ports 0, 1, 5, and 6 handle all computation. 35// Port 4 gets the data half of stores. Store data can be available later than 36// the store address, but since we don't model the latency of stores, we can 37// ignore that. 38// Ports 2 and 3 are identical. They handle loads and the address half of 39// stores. Port 7 can handle address calculations. 40def SKLPort0 : ProcResource<1>; 41def SKLPort1 : ProcResource<1>; 42def SKLPort2 : ProcResource<1>; 43def SKLPort3 : ProcResource<1>; 44def SKLPort4 : ProcResource<1>; 45def SKLPort5 : ProcResource<1>; 46def SKLPort6 : ProcResource<1>; 47def SKLPort7 : ProcResource<1>; 48 49// Many micro-ops are capable of issuing on multiple ports. 50def SKLPort01 : ProcResGroup<[SKLPort0, SKLPort1]>; 51def SKLPort23 : ProcResGroup<[SKLPort2, SKLPort3]>; 52def SKLPort237 : ProcResGroup<[SKLPort2, SKLPort3, SKLPort7]>; 53def SKLPort04 : ProcResGroup<[SKLPort0, SKLPort4]>; 54def SKLPort05 : ProcResGroup<[SKLPort0, SKLPort5]>; 55def SKLPort06 : ProcResGroup<[SKLPort0, SKLPort6]>; 56def SKLPort15 : ProcResGroup<[SKLPort1, SKLPort5]>; 57def SKLPort16 : ProcResGroup<[SKLPort1, SKLPort6]>; 58def SKLPort56 : ProcResGroup<[SKLPort5, SKLPort6]>; 59def SKLPort015 : ProcResGroup<[SKLPort0, SKLPort1, SKLPort5]>; 60def SKLPort056 : ProcResGroup<[SKLPort0, SKLPort5, SKLPort6]>; 61def SKLPort0156: ProcResGroup<[SKLPort0, SKLPort1, SKLPort5, SKLPort6]>; 62 63def SKLDivider : ProcResource<1>; // Integer division issued on port 0. 64// FP division and sqrt on port 0. 65def SKLFPDivider : ProcResource<1>; 66 67// 60 Entry Unified Scheduler 68def SKLPortAny : ProcResGroup<[SKLPort0, SKLPort1, SKLPort2, SKLPort3, SKLPort4, 69 SKLPort5, SKLPort6, SKLPort7]> { 70 let BufferSize=60; 71} 72 73// Integer loads are 5 cycles, so ReadAfterLd registers needn't be available until 5 74// cycles after the memory operand. 75def : ReadAdvance<ReadAfterLd, 5>; 76 77// Vector loads are 5/6/7 cycles, so ReadAfterVec*Ld registers needn't be available 78// until 5/6/7 cycles after the memory operand. 79def : ReadAdvance<ReadAfterVecLd, 5>; 80def : ReadAdvance<ReadAfterVecXLd, 6>; 81def : ReadAdvance<ReadAfterVecYLd, 7>; 82 83def : ReadAdvance<ReadInt2Fpu, 0>; 84 85// Many SchedWrites are defined in pairs with and without a folded load. 86// Instructions with folded loads are usually micro-fused, so they only appear 87// as two micro-ops when queued in the reservation station. 88// This multiclass defines the resource usage for variants with and without 89// folded loads. 90multiclass SKLWriteResPair<X86FoldableSchedWrite SchedRW, 91 list<ProcResourceKind> ExePorts, 92 int Lat, list<int> Res = [1], int UOps = 1, 93 int LoadLat = 5> { 94 // Register variant is using a single cycle on ExePort. 95 def : WriteRes<SchedRW, ExePorts> { 96 let Latency = Lat; 97 let ResourceCycles = Res; 98 let NumMicroOps = UOps; 99 } 100 101 // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to 102 // the latency (default = 5). 103 def : WriteRes<SchedRW.Folded, !listconcat([SKLPort23], ExePorts)> { 104 let Latency = !add(Lat, LoadLat); 105 let ResourceCycles = !listconcat([1], Res); 106 let NumMicroOps = !add(UOps, 1); 107 } 108} 109 110// A folded store needs a cycle on port 4 for the store data, and an extra port 111// 2/3/7 cycle to recompute the address. 112def : WriteRes<WriteRMW, [SKLPort237,SKLPort4]>; 113 114// Arithmetic. 115defm : SKLWriteResPair<WriteALU, [SKLPort0156], 1>; // Simple integer ALU op. 116defm : SKLWriteResPair<WriteADC, [SKLPort06], 1>; // Integer ALU + flags op. 117 118// Integer multiplication. 119defm : SKLWriteResPair<WriteIMul8, [SKLPort1], 3>; 120defm : SKLWriteResPair<WriteIMul16, [SKLPort1,SKLPort06,SKLPort0156], 4, [1,1,2], 4>; 121defm : X86WriteRes<WriteIMul16Imm, [SKLPort1,SKLPort0156], 4, [1,1], 2>; 122defm : X86WriteRes<WriteIMul16ImmLd, [SKLPort1,SKLPort0156,SKLPort23], 8, [1,1,1], 3>; 123defm : SKLWriteResPair<WriteIMul16Reg, [SKLPort1], 3>; 124defm : SKLWriteResPair<WriteIMul32, [SKLPort1,SKLPort06,SKLPort0156], 4, [1,1,1], 3>; 125defm : SKLWriteResPair<WriteIMul32Imm, [SKLPort1], 3>; 126defm : SKLWriteResPair<WriteIMul32Reg, [SKLPort1], 3>; 127defm : SKLWriteResPair<WriteIMul64, [SKLPort1,SKLPort5], 4, [1,1], 2>; 128defm : SKLWriteResPair<WriteIMul64Imm, [SKLPort1], 3>; 129defm : SKLWriteResPair<WriteIMul64Reg, [SKLPort1], 3>; 130def : WriteRes<WriteIMulH, []> { let Latency = 3; } 131 132defm : X86WriteRes<WriteBSWAP32, [SKLPort15], 1, [1], 1>; 133defm : X86WriteRes<WriteBSWAP64, [SKLPort06, SKLPort15], 2, [1,1], 2>; 134defm : X86WriteRes<WriteCMPXCHG,[SKLPort06, SKLPort0156], 5, [2,3], 5>; 135defm : X86WriteRes<WriteCMPXCHGRMW,[SKLPort23,SKLPort06,SKLPort0156,SKLPort237,SKLPort4], 8, [1,2,1,1,1], 6>; 136defm : X86WriteRes<WriteXCHG, [SKLPort0156], 2, [3], 3>; 137 138// TODO: Why isn't the SKLDivider used? 139defm : SKLWriteResPair<WriteDiv8, [SKLPort0,SKLDivider], 25, [1,10], 1, 4>; 140defm : X86WriteRes<WriteDiv16, [SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort05,SKLPort0156], 76, [7,2,8,3,1,11], 32>; 141defm : X86WriteRes<WriteDiv32, [SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort05,SKLPort0156], 76, [7,2,8,3,1,11], 32>; 142defm : X86WriteRes<WriteDiv64, [SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort05,SKLPort0156], 76, [7,2,8,3,1,11], 32>; 143defm : X86WriteRes<WriteDiv16Ld, [SKLPort0,SKLPort23,SKLDivider], 29, [1,1,10], 2>; 144defm : X86WriteRes<WriteDiv32Ld, [SKLPort0,SKLPort23,SKLDivider], 29, [1,1,10], 2>; 145defm : X86WriteRes<WriteDiv64Ld, [SKLPort0,SKLPort23,SKLDivider], 29, [1,1,10], 2>; 146 147defm : X86WriteRes<WriteIDiv8, [SKLPort0,SKLDivider], 25, [1,10], 1>; 148defm : X86WriteRes<WriteIDiv16, [SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort06,SKLPort0156], 102, [4,2,4,8,14,34], 66>; 149defm : X86WriteRes<WriteIDiv32, [SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort06,SKLPort0156], 102, [4,2,4,8,14,34], 66>; 150defm : X86WriteRes<WriteIDiv64, [SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort06,SKLPort0156], 102, [4,2,4,8,14,34], 66>; 151defm : X86WriteRes<WriteIDiv8Ld, [SKLPort0,SKLPort5,SKLPort23,SKLPort0156], 28, [2,4,1,1], 8>; 152defm : X86WriteRes<WriteIDiv16Ld, [SKLPort0,SKLPort5,SKLPort23,SKLPort0156], 28, [2,4,1,1], 8>; 153defm : X86WriteRes<WriteIDiv32Ld, [SKLPort0,SKLPort5,SKLPort23,SKLPort0156], 28, [2,4,1,1], 8>; 154defm : X86WriteRes<WriteIDiv64Ld, [SKLPort0,SKLPort5,SKLPort23,SKLPort0156], 28, [2,4,1,1], 8>; 155 156defm : SKLWriteResPair<WriteCRC32, [SKLPort1], 3>; 157 158def : WriteRes<WriteLEA, [SKLPort15]>; // LEA instructions can't fold loads. 159 160defm : SKLWriteResPair<WriteCMOV, [SKLPort06], 1, [1], 1>; // Conditional move. 161defm : X86WriteRes<WriteFCMOV, [SKLPort1], 3, [1], 1>; // x87 conditional move. 162def : WriteRes<WriteSETCC, [SKLPort06]>; // Setcc. 163def : WriteRes<WriteSETCCStore, [SKLPort06,SKLPort4,SKLPort237]> { 164 let Latency = 2; 165 let NumMicroOps = 3; 166} 167 168defm : X86WriteRes<WriteLAHFSAHF, [SKLPort06], 1, [1], 1>; 169defm : X86WriteRes<WriteBitTest, [SKLPort06], 1, [1], 1>; 170defm : X86WriteRes<WriteBitTestImmLd, [SKLPort06,SKLPort23], 6, [1,1], 2>; 171defm : X86WriteRes<WriteBitTestRegLd, [SKLPort0156,SKLPort23], 6, [1,1], 2>; 172defm : X86WriteRes<WriteBitTestSet, [SKLPort06], 1, [1], 1>; 173defm : X86WriteRes<WriteBitTestSetImmLd, [SKLPort06,SKLPort23], 5, [1,1], 3>; 174defm : X86WriteRes<WriteBitTestSetRegLd, [SKLPort0156,SKLPort23], 5, [1,1], 2>; 175 176// Bit counts. 177defm : SKLWriteResPair<WriteBSF, [SKLPort1], 3>; 178defm : SKLWriteResPair<WriteBSR, [SKLPort1], 3>; 179defm : SKLWriteResPair<WriteLZCNT, [SKLPort1], 3>; 180defm : SKLWriteResPair<WriteTZCNT, [SKLPort1], 3>; 181defm : SKLWriteResPair<WritePOPCNT, [SKLPort1], 3>; 182 183// Integer shifts and rotates. 184defm : SKLWriteResPair<WriteShift, [SKLPort06], 1>; 185defm : SKLWriteResPair<WriteShiftCL, [SKLPort06], 3, [3], 3>; 186defm : SKLWriteResPair<WriteRotate, [SKLPort06], 1, [1], 1>; 187defm : SKLWriteResPair<WriteRotateCL, [SKLPort06], 3, [3], 3>; 188 189// SHLD/SHRD. 190defm : X86WriteRes<WriteSHDrri, [SKLPort1], 3, [1], 1>; 191defm : X86WriteRes<WriteSHDrrcl,[SKLPort1,SKLPort06,SKLPort0156], 6, [1, 2, 1], 4>; 192defm : X86WriteRes<WriteSHDmri, [SKLPort1,SKLPort23,SKLPort237,SKLPort0156], 9, [1, 1, 1, 1], 4>; 193defm : X86WriteRes<WriteSHDmrcl,[SKLPort1,SKLPort23,SKLPort237,SKLPort06,SKLPort0156], 11, [1, 1, 1, 2, 1], 6>; 194 195// BMI1 BEXTR/BLS, BMI2 BZHI 196defm : SKLWriteResPair<WriteBEXTR, [SKLPort06,SKLPort15], 2, [1,1], 2>; 197defm : SKLWriteResPair<WriteBLS, [SKLPort15], 1>; 198defm : SKLWriteResPair<WriteBZHI, [SKLPort15], 1>; 199 200// Loads, stores, and moves, not folded with other operations. 201defm : X86WriteRes<WriteLoad, [SKLPort23], 5, [1], 1>; 202defm : X86WriteRes<WriteStore, [SKLPort237, SKLPort4], 1, [1,1], 1>; 203defm : X86WriteRes<WriteStoreNT, [SKLPort237, SKLPort4], 1, [1,1], 2>; 204defm : X86WriteRes<WriteMove, [SKLPort0156], 1, [1], 1>; 205 206// Model the effect of clobbering the read-write mask operand of the GATHER operation. 207// Does not cost anything by itself, only has latency, matching that of the WriteLoad, 208defm : X86WriteRes<WriteVecMaskedGatherWriteback, [], 5, [], 0>; 209 210// Idioms that clear a register, like xorps %xmm0, %xmm0. 211// These can often bypass execution ports completely. 212def : WriteRes<WriteZero, []>; 213 214// Branches don't produce values, so they have no latency, but they still 215// consume resources. Indirect branches can fold loads. 216defm : SKLWriteResPair<WriteJump, [SKLPort06], 1>; 217 218// Floating point. This covers both scalar and vector operations. 219defm : X86WriteRes<WriteFLD0, [SKLPort05], 1, [1], 1>; 220defm : X86WriteRes<WriteFLD1, [SKLPort05], 1, [2], 2>; 221defm : X86WriteRes<WriteFLDC, [SKLPort05], 1, [2], 2>; 222defm : X86WriteRes<WriteFLoad, [SKLPort23], 5, [1], 1>; 223defm : X86WriteRes<WriteFLoadX, [SKLPort23], 6, [1], 1>; 224defm : X86WriteRes<WriteFLoadY, [SKLPort23], 7, [1], 1>; 225defm : X86WriteRes<WriteFMaskedLoad, [SKLPort23,SKLPort015], 7, [1,1], 2>; 226defm : X86WriteRes<WriteFMaskedLoadY, [SKLPort23,SKLPort015], 8, [1,1], 2>; 227defm : X86WriteRes<WriteFStore, [SKLPort237,SKLPort4], 1, [1,1], 2>; 228defm : X86WriteRes<WriteFStoreX, [SKLPort237,SKLPort4], 1, [1,1], 2>; 229defm : X86WriteRes<WriteFStoreY, [SKLPort237,SKLPort4], 1, [1,1], 2>; 230defm : X86WriteRes<WriteFStoreNT, [SKLPort237,SKLPort4], 1, [1,1], 2>; 231defm : X86WriteRes<WriteFStoreNTX, [SKLPort237,SKLPort4], 1, [1,1], 2>; 232defm : X86WriteRes<WriteFStoreNTY, [SKLPort237,SKLPort4], 1, [1,1], 2>; 233 234defm : X86WriteRes<WriteFMaskedStore32, [SKLPort237,SKLPort0], 2, [1,1], 2>; 235defm : X86WriteRes<WriteFMaskedStore32Y, [SKLPort237,SKLPort0], 2, [1,1], 2>; 236defm : X86WriteRes<WriteFMaskedStore64, [SKLPort237,SKLPort0], 2, [1,1], 2>; 237defm : X86WriteRes<WriteFMaskedStore64Y, [SKLPort237,SKLPort0], 2, [1,1], 2>; 238 239defm : X86WriteRes<WriteFMove, [SKLPort015], 1, [1], 1>; 240defm : X86WriteRes<WriteFMoveX, [SKLPort015], 1, [1], 1>; 241defm : X86WriteRes<WriteFMoveY, [SKLPort015], 1, [1], 1>; 242defm : X86WriteRes<WriteEMMS, [SKLPort05,SKLPort0156], 10, [9,1], 10>; 243 244defm : SKLWriteResPair<WriteFAdd, [SKLPort01], 4, [1], 1, 5>; // Floating point add/sub. 245defm : SKLWriteResPair<WriteFAddX, [SKLPort01], 4, [1], 1, 6>; 246defm : SKLWriteResPair<WriteFAddY, [SKLPort01], 4, [1], 1, 7>; 247defm : X86WriteResPairUnsupported<WriteFAddZ>; 248defm : SKLWriteResPair<WriteFAdd64, [SKLPort01], 4, [1], 1, 5>; // Floating point double add/sub. 249defm : SKLWriteResPair<WriteFAdd64X, [SKLPort01], 4, [1], 1, 6>; 250defm : SKLWriteResPair<WriteFAdd64Y, [SKLPort01], 4, [1], 1, 7>; 251defm : X86WriteResPairUnsupported<WriteFAdd64Z>; 252 253defm : SKLWriteResPair<WriteFCmp, [SKLPort01], 4, [1], 1, 5>; // Floating point compare. 254defm : SKLWriteResPair<WriteFCmpX, [SKLPort01], 4, [1], 1, 6>; 255defm : SKLWriteResPair<WriteFCmpY, [SKLPort01], 4, [1], 1, 7>; 256defm : X86WriteResPairUnsupported<WriteFCmpZ>; 257defm : SKLWriteResPair<WriteFCmp64, [SKLPort01], 4, [1], 1, 5>; // Floating point double compare. 258defm : SKLWriteResPair<WriteFCmp64X, [SKLPort01], 4, [1], 1, 6>; 259defm : SKLWriteResPair<WriteFCmp64Y, [SKLPort01], 4, [1], 1, 7>; 260defm : X86WriteResPairUnsupported<WriteFCmp64Z>; 261 262defm : SKLWriteResPair<WriteFCom, [SKLPort0], 2>; // Floating point compare to flags (X87). 263defm : SKLWriteResPair<WriteFComX, [SKLPort0], 2>; // Floating point compare to flags (SSE). 264 265defm : SKLWriteResPair<WriteFMul, [SKLPort01], 4, [1], 1, 5>; // Floating point multiplication. 266defm : SKLWriteResPair<WriteFMulX, [SKLPort01], 4, [1], 1, 6>; 267defm : SKLWriteResPair<WriteFMulY, [SKLPort01], 4, [1], 1, 7>; 268defm : X86WriteResPairUnsupported<WriteFMulZ>; 269defm : SKLWriteResPair<WriteFMul64, [SKLPort01], 4, [1], 1, 5>; // Floating point double multiplication. 270defm : SKLWriteResPair<WriteFMul64X, [SKLPort01], 4, [1], 1, 6>; 271defm : SKLWriteResPair<WriteFMul64Y, [SKLPort01], 4, [1], 1, 7>; 272defm : X86WriteResPairUnsupported<WriteFMul64Z>; 273 274defm : SKLWriteResPair<WriteFDiv, [SKLPort0,SKLFPDivider], 11, [1,3], 1, 5>; // Floating point division. 275//defm : SKLWriteResPair<WriteFDivX, [SKLPort0,SKLFPDivider], 11, [1,3], 1, 6>; 276defm : SKLWriteResPair<WriteFDivY, [SKLPort0,SKLFPDivider], 11, [1,5], 1, 7>; 277defm : X86WriteResPairUnsupported<WriteFDivZ>; 278//defm : SKLWriteResPair<WriteFDiv64, [SKLPort0,SKLFPDivider], 14, [1,3], 1, 5>; // Floating point double division. 279//defm : SKLWriteResPair<WriteFDiv64X, [SKLPort0,SKLFPDivider], 14, [1,3], 1, 6>; 280//defm : SKLWriteResPair<WriteFDiv64Y, [SKLPort0,SKLFPDivider], 14, [1,5], 1, 7>; 281defm : X86WriteResPairUnsupported<WriteFDiv64Z>; 282 283defm : SKLWriteResPair<WriteFSqrt, [SKLPort0,SKLFPDivider], 12, [1,3], 1, 5>; // Floating point square root. 284defm : SKLWriteResPair<WriteFSqrtX, [SKLPort0,SKLFPDivider], 12, [1,3], 1, 6>; 285defm : SKLWriteResPair<WriteFSqrtY, [SKLPort0,SKLFPDivider], 12, [1,6], 1, 7>; 286defm : X86WriteResPairUnsupported<WriteFSqrtZ>; 287defm : SKLWriteResPair<WriteFSqrt64, [SKLPort0,SKLFPDivider], 18, [1,6], 1, 5>; // Floating point double square root. 288defm : SKLWriteResPair<WriteFSqrt64X, [SKLPort0,SKLFPDivider], 18, [1,6], 1, 6>; 289defm : SKLWriteResPair<WriteFSqrt64Y, [SKLPort0,SKLFPDivider], 18, [1,12],1, 7>; 290defm : X86WriteResPairUnsupported<WriteFSqrt64Z>; 291defm : SKLWriteResPair<WriteFSqrt80, [SKLPort0,SKLFPDivider], 21, [1,7]>; // Floating point long double square root. 292 293defm : SKLWriteResPair<WriteFRcp, [SKLPort0], 4, [1], 1, 5>; // Floating point reciprocal estimate. 294defm : SKLWriteResPair<WriteFRcpX, [SKLPort0], 4, [1], 1, 6>; 295defm : SKLWriteResPair<WriteFRcpY, [SKLPort0], 4, [1], 1, 7>; 296defm : X86WriteResPairUnsupported<WriteFRcpZ>; 297 298defm : SKLWriteResPair<WriteFRsqrt, [SKLPort0], 4, [1], 1, 5>; // Floating point reciprocal square root estimate. 299defm : SKLWriteResPair<WriteFRsqrtX,[SKLPort0], 4, [1], 1, 6>; 300defm : SKLWriteResPair<WriteFRsqrtY,[SKLPort0], 4, [1], 1, 7>; 301defm : X86WriteResPairUnsupported<WriteFRsqrtZ>; 302 303defm : SKLWriteResPair<WriteFMA, [SKLPort01], 4, [1], 1, 5>; // Fused Multiply Add. 304defm : SKLWriteResPair<WriteFMAX, [SKLPort01], 4, [1], 1, 6>; 305defm : SKLWriteResPair<WriteFMAY, [SKLPort01], 4, [1], 1, 7>; 306defm : X86WriteResPairUnsupported<WriteFMAZ>; 307defm : SKLWriteResPair<WriteDPPD, [SKLPort5,SKLPort01], 9, [1,2], 3, 6>; // Floating point double dot product. 308defm : SKLWriteResPair<WriteDPPS, [SKLPort5,SKLPort01], 13, [1,3], 4, 6>; 309defm : SKLWriteResPair<WriteDPPSY, [SKLPort5,SKLPort01], 13, [1,3], 4, 7>; 310defm : X86WriteResPairUnsupported<WriteDPPSZ>; 311defm : SKLWriteResPair<WriteFSign, [SKLPort0], 1>; // Floating point fabs/fchs. 312defm : SKLWriteResPair<WriteFRnd, [SKLPort01], 8, [2], 2, 6>; // Floating point rounding. 313defm : SKLWriteResPair<WriteFRndY, [SKLPort01], 8, [2], 2, 7>; 314defm : X86WriteResPairUnsupported<WriteFRndZ>; 315defm : SKLWriteResPair<WriteFLogic, [SKLPort015], 1, [1], 1, 6>; // Floating point and/or/xor logicals. 316defm : SKLWriteResPair<WriteFLogicY, [SKLPort015], 1, [1], 1, 7>; 317defm : X86WriteResPairUnsupported<WriteFLogicZ>; 318defm : SKLWriteResPair<WriteFTest, [SKLPort0], 2, [1], 1, 6>; // Floating point TEST instructions. 319defm : SKLWriteResPair<WriteFTestY, [SKLPort0], 2, [1], 1, 7>; 320defm : X86WriteResPairUnsupported<WriteFTestZ>; 321defm : SKLWriteResPair<WriteFShuffle, [SKLPort5], 1, [1], 1, 6>; // Floating point vector shuffles. 322defm : SKLWriteResPair<WriteFShuffleY, [SKLPort5], 1, [1], 1, 7>; 323defm : X86WriteResPairUnsupported<WriteFShuffleZ>; 324defm : SKLWriteResPair<WriteFVarShuffle, [SKLPort5], 1, [1], 1, 6>; // Floating point vector shuffles. 325defm : SKLWriteResPair<WriteFVarShuffleY, [SKLPort5], 1, [1], 1, 7>; 326defm : X86WriteResPairUnsupported<WriteFVarShuffleZ>; 327defm : SKLWriteResPair<WriteFBlend, [SKLPort015], 1, [1], 1, 6>; // Floating point vector blends. 328defm : SKLWriteResPair<WriteFBlendY, [SKLPort015], 1, [1], 1, 7>; 329defm : X86WriteResPairUnsupported<WriteFBlendZ>; 330defm : SKLWriteResPair<WriteFVarBlend, [SKLPort015], 2, [2], 2, 6>; // Fp vector variable blends. 331defm : SKLWriteResPair<WriteFVarBlendY,[SKLPort015], 2, [2], 2, 7>; 332defm : X86WriteResPairUnsupported<WriteFVarBlendZ>; 333 334// FMA Scheduling helper class. 335// class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; } 336 337// Vector integer operations. 338defm : X86WriteRes<WriteVecLoad, [SKLPort23], 5, [1], 1>; 339defm : X86WriteRes<WriteVecLoadX, [SKLPort23], 6, [1], 1>; 340defm : X86WriteRes<WriteVecLoadY, [SKLPort23], 7, [1], 1>; 341defm : X86WriteRes<WriteVecLoadNT, [SKLPort23], 6, [1], 1>; 342defm : X86WriteRes<WriteVecLoadNTY, [SKLPort23], 7, [1], 1>; 343defm : X86WriteRes<WriteVecMaskedLoad, [SKLPort23,SKLPort015], 7, [1,1], 2>; 344defm : X86WriteRes<WriteVecMaskedLoadY, [SKLPort23,SKLPort015], 8, [1,1], 2>; 345defm : X86WriteRes<WriteVecStore, [SKLPort237,SKLPort4], 1, [1,1], 2>; 346defm : X86WriteRes<WriteVecStoreX, [SKLPort237,SKLPort4], 1, [1,1], 2>; 347defm : X86WriteRes<WriteVecStoreY, [SKLPort237,SKLPort4], 1, [1,1], 2>; 348defm : X86WriteRes<WriteVecStoreNT, [SKLPort237,SKLPort4], 1, [1,1], 2>; 349defm : X86WriteRes<WriteVecStoreNTY, [SKLPort237,SKLPort4], 1, [1,1], 2>; 350defm : X86WriteRes<WriteVecMaskedStore32, [SKLPort237,SKLPort0], 2, [1,1], 2>; 351defm : X86WriteRes<WriteVecMaskedStore32Y, [SKLPort237,SKLPort0], 2, [1,1], 2>; 352defm : X86WriteRes<WriteVecMaskedStore64, [SKLPort237,SKLPort0], 2, [1,1], 2>; 353defm : X86WriteRes<WriteVecMaskedStore64Y, [SKLPort237,SKLPort0], 2, [1,1], 2>; 354defm : X86WriteRes<WriteVecMove, [SKLPort05], 1, [1], 1>; 355defm : X86WriteRes<WriteVecMoveX, [SKLPort015], 1, [1], 1>; 356defm : X86WriteRes<WriteVecMoveY, [SKLPort015], 1, [1], 1>; 357defm : X86WriteRes<WriteVecMoveToGpr, [SKLPort0], 2, [1], 1>; 358defm : X86WriteRes<WriteVecMoveFromGpr, [SKLPort5], 1, [1], 1>; 359 360defm : SKLWriteResPair<WriteVecALU, [SKLPort05], 1, [1], 1, 5>; // Vector integer ALU op, no logicals. 361defm : SKLWriteResPair<WriteVecALUX, [SKLPort01], 1, [1], 1, 6>; 362defm : SKLWriteResPair<WriteVecALUY, [SKLPort01], 1, [1], 1, 7>; 363defm : X86WriteResPairUnsupported<WriteVecALUZ>; 364defm : SKLWriteResPair<WriteVecLogic, [SKLPort05], 1, [1], 1, 5>; // Vector integer and/or/xor. 365defm : SKLWriteResPair<WriteVecLogicX,[SKLPort015], 1, [1], 1, 6>; 366defm : SKLWriteResPair<WriteVecLogicY,[SKLPort015], 1, [1], 1, 7>; 367defm : X86WriteResPairUnsupported<WriteVecLogicZ>; 368defm : SKLWriteResPair<WriteVecTest, [SKLPort0,SKLPort5], 3, [1,1], 2, 6>; // Vector integer TEST instructions. 369defm : SKLWriteResPair<WriteVecTestY, [SKLPort0,SKLPort5], 3, [1,1], 2, 7>; 370defm : X86WriteResPairUnsupported<WriteVecTestZ>; 371defm : SKLWriteResPair<WriteVecIMul, [SKLPort0] , 5, [1], 1, 5>; // Vector integer multiply. 372defm : SKLWriteResPair<WriteVecIMulX, [SKLPort01], 5, [1], 1, 6>; 373defm : SKLWriteResPair<WriteVecIMulY, [SKLPort01], 5, [1], 1, 7>; 374defm : X86WriteResPairUnsupported<WriteVecIMulZ>; 375defm : SKLWriteResPair<WritePMULLD, [SKLPort01], 10, [2], 2, 6>; // Vector PMULLD. 376defm : SKLWriteResPair<WritePMULLDY, [SKLPort01], 10, [2], 2, 7>; 377defm : X86WriteResPairUnsupported<WritePMULLDZ>; 378defm : SKLWriteResPair<WriteShuffle, [SKLPort5], 1, [1], 1, 5>; // Vector shuffles. 379defm : SKLWriteResPair<WriteShuffleX, [SKLPort5], 1, [1], 1, 6>; 380defm : SKLWriteResPair<WriteShuffleY, [SKLPort5], 1, [1], 1, 7>; 381defm : X86WriteResPairUnsupported<WriteShuffleZ>; 382defm : SKLWriteResPair<WriteVarShuffle, [SKLPort5], 1, [1], 1, 5>; // Vector shuffles. 383defm : SKLWriteResPair<WriteVarShuffleX, [SKLPort5], 1, [1], 1, 6>; 384defm : SKLWriteResPair<WriteVarShuffleY, [SKLPort5], 1, [1], 1, 7>; 385defm : X86WriteResPairUnsupported<WriteVarShuffleZ>; 386defm : SKLWriteResPair<WriteBlend, [SKLPort5], 1, [1], 1, 6>; // Vector blends. 387defm : SKLWriteResPair<WriteBlendY, [SKLPort5], 1, [1], 1, 7>; 388defm : X86WriteResPairUnsupported<WriteBlendZ>; 389defm : SKLWriteResPair<WriteVarBlend, [SKLPort015], 2, [2], 2, 6>; // Vector variable blends. 390defm : SKLWriteResPair<WriteVarBlendY, [SKLPort015], 2, [2], 2, 6>; 391defm : X86WriteResPairUnsupported<WriteVarBlendZ>; 392defm : SKLWriteResPair<WriteMPSAD, [SKLPort5], 4, [2], 2, 6>; // Vector MPSAD. 393defm : SKLWriteResPair<WriteMPSADY, [SKLPort5], 4, [2], 2, 7>; 394defm : X86WriteResPairUnsupported<WriteMPSADZ>; 395defm : SKLWriteResPair<WritePSADBW, [SKLPort5], 3, [1], 1, 5>; // Vector PSADBW. 396defm : SKLWriteResPair<WritePSADBWX, [SKLPort5], 3, [1], 1, 6>; 397defm : SKLWriteResPair<WritePSADBWY, [SKLPort5], 3, [1], 1, 7>; 398defm : X86WriteResPairUnsupported<WritePSADBWZ>; 399defm : SKLWriteResPair<WritePHMINPOS, [SKLPort01], 4, [1], 1, 6>; // Vector PHMINPOS. 400 401// Vector integer shifts. 402defm : SKLWriteResPair<WriteVecShift, [SKLPort0], 1, [1], 1, 5>; 403defm : X86WriteRes<WriteVecShiftX, [SKLPort5,SKLPort01], 2, [1,1], 2>; 404defm : X86WriteRes<WriteVecShiftY, [SKLPort5,SKLPort01], 4, [1,1], 2>; 405defm : X86WriteRes<WriteVecShiftXLd, [SKLPort01,SKLPort23], 7, [1,1], 2>; 406defm : X86WriteRes<WriteVecShiftYLd, [SKLPort01,SKLPort23], 8, [1,1], 2>; 407defm : X86WriteResPairUnsupported<WriteVecShiftZ>; 408 409defm : SKLWriteResPair<WriteVecShiftImm, [SKLPort0], 1, [1], 1, 5>; // Vector integer immediate shifts. 410defm : SKLWriteResPair<WriteVecShiftImmX, [SKLPort01], 1, [1], 1, 6>; 411defm : SKLWriteResPair<WriteVecShiftImmY, [SKLPort01], 1, [1], 1, 7>; 412defm : X86WriteResPairUnsupported<WriteVecShiftImmZ>; 413defm : SKLWriteResPair<WriteVarVecShift, [SKLPort01], 1, [1], 1, 6>; // Variable vector shifts. 414defm : SKLWriteResPair<WriteVarVecShiftY, [SKLPort01], 1, [1], 1, 7>; 415defm : X86WriteResPairUnsupported<WriteVarVecShiftZ>; 416 417// Vector insert/extract operations. 418def : WriteRes<WriteVecInsert, [SKLPort5]> { 419 let Latency = 2; 420 let NumMicroOps = 2; 421 let ResourceCycles = [2]; 422} 423def : WriteRes<WriteVecInsertLd, [SKLPort5,SKLPort23]> { 424 let Latency = 6; 425 let NumMicroOps = 2; 426} 427def: InstRW<[WriteVecInsertLd], (instregex "(V?)MOV(H|L)(PD|PS)rm")>; 428 429def : WriteRes<WriteVecExtract, [SKLPort0,SKLPort5]> { 430 let Latency = 3; 431 let NumMicroOps = 2; 432} 433def : WriteRes<WriteVecExtractSt, [SKLPort4,SKLPort5,SKLPort237]> { 434 let Latency = 2; 435 let NumMicroOps = 3; 436} 437 438// Conversion between integer and float. 439defm : SKLWriteResPair<WriteCvtSS2I, [SKLPort1], 3>; 440defm : SKLWriteResPair<WriteCvtPS2I, [SKLPort1], 3>; 441defm : SKLWriteResPair<WriteCvtPS2IY, [SKLPort1], 3>; 442defm : X86WriteResPairUnsupported<WriteCvtPS2IZ>; 443defm : SKLWriteResPair<WriteCvtSD2I, [SKLPort1], 3>; 444defm : SKLWriteResPair<WriteCvtPD2I, [SKLPort1], 3>; 445defm : SKLWriteResPair<WriteCvtPD2IY, [SKLPort1], 3>; 446defm : X86WriteResPairUnsupported<WriteCvtPD2IZ>; 447 448defm : SKLWriteResPair<WriteCvtI2SS, [SKLPort1], 4>; 449defm : SKLWriteResPair<WriteCvtI2PS, [SKLPort1], 4>; 450defm : SKLWriteResPair<WriteCvtI2PSY, [SKLPort1], 4>; 451defm : X86WriteResPairUnsupported<WriteCvtI2PSZ>; 452defm : SKLWriteResPair<WriteCvtI2SD, [SKLPort1], 4>; 453defm : SKLWriteResPair<WriteCvtI2PD, [SKLPort1], 4>; 454defm : SKLWriteResPair<WriteCvtI2PDY, [SKLPort1], 4>; 455defm : X86WriteResPairUnsupported<WriteCvtI2PDZ>; 456 457defm : SKLWriteResPair<WriteCvtSS2SD, [SKLPort1], 3>; 458defm : SKLWriteResPair<WriteCvtPS2PD, [SKLPort1], 3>; 459defm : SKLWriteResPair<WriteCvtPS2PDY, [SKLPort1], 3>; 460defm : X86WriteResPairUnsupported<WriteCvtPS2PDZ>; 461defm : SKLWriteResPair<WriteCvtSD2SS, [SKLPort1], 3>; 462defm : SKLWriteResPair<WriteCvtPD2PS, [SKLPort1], 3>; 463defm : SKLWriteResPair<WriteCvtPD2PSY, [SKLPort1], 3>; 464defm : X86WriteResPairUnsupported<WriteCvtPD2PSZ>; 465 466defm : X86WriteRes<WriteCvtPH2PS, [SKLPort5,SKLPort015], 5, [1,1], 2>; 467defm : X86WriteRes<WriteCvtPH2PSY, [SKLPort5,SKLPort01], 7, [1,1], 2>; 468defm : X86WriteResUnsupported<WriteCvtPH2PSZ>; 469defm : X86WriteRes<WriteCvtPH2PSLd, [SKLPort23,SKLPort01], 9, [1,1], 2>; 470defm : X86WriteRes<WriteCvtPH2PSYLd, [SKLPort23,SKLPort01], 10, [1,1], 2>; 471defm : X86WriteResUnsupported<WriteCvtPH2PSZLd>; 472 473defm : X86WriteRes<WriteCvtPS2PH, [SKLPort5,SKLPort015], 5, [1,1], 2>; 474defm : X86WriteRes<WriteCvtPS2PHY, [SKLPort5,SKLPort01], 7, [1,1], 2>; 475defm : X86WriteResUnsupported<WriteCvtPS2PHZ>; 476defm : X86WriteRes<WriteCvtPS2PHSt, [SKLPort4,SKLPort5,SKLPort237,SKLPort01], 6, [1,1,1,1], 4>; 477defm : X86WriteRes<WriteCvtPS2PHYSt, [SKLPort4,SKLPort5,SKLPort237,SKLPort01], 8, [1,1,1,1], 4>; 478defm : X86WriteResUnsupported<WriteCvtPS2PHZSt>; 479 480// Strings instructions. 481 482// Packed Compare Implicit Length Strings, Return Mask 483def : WriteRes<WritePCmpIStrM, [SKLPort0]> { 484 let Latency = 10; 485 let NumMicroOps = 3; 486 let ResourceCycles = [3]; 487} 488def : WriteRes<WritePCmpIStrMLd, [SKLPort0, SKLPort23]> { 489 let Latency = 16; 490 let NumMicroOps = 4; 491 let ResourceCycles = [3,1]; 492} 493 494// Packed Compare Explicit Length Strings, Return Mask 495def : WriteRes<WritePCmpEStrM, [SKLPort0, SKLPort5, SKLPort015, SKLPort0156]> { 496 let Latency = 19; 497 let NumMicroOps = 9; 498 let ResourceCycles = [4,3,1,1]; 499} 500def : WriteRes<WritePCmpEStrMLd, [SKLPort0, SKLPort5,SKLPort23, SKLPort015, SKLPort0156]> { 501 let Latency = 25; 502 let NumMicroOps = 10; 503 let ResourceCycles = [4,3,1,1,1]; 504} 505 506// Packed Compare Implicit Length Strings, Return Index 507def : WriteRes<WritePCmpIStrI, [SKLPort0]> { 508 let Latency = 10; 509 let NumMicroOps = 3; 510 let ResourceCycles = [3]; 511} 512def : WriteRes<WritePCmpIStrILd, [SKLPort0, SKLPort23]> { 513 let Latency = 16; 514 let NumMicroOps = 4; 515 let ResourceCycles = [3,1]; 516} 517 518// Packed Compare Explicit Length Strings, Return Index 519def : WriteRes<WritePCmpEStrI, [SKLPort0, SKLPort5, SKLPort0156]> { 520 let Latency = 18; 521 let NumMicroOps = 8; 522 let ResourceCycles = [4,3,1]; 523} 524def : WriteRes<WritePCmpEStrILd, [SKLPort0, SKLPort5, SKLPort23, SKLPort0156]> { 525 let Latency = 24; 526 let NumMicroOps = 9; 527 let ResourceCycles = [4,3,1,1]; 528} 529 530// MOVMSK Instructions. 531def : WriteRes<WriteFMOVMSK, [SKLPort0]> { let Latency = 2; } 532def : WriteRes<WriteVecMOVMSK, [SKLPort0]> { let Latency = 2; } 533def : WriteRes<WriteVecMOVMSKY, [SKLPort0]> { let Latency = 2; } 534def : WriteRes<WriteMMXMOVMSK, [SKLPort0]> { let Latency = 2; } 535 536// AES instructions. 537def : WriteRes<WriteAESDecEnc, [SKLPort0]> { // Decryption, encryption. 538 let Latency = 4; 539 let NumMicroOps = 1; 540 let ResourceCycles = [1]; 541} 542def : WriteRes<WriteAESDecEncLd, [SKLPort0, SKLPort23]> { 543 let Latency = 10; 544 let NumMicroOps = 2; 545 let ResourceCycles = [1,1]; 546} 547 548def : WriteRes<WriteAESIMC, [SKLPort0]> { // InvMixColumn. 549 let Latency = 8; 550 let NumMicroOps = 2; 551 let ResourceCycles = [2]; 552} 553def : WriteRes<WriteAESIMCLd, [SKLPort0, SKLPort23]> { 554 let Latency = 14; 555 let NumMicroOps = 3; 556 let ResourceCycles = [2,1]; 557} 558 559def : WriteRes<WriteAESKeyGen, [SKLPort0, SKLPort5, SKLPort015]> { // Key Generation. 560 let Latency = 20; 561 let NumMicroOps = 11; 562 let ResourceCycles = [3,6,2]; 563} 564def : WriteRes<WriteAESKeyGenLd, [SKLPort0, SKLPort5, SKLPort23, SKLPort015]> { 565 let Latency = 25; 566 let NumMicroOps = 11; 567 let ResourceCycles = [3,6,1,1]; 568} 569 570// Carry-less multiplication instructions. 571def : WriteRes<WriteCLMul, [SKLPort5]> { 572 let Latency = 6; 573 let NumMicroOps = 1; 574 let ResourceCycles = [1]; 575} 576def : WriteRes<WriteCLMulLd, [SKLPort5, SKLPort23]> { 577 let Latency = 12; 578 let NumMicroOps = 2; 579 let ResourceCycles = [1,1]; 580} 581 582// Catch-all for expensive system instructions. 583def : WriteRes<WriteSystem, [SKLPort0156]> { let Latency = 100; } // def WriteSystem : SchedWrite; 584 585// AVX2. 586defm : SKLWriteResPair<WriteFShuffle256, [SKLPort5], 3, [1], 1, 7>; // Fp 256-bit width vector shuffles. 587defm : SKLWriteResPair<WriteFVarShuffle256, [SKLPort5], 3, [1], 1, 7>; // Fp 256-bit width vector variable shuffles. 588defm : SKLWriteResPair<WriteShuffle256, [SKLPort5], 3, [1], 1, 7>; // 256-bit width vector shuffles. 589defm : SKLWriteResPair<WriteVPMOV256, [SKLPort5], 3, [1], 1, 7>; // 256-bit width packed vector width-changing move. 590defm : SKLWriteResPair<WriteVarShuffle256, [SKLPort5], 3, [1], 1, 7>; // 256-bit width vector variable shuffles. 591 592// Old microcoded instructions that nobody use. 593def : WriteRes<WriteMicrocoded, [SKLPort0156]> { let Latency = 100; } // def WriteMicrocoded : SchedWrite; 594 595// Fence instructions. 596def : WriteRes<WriteFence, [SKLPort23, SKLPort4]>; 597 598// Load/store MXCSR. 599def : WriteRes<WriteLDMXCSR, [SKLPort0,SKLPort23,SKLPort0156]> { let Latency = 7; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } 600def : WriteRes<WriteSTMXCSR, [SKLPort4,SKLPort5,SKLPort237]> { let Latency = 2; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } 601 602// Nop, not very useful expect it provides a model for nops! 603def : WriteRes<WriteNop, []>; 604 605//////////////////////////////////////////////////////////////////////////////// 606// Horizontal add/sub instructions. 607//////////////////////////////////////////////////////////////////////////////// 608 609defm : SKLWriteResPair<WriteFHAdd, [SKLPort5,SKLPort01], 6, [2,1], 3, 6>; 610defm : SKLWriteResPair<WriteFHAddY, [SKLPort5,SKLPort01], 6, [2,1], 3, 7>; 611defm : SKLWriteResPair<WritePHAdd, [SKLPort5,SKLPort05], 3, [2,1], 3, 5>; 612defm : SKLWriteResPair<WritePHAddX, [SKLPort5,SKLPort015], 3, [2,1], 3, 6>; 613defm : SKLWriteResPair<WritePHAddY, [SKLPort5,SKLPort015], 3, [2,1], 3, 7>; 614 615// Remaining instrs. 616 617def SKLWriteResGroup1 : SchedWriteRes<[SKLPort0]> { 618 let Latency = 1; 619 let NumMicroOps = 1; 620 let ResourceCycles = [1]; 621} 622def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PADDS(B|W)irr", 623 "MMX_PADDUS(B|W)irr", 624 "MMX_PAVG(B|W)irr", 625 "MMX_PCMPEQ(B|D|W)irr", 626 "MMX_PCMPGT(B|D|W)irr", 627 "MMX_P(MAX|MIN)SWirr", 628 "MMX_P(MAX|MIN)UBirr", 629 "MMX_PSUBS(B|W)irr", 630 "MMX_PSUBUS(B|W)irr")>; 631 632def SKLWriteResGroup3 : SchedWriteRes<[SKLPort5]> { 633 let Latency = 1; 634 let NumMicroOps = 1; 635 let ResourceCycles = [1]; 636} 637def: InstRW<[SKLWriteResGroup3], (instregex "COM(P?)_FST0r", 638 "UCOM_F(P?)r")>; 639 640def SKLWriteResGroup4 : SchedWriteRes<[SKLPort6]> { 641 let Latency = 1; 642 let NumMicroOps = 1; 643 let ResourceCycles = [1]; 644} 645def: InstRW<[SKLWriteResGroup4], (instregex "JMP(16|32|64)r")>; 646 647def SKLWriteResGroup6 : SchedWriteRes<[SKLPort05]> { 648 let Latency = 1; 649 let NumMicroOps = 1; 650 let ResourceCycles = [1]; 651} 652def: InstRW<[SKLWriteResGroup6], (instrs FINCSTP, FNOP)>; 653 654def SKLWriteResGroup7 : SchedWriteRes<[SKLPort06]> { 655 let Latency = 1; 656 let NumMicroOps = 1; 657 let ResourceCycles = [1]; 658} 659def: InstRW<[SKLWriteResGroup7], (instrs CDQ, CQO, CLAC, STAC)>; 660 661def SKLWriteResGroup8 : SchedWriteRes<[SKLPort15]> { 662 let Latency = 1; 663 let NumMicroOps = 1; 664 let ResourceCycles = [1]; 665} 666def: InstRW<[SKLWriteResGroup8], (instregex "ANDN(32|64)rr")>; 667 668def SKLWriteResGroup9 : SchedWriteRes<[SKLPort015]> { 669 let Latency = 1; 670 let NumMicroOps = 1; 671 let ResourceCycles = [1]; 672} 673def: InstRW<[SKLWriteResGroup9], (instregex "(V?)PADD(B|D|Q|W)(Y?)rr", 674 "VPBLENDD(Y?)rri")>; 675 676def SKLWriteResGroup10 : SchedWriteRes<[SKLPort0156]> { 677 let Latency = 1; 678 let NumMicroOps = 1; 679 let ResourceCycles = [1]; 680} 681def: InstRW<[SKLWriteResGroup10], (instrs CBW, CWDE, CDQE, 682 CMC, STC, 683 SGDT64m, 684 SIDT64m, 685 SMSW16m, 686 STRm, 687 SYSCALL)>; 688 689def SKLWriteResGroup11 : SchedWriteRes<[SKLPort4,SKLPort237]> { 690 let Latency = 1; 691 let NumMicroOps = 2; 692 let ResourceCycles = [1,1]; 693} 694def: InstRW<[SKLWriteResGroup11], (instrs FBSTPm, VMPTRSTm)>; 695def: InstRW<[SKLWriteResGroup11], (instregex "ST_FP(32|64|80)m")>; 696 697def SKLWriteResGroup13 : SchedWriteRes<[SKLPort5]> { 698 let Latency = 2; 699 let NumMicroOps = 2; 700 let ResourceCycles = [2]; 701} 702def: InstRW<[SKLWriteResGroup13], (instrs MMX_MOVQ2DQrr)>; 703 704def SKLWriteResGroup14 : SchedWriteRes<[SKLPort05]> { 705 let Latency = 2; 706 let NumMicroOps = 2; 707 let ResourceCycles = [2]; 708} 709def: InstRW<[SKLWriteResGroup14], (instrs FDECSTP, 710 MMX_MOVDQ2Qrr)>; 711 712def SKLWriteResGroup17 : SchedWriteRes<[SKLPort0156]> { 713 let Latency = 2; 714 let NumMicroOps = 2; 715 let ResourceCycles = [2]; 716} 717def: InstRW<[SKLWriteResGroup17], (instrs LFENCE, 718 WAIT, 719 XGETBV)>; 720 721def SKLWriteResGroup20 : SchedWriteRes<[SKLPort6,SKLPort0156]> { 722 let Latency = 2; 723 let NumMicroOps = 2; 724 let ResourceCycles = [1,1]; 725} 726def: InstRW<[SKLWriteResGroup20], (instregex "CLFLUSH")>; 727 728def SKLWriteResGroup21 : SchedWriteRes<[SKLPort237,SKLPort0156]> { 729 let Latency = 2; 730 let NumMicroOps = 2; 731 let ResourceCycles = [1,1]; 732} 733def: InstRW<[SKLWriteResGroup21], (instrs SFENCE)>; 734 735def SKLWriteResGroup23 : SchedWriteRes<[SKLPort06,SKLPort0156]> { 736 let Latency = 2; 737 let NumMicroOps = 2; 738 let ResourceCycles = [1,1]; 739} 740def: InstRW<[SKLWriteResGroup23], (instrs CWD, 741 JCXZ, JECXZ, JRCXZ, 742 ADC8i8, SBB8i8, 743 ADC16i16, SBB16i16, 744 ADC32i32, SBB32i32, 745 ADC64i32, SBB64i32)>; 746 747def SKLWriteResGroup25 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort237]> { 748 let Latency = 2; 749 let NumMicroOps = 3; 750 let ResourceCycles = [1,1,1]; 751} 752def: InstRW<[SKLWriteResGroup25], (instrs FNSTCW16m)>; 753 754def SKLWriteResGroup27 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort15]> { 755 let Latency = 2; 756 let NumMicroOps = 3; 757 let ResourceCycles = [1,1,1]; 758} 759def: InstRW<[SKLWriteResGroup27], (instregex "MOVBE(16|32|64)mr")>; 760 761def SKLWriteResGroup28 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort0156]> { 762 let Latency = 2; 763 let NumMicroOps = 3; 764 let ResourceCycles = [1,1,1]; 765} 766def: InstRW<[SKLWriteResGroup28], (instrs PUSH16r, PUSH32r, PUSH64r, PUSH64i8, 767 STOSB, STOSL, STOSQ, STOSW)>; 768def: InstRW<[SKLWriteResGroup28], (instregex "PUSH(16|32|64)rmr")>; 769 770def SKLWriteResGroup29 : SchedWriteRes<[SKLPort1]> { 771 let Latency = 3; 772 let NumMicroOps = 1; 773 let ResourceCycles = [1]; 774} 775def: InstRW<[SKLWriteResGroup29], (instregex "PDEP(32|64)rr", 776 "PEXT(32|64)rr")>; 777 778def SKLWriteResGroup30 : SchedWriteRes<[SKLPort5]> { 779 let Latency = 3; 780 let NumMicroOps = 1; 781 let ResourceCycles = [1]; 782} 783def: InstRW<[SKLWriteResGroup30], (instregex "(ADD|SUB|SUBR)_(FPrST0|FST0r|FrST0)", 784 "VPBROADCAST(B|W)rr")>; 785 786def SKLWriteResGroup32 : SchedWriteRes<[SKLPort0,SKLPort0156]> { 787 let Latency = 3; 788 let NumMicroOps = 2; 789 let ResourceCycles = [1,1]; 790} 791def: InstRW<[SKLWriteResGroup32], (instrs FNSTSW16r)>; 792 793def SKLWriteResGroup35 : SchedWriteRes<[SKLPort0,SKLPort5]> { 794 let Latency = 3; 795 let NumMicroOps = 3; 796 let ResourceCycles = [1,2]; 797} 798def: InstRW<[SKLWriteResGroup35], (instregex "MMX_PH(ADD|SUB)SWrr")>; 799 800def SKLWriteResGroup36 : SchedWriteRes<[SKLPort5,SKLPort01]> { 801 let Latency = 3; 802 let NumMicroOps = 3; 803 let ResourceCycles = [2,1]; 804} 805def: InstRW<[SKLWriteResGroup36], (instregex "(V?)PHADDSW(Y?)rr", 806 "(V?)PHSUBSW(Y?)rr")>; 807 808def SKLWriteResGroup39 : SchedWriteRes<[SKLPort5,SKLPort0156]> { 809 let Latency = 3; 810 let NumMicroOps = 3; 811 let ResourceCycles = [2,1]; 812} 813def: InstRW<[SKLWriteResGroup39], (instrs MMX_PACKSSDWirr, 814 MMX_PACKSSWBirr, 815 MMX_PACKUSWBirr)>; 816 817def SKLWriteResGroup40 : SchedWriteRes<[SKLPort6,SKLPort0156]> { 818 let Latency = 3; 819 let NumMicroOps = 3; 820 let ResourceCycles = [1,2]; 821} 822def: InstRW<[SKLWriteResGroup40], (instregex "CLD")>; 823 824def SKLWriteResGroup41 : SchedWriteRes<[SKLPort237,SKLPort0156]> { 825 let Latency = 3; 826 let NumMicroOps = 3; 827 let ResourceCycles = [1,2]; 828} 829def: InstRW<[SKLWriteResGroup41], (instrs MFENCE)>; 830 831def SKLWriteResGroup42 : SchedWriteRes<[SKLPort06,SKLPort0156]> { 832 let Latency = 3; 833 let NumMicroOps = 3; 834 let ResourceCycles = [1,2]; 835} 836def: InstRW<[SKLWriteResGroup42], (instregex "RCL(8|16|32|64)r(1|i)", 837 "RCR(8|16|32|64)r(1|i)")>; 838 839def SKLWriteResGroup43 : SchedWriteRes<[SKLPort0,SKLPort4,SKLPort237]> { 840 let Latency = 3; 841 let NumMicroOps = 3; 842 let ResourceCycles = [1,1,1]; 843} 844def: InstRW<[SKLWriteResGroup43], (instrs FNSTSWm)>; 845 846def SKLWriteResGroup45 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort237,SKLPort0156]> { 847 let Latency = 3; 848 let NumMicroOps = 4; 849 let ResourceCycles = [1,1,1,1]; 850} 851def: InstRW<[SKLWriteResGroup45], (instregex "CALL(16|32|64)r")>; 852 853def SKLWriteResGroup46 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort06,SKLPort0156]> { 854 let Latency = 3; 855 let NumMicroOps = 4; 856 let ResourceCycles = [1,1,1,1]; 857} 858def: InstRW<[SKLWriteResGroup46], (instrs CALL64pcrel32)>; 859 860def SKLWriteResGroup47 : SchedWriteRes<[SKLPort0]> { 861 let Latency = 4; 862 let NumMicroOps = 1; 863 let ResourceCycles = [1]; 864} 865def: InstRW<[SKLWriteResGroup47], (instregex "MUL_(FPrST0|FST0r|FrST0)")>; 866 867def SKLWriteResGroup48 : SchedWriteRes<[SKLPort01]> { 868 let Latency = 4; 869 let NumMicroOps = 1; 870 let ResourceCycles = [1]; 871} 872def: InstRW<[SKLWriteResGroup48], (instregex "(V?)CVTDQ2PS(Y?)rr", 873 "(V?)CVT(T?)PS2DQ(Y?)rr")>; 874 875def SKLWriteResGroup53 : SchedWriteRes<[SKLPort4,SKLPort5,SKLPort237]> { 876 let Latency = 4; 877 let NumMicroOps = 3; 878 let ResourceCycles = [1,1,1]; 879} 880def: InstRW<[SKLWriteResGroup53], (instregex "IST(T?)_FP(16|32|64)m", 881 "IST_F(16|32)m")>; 882 883def SKLWriteResGroup54 : SchedWriteRes<[SKLPort0156]> { 884 let Latency = 4; 885 let NumMicroOps = 4; 886 let ResourceCycles = [4]; 887} 888def: InstRW<[SKLWriteResGroup54], (instrs FNCLEX)>; 889 890def SKLWriteResGroup55 : SchedWriteRes<[SKLPort6,SKLPort0156]> { 891 let Latency = 4; 892 let NumMicroOps = 4; 893 let ResourceCycles = [1,3]; 894} 895def: InstRW<[SKLWriteResGroup55], (instrs PAUSE)>; 896 897def SKLWriteResGroup56 : SchedWriteRes<[]> { 898 let Latency = 0; 899 let NumMicroOps = 4; 900 let ResourceCycles = []; 901} 902def: InstRW<[SKLWriteResGroup56], (instrs VZEROUPPER)>; 903 904def SKLWriteResGroup57 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort0156]> { 905 let Latency = 4; 906 let NumMicroOps = 4; 907 let ResourceCycles = [1,1,2]; 908} 909def: InstRW<[SKLWriteResGroup57], (instregex "LAR(16|32|64)rr")>; 910 911def SKLWriteResGroup58 : SchedWriteRes<[SKLPort23]> { 912 let Latency = 5; 913 let NumMicroOps = 1; 914 let ResourceCycles = [1]; 915} 916def: InstRW<[SKLWriteResGroup58], (instregex "MOVSX(16|32|64)rm(8|16|32)", 917 "MOVZX(16|32|64)rm(8|16)", 918 "(V?)MOVDDUPrm")>; // TODO: Should this be SKLWriteResGroup67? 919 920def SKLWriteResGroup59 : SchedWriteRes<[SKLPort0,SKLPort5]> { 921 let Latency = 5; 922 let NumMicroOps = 2; 923 let ResourceCycles = [1,1]; 924} 925def: InstRW<[SKLWriteResGroup59], (instrs MMX_CVTPI2PDirr, 926 CVTDQ2PDrr, 927 VCVTDQ2PDrr)>; 928 929def SKLWriteResGroup60 : SchedWriteRes<[SKLPort5,SKLPort015]> { 930 let Latency = 5; 931 let NumMicroOps = 2; 932 let ResourceCycles = [1,1]; 933} 934def: InstRW<[SKLWriteResGroup60], (instregex "MMX_CVT(T?)PD2PIirr", 935 "MMX_CVT(T?)PS2PIirr", 936 "(V?)CVT(T?)PD2DQrr", 937 "(V?)CVTPD2PSrr", 938 "(V?)CVTPS2PDrr", 939 "(V?)CVTSD2SSrr", 940 "(V?)CVTSI642SDrr", 941 "(V?)CVTSI2SDrr", 942 "(V?)CVTSI2SSrr", 943 "(V?)CVTSS2SDrr")>; 944 945def SKLWriteResGroup61 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort06]> { 946 let Latency = 5; 947 let NumMicroOps = 3; 948 let ResourceCycles = [1,1,1]; 949} 950def: InstRW<[SKLWriteResGroup61], (instregex "STR(16|32|64)r")>; 951 952def SKLWriteResGroup63 : SchedWriteRes<[SKLPort06,SKLPort0156]> { 953 let Latency = 5; 954 let NumMicroOps = 5; 955 let ResourceCycles = [1,4]; 956} 957def: InstRW<[SKLWriteResGroup63], (instrs XSETBV)>; 958 959def SKLWriteResGroup65 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort0156]> { 960 let Latency = 5; 961 let NumMicroOps = 6; 962 let ResourceCycles = [1,1,4]; 963} 964def: InstRW<[SKLWriteResGroup65], (instregex "PUSHF(16|64)")>; 965 966def SKLWriteResGroup67 : SchedWriteRes<[SKLPort23]> { 967 let Latency = 6; 968 let NumMicroOps = 1; 969 let ResourceCycles = [1]; 970} 971def: InstRW<[SKLWriteResGroup67], (instrs VBROADCASTSSrm, 972 VPBROADCASTDrm, 973 VPBROADCASTQrm)>; 974def: InstRW<[SKLWriteResGroup67], (instregex "(V?)MOVSHDUPrm", 975 "(V?)MOVSLDUPrm")>; 976 977def SKLWriteResGroup68 : SchedWriteRes<[SKLPort0]> { 978 let Latency = 6; 979 let NumMicroOps = 2; 980 let ResourceCycles = [2]; 981} 982def: InstRW<[SKLWriteResGroup68], (instrs MMX_CVTPI2PSirr)>; 983 984def SKLWriteResGroup69 : SchedWriteRes<[SKLPort0,SKLPort23]> { 985 let Latency = 6; 986 let NumMicroOps = 2; 987 let ResourceCycles = [1,1]; 988} 989def: InstRW<[SKLWriteResGroup69], (instrs MMX_PADDSBirm, 990 MMX_PADDSWirm, 991 MMX_PADDUSBirm, 992 MMX_PADDUSWirm, 993 MMX_PAVGBirm, 994 MMX_PAVGWirm, 995 MMX_PCMPEQBirm, 996 MMX_PCMPEQDirm, 997 MMX_PCMPEQWirm, 998 MMX_PCMPGTBirm, 999 MMX_PCMPGTDirm, 1000 MMX_PCMPGTWirm, 1001 MMX_PMAXSWirm, 1002 MMX_PMAXUBirm, 1003 MMX_PMINSWirm, 1004 MMX_PMINUBirm, 1005 MMX_PSUBSBirm, 1006 MMX_PSUBSWirm, 1007 MMX_PSUBUSBirm, 1008 MMX_PSUBUSWirm)>; 1009 1010def SKLWriteResGroup70 : SchedWriteRes<[SKLPort0,SKLPort01]> { 1011 let Latency = 6; 1012 let NumMicroOps = 2; 1013 let ResourceCycles = [1,1]; 1014} 1015def: InstRW<[SKLWriteResGroup70], (instregex "(V?)CVTSS2SI(64)?rr", 1016 "(V?)CVT(T?)SD2SI(64)?rr")>; 1017 1018def SKLWriteResGroup72 : SchedWriteRes<[SKLPort6,SKLPort23]> { 1019 let Latency = 6; 1020 let NumMicroOps = 2; 1021 let ResourceCycles = [1,1]; 1022} 1023def: InstRW<[SKLWriteResGroup72], (instrs FARJMP64m)>; 1024def: InstRW<[SKLWriteResGroup72], (instregex "JMP(16|32|64)m")>; 1025 1026def SKLWriteResGroup75 : SchedWriteRes<[SKLPort23,SKLPort15]> { 1027 let Latency = 6; 1028 let NumMicroOps = 2; 1029 let ResourceCycles = [1,1]; 1030} 1031def: InstRW<[SKLWriteResGroup75], (instregex "ANDN(32|64)rm", 1032 "MOVBE(16|32|64)rm")>; 1033 1034def SKLWriteResGroup76 : SchedWriteRes<[SKLPort23,SKLPort0156]> { 1035 let Latency = 6; 1036 let NumMicroOps = 2; 1037 let ResourceCycles = [1,1]; 1038} 1039def: InstRW<[SKLWriteResGroup76], (instrs POP16r, POP32r, POP64r)>; 1040def: InstRW<[SKLWriteResGroup76], (instregex "POP(16|32|64)rmr")>; 1041 1042def SKLWriteResGroup78 : SchedWriteRes<[SKLPort5,SKLPort01]> { 1043 let Latency = 6; 1044 let NumMicroOps = 3; 1045 let ResourceCycles = [2,1]; 1046} 1047def: InstRW<[SKLWriteResGroup78], (instregex "(V?)CVTSI642SSrr")>; 1048 1049def SKLWriteResGroup80 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort06,SKLPort0156]> { 1050 let Latency = 6; 1051 let NumMicroOps = 4; 1052 let ResourceCycles = [1,1,1,1]; 1053} 1054def: InstRW<[SKLWriteResGroup80], (instregex "SLDT(16|32|64)r")>; 1055 1056def SKLWriteResGroup82 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> { 1057 let Latency = 6; 1058 let NumMicroOps = 4; 1059 let ResourceCycles = [1,1,1,1]; 1060} 1061def: InstRW<[SKLWriteResGroup82], (instregex "SAR(8|16|32|64)m(1|i)", 1062 "SHL(8|16|32|64)m(1|i)", 1063 "SHR(8|16|32|64)m(1|i)")>; 1064 1065def SKLWriteResGroup83 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort0156]> { 1066 let Latency = 6; 1067 let NumMicroOps = 4; 1068 let ResourceCycles = [1,1,1,1]; 1069} 1070def: InstRW<[SKLWriteResGroup83], (instregex "POP(16|32|64)rmm", 1071 "PUSH(16|32|64)rmm")>; 1072 1073def SKLWriteResGroup84 : SchedWriteRes<[SKLPort6,SKLPort0156]> { 1074 let Latency = 6; 1075 let NumMicroOps = 6; 1076 let ResourceCycles = [1,5]; 1077} 1078def: InstRW<[SKLWriteResGroup84], (instrs STD)>; 1079 1080def SKLWriteResGroup85 : SchedWriteRes<[SKLPort23]> { 1081 let Latency = 7; 1082 let NumMicroOps = 1; 1083 let ResourceCycles = [1]; 1084} 1085def: InstRW<[SKLWriteResGroup85], (instregex "LD_F(32|64|80)m")>; 1086def: InstRW<[SKLWriteResGroup85], (instrs VBROADCASTF128, 1087 VBROADCASTI128, 1088 VBROADCASTSDYrm, 1089 VBROADCASTSSYrm, 1090 VMOVDDUPYrm, 1091 VMOVSHDUPYrm, 1092 VMOVSLDUPYrm, 1093 VPBROADCASTDYrm, 1094 VPBROADCASTQYrm)>; 1095 1096def SKLWriteResGroup86 : SchedWriteRes<[SKLPort0,SKLPort5]> { 1097 let Latency = 7; 1098 let NumMicroOps = 2; 1099 let ResourceCycles = [1,1]; 1100} 1101def: InstRW<[SKLWriteResGroup86], (instrs VCVTDQ2PDYrr)>; 1102 1103def SKLWriteResGroup88 : SchedWriteRes<[SKLPort5,SKLPort23]> { 1104 let Latency = 6; 1105 let NumMicroOps = 2; 1106 let ResourceCycles = [1,1]; 1107} 1108def: InstRW<[SKLWriteResGroup88], (instregex "(V?)PMOV(SX|ZX)BDrm", 1109 "(V?)PMOV(SX|ZX)BQrm", 1110 "(V?)PMOV(SX|ZX)BWrm", 1111 "(V?)PMOV(SX|ZX)DQrm", 1112 "(V?)PMOV(SX|ZX)WDrm", 1113 "(V?)PMOV(SX|ZX)WQrm")>; 1114 1115def SKLWriteResGroup89 : SchedWriteRes<[SKLPort5,SKLPort01]> { 1116 let Latency = 7; 1117 let NumMicroOps = 2; 1118 let ResourceCycles = [1,1]; 1119} 1120def: InstRW<[SKLWriteResGroup89], (instrs VCVTPD2PSYrr, 1121 VCVTPS2PDYrr, 1122 VCVTPD2DQYrr, 1123 VCVTTPD2DQYrr)>; 1124 1125def SKLWriteResGroup91 : SchedWriteRes<[SKLPort23,SKLPort015]> { 1126 let Latency = 7; 1127 let NumMicroOps = 2; 1128 let ResourceCycles = [1,1]; 1129} 1130def: InstRW<[SKLWriteResGroup91], (instrs VINSERTF128rm, 1131 VINSERTI128rm, 1132 VPBLENDDrmi)>; 1133def: InstRW<[SKLWriteResGroup91, ReadAfterVecXLd], 1134 (instregex "(V?)PADD(B|D|Q|W)rm", 1135 "(V?)PSUB(B|D|Q|W)rm")>; 1136 1137def SKLWriteResGroup92 : SchedWriteRes<[SKLPort5,SKLPort23]> { 1138 let Latency = 7; 1139 let NumMicroOps = 3; 1140 let ResourceCycles = [2,1]; 1141} 1142def: InstRW<[SKLWriteResGroup92], (instrs MMX_PACKSSDWirm, 1143 MMX_PACKSSWBirm, 1144 MMX_PACKUSWBirm)>; 1145 1146def SKLWriteResGroup94 : SchedWriteRes<[SKLPort23,SKLPort0156]> { 1147 let Latency = 7; 1148 let NumMicroOps = 3; 1149 let ResourceCycles = [1,2]; 1150} 1151def: InstRW<[SKLWriteResGroup94], (instrs LEAVE, LEAVE64, 1152 SCASB, SCASL, SCASQ, SCASW)>; 1153 1154def SKLWriteResGroup95 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort01]> { 1155 let Latency = 7; 1156 let NumMicroOps = 3; 1157 let ResourceCycles = [1,1,1]; 1158} 1159def: InstRW<[SKLWriteResGroup95], (instregex "(V?)CVTTSS2SI(64)?rr")>; 1160 1161def SKLWriteResGroup96 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort05]> { 1162 let Latency = 7; 1163 let NumMicroOps = 3; 1164 let ResourceCycles = [1,1,1]; 1165} 1166def: InstRW<[SKLWriteResGroup96], (instrs FLDCW16m)>; 1167 1168def SKLWriteResGroup98 : SchedWriteRes<[SKLPort6,SKLPort23,SKLPort0156]> { 1169 let Latency = 7; 1170 let NumMicroOps = 3; 1171 let ResourceCycles = [1,1,1]; 1172} 1173def: InstRW<[SKLWriteResGroup98], (instrs LRETQ, RETQ)>; 1174 1175def SKLWriteResGroup100 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> { 1176 let Latency = 7; 1177 let NumMicroOps = 5; 1178 let ResourceCycles = [1,1,1,2]; 1179} 1180def: InstRW<[SKLWriteResGroup100], (instregex "ROL(8|16|32|64)m(1|i)", 1181 "ROR(8|16|32|64)m(1|i)")>; 1182 1183def SKLWriteResGroup100_1 : SchedWriteRes<[SKLPort06]> { 1184 let Latency = 2; 1185 let NumMicroOps = 2; 1186 let ResourceCycles = [2]; 1187} 1188def: InstRW<[SKLWriteResGroup100_1], (instrs ROL8r1, ROL16r1, ROL32r1, ROL64r1, 1189 ROR8r1, ROR16r1, ROR32r1, ROR64r1)>; 1190 1191def SKLWriteResGroup101 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort0156]> { 1192 let Latency = 7; 1193 let NumMicroOps = 5; 1194 let ResourceCycles = [1,1,1,2]; 1195} 1196def: InstRW<[SKLWriteResGroup101], (instregex "XADD(8|16|32|64)rm")>; 1197 1198def SKLWriteResGroup102 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> { 1199 let Latency = 7; 1200 let NumMicroOps = 5; 1201 let ResourceCycles = [1,1,1,1,1]; 1202} 1203def: InstRW<[SKLWriteResGroup102], (instregex "CALL(16|32|64)m")>; 1204def: InstRW<[SKLWriteResGroup102], (instrs FARCALL64m)>; 1205 1206def SKLWriteResGroup103 : SchedWriteRes<[SKLPort6,SKLPort06,SKLPort15,SKLPort0156]> { 1207 let Latency = 7; 1208 let NumMicroOps = 7; 1209 let ResourceCycles = [1,3,1,2]; 1210} 1211def: InstRW<[SKLWriteResGroup103], (instrs LOOP)>; 1212 1213def SKLWriteResGroup107 : SchedWriteRes<[SKLPort1,SKLPort23]> { 1214 let Latency = 8; 1215 let NumMicroOps = 2; 1216 let ResourceCycles = [1,1]; 1217} 1218def: InstRW<[SKLWriteResGroup107], (instregex "PDEP(32|64)rm", 1219 "PEXT(32|64)rm")>; 1220 1221def SKLWriteResGroup108 : SchedWriteRes<[SKLPort5,SKLPort23]> { 1222 let Latency = 8; 1223 let NumMicroOps = 2; 1224 let ResourceCycles = [1,1]; 1225} 1226def: InstRW<[SKLWriteResGroup108], (instregex "FCOM(P?)(32|64)m")>; 1227def: InstRW<[SKLWriteResGroup108], (instrs VPBROADCASTBYrm, 1228 VPBROADCASTWYrm, 1229 VPMOVSXBDYrm, 1230 VPMOVSXBQYrm, 1231 VPMOVSXWQYrm)>; 1232 1233def SKLWriteResGroup110 : SchedWriteRes<[SKLPort23,SKLPort015]> { 1234 let Latency = 8; 1235 let NumMicroOps = 2; 1236 let ResourceCycles = [1,1]; 1237} 1238def: InstRW<[SKLWriteResGroup110], (instrs VPBLENDDYrmi)>; 1239def: InstRW<[SKLWriteResGroup110, ReadAfterVecYLd], 1240 (instregex "VPADD(B|D|Q|W)Yrm", 1241 "VPSUB(B|D|Q|W)Yrm")>; 1242 1243def SKLWriteResGroup112 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> { 1244 let Latency = 8; 1245 let NumMicroOps = 4; 1246 let ResourceCycles = [1,2,1]; 1247} 1248def: InstRW<[SKLWriteResGroup112], (instregex "MMX_PH(ADD|SUB)SWrm")>; 1249 1250def SKLWriteResGroup116 : SchedWriteRes<[SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> { 1251 let Latency = 8; 1252 let NumMicroOps = 5; 1253 let ResourceCycles = [1,1,1,2]; 1254} 1255def: InstRW<[SKLWriteResGroup116], (instregex "RCL(8|16|32|64)m(1|i)", 1256 "RCR(8|16|32|64)m(1|i)")>; 1257 1258def SKLWriteResGroup117 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> { 1259 let Latency = 8; 1260 let NumMicroOps = 6; 1261 let ResourceCycles = [1,1,1,3]; 1262} 1263def: InstRW<[SKLWriteResGroup117], (instregex "ROL(8|16|32|64)mCL", 1264 "ROR(8|16|32|64)mCL", 1265 "SAR(8|16|32|64)mCL", 1266 "SHL(8|16|32|64)mCL", 1267 "SHR(8|16|32|64)mCL")>; 1268 1269def SKLWriteResGroup119 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> { 1270 let Latency = 8; 1271 let NumMicroOps = 6; 1272 let ResourceCycles = [1,1,1,2,1]; 1273} 1274def: SchedAlias<WriteADCRMW, SKLWriteResGroup119>; 1275 1276def SKLWriteResGroup120 : SchedWriteRes<[SKLPort0,SKLPort23]> { 1277 let Latency = 9; 1278 let NumMicroOps = 2; 1279 let ResourceCycles = [1,1]; 1280} 1281def: InstRW<[SKLWriteResGroup120], (instrs MMX_CVTPI2PSirm)>; 1282 1283def SKLWriteResGroup121 : SchedWriteRes<[SKLPort5,SKLPort23]> { 1284 let Latency = 9; 1285 let NumMicroOps = 2; 1286 let ResourceCycles = [1,1]; 1287} 1288def: InstRW<[SKLWriteResGroup121], (instrs PCMPGTQrm, 1289 VPCMPGTQrm, 1290 VPMOVSXBWYrm, 1291 VPMOVSXDQYrm, 1292 VPMOVSXWDYrm, 1293 VPMOVZXWDYrm)>; 1294 1295def SKLWriteResGroup123 : SchedWriteRes<[SKLPort23,SKLPort01]> { 1296 let Latency = 9; 1297 let NumMicroOps = 2; 1298 let ResourceCycles = [1,1]; 1299} 1300def: InstRW<[SKLWriteResGroup123], (instregex "MMX_CVT(T?)PS2PIirm", 1301 "(V?)CVTPS2PDrm")>; 1302 1303def SKLWriteResGroup128 : SchedWriteRes<[SKLPort5,SKLPort01,SKLPort23]> { 1304 let Latency = 9; 1305 let NumMicroOps = 4; 1306 let ResourceCycles = [2,1,1]; 1307} 1308def: InstRW<[SKLWriteResGroup128], (instregex "(V?)PHADDSWrm", 1309 "(V?)PHSUBSWrm")>; 1310 1311def SKLWriteResGroup131 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort23,SKLPort0156]> { 1312 let Latency = 9; 1313 let NumMicroOps = 5; 1314 let ResourceCycles = [1,2,1,1]; 1315} 1316def: InstRW<[SKLWriteResGroup131], (instregex "LAR(16|32|64)rm", 1317 "LSL(16|32|64)rm")>; 1318 1319def SKLWriteResGroup133 : SchedWriteRes<[SKLPort5,SKLPort23]> { 1320 let Latency = 10; 1321 let NumMicroOps = 2; 1322 let ResourceCycles = [1,1]; 1323} 1324def: InstRW<[SKLWriteResGroup133], (instregex "(ADD|SUB|SUBR)_F(32|64)m", 1325 "ILD_F(16|32|64)m")>; 1326def: InstRW<[SKLWriteResGroup133], (instrs VPCMPGTQYrm)>; 1327 1328def SKLWriteResGroup134 : SchedWriteRes<[SKLPort01,SKLPort23]> { 1329 let Latency = 10; 1330 let NumMicroOps = 2; 1331 let ResourceCycles = [1,1]; 1332} 1333def: InstRW<[SKLWriteResGroup134], (instregex "(V?)CVTDQ2PSrm", 1334 "(V?)CVTPS2DQrm", 1335 "(V?)CVTSS2SDrm", 1336 "(V?)CVTTPS2DQrm")>; 1337 1338def SKLWriteResGroup138 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> { 1339 let Latency = 10; 1340 let NumMicroOps = 3; 1341 let ResourceCycles = [1,1,1]; 1342} 1343def: InstRW<[SKLWriteResGroup138], (instrs MMX_CVTPI2PDirm)>; 1344 1345def SKLWriteResGroup139 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort01]> { 1346 let Latency = 10; 1347 let NumMicroOps = 3; 1348 let ResourceCycles = [1,1,1]; 1349} 1350def: InstRW<[SKLWriteResGroup139], (instregex "(V?)CVTSD2SSrm")>; 1351 1352def SKLWriteResGroup140 : SchedWriteRes<[SKLPort5,SKLPort01,SKLPort23]> { 1353 let Latency = 10; 1354 let NumMicroOps = 4; 1355 let ResourceCycles = [2,1,1]; 1356} 1357def: InstRW<[SKLWriteResGroup140], (instrs VPHADDSWYrm, 1358 VPHSUBSWYrm)>; 1359 1360def SKLWriteResGroup143 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> { 1361 let Latency = 10; 1362 let NumMicroOps = 8; 1363 let ResourceCycles = [1,1,1,1,1,3]; 1364} 1365def: InstRW<[SKLWriteResGroup143], (instregex "XCHG(8|16|32|64)rm")>; 1366 1367def SKLWriteResGroup145 : SchedWriteRes<[SKLPort0,SKLFPDivider]> { 1368 let Latency = 11; 1369 let NumMicroOps = 1; 1370 let ResourceCycles = [1,3]; 1371} 1372def : SchedAlias<WriteFDivX, SKLWriteResGroup145>; // TODO - convert to ZnWriteResFpuPair 1373 1374def SKLWriteResGroup146 : SchedWriteRes<[SKLPort0,SKLPort23]> { 1375 let Latency = 11; 1376 let NumMicroOps = 2; 1377 let ResourceCycles = [1,1]; 1378} 1379def: InstRW<[SKLWriteResGroup146], (instregex "MUL_F(32|64)m")>; 1380 1381def SKLWriteResGroup147 : SchedWriteRes<[SKLPort01,SKLPort23]> { 1382 let Latency = 11; 1383 let NumMicroOps = 2; 1384 let ResourceCycles = [1,1]; 1385} 1386def: InstRW<[SKLWriteResGroup147], (instrs VCVTDQ2PSYrm, 1387 VCVTPS2PDYrm, 1388 VCVTPS2DQYrm, 1389 VCVTTPS2DQYrm)>; 1390 1391def SKLWriteResGroup149 : SchedWriteRes<[SKLPort5,SKLPort23]> { 1392 let Latency = 11; 1393 let NumMicroOps = 3; 1394 let ResourceCycles = [2,1]; 1395} 1396def: InstRW<[SKLWriteResGroup149], (instregex "FICOM(P?)(16|32)m")>; 1397 1398def SKLWriteResGroup150 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> { 1399 let Latency = 11; 1400 let NumMicroOps = 3; 1401 let ResourceCycles = [1,1,1]; 1402} 1403def: InstRW<[SKLWriteResGroup150], (instregex "(V?)CVTDQ2PDrm")>; 1404 1405def SKLWriteResGroup151 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort01]> { 1406 let Latency = 11; 1407 let NumMicroOps = 3; 1408 let ResourceCycles = [1,1,1]; 1409} 1410def: InstRW<[SKLWriteResGroup151], (instregex "(V?)CVTSS2SI64rm", 1411 "(V?)CVT(T?)SD2SI(64)?rm", 1412 "VCVTTSS2SI64rm", 1413 "(V?)CVT(T?)SS2SIrm")>; 1414 1415def SKLWriteResGroup152 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort01]> { 1416 let Latency = 11; 1417 let NumMicroOps = 3; 1418 let ResourceCycles = [1,1,1]; 1419} 1420def: InstRW<[SKLWriteResGroup152], (instrs CVTPD2PSrm, 1421 CVTPD2DQrm, 1422 CVTTPD2DQrm, 1423 MMX_CVTPD2PIirm, 1424 MMX_CVTTPD2PIirm)>; 1425 1426def SKLWriteResGroup154 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort0156]> { 1427 let Latency = 11; 1428 let NumMicroOps = 7; 1429 let ResourceCycles = [2,3,2]; 1430} 1431def: InstRW<[SKLWriteResGroup154], (instregex "RCL(16|32|64)rCL", 1432 "RCR(16|32|64)rCL")>; 1433 1434def SKLWriteResGroup155 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort15,SKLPort0156]> { 1435 let Latency = 11; 1436 let NumMicroOps = 9; 1437 let ResourceCycles = [1,5,1,2]; 1438} 1439def: InstRW<[SKLWriteResGroup155], (instrs RCL8rCL)>; 1440 1441def SKLWriteResGroup156 : SchedWriteRes<[SKLPort06,SKLPort0156]> { 1442 let Latency = 11; 1443 let NumMicroOps = 11; 1444 let ResourceCycles = [2,9]; 1445} 1446def: InstRW<[SKLWriteResGroup156], (instrs LOOPE, LOOPNE)>; 1447 1448def SKLWriteResGroup160 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23,SKLPort01]> { 1449 let Latency = 12; 1450 let NumMicroOps = 4; 1451 let ResourceCycles = [1,1,1,1]; 1452} 1453def: InstRW<[SKLWriteResGroup160], (instregex "CVTTSS2SI64rm")>; 1454 1455def SKLWriteResGroup162 : SchedWriteRes<[SKLPort5,SKLPort23]> { 1456 let Latency = 13; 1457 let NumMicroOps = 3; 1458 let ResourceCycles = [2,1]; 1459} 1460def: InstRW<[SKLWriteResGroup162], (instregex "(ADD|SUB|SUBR)_FI(16|32)m")>; 1461 1462def SKLWriteResGroup163 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> { 1463 let Latency = 13; 1464 let NumMicroOps = 3; 1465 let ResourceCycles = [1,1,1]; 1466} 1467def: InstRW<[SKLWriteResGroup163], (instrs VCVTDQ2PDYrm)>; 1468 1469def SKLWriteResGroup166 : SchedWriteRes<[SKLPort0,SKLFPDivider]> { 1470 let Latency = 14; 1471 let NumMicroOps = 1; 1472 let ResourceCycles = [1,3]; 1473} 1474def : SchedAlias<WriteFDiv64, SKLWriteResGroup166>; // TODO - convert to ZnWriteResFpuPair 1475def : SchedAlias<WriteFDiv64X, SKLWriteResGroup166>; // TODO - convert to ZnWriteResFpuPair 1476 1477def SKLWriteResGroup166_1 : SchedWriteRes<[SKLPort0,SKLFPDivider]> { 1478 let Latency = 14; 1479 let NumMicroOps = 1; 1480 let ResourceCycles = [1,5]; 1481} 1482def : SchedAlias<WriteFDiv64Y, SKLWriteResGroup166_1>; // TODO - convert to ZnWriteResFpuPair 1483 1484def SKLWriteResGroup169 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> { 1485 let Latency = 14; 1486 let NumMicroOps = 3; 1487 let ResourceCycles = [1,1,1]; 1488} 1489def: InstRW<[SKLWriteResGroup169], (instregex "MUL_FI(16|32)m")>; 1490 1491def SKLWriteResGroup170 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort15,SKLPort0156]> { 1492 let Latency = 14; 1493 let NumMicroOps = 10; 1494 let ResourceCycles = [2,4,1,3]; 1495} 1496def: InstRW<[SKLWriteResGroup170], (instrs RCR8rCL)>; 1497 1498def SKLWriteResGroup171 : SchedWriteRes<[SKLPort0]> { 1499 let Latency = 15; 1500 let NumMicroOps = 1; 1501 let ResourceCycles = [1]; 1502} 1503def: InstRW<[SKLWriteResGroup171], (instregex "DIVR_(FPrST0|FST0r|FrST0)")>; 1504 1505def SKLWriteResGroup174 : SchedWriteRes<[SKLPort1,SKLPort23,SKLPort237,SKLPort06,SKLPort15,SKLPort0156]> { 1506 let Latency = 15; 1507 let NumMicroOps = 10; 1508 let ResourceCycles = [1,1,1,5,1,1]; 1509} 1510def: InstRW<[SKLWriteResGroup174], (instregex "RCL(8|16|32|64)mCL")>; 1511 1512def SKLWriteResGroup177 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06,SKLPort15,SKLPort0156]> { 1513 let Latency = 16; 1514 let NumMicroOps = 14; 1515 let ResourceCycles = [1,1,1,4,2,5]; 1516} 1517def: InstRW<[SKLWriteResGroup177], (instrs CMPXCHG8B)>; 1518 1519def SKLWriteResGroup178 : SchedWriteRes<[SKLPort0156]> { 1520 let Latency = 16; 1521 let NumMicroOps = 16; 1522 let ResourceCycles = [16]; 1523} 1524def: InstRW<[SKLWriteResGroup178], (instrs VZEROALL)>; 1525 1526def SKLWriteResGroup179 : SchedWriteRes<[SKLPort0,SKLPort23,SKLFPDivider]> { 1527 let Latency = 17; 1528 let NumMicroOps = 2; 1529 let ResourceCycles = [1,1,5]; 1530} 1531def : SchedAlias<WriteFDivXLd, SKLWriteResGroup179>; // TODO - convert to ZnWriteResFpuPair 1532 1533def SKLWriteResGroup180 : SchedWriteRes<[SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort05,SKLPort0156]> { 1534 let Latency = 17; 1535 let NumMicroOps = 15; 1536 let ResourceCycles = [2,1,2,4,2,4]; 1537} 1538def: InstRW<[SKLWriteResGroup180], (instrs XCH_F)>; 1539 1540def SKLWriteResGroup184 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort06,SKLPort0156]> { 1541 let Latency = 18; 1542 let NumMicroOps = 8; 1543 let ResourceCycles = [1,1,1,5]; 1544} 1545def: InstRW<[SKLWriteResGroup184], (instrs CPUID, RDTSC)>; 1546 1547def SKLWriteResGroup185 : SchedWriteRes<[SKLPort1,SKLPort23,SKLPort237,SKLPort06,SKLPort15,SKLPort0156]> { 1548 let Latency = 18; 1549 let NumMicroOps = 11; 1550 let ResourceCycles = [2,1,1,4,1,2]; 1551} 1552def: InstRW<[SKLWriteResGroup185], (instregex "RCR(8|16|32|64)mCL")>; 1553 1554def SKLWriteResGroup186 : SchedWriteRes<[SKLPort0,SKLPort23,SKLFPDivider]> { 1555 let Latency = 19; 1556 let NumMicroOps = 2; 1557 let ResourceCycles = [1,1,4]; 1558} 1559def : SchedAlias<WriteFDiv64Ld, SKLWriteResGroup186>; // TODO - convert to ZnWriteResFpuPair 1560 1561def SKLWriteResGroup189 : SchedWriteRes<[SKLPort0]> { 1562 let Latency = 20; 1563 let NumMicroOps = 1; 1564 let ResourceCycles = [1]; 1565} 1566def: InstRW<[SKLWriteResGroup189], (instregex "DIV_(FPrST0|FST0r|FrST0)")>; 1567 1568def SKLWriteResGroup190 : SchedWriteRes<[SKLPort0,SKLPort23,SKLFPDivider]> { 1569 let Latency = 20; 1570 let NumMicroOps = 2; 1571 let ResourceCycles = [1,1,4]; 1572} 1573def : SchedAlias<WriteFDiv64XLd, SKLWriteResGroup190>; // TODO - convert to ZnWriteResFpuPair 1574 1575def SKLWriteResGroup192 : SchedWriteRes<[SKLPort4,SKLPort5,SKLPort6,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> { 1576 let Latency = 20; 1577 let NumMicroOps = 8; 1578 let ResourceCycles = [1,1,1,1,1,1,2]; 1579} 1580def: InstRW<[SKLWriteResGroup192], (instrs INSB, INSL, INSW)>; 1581 1582def SKLWriteResGroup193 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort0156]> { 1583 let Latency = 20; 1584 let NumMicroOps = 10; 1585 let ResourceCycles = [1,2,7]; 1586} 1587def: InstRW<[SKLWriteResGroup193], (instrs MWAITrr)>; 1588 1589def SKLWriteResGroup195 : SchedWriteRes<[SKLPort0,SKLPort23,SKLFPDivider]> { 1590 let Latency = 21; 1591 let NumMicroOps = 2; 1592 let ResourceCycles = [1,1,8]; 1593} 1594def : SchedAlias<WriteFDiv64YLd, SKLWriteResGroup195>; // TODO - convert to ZnWriteResFpuPair 1595 1596def SKLWriteResGroup196 : SchedWriteRes<[SKLPort0,SKLPort23]> { 1597 let Latency = 22; 1598 let NumMicroOps = 2; 1599 let ResourceCycles = [1,1]; 1600} 1601def: InstRW<[SKLWriteResGroup196], (instregex "DIV_F(32|64)m")>; 1602 1603def SKLWriteResGroupVEX2 : SchedWriteRes<[SKLPort0, SKLPort23, SKLPort5, SKLPort015]> { 1604 let Latency = 18; 1605 let NumMicroOps = 5; // 2 uops perform multiple loads 1606 let ResourceCycles = [1,2,1,1]; 1607} 1608def: InstRW<[SKLWriteResGroupVEX2], (instrs VGATHERDPDrm, VPGATHERDQrm, 1609 VGATHERQPDrm, VPGATHERQQrm, 1610 VGATHERQPSrm, VPGATHERQDrm)>; 1611 1612def SKLWriteResGroupVEX4 : SchedWriteRes<[SKLPort0, SKLPort23, SKLPort5, SKLPort015]> { 1613 let Latency = 20; 1614 let NumMicroOps = 5; // 2 uops peform multiple loads 1615 let ResourceCycles = [1,4,1,1]; 1616} 1617def: InstRW<[SKLWriteResGroupVEX4], (instrs VGATHERDPDYrm, VPGATHERDQYrm, 1618 VGATHERDPSrm, VPGATHERDDrm, 1619 VGATHERQPDYrm, VPGATHERQQYrm, 1620 VGATHERQPSYrm, VPGATHERQDYrm)>; 1621 1622def SKLWriteResGroupVEX8 : SchedWriteRes<[SKLPort0, SKLPort23, SKLPort5, SKLPort015]> { 1623 let Latency = 22; 1624 let NumMicroOps = 5; // 2 uops perform multiple loads 1625 let ResourceCycles = [1,8,1,1]; 1626} 1627def: InstRW<[SKLWriteResGroupVEX8], (instrs VGATHERDPSYrm, VPGATHERDDYrm)>; 1628 1629def SKLWriteResGroup198 : SchedWriteRes<[SKLPort0,SKLPort4,SKLPort5,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> { 1630 let Latency = 23; 1631 let NumMicroOps = 19; 1632 let ResourceCycles = [2,1,4,1,1,4,6]; 1633} 1634def: InstRW<[SKLWriteResGroup198], (instrs CMPXCHG16B)>; 1635 1636def SKLWriteResGroup202 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> { 1637 let Latency = 25; 1638 let NumMicroOps = 3; 1639 let ResourceCycles = [1,1,1]; 1640} 1641def: InstRW<[SKLWriteResGroup202], (instregex "DIV_FI(16|32)m")>; 1642 1643def SKLWriteResGroup206 : SchedWriteRes<[SKLPort0,SKLPort23]> { 1644 let Latency = 27; 1645 let NumMicroOps = 2; 1646 let ResourceCycles = [1,1]; 1647} 1648def: InstRW<[SKLWriteResGroup206], (instregex "DIVR_F(32|64)m")>; 1649 1650def SKLWriteResGroup208 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> { 1651 let Latency = 30; 1652 let NumMicroOps = 3; 1653 let ResourceCycles = [1,1,1]; 1654} 1655def: InstRW<[SKLWriteResGroup208], (instregex "DIVR_FI(16|32)m")>; 1656 1657def SKLWriteResGroup209 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort23,SKLPort06,SKLPort0156]> { 1658 let Latency = 35; 1659 let NumMicroOps = 23; 1660 let ResourceCycles = [1,5,3,4,10]; 1661} 1662def: InstRW<[SKLWriteResGroup209], (instregex "IN(8|16|32)ri", 1663 "IN(8|16|32)rr")>; 1664 1665def SKLWriteResGroup210 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> { 1666 let Latency = 35; 1667 let NumMicroOps = 23; 1668 let ResourceCycles = [1,5,2,1,4,10]; 1669} 1670def: InstRW<[SKLWriteResGroup210], (instregex "OUT(8|16|32)ir", 1671 "OUT(8|16|32)rr")>; 1672 1673def SKLWriteResGroup211 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort23,SKLPort0156]> { 1674 let Latency = 37; 1675 let NumMicroOps = 31; 1676 let ResourceCycles = [1,8,1,21]; 1677} 1678def: InstRW<[SKLWriteResGroup211], (instregex "XRSTOR(64)?")>; 1679 1680def SKLWriteResGroup212 : SchedWriteRes<[SKLPort1,SKLPort4,SKLPort5,SKLPort6,SKLPort23,SKLPort237,SKLPort15,SKLPort0156]> { 1681 let Latency = 40; 1682 let NumMicroOps = 18; 1683 let ResourceCycles = [1,1,2,3,1,1,1,8]; 1684} 1685def: InstRW<[SKLWriteResGroup212], (instrs VMCLEARm)>; 1686 1687def SKLWriteResGroup213 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> { 1688 let Latency = 41; 1689 let NumMicroOps = 39; 1690 let ResourceCycles = [1,10,1,1,26]; 1691} 1692def: InstRW<[SKLWriteResGroup213], (instrs XSAVE64)>; 1693 1694def SKLWriteResGroup214 : SchedWriteRes<[SKLPort5,SKLPort0156]> { 1695 let Latency = 42; 1696 let NumMicroOps = 22; 1697 let ResourceCycles = [2,20]; 1698} 1699def: InstRW<[SKLWriteResGroup214], (instrs RDTSCP)>; 1700 1701def SKLWriteResGroup215 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> { 1702 let Latency = 42; 1703 let NumMicroOps = 40; 1704 let ResourceCycles = [1,11,1,1,26]; 1705} 1706def: InstRW<[SKLWriteResGroup215], (instrs XSAVE)>; 1707def: InstRW<[SKLWriteResGroup215], (instregex "XSAVEC", "XSAVES")>; 1708 1709def SKLWriteResGroup216 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> { 1710 let Latency = 46; 1711 let NumMicroOps = 44; 1712 let ResourceCycles = [1,11,1,1,30]; 1713} 1714def: InstRW<[SKLWriteResGroup216], (instregex "XSAVEOPT")>; 1715 1716def SKLWriteResGroup217 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort05,SKLPort06,SKLPort0156]> { 1717 let Latency = 62; 1718 let NumMicroOps = 64; 1719 let ResourceCycles = [2,8,5,10,39]; 1720} 1721def: InstRW<[SKLWriteResGroup217], (instrs FLDENVm)>; 1722 1723def SKLWriteResGroup218 : SchedWriteRes<[SKLPort0,SKLPort6,SKLPort23,SKLPort05,SKLPort06,SKLPort15,SKLPort0156]> { 1724 let Latency = 63; 1725 let NumMicroOps = 88; 1726 let ResourceCycles = [4,4,31,1,2,1,45]; 1727} 1728def: InstRW<[SKLWriteResGroup218], (instrs FXRSTOR64)>; 1729 1730def SKLWriteResGroup219 : SchedWriteRes<[SKLPort0,SKLPort6,SKLPort23,SKLPort05,SKLPort06,SKLPort15,SKLPort0156]> { 1731 let Latency = 63; 1732 let NumMicroOps = 90; 1733 let ResourceCycles = [4,2,33,1,2,1,47]; 1734} 1735def: InstRW<[SKLWriteResGroup219], (instrs FXRSTOR)>; 1736 1737def SKLWriteResGroup220 : SchedWriteRes<[SKLPort5,SKLPort05,SKLPort0156]> { 1738 let Latency = 75; 1739 let NumMicroOps = 15; 1740 let ResourceCycles = [6,3,6]; 1741} 1742def: InstRW<[SKLWriteResGroup220], (instrs FNINIT)>; 1743 1744def SKLWriteResGroup223 : SchedWriteRes<[SKLPort0,SKLPort1,SKLPort4,SKLPort5,SKLPort6,SKLPort237,SKLPort06,SKLPort0156]> { 1745 let Latency = 106; 1746 let NumMicroOps = 100; 1747 let ResourceCycles = [9,1,11,16,1,11,21,30]; 1748} 1749def: InstRW<[SKLWriteResGroup223], (instrs FSTENVm)>; 1750 1751def: InstRW<[WriteZero], (instrs CLC)>; 1752 1753 1754// Instruction variants handled by the renamer. These might not need execution 1755// ports in certain conditions. 1756// See Agner's Fog "The microarchitecture of Intel, AMD and VIA CPUs", 1757// section "Skylake Pipeline" > "Register allocation and renaming". 1758// These can be investigated with llvm-exegesis, e.g. 1759// echo 'pxor %mm0, %mm0' | /tmp/llvm-exegesis -mode=uops -snippets-file=- 1760// echo 'vxorpd %xmm0, %xmm0, %xmm1' | /tmp/llvm-exegesis -mode=uops -snippets-file=- 1761 1762def SKLWriteZeroLatency : SchedWriteRes<[]> { 1763 let Latency = 0; 1764} 1765 1766def SKLWriteZeroIdiom : SchedWriteVariant<[ 1767 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>, 1768 SchedVar<NoSchedPred, [WriteALU]> 1769]>; 1770def : InstRW<[SKLWriteZeroIdiom], (instrs SUB32rr, SUB64rr, 1771 XOR32rr, XOR64rr)>; 1772 1773def SKLWriteFZeroIdiom : SchedWriteVariant<[ 1774 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>, 1775 SchedVar<NoSchedPred, [WriteFLogic]> 1776]>; 1777def : InstRW<[SKLWriteFZeroIdiom], (instrs XORPSrr, VXORPSrr, XORPDrr, 1778 VXORPDrr)>; 1779 1780def SKLWriteFZeroIdiomY : SchedWriteVariant<[ 1781 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>, 1782 SchedVar<NoSchedPred, [WriteFLogicY]> 1783]>; 1784def : InstRW<[SKLWriteFZeroIdiomY], (instrs VXORPSYrr, VXORPDYrr)>; 1785 1786def SKLWriteVZeroIdiomLogicX : SchedWriteVariant<[ 1787 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>, 1788 SchedVar<NoSchedPred, [WriteVecLogicX]> 1789]>; 1790def : InstRW<[SKLWriteVZeroIdiomLogicX], (instrs PXORrr, VPXORrr)>; 1791 1792def SKLWriteVZeroIdiomLogicY : SchedWriteVariant<[ 1793 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>, 1794 SchedVar<NoSchedPred, [WriteVecLogicY]> 1795]>; 1796def : InstRW<[SKLWriteVZeroIdiomLogicY], (instrs VPXORYrr)>; 1797 1798def SKLWriteVZeroIdiomALUX : SchedWriteVariant<[ 1799 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>, 1800 SchedVar<NoSchedPred, [WriteVecALUX]> 1801]>; 1802def : InstRW<[SKLWriteVZeroIdiomALUX], (instrs PCMPGTBrr, VPCMPGTBrr, 1803 PCMPGTDrr, VPCMPGTDrr, 1804 PCMPGTWrr, VPCMPGTWrr)>; 1805 1806def SKLWriteVZeroIdiomALUY : SchedWriteVariant<[ 1807 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>, 1808 SchedVar<NoSchedPred, [WriteVecALUY]> 1809]>; 1810def : InstRW<[SKLWriteVZeroIdiomALUY], (instrs VPCMPGTBYrr, 1811 VPCMPGTDYrr, 1812 VPCMPGTWYrr)>; 1813 1814def SKLWritePSUB : SchedWriteRes<[SKLPort015]> { 1815 let Latency = 1; 1816 let NumMicroOps = 1; 1817 let ResourceCycles = [1]; 1818} 1819 1820def SKLWriteVZeroIdiomPSUB : SchedWriteVariant<[ 1821 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>, 1822 SchedVar<NoSchedPred, [SKLWritePSUB]> 1823]>; 1824def : InstRW<[SKLWriteVZeroIdiomPSUB], (instrs PSUBBrr, VPSUBBrr, 1825 PSUBDrr, VPSUBDrr, 1826 PSUBQrr, VPSUBQrr, 1827 PSUBWrr, VPSUBWrr, 1828 VPSUBBYrr, 1829 VPSUBDYrr, 1830 VPSUBQYrr, 1831 VPSUBWYrr)>; 1832 1833def SKLWritePCMPGTQ : SchedWriteRes<[SKLPort5]> { 1834 let Latency = 3; 1835 let NumMicroOps = 1; 1836 let ResourceCycles = [1]; 1837} 1838 1839def SKLWriteVZeroIdiomPCMPGTQ : SchedWriteVariant<[ 1840 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>, 1841 SchedVar<NoSchedPred, [SKLWritePCMPGTQ]> 1842]>; 1843def : InstRW<[SKLWriteVZeroIdiomPCMPGTQ], (instrs PCMPGTQrr, VPCMPGTQrr, 1844 VPCMPGTQYrr)>; 1845 1846 1847// CMOVs that use both Z and C flag require an extra uop. 1848def SKLWriteCMOVA_CMOVBErr : SchedWriteRes<[SKLPort06]> { 1849 let Latency = 2; 1850 let ResourceCycles = [2]; 1851 let NumMicroOps = 2; 1852} 1853 1854def SKLWriteCMOVA_CMOVBErm : SchedWriteRes<[SKLPort23,SKLPort06]> { 1855 let Latency = 7; 1856 let ResourceCycles = [1,2]; 1857 let NumMicroOps = 3; 1858} 1859 1860def SKLCMOVA_CMOVBErr : SchedWriteVariant<[ 1861 SchedVar<MCSchedPredicate<IsCMOVArr_Or_CMOVBErr>, [SKLWriteCMOVA_CMOVBErr]>, 1862 SchedVar<NoSchedPred, [WriteCMOV]> 1863]>; 1864 1865def SKLCMOVA_CMOVBErm : SchedWriteVariant<[ 1866 SchedVar<MCSchedPredicate<IsCMOVArm_Or_CMOVBErm>, [SKLWriteCMOVA_CMOVBErm]>, 1867 SchedVar<NoSchedPred, [WriteCMOV.Folded]> 1868]>; 1869 1870def : InstRW<[SKLCMOVA_CMOVBErr], (instrs CMOV16rr, CMOV32rr, CMOV64rr)>; 1871def : InstRW<[SKLCMOVA_CMOVBErm], (instrs CMOV16rm, CMOV32rm, CMOV64rm)>; 1872 1873// SETCCs that use both Z and C flag require an extra uop. 1874def SKLWriteSETA_SETBEr : SchedWriteRes<[SKLPort06]> { 1875 let Latency = 2; 1876 let ResourceCycles = [2]; 1877 let NumMicroOps = 2; 1878} 1879 1880def SKLWriteSETA_SETBEm : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort06]> { 1881 let Latency = 3; 1882 let ResourceCycles = [1,1,2]; 1883 let NumMicroOps = 4; 1884} 1885 1886def SKLSETA_SETBErr : SchedWriteVariant<[ 1887 SchedVar<MCSchedPredicate<IsSETAr_Or_SETBEr>, [SKLWriteSETA_SETBEr]>, 1888 SchedVar<NoSchedPred, [WriteSETCC]> 1889]>; 1890 1891def SKLSETA_SETBErm : SchedWriteVariant<[ 1892 SchedVar<MCSchedPredicate<IsSETAm_Or_SETBEm>, [SKLWriteSETA_SETBEm]>, 1893 SchedVar<NoSchedPred, [WriteSETCCStore]> 1894]>; 1895 1896def : InstRW<[SKLSETA_SETBErr], (instrs SETCCr)>; 1897def : InstRW<[SKLSETA_SETBErm], (instrs SETCCm)>; 1898 1899} // SchedModel 1900