1//=- X86SchedSkylake.td - X86 Skylake Client Scheduling ------*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the machine model for Skylake Client to support 10// instruction scheduling and other instruction cost heuristics. 11// 12//===----------------------------------------------------------------------===// 13 14def SkylakeClientModel : SchedMachineModel { 15 // All x86 instructions are modeled as a single micro-op, and SKylake can 16 // decode 6 instructions per cycle. 17 let IssueWidth = 6; 18 let MicroOpBufferSize = 224; // Based on the reorder buffer. 19 let LoadLatency = 5; 20 let MispredictPenalty = 14; 21 22 // Based on the LSD (loop-stream detector) queue size and benchmarking data. 23 let LoopMicroOpBufferSize = 50; 24 25 // This flag is set to allow the scheduler to assign a default model to 26 // unrecognized opcodes. 27 let CompleteModel = 0; 28} 29 30let SchedModel = SkylakeClientModel in { 31 32// Skylake Client can issue micro-ops to 8 different ports in one cycle. 33 34// Ports 0, 1, 5, and 6 handle all computation. 35// Port 4 gets the data half of stores. Store data can be available later than 36// the store address, but since we don't model the latency of stores, we can 37// ignore that. 38// Ports 2 and 3 are identical. They handle loads and the address half of 39// stores. Port 7 can handle address calculations. 40def SKLPort0 : ProcResource<1>; 41def SKLPort1 : ProcResource<1>; 42def SKLPort2 : ProcResource<1>; 43def SKLPort3 : ProcResource<1>; 44def SKLPort4 : ProcResource<1>; 45def SKLPort5 : ProcResource<1>; 46def SKLPort6 : ProcResource<1>; 47def SKLPort7 : ProcResource<1>; 48 49// Many micro-ops are capable of issuing on multiple ports. 50def SKLPort01 : ProcResGroup<[SKLPort0, SKLPort1]>; 51def SKLPort23 : ProcResGroup<[SKLPort2, SKLPort3]>; 52def SKLPort237 : ProcResGroup<[SKLPort2, SKLPort3, SKLPort7]>; 53def SKLPort04 : ProcResGroup<[SKLPort0, SKLPort4]>; 54def SKLPort05 : ProcResGroup<[SKLPort0, SKLPort5]>; 55def SKLPort06 : ProcResGroup<[SKLPort0, SKLPort6]>; 56def SKLPort15 : ProcResGroup<[SKLPort1, SKLPort5]>; 57def SKLPort16 : ProcResGroup<[SKLPort1, SKLPort6]>; 58def SKLPort56 : ProcResGroup<[SKLPort5, SKLPort6]>; 59def SKLPort015 : ProcResGroup<[SKLPort0, SKLPort1, SKLPort5]>; 60def SKLPort056 : ProcResGroup<[SKLPort0, SKLPort5, SKLPort6]>; 61def SKLPort0156: ProcResGroup<[SKLPort0, SKLPort1, SKLPort5, SKLPort6]>; 62 63def SKLDivider : ProcResource<1>; // Integer division issued on port 0. 64// FP division and sqrt on port 0. 65def SKLFPDivider : ProcResource<1>; 66 67// 60 Entry Unified Scheduler 68def SKLPortAny : ProcResGroup<[SKLPort0, SKLPort1, SKLPort2, SKLPort3, SKLPort4, 69 SKLPort5, SKLPort6, SKLPort7]> { 70 let BufferSize=60; 71} 72 73// Integer loads are 5 cycles, so ReadAfterLd registers needn't be available until 5 74// cycles after the memory operand. 75def : ReadAdvance<ReadAfterLd, 5>; 76 77// Vector loads are 5/6/7 cycles, so ReadAfterVec*Ld registers needn't be available 78// until 5/6/7 cycles after the memory operand. 79def : ReadAdvance<ReadAfterVecLd, 5>; 80def : ReadAdvance<ReadAfterVecXLd, 6>; 81def : ReadAdvance<ReadAfterVecYLd, 7>; 82 83def : ReadAdvance<ReadInt2Fpu, 0>; 84 85// Many SchedWrites are defined in pairs with and without a folded load. 86// Instructions with folded loads are usually micro-fused, so they only appear 87// as two micro-ops when queued in the reservation station. 88// This multiclass defines the resource usage for variants with and without 89// folded loads. 90multiclass SKLWriteResPair<X86FoldableSchedWrite SchedRW, 91 list<ProcResourceKind> ExePorts, 92 int Lat, list<int> Res = [1], int UOps = 1, 93 int LoadLat = 5> { 94 // Register variant is using a single cycle on ExePort. 95 def : WriteRes<SchedRW, ExePorts> { 96 let Latency = Lat; 97 let ResourceCycles = Res; 98 let NumMicroOps = UOps; 99 } 100 101 // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to 102 // the latency (default = 5). 103 def : WriteRes<SchedRW.Folded, !listconcat([SKLPort23], ExePorts)> { 104 let Latency = !add(Lat, LoadLat); 105 let ResourceCycles = !listconcat([1], Res); 106 let NumMicroOps = !add(UOps, 1); 107 } 108} 109 110// A folded store needs a cycle on port 4 for the store data, and an extra port 111// 2/3/7 cycle to recompute the address. 112def : WriteRes<WriteRMW, [SKLPort237,SKLPort4]>; 113 114// Arithmetic. 115defm : SKLWriteResPair<WriteALU, [SKLPort0156], 1>; // Simple integer ALU op. 116defm : SKLWriteResPair<WriteADC, [SKLPort06], 1>; // Integer ALU + flags op. 117 118// Integer multiplication. 119defm : SKLWriteResPair<WriteIMul8, [SKLPort1], 3>; 120defm : SKLWriteResPair<WriteIMul16, [SKLPort1,SKLPort06,SKLPort0156], 4, [1,1,2], 4>; 121defm : X86WriteRes<WriteIMul16Imm, [SKLPort1,SKLPort0156], 4, [1,1], 2>; 122defm : X86WriteRes<WriteIMul16ImmLd, [SKLPort1,SKLPort0156,SKLPort23], 8, [1,1,1], 3>; 123defm : SKLWriteResPair<WriteIMul16Reg, [SKLPort1], 3>; 124defm : SKLWriteResPair<WriteIMul32, [SKLPort1,SKLPort06,SKLPort0156], 4, [1,1,1], 3>; 125defm : SKLWriteResPair<WriteMULX32, [SKLPort1,SKLPort06,SKLPort0156], 3, [1,1,1], 3>; 126defm : SKLWriteResPair<WriteIMul32Imm, [SKLPort1], 3>; 127defm : SKLWriteResPair<WriteIMul32Reg, [SKLPort1], 3>; 128defm : SKLWriteResPair<WriteIMul64, [SKLPort1,SKLPort5], 4, [1,1], 2>; 129defm : SKLWriteResPair<WriteMULX64, [SKLPort1,SKLPort5], 3, [1,1], 2>; 130defm : SKLWriteResPair<WriteIMul64Imm, [SKLPort1], 3>; 131defm : SKLWriteResPair<WriteIMul64Reg, [SKLPort1], 3>; 132def SKLWriteIMulH : WriteRes<WriteIMulH, []> { let Latency = 4; } 133def : WriteRes<WriteIMulHLd, []> { 134 let Latency = !add(SKLWriteIMulH.Latency, SkylakeClientModel.LoadLatency); 135} 136 137defm : X86WriteRes<WriteBSWAP32, [SKLPort15], 1, [1], 1>; 138defm : X86WriteRes<WriteBSWAP64, [SKLPort06, SKLPort15], 2, [1,1], 2>; 139defm : X86WriteRes<WriteCMPXCHG,[SKLPort06, SKLPort0156], 5, [2,3], 5>; 140defm : X86WriteRes<WriteCMPXCHGRMW,[SKLPort23,SKLPort06,SKLPort0156,SKLPort237,SKLPort4], 8, [1,2,1,1,1], 6>; 141defm : X86WriteRes<WriteXCHG, [SKLPort0156], 2, [3], 3>; 142 143// TODO: Why isn't the SKLDivider used? 144defm : SKLWriteResPair<WriteDiv8, [SKLPort0,SKLDivider], 25, [1,10], 1, 4>; 145defm : X86WriteRes<WriteDiv16, [SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort05,SKLPort0156], 76, [7,2,8,3,1,11], 32>; 146defm : X86WriteRes<WriteDiv32, [SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort05,SKLPort0156], 76, [7,2,8,3,1,11], 32>; 147defm : X86WriteRes<WriteDiv64, [SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort05,SKLPort0156], 76, [7,2,8,3,1,11], 32>; 148defm : X86WriteRes<WriteDiv16Ld, [SKLPort0,SKLPort23,SKLDivider], 29, [1,1,10], 2>; 149defm : X86WriteRes<WriteDiv32Ld, [SKLPort0,SKLPort23,SKLDivider], 29, [1,1,10], 2>; 150defm : X86WriteRes<WriteDiv64Ld, [SKLPort0,SKLPort23,SKLDivider], 29, [1,1,10], 2>; 151 152defm : X86WriteRes<WriteIDiv8, [SKLPort0,SKLDivider], 25, [1,10], 1>; 153defm : X86WriteRes<WriteIDiv16, [SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort06,SKLPort0156], 102, [4,2,4,8,14,34], 66>; 154defm : X86WriteRes<WriteIDiv32, [SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort06,SKLPort0156], 102, [4,2,4,8,14,34], 66>; 155defm : X86WriteRes<WriteIDiv64, [SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort06,SKLPort0156], 102, [4,2,4,8,14,34], 66>; 156defm : X86WriteRes<WriteIDiv8Ld, [SKLPort0,SKLPort5,SKLPort23,SKLPort0156], 28, [2,4,1,1], 8>; 157defm : X86WriteRes<WriteIDiv16Ld, [SKLPort0,SKLPort5,SKLPort23,SKLPort0156], 28, [2,4,1,1], 8>; 158defm : X86WriteRes<WriteIDiv32Ld, [SKLPort0,SKLPort5,SKLPort23,SKLPort0156], 28, [2,4,1,1], 8>; 159defm : X86WriteRes<WriteIDiv64Ld, [SKLPort0,SKLPort5,SKLPort23,SKLPort0156], 28, [2,4,1,1], 8>; 160 161defm : SKLWriteResPair<WriteCRC32, [SKLPort1], 3>; 162 163def : WriteRes<WriteLEA, [SKLPort15]>; // LEA instructions can't fold loads. 164 165defm : SKLWriteResPair<WriteCMOV, [SKLPort06], 1, [1], 1>; // Conditional move. 166defm : X86WriteRes<WriteFCMOV, [SKLPort1], 3, [1], 1>; // x87 conditional move. 167def : WriteRes<WriteSETCC, [SKLPort06]>; // Setcc. 168def : WriteRes<WriteSETCCStore, [SKLPort06,SKLPort4,SKLPort237]> { 169 let Latency = 2; 170 let NumMicroOps = 3; 171} 172 173defm : X86WriteRes<WriteLAHFSAHF, [SKLPort06], 1, [1], 1>; 174defm : X86WriteRes<WriteBitTest, [SKLPort06], 1, [1], 1>; 175defm : X86WriteRes<WriteBitTestImmLd, [SKLPort06,SKLPort23], 6, [1,1], 2>; 176defm : X86WriteRes<WriteBitTestRegLd, [SKLPort0156,SKLPort23], 6, [1,1], 2>; 177defm : X86WriteRes<WriteBitTestSet, [SKLPort06], 1, [1], 1>; 178defm : X86WriteRes<WriteBitTestSetImmLd, [SKLPort06,SKLPort23], 5, [1,1], 3>; 179defm : X86WriteRes<WriteBitTestSetRegLd, [SKLPort0156,SKLPort23], 5, [1,1], 2>; 180 181// Bit counts. 182defm : SKLWriteResPair<WriteBSF, [SKLPort1], 3>; 183defm : SKLWriteResPair<WriteBSR, [SKLPort1], 3>; 184defm : SKLWriteResPair<WriteLZCNT, [SKLPort1], 3>; 185defm : SKLWriteResPair<WriteTZCNT, [SKLPort1], 3>; 186defm : SKLWriteResPair<WritePOPCNT, [SKLPort1], 3>; 187 188// Integer shifts and rotates. 189defm : SKLWriteResPair<WriteShift, [SKLPort06], 1>; 190defm : SKLWriteResPair<WriteShiftCL, [SKLPort06], 3, [3], 3>; 191defm : SKLWriteResPair<WriteRotate, [SKLPort06], 1, [1], 1>; 192defm : SKLWriteResPair<WriteRotateCL, [SKLPort06], 3, [3], 3>; 193 194// SHLD/SHRD. 195defm : X86WriteRes<WriteSHDrri, [SKLPort1], 3, [1], 1>; 196defm : X86WriteRes<WriteSHDrrcl,[SKLPort1,SKLPort06,SKLPort0156], 6, [1, 2, 1], 4>; 197defm : X86WriteRes<WriteSHDmri, [SKLPort1,SKLPort23,SKLPort237,SKLPort0156], 9, [1, 1, 1, 1], 4>; 198defm : X86WriteRes<WriteSHDmrcl,[SKLPort1,SKLPort23,SKLPort237,SKLPort06,SKLPort0156], 11, [1, 1, 1, 2, 1], 6>; 199 200// BMI1 BEXTR/BLS, BMI2 BZHI 201defm : SKLWriteResPair<WriteBEXTR, [SKLPort06,SKLPort15], 2, [1,1], 2>; 202defm : SKLWriteResPair<WriteBLS, [SKLPort15], 1>; 203defm : SKLWriteResPair<WriteBZHI, [SKLPort15], 1>; 204 205// Loads, stores, and moves, not folded with other operations. 206defm : X86WriteRes<WriteLoad, [SKLPort23], 5, [1], 1>; 207defm : X86WriteRes<WriteStore, [SKLPort237, SKLPort4], 1, [1,1], 1>; 208defm : X86WriteRes<WriteStoreNT, [SKLPort237, SKLPort4], 1, [1,1], 2>; 209defm : X86WriteRes<WriteMove, [SKLPort0156], 1, [1], 1>; 210 211// Model the effect of clobbering the read-write mask operand of the GATHER operation. 212// Does not cost anything by itself, only has latency, matching that of the WriteLoad, 213defm : X86WriteRes<WriteVecMaskedGatherWriteback, [], 5, [], 0>; 214 215// Idioms that clear a register, like xorps %xmm0, %xmm0. 216// These can often bypass execution ports completely. 217def : WriteRes<WriteZero, []>; 218 219// Branches don't produce values, so they have no latency, but they still 220// consume resources. Indirect branches can fold loads. 221defm : SKLWriteResPair<WriteJump, [SKLPort06], 1>; 222 223// Floating point. This covers both scalar and vector operations. 224defm : X86WriteRes<WriteFLD0, [SKLPort05], 1, [1], 1>; 225defm : X86WriteRes<WriteFLD1, [SKLPort05], 1, [2], 2>; 226defm : X86WriteRes<WriteFLDC, [SKLPort05], 1, [2], 2>; 227defm : X86WriteRes<WriteFLoad, [SKLPort23], 5, [1], 1>; 228defm : X86WriteRes<WriteFLoadX, [SKLPort23], 6, [1], 1>; 229defm : X86WriteRes<WriteFLoadY, [SKLPort23], 7, [1], 1>; 230defm : X86WriteRes<WriteFMaskedLoad, [SKLPort23,SKLPort015], 7, [1,1], 2>; 231defm : X86WriteRes<WriteFMaskedLoadY, [SKLPort23,SKLPort015], 8, [1,1], 2>; 232defm : X86WriteRes<WriteFStore, [SKLPort237,SKLPort4], 1, [1,1], 2>; 233defm : X86WriteRes<WriteFStoreX, [SKLPort237,SKLPort4], 1, [1,1], 2>; 234defm : X86WriteRes<WriteFStoreY, [SKLPort237,SKLPort4], 1, [1,1], 2>; 235defm : X86WriteRes<WriteFStoreNT, [SKLPort237,SKLPort4], 1, [1,1], 2>; 236defm : X86WriteRes<WriteFStoreNTX, [SKLPort237,SKLPort4], 1, [1,1], 2>; 237defm : X86WriteRes<WriteFStoreNTY, [SKLPort237,SKLPort4], 1, [1,1], 2>; 238 239defm : X86WriteRes<WriteFMaskedStore32, [SKLPort237,SKLPort0], 2, [1,1], 2>; 240defm : X86WriteRes<WriteFMaskedStore32Y, [SKLPort237,SKLPort0], 2, [1,1], 2>; 241defm : X86WriteRes<WriteFMaskedStore64, [SKLPort237,SKLPort0], 2, [1,1], 2>; 242defm : X86WriteRes<WriteFMaskedStore64Y, [SKLPort237,SKLPort0], 2, [1,1], 2>; 243 244defm : X86WriteRes<WriteFMove, [SKLPort015], 1, [1], 1>; 245defm : X86WriteRes<WriteFMoveX, [SKLPort015], 1, [1], 1>; 246defm : X86WriteRes<WriteFMoveY, [SKLPort015], 1, [1], 1>; 247defm : X86WriteRes<WriteEMMS, [SKLPort05,SKLPort0156], 10, [9,1], 10>; 248 249defm : SKLWriteResPair<WriteFAdd, [SKLPort01], 4, [1], 1, 5>; // Floating point add/sub. 250defm : SKLWriteResPair<WriteFAddX, [SKLPort01], 4, [1], 1, 6>; 251defm : SKLWriteResPair<WriteFAddY, [SKLPort01], 4, [1], 1, 7>; 252defm : X86WriteResPairUnsupported<WriteFAddZ>; 253defm : SKLWriteResPair<WriteFAdd64, [SKLPort01], 4, [1], 1, 5>; // Floating point double add/sub. 254defm : SKLWriteResPair<WriteFAdd64X, [SKLPort01], 4, [1], 1, 6>; 255defm : SKLWriteResPair<WriteFAdd64Y, [SKLPort01], 4, [1], 1, 7>; 256defm : X86WriteResPairUnsupported<WriteFAdd64Z>; 257 258defm : SKLWriteResPair<WriteFCmp, [SKLPort01], 4, [1], 1, 5>; // Floating point compare. 259defm : SKLWriteResPair<WriteFCmpX, [SKLPort01], 4, [1], 1, 6>; 260defm : SKLWriteResPair<WriteFCmpY, [SKLPort01], 4, [1], 1, 7>; 261defm : X86WriteResPairUnsupported<WriteFCmpZ>; 262defm : SKLWriteResPair<WriteFCmp64, [SKLPort01], 4, [1], 1, 5>; // Floating point double compare. 263defm : SKLWriteResPair<WriteFCmp64X, [SKLPort01], 4, [1], 1, 6>; 264defm : SKLWriteResPair<WriteFCmp64Y, [SKLPort01], 4, [1], 1, 7>; 265defm : X86WriteResPairUnsupported<WriteFCmp64Z>; 266 267defm : SKLWriteResPair<WriteFCom, [SKLPort0], 2>; // Floating point compare to flags (X87). 268defm : SKLWriteResPair<WriteFComX, [SKLPort0], 2>; // Floating point compare to flags (SSE). 269 270defm : SKLWriteResPair<WriteFMul, [SKLPort01], 4, [1], 1, 5>; // Floating point multiplication. 271defm : SKLWriteResPair<WriteFMulX, [SKLPort01], 4, [1], 1, 6>; 272defm : SKLWriteResPair<WriteFMulY, [SKLPort01], 4, [1], 1, 7>; 273defm : X86WriteResPairUnsupported<WriteFMulZ>; 274defm : SKLWriteResPair<WriteFMul64, [SKLPort01], 4, [1], 1, 5>; // Floating point double multiplication. 275defm : SKLWriteResPair<WriteFMul64X, [SKLPort01], 4, [1], 1, 6>; 276defm : SKLWriteResPair<WriteFMul64Y, [SKLPort01], 4, [1], 1, 7>; 277defm : X86WriteResPairUnsupported<WriteFMul64Z>; 278 279defm : SKLWriteResPair<WriteFDiv, [SKLPort0,SKLFPDivider], 11, [1,3], 1, 5>; // Floating point division. 280//defm : SKLWriteResPair<WriteFDivX, [SKLPort0,SKLFPDivider], 11, [1,3], 1, 6>; 281defm : SKLWriteResPair<WriteFDivY, [SKLPort0,SKLFPDivider], 11, [1,5], 1, 7>; 282defm : X86WriteResPairUnsupported<WriteFDivZ>; 283//defm : SKLWriteResPair<WriteFDiv64, [SKLPort0,SKLFPDivider], 14, [1,3], 1, 5>; // Floating point double division. 284//defm : SKLWriteResPair<WriteFDiv64X, [SKLPort0,SKLFPDivider], 14, [1,3], 1, 6>; 285//defm : SKLWriteResPair<WriteFDiv64Y, [SKLPort0,SKLFPDivider], 14, [1,5], 1, 7>; 286defm : X86WriteResPairUnsupported<WriteFDiv64Z>; 287 288defm : SKLWriteResPair<WriteFSqrt, [SKLPort0,SKLFPDivider], 12, [1,3], 1, 5>; // Floating point square root. 289defm : SKLWriteResPair<WriteFSqrtX, [SKLPort0,SKLFPDivider], 12, [1,3], 1, 6>; 290defm : SKLWriteResPair<WriteFSqrtY, [SKLPort0,SKLFPDivider], 12, [1,6], 1, 7>; 291defm : X86WriteResPairUnsupported<WriteFSqrtZ>; 292defm : SKLWriteResPair<WriteFSqrt64, [SKLPort0,SKLFPDivider], 18, [1,6], 1, 5>; // Floating point double square root. 293defm : SKLWriteResPair<WriteFSqrt64X, [SKLPort0,SKLFPDivider], 18, [1,6], 1, 6>; 294defm : SKLWriteResPair<WriteFSqrt64Y, [SKLPort0,SKLFPDivider], 18, [1,12],1, 7>; 295defm : X86WriteResPairUnsupported<WriteFSqrt64Z>; 296defm : SKLWriteResPair<WriteFSqrt80, [SKLPort0,SKLFPDivider], 21, [1,7]>; // Floating point long double square root. 297 298defm : SKLWriteResPair<WriteFRcp, [SKLPort0], 4, [1], 1, 5>; // Floating point reciprocal estimate. 299defm : SKLWriteResPair<WriteFRcpX, [SKLPort0], 4, [1], 1, 6>; 300defm : SKLWriteResPair<WriteFRcpY, [SKLPort0], 4, [1], 1, 7>; 301defm : X86WriteResPairUnsupported<WriteFRcpZ>; 302 303defm : SKLWriteResPair<WriteFRsqrt, [SKLPort0], 4, [1], 1, 5>; // Floating point reciprocal square root estimate. 304defm : SKLWriteResPair<WriteFRsqrtX,[SKLPort0], 4, [1], 1, 6>; 305defm : SKLWriteResPair<WriteFRsqrtY,[SKLPort0], 4, [1], 1, 7>; 306defm : X86WriteResPairUnsupported<WriteFRsqrtZ>; 307 308defm : SKLWriteResPair<WriteFMA, [SKLPort01], 4, [1], 1, 5>; // Fused Multiply Add. 309defm : SKLWriteResPair<WriteFMAX, [SKLPort01], 4, [1], 1, 6>; 310defm : SKLWriteResPair<WriteFMAY, [SKLPort01], 4, [1], 1, 7>; 311defm : X86WriteResPairUnsupported<WriteFMAZ>; 312defm : SKLWriteResPair<WriteDPPD, [SKLPort5,SKLPort01], 9, [1,2], 3, 6>; // Floating point double dot product. 313defm : SKLWriteResPair<WriteDPPS, [SKLPort5,SKLPort01], 13, [1,3], 4, 6>; 314defm : SKLWriteResPair<WriteDPPSY, [SKLPort5,SKLPort01], 13, [1,3], 4, 7>; 315defm : X86WriteResPairUnsupported<WriteDPPSZ>; 316defm : SKLWriteResPair<WriteFSign, [SKLPort0], 1>; // Floating point fabs/fchs. 317defm : SKLWriteResPair<WriteFRnd, [SKLPort01], 8, [2], 2, 6>; // Floating point rounding. 318defm : SKLWriteResPair<WriteFRndY, [SKLPort01], 8, [2], 2, 7>; 319defm : X86WriteResPairUnsupported<WriteFRndZ>; 320defm : SKLWriteResPair<WriteFLogic, [SKLPort015], 1, [1], 1, 6>; // Floating point and/or/xor logicals. 321defm : SKLWriteResPair<WriteFLogicY, [SKLPort015], 1, [1], 1, 7>; 322defm : X86WriteResPairUnsupported<WriteFLogicZ>; 323defm : SKLWriteResPair<WriteFTest, [SKLPort0], 2, [1], 1, 6>; // Floating point TEST instructions. 324defm : SKLWriteResPair<WriteFTestY, [SKLPort0], 2, [1], 1, 7>; 325defm : X86WriteResPairUnsupported<WriteFTestZ>; 326defm : SKLWriteResPair<WriteFShuffle, [SKLPort5], 1, [1], 1, 6>; // Floating point vector shuffles. 327defm : SKLWriteResPair<WriteFShuffleY, [SKLPort5], 1, [1], 1, 7>; 328defm : X86WriteResPairUnsupported<WriteFShuffleZ>; 329defm : SKLWriteResPair<WriteFVarShuffle, [SKLPort5], 1, [1], 1, 6>; // Floating point vector shuffles. 330defm : SKLWriteResPair<WriteFVarShuffleY, [SKLPort5], 1, [1], 1, 7>; 331defm : X86WriteResPairUnsupported<WriteFVarShuffleZ>; 332defm : SKLWriteResPair<WriteFBlend, [SKLPort015], 1, [1], 1, 6>; // Floating point vector blends. 333defm : SKLWriteResPair<WriteFBlendY, [SKLPort015], 1, [1], 1, 7>; 334defm : X86WriteResPairUnsupported<WriteFBlendZ>; 335defm : SKLWriteResPair<WriteFVarBlend, [SKLPort015], 2, [2], 2, 6>; // Fp vector variable blends. 336defm : SKLWriteResPair<WriteFVarBlendY,[SKLPort015], 2, [2], 2, 7>; 337defm : X86WriteResPairUnsupported<WriteFVarBlendZ>; 338 339// FMA Scheduling helper class. 340// class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; } 341 342// Vector integer operations. 343defm : X86WriteRes<WriteVecLoad, [SKLPort23], 5, [1], 1>; 344defm : X86WriteRes<WriteVecLoadX, [SKLPort23], 6, [1], 1>; 345defm : X86WriteRes<WriteVecLoadY, [SKLPort23], 7, [1], 1>; 346defm : X86WriteRes<WriteVecLoadNT, [SKLPort23], 6, [1], 1>; 347defm : X86WriteRes<WriteVecLoadNTY, [SKLPort23], 7, [1], 1>; 348defm : X86WriteRes<WriteVecMaskedLoad, [SKLPort23,SKLPort015], 7, [1,1], 2>; 349defm : X86WriteRes<WriteVecMaskedLoadY, [SKLPort23,SKLPort015], 8, [1,1], 2>; 350defm : X86WriteRes<WriteVecStore, [SKLPort237,SKLPort4], 1, [1,1], 2>; 351defm : X86WriteRes<WriteVecStoreX, [SKLPort237,SKLPort4], 1, [1,1], 2>; 352defm : X86WriteRes<WriteVecStoreY, [SKLPort237,SKLPort4], 1, [1,1], 2>; 353defm : X86WriteRes<WriteVecStoreNT, [SKLPort237,SKLPort4], 1, [1,1], 2>; 354defm : X86WriteRes<WriteVecStoreNTY, [SKLPort237,SKLPort4], 1, [1,1], 2>; 355defm : X86WriteRes<WriteVecMaskedStore32, [SKLPort237,SKLPort0], 2, [1,1], 2>; 356defm : X86WriteRes<WriteVecMaskedStore32Y, [SKLPort237,SKLPort0], 2, [1,1], 2>; 357defm : X86WriteRes<WriteVecMaskedStore64, [SKLPort237,SKLPort0], 2, [1,1], 2>; 358defm : X86WriteRes<WriteVecMaskedStore64Y, [SKLPort237,SKLPort0], 2, [1,1], 2>; 359defm : X86WriteRes<WriteVecMove, [SKLPort05], 1, [1], 1>; 360defm : X86WriteRes<WriteVecMoveX, [SKLPort015], 1, [1], 1>; 361defm : X86WriteRes<WriteVecMoveY, [SKLPort015], 1, [1], 1>; 362defm : X86WriteRes<WriteVecMoveToGpr, [SKLPort0], 2, [1], 1>; 363defm : X86WriteRes<WriteVecMoveFromGpr, [SKLPort5], 1, [1], 1>; 364 365defm : SKLWriteResPair<WriteVecALU, [SKLPort05], 1, [1], 1, 5>; // Vector integer ALU op, no logicals. 366defm : SKLWriteResPair<WriteVecALUX, [SKLPort01], 1, [1], 1, 6>; 367defm : SKLWriteResPair<WriteVecALUY, [SKLPort01], 1, [1], 1, 7>; 368defm : X86WriteResPairUnsupported<WriteVecALUZ>; 369defm : SKLWriteResPair<WriteVecLogic, [SKLPort05], 1, [1], 1, 5>; // Vector integer and/or/xor. 370defm : SKLWriteResPair<WriteVecLogicX,[SKLPort015], 1, [1], 1, 6>; 371defm : SKLWriteResPair<WriteVecLogicY,[SKLPort015], 1, [1], 1, 7>; 372defm : X86WriteResPairUnsupported<WriteVecLogicZ>; 373defm : SKLWriteResPair<WriteVecTest, [SKLPort0,SKLPort5], 3, [1,1], 2, 6>; // Vector integer TEST instructions. 374defm : SKLWriteResPair<WriteVecTestY, [SKLPort0,SKLPort5], 3, [1,1], 2, 7>; 375defm : X86WriteResPairUnsupported<WriteVecTestZ>; 376defm : SKLWriteResPair<WriteVecIMul, [SKLPort0] , 5, [1], 1, 5>; // Vector integer multiply. 377defm : SKLWriteResPair<WriteVecIMulX, [SKLPort01], 5, [1], 1, 6>; 378defm : SKLWriteResPair<WriteVecIMulY, [SKLPort01], 5, [1], 1, 7>; 379defm : X86WriteResPairUnsupported<WriteVecIMulZ>; 380defm : SKLWriteResPair<WritePMULLD, [SKLPort01], 10, [2], 2, 6>; // Vector PMULLD. 381defm : SKLWriteResPair<WritePMULLDY, [SKLPort01], 10, [2], 2, 7>; 382defm : X86WriteResPairUnsupported<WritePMULLDZ>; 383defm : SKLWriteResPair<WriteShuffle, [SKLPort5], 1, [1], 1, 5>; // Vector shuffles. 384defm : SKLWriteResPair<WriteShuffleX, [SKLPort5], 1, [1], 1, 6>; 385defm : SKLWriteResPair<WriteShuffleY, [SKLPort5], 1, [1], 1, 7>; 386defm : X86WriteResPairUnsupported<WriteShuffleZ>; 387defm : SKLWriteResPair<WriteVarShuffle, [SKLPort5], 1, [1], 1, 5>; // Vector shuffles. 388defm : SKLWriteResPair<WriteVarShuffleX, [SKLPort5], 1, [1], 1, 6>; 389defm : SKLWriteResPair<WriteVarShuffleY, [SKLPort5], 1, [1], 1, 7>; 390defm : X86WriteResPairUnsupported<WriteVarShuffleZ>; 391defm : SKLWriteResPair<WriteBlend, [SKLPort5], 1, [1], 1, 6>; // Vector blends. 392defm : SKLWriteResPair<WriteBlendY, [SKLPort5], 1, [1], 1, 7>; 393defm : X86WriteResPairUnsupported<WriteBlendZ>; 394defm : SKLWriteResPair<WriteVarBlend, [SKLPort015], 2, [2], 2, 6>; // Vector variable blends. 395defm : SKLWriteResPair<WriteVarBlendY, [SKLPort015], 2, [2], 2, 6>; 396defm : X86WriteResPairUnsupported<WriteVarBlendZ>; 397defm : SKLWriteResPair<WriteMPSAD, [SKLPort5], 4, [2], 2, 6>; // Vector MPSAD. 398defm : SKLWriteResPair<WriteMPSADY, [SKLPort5], 4, [2], 2, 7>; 399defm : X86WriteResPairUnsupported<WriteMPSADZ>; 400defm : SKLWriteResPair<WritePSADBW, [SKLPort5], 3, [1], 1, 5>; // Vector PSADBW. 401defm : SKLWriteResPair<WritePSADBWX, [SKLPort5], 3, [1], 1, 6>; 402defm : SKLWriteResPair<WritePSADBWY, [SKLPort5], 3, [1], 1, 7>; 403defm : X86WriteResPairUnsupported<WritePSADBWZ>; 404defm : SKLWriteResPair<WritePHMINPOS, [SKLPort01], 4, [1], 1, 6>; // Vector PHMINPOS. 405 406// Vector integer shifts. 407defm : SKLWriteResPair<WriteVecShift, [SKLPort0], 1, [1], 1, 5>; 408defm : X86WriteRes<WriteVecShiftX, [SKLPort5,SKLPort01], 2, [1,1], 2>; 409defm : X86WriteRes<WriteVecShiftY, [SKLPort5,SKLPort01], 4, [1,1], 2>; 410defm : X86WriteRes<WriteVecShiftXLd, [SKLPort01,SKLPort23], 7, [1,1], 2>; 411defm : X86WriteRes<WriteVecShiftYLd, [SKLPort01,SKLPort23], 8, [1,1], 2>; 412defm : X86WriteResPairUnsupported<WriteVecShiftZ>; 413 414defm : SKLWriteResPair<WriteVecShiftImm, [SKLPort0], 1, [1], 1, 5>; // Vector integer immediate shifts. 415defm : SKLWriteResPair<WriteVecShiftImmX, [SKLPort01], 1, [1], 1, 6>; 416defm : SKLWriteResPair<WriteVecShiftImmY, [SKLPort01], 1, [1], 1, 7>; 417defm : X86WriteResPairUnsupported<WriteVecShiftImmZ>; 418defm : SKLWriteResPair<WriteVarVecShift, [SKLPort01], 1, [1], 1, 6>; // Variable vector shifts. 419defm : SKLWriteResPair<WriteVarVecShiftY, [SKLPort01], 1, [1], 1, 7>; 420defm : X86WriteResPairUnsupported<WriteVarVecShiftZ>; 421 422// Vector insert/extract operations. 423def : WriteRes<WriteVecInsert, [SKLPort5]> { 424 let Latency = 2; 425 let NumMicroOps = 2; 426 let ResourceCycles = [2]; 427} 428def : WriteRes<WriteVecInsertLd, [SKLPort5,SKLPort23]> { 429 let Latency = 6; 430 let NumMicroOps = 2; 431} 432def: InstRW<[WriteVecInsertLd], (instregex "(V?)MOV(H|L)(PD|PS)rm")>; 433 434def : WriteRes<WriteVecExtract, [SKLPort0,SKLPort5]> { 435 let Latency = 3; 436 let NumMicroOps = 2; 437} 438def : WriteRes<WriteVecExtractSt, [SKLPort4,SKLPort5,SKLPort237]> { 439 let Latency = 2; 440 let NumMicroOps = 3; 441} 442 443// Conversion between integer and float. 444defm : SKLWriteResPair<WriteCvtSS2I, [SKLPort1], 3>; 445defm : SKLWriteResPair<WriteCvtPS2I, [SKLPort1], 3>; 446defm : SKLWriteResPair<WriteCvtPS2IY, [SKLPort1], 3>; 447defm : X86WriteResPairUnsupported<WriteCvtPS2IZ>; 448defm : SKLWriteResPair<WriteCvtSD2I, [SKLPort1], 3>; 449defm : SKLWriteResPair<WriteCvtPD2I, [SKLPort1], 3>; 450defm : SKLWriteResPair<WriteCvtPD2IY, [SKLPort1], 3>; 451defm : X86WriteResPairUnsupported<WriteCvtPD2IZ>; 452 453defm : SKLWriteResPair<WriteCvtI2SS, [SKLPort1], 4>; 454defm : SKLWriteResPair<WriteCvtI2PS, [SKLPort1], 4>; 455defm : SKLWriteResPair<WriteCvtI2PSY, [SKLPort1], 4>; 456defm : X86WriteResPairUnsupported<WriteCvtI2PSZ>; 457defm : SKLWriteResPair<WriteCvtI2SD, [SKLPort1], 4>; 458defm : SKLWriteResPair<WriteCvtI2PD, [SKLPort1], 4>; 459defm : SKLWriteResPair<WriteCvtI2PDY, [SKLPort1], 4>; 460defm : X86WriteResPairUnsupported<WriteCvtI2PDZ>; 461 462defm : SKLWriteResPair<WriteCvtSS2SD, [SKLPort1], 3>; 463defm : SKLWriteResPair<WriteCvtPS2PD, [SKLPort1], 3>; 464defm : SKLWriteResPair<WriteCvtPS2PDY, [SKLPort1], 3>; 465defm : X86WriteResPairUnsupported<WriteCvtPS2PDZ>; 466defm : SKLWriteResPair<WriteCvtSD2SS, [SKLPort1], 3>; 467defm : SKLWriteResPair<WriteCvtPD2PS, [SKLPort1], 3>; 468defm : SKLWriteResPair<WriteCvtPD2PSY, [SKLPort1], 3>; 469defm : X86WriteResPairUnsupported<WriteCvtPD2PSZ>; 470 471defm : X86WriteRes<WriteCvtPH2PS, [SKLPort5,SKLPort015], 5, [1,1], 2>; 472defm : X86WriteRes<WriteCvtPH2PSY, [SKLPort5,SKLPort01], 7, [1,1], 2>; 473defm : X86WriteResUnsupported<WriteCvtPH2PSZ>; 474defm : X86WriteRes<WriteCvtPH2PSLd, [SKLPort23,SKLPort01], 9, [1,1], 2>; 475defm : X86WriteRes<WriteCvtPH2PSYLd, [SKLPort23,SKLPort01], 10, [1,1], 2>; 476defm : X86WriteResUnsupported<WriteCvtPH2PSZLd>; 477 478defm : X86WriteRes<WriteCvtPS2PH, [SKLPort5,SKLPort015], 5, [1,1], 2>; 479defm : X86WriteRes<WriteCvtPS2PHY, [SKLPort5,SKLPort01], 7, [1,1], 2>; 480defm : X86WriteResUnsupported<WriteCvtPS2PHZ>; 481defm : X86WriteRes<WriteCvtPS2PHSt, [SKLPort4,SKLPort5,SKLPort237,SKLPort01], 6, [1,1,1,1], 4>; 482defm : X86WriteRes<WriteCvtPS2PHYSt, [SKLPort4,SKLPort5,SKLPort237,SKLPort01], 8, [1,1,1,1], 4>; 483defm : X86WriteResUnsupported<WriteCvtPS2PHZSt>; 484 485// Strings instructions. 486 487// Packed Compare Implicit Length Strings, Return Mask 488def : WriteRes<WritePCmpIStrM, [SKLPort0]> { 489 let Latency = 10; 490 let NumMicroOps = 3; 491 let ResourceCycles = [3]; 492} 493def : WriteRes<WritePCmpIStrMLd, [SKLPort0, SKLPort23]> { 494 let Latency = 16; 495 let NumMicroOps = 4; 496 let ResourceCycles = [3,1]; 497} 498 499// Packed Compare Explicit Length Strings, Return Mask 500def : WriteRes<WritePCmpEStrM, [SKLPort0, SKLPort5, SKLPort015, SKLPort0156]> { 501 let Latency = 19; 502 let NumMicroOps = 9; 503 let ResourceCycles = [4,3,1,1]; 504} 505def : WriteRes<WritePCmpEStrMLd, [SKLPort0, SKLPort5,SKLPort23, SKLPort015, SKLPort0156]> { 506 let Latency = 25; 507 let NumMicroOps = 10; 508 let ResourceCycles = [4,3,1,1,1]; 509} 510 511// Packed Compare Implicit Length Strings, Return Index 512def : WriteRes<WritePCmpIStrI, [SKLPort0]> { 513 let Latency = 10; 514 let NumMicroOps = 3; 515 let ResourceCycles = [3]; 516} 517def : WriteRes<WritePCmpIStrILd, [SKLPort0, SKLPort23]> { 518 let Latency = 16; 519 let NumMicroOps = 4; 520 let ResourceCycles = [3,1]; 521} 522 523// Packed Compare Explicit Length Strings, Return Index 524def : WriteRes<WritePCmpEStrI, [SKLPort0, SKLPort5, SKLPort0156]> { 525 let Latency = 18; 526 let NumMicroOps = 8; 527 let ResourceCycles = [4,3,1]; 528} 529def : WriteRes<WritePCmpEStrILd, [SKLPort0, SKLPort5, SKLPort23, SKLPort0156]> { 530 let Latency = 24; 531 let NumMicroOps = 9; 532 let ResourceCycles = [4,3,1,1]; 533} 534 535// MOVMSK Instructions. 536def : WriteRes<WriteFMOVMSK, [SKLPort0]> { let Latency = 2; } 537def : WriteRes<WriteVecMOVMSK, [SKLPort0]> { let Latency = 2; } 538def : WriteRes<WriteVecMOVMSKY, [SKLPort0]> { let Latency = 2; } 539def : WriteRes<WriteMMXMOVMSK, [SKLPort0]> { let Latency = 2; } 540 541// AES instructions. 542def : WriteRes<WriteAESDecEnc, [SKLPort0]> { // Decryption, encryption. 543 let Latency = 4; 544 let NumMicroOps = 1; 545 let ResourceCycles = [1]; 546} 547def : WriteRes<WriteAESDecEncLd, [SKLPort0, SKLPort23]> { 548 let Latency = 10; 549 let NumMicroOps = 2; 550 let ResourceCycles = [1,1]; 551} 552 553def : WriteRes<WriteAESIMC, [SKLPort0]> { // InvMixColumn. 554 let Latency = 8; 555 let NumMicroOps = 2; 556 let ResourceCycles = [2]; 557} 558def : WriteRes<WriteAESIMCLd, [SKLPort0, SKLPort23]> { 559 let Latency = 14; 560 let NumMicroOps = 3; 561 let ResourceCycles = [2,1]; 562} 563 564def : WriteRes<WriteAESKeyGen, [SKLPort0, SKLPort5, SKLPort015]> { // Key Generation. 565 let Latency = 20; 566 let NumMicroOps = 11; 567 let ResourceCycles = [3,6,2]; 568} 569def : WriteRes<WriteAESKeyGenLd, [SKLPort0, SKLPort5, SKLPort23, SKLPort015]> { 570 let Latency = 25; 571 let NumMicroOps = 11; 572 let ResourceCycles = [3,6,1,1]; 573} 574 575// Carry-less multiplication instructions. 576def : WriteRes<WriteCLMul, [SKLPort5]> { 577 let Latency = 6; 578 let NumMicroOps = 1; 579 let ResourceCycles = [1]; 580} 581def : WriteRes<WriteCLMulLd, [SKLPort5, SKLPort23]> { 582 let Latency = 12; 583 let NumMicroOps = 2; 584 let ResourceCycles = [1,1]; 585} 586 587// Catch-all for expensive system instructions. 588def : WriteRes<WriteSystem, [SKLPort0156]> { let Latency = 100; } // def WriteSystem : SchedWrite; 589 590// AVX2. 591defm : SKLWriteResPair<WriteFShuffle256, [SKLPort5], 3, [1], 1, 7>; // Fp 256-bit width vector shuffles. 592defm : SKLWriteResPair<WriteFVarShuffle256, [SKLPort5], 3, [1], 1, 7>; // Fp 256-bit width vector variable shuffles. 593defm : SKLWriteResPair<WriteShuffle256, [SKLPort5], 3, [1], 1, 7>; // 256-bit width vector shuffles. 594defm : SKLWriteResPair<WriteVPMOV256, [SKLPort5], 3, [1], 1, 7>; // 256-bit width packed vector width-changing move. 595defm : SKLWriteResPair<WriteVarShuffle256, [SKLPort5], 3, [1], 1, 7>; // 256-bit width vector variable shuffles. 596 597// Old microcoded instructions that nobody use. 598def : WriteRes<WriteMicrocoded, [SKLPort0156]> { let Latency = 100; } // def WriteMicrocoded : SchedWrite; 599 600// Fence instructions. 601def : WriteRes<WriteFence, [SKLPort23, SKLPort4]>; 602 603// Load/store MXCSR. 604def : WriteRes<WriteLDMXCSR, [SKLPort0,SKLPort23,SKLPort0156]> { let Latency = 7; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } 605def : WriteRes<WriteSTMXCSR, [SKLPort4,SKLPort5,SKLPort237]> { let Latency = 2; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } 606 607// Nop, not very useful expect it provides a model for nops! 608def : WriteRes<WriteNop, []>; 609 610//////////////////////////////////////////////////////////////////////////////// 611// Horizontal add/sub instructions. 612//////////////////////////////////////////////////////////////////////////////// 613 614defm : SKLWriteResPair<WriteFHAdd, [SKLPort5,SKLPort01], 6, [2,1], 3, 6>; 615defm : SKLWriteResPair<WriteFHAddY, [SKLPort5,SKLPort01], 6, [2,1], 3, 7>; 616defm : SKLWriteResPair<WritePHAdd, [SKLPort5,SKLPort05], 3, [2,1], 3, 5>; 617defm : SKLWriteResPair<WritePHAddX, [SKLPort5,SKLPort015], 3, [2,1], 3, 6>; 618defm : SKLWriteResPair<WritePHAddY, [SKLPort5,SKLPort015], 3, [2,1], 3, 7>; 619 620// Remaining instrs. 621 622def SKLWriteResGroup1 : SchedWriteRes<[SKLPort0]> { 623 let Latency = 1; 624 let NumMicroOps = 1; 625 let ResourceCycles = [1]; 626} 627def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PADDS(B|W)irr", 628 "MMX_PADDUS(B|W)irr", 629 "MMX_PAVG(B|W)irr", 630 "MMX_PCMPEQ(B|D|W)irr", 631 "MMX_PCMPGT(B|D|W)irr", 632 "MMX_P(MAX|MIN)SWirr", 633 "MMX_P(MAX|MIN)UBirr", 634 "MMX_PSUBS(B|W)irr", 635 "MMX_PSUBUS(B|W)irr")>; 636 637def SKLWriteResGroup3 : SchedWriteRes<[SKLPort5]> { 638 let Latency = 1; 639 let NumMicroOps = 1; 640 let ResourceCycles = [1]; 641} 642def: InstRW<[SKLWriteResGroup3], (instregex "COM(P?)_FST0r", 643 "UCOM_F(P?)r")>; 644 645def SKLWriteResGroup4 : SchedWriteRes<[SKLPort6]> { 646 let Latency = 1; 647 let NumMicroOps = 1; 648 let ResourceCycles = [1]; 649} 650def: InstRW<[SKLWriteResGroup4], (instregex "JMP(16|32|64)r")>; 651 652def SKLWriteResGroup6 : SchedWriteRes<[SKLPort05]> { 653 let Latency = 1; 654 let NumMicroOps = 1; 655 let ResourceCycles = [1]; 656} 657def: InstRW<[SKLWriteResGroup6], (instrs FINCSTP, FNOP)>; 658 659def SKLWriteResGroup7 : SchedWriteRes<[SKLPort06]> { 660 let Latency = 1; 661 let NumMicroOps = 1; 662 let ResourceCycles = [1]; 663} 664def: InstRW<[SKLWriteResGroup7], (instrs CDQ, CQO, CLAC, STAC)>; 665 666def SKLWriteResGroup8 : SchedWriteRes<[SKLPort15]> { 667 let Latency = 1; 668 let NumMicroOps = 1; 669 let ResourceCycles = [1]; 670} 671def: InstRW<[SKLWriteResGroup8], (instregex "ANDN(32|64)rr")>; 672 673def SKLWriteResGroup9 : SchedWriteRes<[SKLPort015]> { 674 let Latency = 1; 675 let NumMicroOps = 1; 676 let ResourceCycles = [1]; 677} 678def: InstRW<[SKLWriteResGroup9], (instregex "(V?)PADD(B|D|Q|W)(Y?)rr", 679 "VPBLENDD(Y?)rri")>; 680 681def SKLWriteResGroup10 : SchedWriteRes<[SKLPort0156]> { 682 let Latency = 1; 683 let NumMicroOps = 1; 684 let ResourceCycles = [1]; 685} 686def: InstRW<[SKLWriteResGroup10], (instrs CBW, CWDE, CDQE, 687 CMC, STC, 688 SGDT64m, 689 SIDT64m, 690 SMSW16m, 691 STRm, 692 SYSCALL)>; 693 694def SKLWriteResGroup11 : SchedWriteRes<[SKLPort4,SKLPort237]> { 695 let Latency = 1; 696 let NumMicroOps = 2; 697 let ResourceCycles = [1,1]; 698} 699def: InstRW<[SKLWriteResGroup11], (instrs FBSTPm, VMPTRSTm)>; 700def: InstRW<[SKLWriteResGroup11], (instregex "ST_FP(32|64|80)m")>; 701 702def SKLWriteResGroup13 : SchedWriteRes<[SKLPort5]> { 703 let Latency = 2; 704 let NumMicroOps = 2; 705 let ResourceCycles = [2]; 706} 707def: InstRW<[SKLWriteResGroup13], (instrs MMX_MOVQ2DQrr)>; 708 709def SKLWriteResGroup14 : SchedWriteRes<[SKLPort05]> { 710 let Latency = 2; 711 let NumMicroOps = 2; 712 let ResourceCycles = [2]; 713} 714def: InstRW<[SKLWriteResGroup14], (instrs FDECSTP, 715 MMX_MOVDQ2Qrr)>; 716 717def SKLWriteResGroup17 : SchedWriteRes<[SKLPort0156]> { 718 let Latency = 2; 719 let NumMicroOps = 2; 720 let ResourceCycles = [2]; 721} 722def: InstRW<[SKLWriteResGroup17], (instrs LFENCE, 723 WAIT, 724 XGETBV)>; 725 726def SKLWriteResGroup20 : SchedWriteRes<[SKLPort6,SKLPort0156]> { 727 let Latency = 2; 728 let NumMicroOps = 2; 729 let ResourceCycles = [1,1]; 730} 731def: InstRW<[SKLWriteResGroup20], (instregex "CLFLUSH")>; 732 733def SKLWriteResGroup21 : SchedWriteRes<[SKLPort237,SKLPort0156]> { 734 let Latency = 2; 735 let NumMicroOps = 2; 736 let ResourceCycles = [1,1]; 737} 738def: InstRW<[SKLWriteResGroup21], (instrs SFENCE)>; 739 740def SKLWriteResGroup23 : SchedWriteRes<[SKLPort06,SKLPort0156]> { 741 let Latency = 2; 742 let NumMicroOps = 2; 743 let ResourceCycles = [1,1]; 744} 745def: InstRW<[SKLWriteResGroup23], (instrs CWD, 746 JCXZ, JECXZ, JRCXZ, 747 ADC8i8, SBB8i8, 748 ADC16i16, SBB16i16, 749 ADC32i32, SBB32i32, 750 ADC64i32, SBB64i32)>; 751 752def SKLWriteResGroup25 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort237]> { 753 let Latency = 2; 754 let NumMicroOps = 3; 755 let ResourceCycles = [1,1,1]; 756} 757def: InstRW<[SKLWriteResGroup25], (instrs FNSTCW16m)>; 758 759def SKLWriteResGroup27 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort15]> { 760 let Latency = 2; 761 let NumMicroOps = 3; 762 let ResourceCycles = [1,1,1]; 763} 764def: InstRW<[SKLWriteResGroup27], (instregex "MOVBE(16|32|64)mr")>; 765 766def SKLWriteResGroup28 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort0156]> { 767 let Latency = 2; 768 let NumMicroOps = 3; 769 let ResourceCycles = [1,1,1]; 770} 771def: InstRW<[SKLWriteResGroup28], (instrs PUSH16r, PUSH32r, PUSH64r, PUSH64i8, 772 STOSB, STOSL, STOSQ, STOSW)>; 773def: InstRW<[SKLWriteResGroup28], (instregex "PUSH(16|32|64)rmr")>; 774 775def SKLWriteResGroup29 : SchedWriteRes<[SKLPort1]> { 776 let Latency = 3; 777 let NumMicroOps = 1; 778 let ResourceCycles = [1]; 779} 780def: InstRW<[SKLWriteResGroup29], (instregex "PDEP(32|64)rr", 781 "PEXT(32|64)rr")>; 782 783def SKLWriteResGroup30 : SchedWriteRes<[SKLPort5]> { 784 let Latency = 3; 785 let NumMicroOps = 1; 786 let ResourceCycles = [1]; 787} 788def: InstRW<[SKLWriteResGroup30], (instregex "(ADD|SUB|SUBR)_(FPrST0|FST0r|FrST0)", 789 "VPBROADCAST(B|W)rr")>; 790 791def SKLWriteResGroup32 : SchedWriteRes<[SKLPort0,SKLPort0156]> { 792 let Latency = 3; 793 let NumMicroOps = 2; 794 let ResourceCycles = [1,1]; 795} 796def: InstRW<[SKLWriteResGroup32], (instrs FNSTSW16r)>; 797 798def SKLWriteResGroup35 : SchedWriteRes<[SKLPort0,SKLPort5]> { 799 let Latency = 3; 800 let NumMicroOps = 3; 801 let ResourceCycles = [1,2]; 802} 803def: InstRW<[SKLWriteResGroup35], (instregex "MMX_PH(ADD|SUB)SWrr")>; 804 805def SKLWriteResGroup36 : SchedWriteRes<[SKLPort5,SKLPort01]> { 806 let Latency = 3; 807 let NumMicroOps = 3; 808 let ResourceCycles = [2,1]; 809} 810def: InstRW<[SKLWriteResGroup36], (instregex "(V?)PHADDSW(Y?)rr", 811 "(V?)PHSUBSW(Y?)rr")>; 812 813def SKLWriteResGroup39 : SchedWriteRes<[SKLPort5,SKLPort0156]> { 814 let Latency = 3; 815 let NumMicroOps = 3; 816 let ResourceCycles = [2,1]; 817} 818def: InstRW<[SKLWriteResGroup39], (instrs MMX_PACKSSDWirr, 819 MMX_PACKSSWBirr, 820 MMX_PACKUSWBirr)>; 821 822def SKLWriteResGroup40 : SchedWriteRes<[SKLPort6,SKLPort0156]> { 823 let Latency = 3; 824 let NumMicroOps = 3; 825 let ResourceCycles = [1,2]; 826} 827def: InstRW<[SKLWriteResGroup40], (instregex "CLD")>; 828 829def SKLWriteResGroup41 : SchedWriteRes<[SKLPort237,SKLPort0156]> { 830 let Latency = 3; 831 let NumMicroOps = 3; 832 let ResourceCycles = [1,2]; 833} 834def: InstRW<[SKLWriteResGroup41], (instrs MFENCE)>; 835 836def SKLWriteResGroup42 : SchedWriteRes<[SKLPort06,SKLPort0156]> { 837 let Latency = 3; 838 let NumMicroOps = 3; 839 let ResourceCycles = [1,2]; 840} 841def: InstRW<[SKLWriteResGroup42], (instregex "RCL(8|16|32|64)r(1|i)", 842 "RCR(8|16|32|64)r(1|i)")>; 843 844def SKLWriteResGroup43 : SchedWriteRes<[SKLPort0,SKLPort4,SKLPort237]> { 845 let Latency = 3; 846 let NumMicroOps = 3; 847 let ResourceCycles = [1,1,1]; 848} 849def: InstRW<[SKLWriteResGroup43], (instrs FNSTSWm)>; 850 851def SKLWriteResGroup45 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort237,SKLPort0156]> { 852 let Latency = 3; 853 let NumMicroOps = 4; 854 let ResourceCycles = [1,1,1,1]; 855} 856def: InstRW<[SKLWriteResGroup45], (instregex "CALL(16|32|64)r")>; 857 858def SKLWriteResGroup46 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort06,SKLPort0156]> { 859 let Latency = 3; 860 let NumMicroOps = 4; 861 let ResourceCycles = [1,1,1,1]; 862} 863def: InstRW<[SKLWriteResGroup46], (instrs CALL64pcrel32)>; 864 865def SKLWriteResGroup47 : SchedWriteRes<[SKLPort0]> { 866 let Latency = 4; 867 let NumMicroOps = 1; 868 let ResourceCycles = [1]; 869} 870def: InstRW<[SKLWriteResGroup47], (instregex "MUL_(FPrST0|FST0r|FrST0)")>; 871 872def SKLWriteResGroup48 : SchedWriteRes<[SKLPort01]> { 873 let Latency = 4; 874 let NumMicroOps = 1; 875 let ResourceCycles = [1]; 876} 877def: InstRW<[SKLWriteResGroup48], (instregex "(V?)CVTDQ2PS(Y?)rr", 878 "(V?)CVT(T?)PS2DQ(Y?)rr")>; 879 880def SKLWriteResGroup53 : SchedWriteRes<[SKLPort4,SKLPort5,SKLPort237]> { 881 let Latency = 4; 882 let NumMicroOps = 3; 883 let ResourceCycles = [1,1,1]; 884} 885def: InstRW<[SKLWriteResGroup53], (instregex "IST(T?)_FP(16|32|64)m", 886 "IST_F(16|32)m")>; 887 888def SKLWriteResGroup54 : SchedWriteRes<[SKLPort0156]> { 889 let Latency = 4; 890 let NumMicroOps = 4; 891 let ResourceCycles = [4]; 892} 893def: InstRW<[SKLWriteResGroup54], (instrs FNCLEX)>; 894 895def SKLWriteResGroup55 : SchedWriteRes<[SKLPort6,SKLPort0156]> { 896 let Latency = 4; 897 let NumMicroOps = 4; 898 let ResourceCycles = [1,3]; 899} 900def: InstRW<[SKLWriteResGroup55], (instrs PAUSE)>; 901 902def SKLWriteResGroup56 : SchedWriteRes<[]> { 903 let Latency = 0; 904 let NumMicroOps = 4; 905 let ResourceCycles = []; 906} 907def: InstRW<[SKLWriteResGroup56], (instrs VZEROUPPER)>; 908 909def SKLWriteResGroup57 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort0156]> { 910 let Latency = 4; 911 let NumMicroOps = 4; 912 let ResourceCycles = [1,1,2]; 913} 914def: InstRW<[SKLWriteResGroup57], (instregex "LAR(16|32|64)rr")>; 915 916def SKLWriteResGroup58 : SchedWriteRes<[SKLPort23]> { 917 let Latency = 5; 918 let NumMicroOps = 1; 919 let ResourceCycles = [1]; 920} 921def: InstRW<[SKLWriteResGroup58], (instregex "MOVSX(16|32|64)rm(8|16|32)", 922 "MOVZX(16|32|64)rm(8|16)", 923 "(V?)MOVDDUPrm")>; // TODO: Should this be SKLWriteResGroup67? 924 925def SKLWriteResGroup59 : SchedWriteRes<[SKLPort0,SKLPort5]> { 926 let Latency = 5; 927 let NumMicroOps = 2; 928 let ResourceCycles = [1,1]; 929} 930def: InstRW<[SKLWriteResGroup59], (instrs MMX_CVTPI2PDirr, 931 CVTDQ2PDrr, 932 VCVTDQ2PDrr)>; 933 934def SKLWriteResGroup60 : SchedWriteRes<[SKLPort5,SKLPort015]> { 935 let Latency = 5; 936 let NumMicroOps = 2; 937 let ResourceCycles = [1,1]; 938} 939def: InstRW<[SKLWriteResGroup60], (instregex "MMX_CVT(T?)PD2PIirr", 940 "MMX_CVT(T?)PS2PIirr", 941 "(V?)CVT(T?)PD2DQrr", 942 "(V?)CVTPD2PSrr", 943 "(V?)CVTPS2PDrr", 944 "(V?)CVTSD2SSrr", 945 "(V?)CVTSI642SDrr", 946 "(V?)CVTSI2SDrr", 947 "(V?)CVTSI2SSrr", 948 "(V?)CVTSS2SDrr")>; 949 950def SKLWriteResGroup61 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort06]> { 951 let Latency = 5; 952 let NumMicroOps = 3; 953 let ResourceCycles = [1,1,1]; 954} 955def: InstRW<[SKLWriteResGroup61], (instregex "STR(16|32|64)r")>; 956 957def SKLWriteResGroup63 : SchedWriteRes<[SKLPort06,SKLPort0156]> { 958 let Latency = 5; 959 let NumMicroOps = 5; 960 let ResourceCycles = [1,4]; 961} 962def: InstRW<[SKLWriteResGroup63], (instrs XSETBV)>; 963 964def SKLWriteResGroup65 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort0156]> { 965 let Latency = 5; 966 let NumMicroOps = 6; 967 let ResourceCycles = [1,1,4]; 968} 969def: InstRW<[SKLWriteResGroup65], (instregex "PUSHF(16|64)")>; 970 971def SKLWriteResGroup67 : SchedWriteRes<[SKLPort23]> { 972 let Latency = 6; 973 let NumMicroOps = 1; 974 let ResourceCycles = [1]; 975} 976def: InstRW<[SKLWriteResGroup67], (instrs VBROADCASTSSrm, 977 VPBROADCASTDrm, 978 VPBROADCASTQrm)>; 979def: InstRW<[SKLWriteResGroup67], (instregex "(V?)MOVSHDUPrm", 980 "(V?)MOVSLDUPrm")>; 981 982def SKLWriteResGroup68 : SchedWriteRes<[SKLPort0]> { 983 let Latency = 6; 984 let NumMicroOps = 2; 985 let ResourceCycles = [2]; 986} 987def: InstRW<[SKLWriteResGroup68], (instrs MMX_CVTPI2PSirr)>; 988 989def SKLWriteResGroup69 : SchedWriteRes<[SKLPort0,SKLPort23]> { 990 let Latency = 6; 991 let NumMicroOps = 2; 992 let ResourceCycles = [1,1]; 993} 994def: InstRW<[SKLWriteResGroup69], (instrs MMX_PADDSBirm, 995 MMX_PADDSWirm, 996 MMX_PADDUSBirm, 997 MMX_PADDUSWirm, 998 MMX_PAVGBirm, 999 MMX_PAVGWirm, 1000 MMX_PCMPEQBirm, 1001 MMX_PCMPEQDirm, 1002 MMX_PCMPEQWirm, 1003 MMX_PCMPGTBirm, 1004 MMX_PCMPGTDirm, 1005 MMX_PCMPGTWirm, 1006 MMX_PMAXSWirm, 1007 MMX_PMAXUBirm, 1008 MMX_PMINSWirm, 1009 MMX_PMINUBirm, 1010 MMX_PSUBSBirm, 1011 MMX_PSUBSWirm, 1012 MMX_PSUBUSBirm, 1013 MMX_PSUBUSWirm)>; 1014 1015def SKLWriteResGroup70 : SchedWriteRes<[SKLPort0,SKLPort01]> { 1016 let Latency = 6; 1017 let NumMicroOps = 2; 1018 let ResourceCycles = [1,1]; 1019} 1020def: InstRW<[SKLWriteResGroup70], (instregex "(V?)CVTSS2SI(64)?rr", 1021 "(V?)CVT(T?)SD2SI(64)?rr")>; 1022 1023def SKLWriteResGroup72 : SchedWriteRes<[SKLPort6,SKLPort23]> { 1024 let Latency = 6; 1025 let NumMicroOps = 2; 1026 let ResourceCycles = [1,1]; 1027} 1028def: InstRW<[SKLWriteResGroup72], (instrs FARJMP64m)>; 1029def: InstRW<[SKLWriteResGroup72], (instregex "JMP(16|32|64)m")>; 1030 1031def SKLWriteResGroup75 : SchedWriteRes<[SKLPort23,SKLPort15]> { 1032 let Latency = 6; 1033 let NumMicroOps = 2; 1034 let ResourceCycles = [1,1]; 1035} 1036def: InstRW<[SKLWriteResGroup75], (instregex "ANDN(32|64)rm", 1037 "MOVBE(16|32|64)rm")>; 1038 1039def SKLWriteResGroup76 : SchedWriteRes<[SKLPort23,SKLPort0156]> { 1040 let Latency = 6; 1041 let NumMicroOps = 2; 1042 let ResourceCycles = [1,1]; 1043} 1044def: InstRW<[SKLWriteResGroup76], (instrs POP16r, POP32r, POP64r)>; 1045def: InstRW<[SKLWriteResGroup76], (instregex "POP(16|32|64)rmr")>; 1046 1047def SKLWriteResGroup78 : SchedWriteRes<[SKLPort5,SKLPort01]> { 1048 let Latency = 6; 1049 let NumMicroOps = 3; 1050 let ResourceCycles = [2,1]; 1051} 1052def: InstRW<[SKLWriteResGroup78], (instregex "(V?)CVTSI642SSrr")>; 1053 1054def SKLWriteResGroup80 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort06,SKLPort0156]> { 1055 let Latency = 6; 1056 let NumMicroOps = 4; 1057 let ResourceCycles = [1,1,1,1]; 1058} 1059def: InstRW<[SKLWriteResGroup80], (instregex "SLDT(16|32|64)r")>; 1060 1061def SKLWriteResGroup82 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> { 1062 let Latency = 6; 1063 let NumMicroOps = 4; 1064 let ResourceCycles = [1,1,1,1]; 1065} 1066def: InstRW<[SKLWriteResGroup82], (instregex "SAR(8|16|32|64)m(1|i)", 1067 "SHL(8|16|32|64)m(1|i)", 1068 "SHR(8|16|32|64)m(1|i)")>; 1069 1070def SKLWriteResGroup83 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort0156]> { 1071 let Latency = 6; 1072 let NumMicroOps = 4; 1073 let ResourceCycles = [1,1,1,1]; 1074} 1075def: InstRW<[SKLWriteResGroup83], (instregex "POP(16|32|64)rmm", 1076 "PUSH(16|32|64)rmm")>; 1077 1078def SKLWriteResGroup84 : SchedWriteRes<[SKLPort6,SKLPort0156]> { 1079 let Latency = 6; 1080 let NumMicroOps = 6; 1081 let ResourceCycles = [1,5]; 1082} 1083def: InstRW<[SKLWriteResGroup84], (instrs STD)>; 1084 1085def SKLWriteResGroup85 : SchedWriteRes<[SKLPort23]> { 1086 let Latency = 7; 1087 let NumMicroOps = 1; 1088 let ResourceCycles = [1]; 1089} 1090def: InstRW<[SKLWriteResGroup85], (instregex "LD_F(32|64|80)m")>; 1091def: InstRW<[SKLWriteResGroup85], (instrs VBROADCASTF128, 1092 VBROADCASTI128, 1093 VBROADCASTSDYrm, 1094 VBROADCASTSSYrm, 1095 VMOVDDUPYrm, 1096 VMOVSHDUPYrm, 1097 VMOVSLDUPYrm, 1098 VPBROADCASTDYrm, 1099 VPBROADCASTQYrm)>; 1100 1101def SKLWriteResGroup86 : SchedWriteRes<[SKLPort0,SKLPort5]> { 1102 let Latency = 7; 1103 let NumMicroOps = 2; 1104 let ResourceCycles = [1,1]; 1105} 1106def: InstRW<[SKLWriteResGroup86], (instrs VCVTDQ2PDYrr)>; 1107 1108def SKLWriteResGroup88 : SchedWriteRes<[SKLPort5,SKLPort23]> { 1109 let Latency = 6; 1110 let NumMicroOps = 2; 1111 let ResourceCycles = [1,1]; 1112} 1113def: InstRW<[SKLWriteResGroup88], (instregex "(V?)PMOV(SX|ZX)BDrm", 1114 "(V?)PMOV(SX|ZX)BQrm", 1115 "(V?)PMOV(SX|ZX)BWrm", 1116 "(V?)PMOV(SX|ZX)DQrm", 1117 "(V?)PMOV(SX|ZX)WDrm", 1118 "(V?)PMOV(SX|ZX)WQrm")>; 1119 1120def SKLWriteResGroup89 : SchedWriteRes<[SKLPort5,SKLPort01]> { 1121 let Latency = 7; 1122 let NumMicroOps = 2; 1123 let ResourceCycles = [1,1]; 1124} 1125def: InstRW<[SKLWriteResGroup89], (instrs VCVTPD2PSYrr, 1126 VCVTPS2PDYrr, 1127 VCVTPD2DQYrr, 1128 VCVTTPD2DQYrr)>; 1129 1130def SKLWriteResGroup91 : SchedWriteRes<[SKLPort23,SKLPort015]> { 1131 let Latency = 7; 1132 let NumMicroOps = 2; 1133 let ResourceCycles = [1,1]; 1134} 1135def: InstRW<[SKLWriteResGroup91], (instrs VINSERTF128rm, 1136 VINSERTI128rm, 1137 VPBLENDDrmi)>; 1138def: InstRW<[SKLWriteResGroup91, ReadAfterVecXLd], 1139 (instregex "(V?)PADD(B|D|Q|W)rm", 1140 "(V?)PSUB(B|D|Q|W)rm")>; 1141 1142def SKLWriteResGroup92 : SchedWriteRes<[SKLPort5,SKLPort23]> { 1143 let Latency = 7; 1144 let NumMicroOps = 3; 1145 let ResourceCycles = [2,1]; 1146} 1147def: InstRW<[SKLWriteResGroup92], (instrs MMX_PACKSSDWirm, 1148 MMX_PACKSSWBirm, 1149 MMX_PACKUSWBirm)>; 1150 1151def SKLWriteResGroup94 : SchedWriteRes<[SKLPort23,SKLPort0156]> { 1152 let Latency = 7; 1153 let NumMicroOps = 3; 1154 let ResourceCycles = [1,2]; 1155} 1156def: InstRW<[SKLWriteResGroup94], (instrs LEAVE, LEAVE64, 1157 SCASB, SCASL, SCASQ, SCASW)>; 1158 1159def SKLWriteResGroup95 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort01]> { 1160 let Latency = 7; 1161 let NumMicroOps = 3; 1162 let ResourceCycles = [1,1,1]; 1163} 1164def: InstRW<[SKLWriteResGroup95], (instregex "(V?)CVTTSS2SI(64)?rr")>; 1165 1166def SKLWriteResGroup96 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort05]> { 1167 let Latency = 7; 1168 let NumMicroOps = 3; 1169 let ResourceCycles = [1,1,1]; 1170} 1171def: InstRW<[SKLWriteResGroup96], (instrs FLDCW16m)>; 1172 1173def SKLWriteResGroup98 : SchedWriteRes<[SKLPort6,SKLPort23,SKLPort0156]> { 1174 let Latency = 7; 1175 let NumMicroOps = 3; 1176 let ResourceCycles = [1,1,1]; 1177} 1178def: InstRW<[SKLWriteResGroup98], (instrs LRET64, RET64)>; 1179 1180def SKLWriteResGroup100 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> { 1181 let Latency = 7; 1182 let NumMicroOps = 5; 1183 let ResourceCycles = [1,1,1,2]; 1184} 1185def: InstRW<[SKLWriteResGroup100], (instregex "ROL(8|16|32|64)m(1|i)", 1186 "ROR(8|16|32|64)m(1|i)")>; 1187 1188def SKLWriteResGroup100_1 : SchedWriteRes<[SKLPort06]> { 1189 let Latency = 2; 1190 let NumMicroOps = 2; 1191 let ResourceCycles = [2]; 1192} 1193def: InstRW<[SKLWriteResGroup100_1], (instrs ROL8r1, ROL16r1, ROL32r1, ROL64r1, 1194 ROR8r1, ROR16r1, ROR32r1, ROR64r1)>; 1195 1196def SKLWriteResGroup101 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort0156]> { 1197 let Latency = 7; 1198 let NumMicroOps = 5; 1199 let ResourceCycles = [1,1,1,2]; 1200} 1201def: InstRW<[SKLWriteResGroup101], (instregex "XADD(8|16|32|64)rm")>; 1202 1203def SKLWriteResGroup102 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> { 1204 let Latency = 7; 1205 let NumMicroOps = 5; 1206 let ResourceCycles = [1,1,1,1,1]; 1207} 1208def: InstRW<[SKLWriteResGroup102], (instregex "CALL(16|32|64)m")>; 1209def: InstRW<[SKLWriteResGroup102], (instrs FARCALL64m)>; 1210 1211def SKLWriteResGroup103 : SchedWriteRes<[SKLPort6,SKLPort06,SKLPort15,SKLPort0156]> { 1212 let Latency = 7; 1213 let NumMicroOps = 7; 1214 let ResourceCycles = [1,3,1,2]; 1215} 1216def: InstRW<[SKLWriteResGroup103], (instrs LOOP)>; 1217 1218def SKLWriteResGroup107 : SchedWriteRes<[SKLPort1,SKLPort23]> { 1219 let Latency = 8; 1220 let NumMicroOps = 2; 1221 let ResourceCycles = [1,1]; 1222} 1223def: InstRW<[SKLWriteResGroup107], (instregex "PDEP(32|64)rm", 1224 "PEXT(32|64)rm")>; 1225 1226def SKLWriteResGroup108 : SchedWriteRes<[SKLPort5,SKLPort23]> { 1227 let Latency = 8; 1228 let NumMicroOps = 2; 1229 let ResourceCycles = [1,1]; 1230} 1231def: InstRW<[SKLWriteResGroup108], (instregex "FCOM(P?)(32|64)m")>; 1232def: InstRW<[SKLWriteResGroup108], (instrs VPBROADCASTBYrm, 1233 VPBROADCASTWYrm, 1234 VPMOVSXBDYrm, 1235 VPMOVSXBQYrm, 1236 VPMOVSXWQYrm)>; 1237 1238def SKLWriteResGroup110 : SchedWriteRes<[SKLPort23,SKLPort015]> { 1239 let Latency = 8; 1240 let NumMicroOps = 2; 1241 let ResourceCycles = [1,1]; 1242} 1243def: InstRW<[SKLWriteResGroup110], (instrs VPBLENDDYrmi)>; 1244def: InstRW<[SKLWriteResGroup110, ReadAfterVecYLd], 1245 (instregex "VPADD(B|D|Q|W)Yrm", 1246 "VPSUB(B|D|Q|W)Yrm")>; 1247 1248def SKLWriteResGroup112 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> { 1249 let Latency = 8; 1250 let NumMicroOps = 4; 1251 let ResourceCycles = [1,2,1]; 1252} 1253def: InstRW<[SKLWriteResGroup112], (instregex "MMX_PH(ADD|SUB)SWrm")>; 1254 1255def SKLWriteResGroup116 : SchedWriteRes<[SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> { 1256 let Latency = 8; 1257 let NumMicroOps = 5; 1258 let ResourceCycles = [1,1,1,2]; 1259} 1260def: InstRW<[SKLWriteResGroup116], (instregex "RCL(8|16|32|64)m(1|i)", 1261 "RCR(8|16|32|64)m(1|i)")>; 1262 1263def SKLWriteResGroup117 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> { 1264 let Latency = 8; 1265 let NumMicroOps = 6; 1266 let ResourceCycles = [1,1,1,3]; 1267} 1268def: InstRW<[SKLWriteResGroup117], (instregex "ROL(8|16|32|64)mCL", 1269 "ROR(8|16|32|64)mCL", 1270 "SAR(8|16|32|64)mCL", 1271 "SHL(8|16|32|64)mCL", 1272 "SHR(8|16|32|64)mCL")>; 1273 1274def SKLWriteResGroup119 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> { 1275 let Latency = 8; 1276 let NumMicroOps = 6; 1277 let ResourceCycles = [1,1,1,2,1]; 1278} 1279def: SchedAlias<WriteADCRMW, SKLWriteResGroup119>; 1280 1281def SKLWriteResGroup120 : SchedWriteRes<[SKLPort0,SKLPort23]> { 1282 let Latency = 9; 1283 let NumMicroOps = 2; 1284 let ResourceCycles = [1,1]; 1285} 1286def: InstRW<[SKLWriteResGroup120], (instrs MMX_CVTPI2PSirm)>; 1287 1288def SKLWriteResGroup121 : SchedWriteRes<[SKLPort5,SKLPort23]> { 1289 let Latency = 9; 1290 let NumMicroOps = 2; 1291 let ResourceCycles = [1,1]; 1292} 1293def: InstRW<[SKLWriteResGroup121], (instrs PCMPGTQrm, 1294 VPCMPGTQrm, 1295 VPMOVSXBWYrm, 1296 VPMOVSXDQYrm, 1297 VPMOVSXWDYrm, 1298 VPMOVZXWDYrm)>; 1299 1300def SKLWriteResGroup123 : SchedWriteRes<[SKLPort23,SKLPort01]> { 1301 let Latency = 9; 1302 let NumMicroOps = 2; 1303 let ResourceCycles = [1,1]; 1304} 1305def: InstRW<[SKLWriteResGroup123], (instregex "MMX_CVT(T?)PS2PIirm", 1306 "(V?)CVTPS2PDrm")>; 1307 1308def SKLWriteResGroup128 : SchedWriteRes<[SKLPort5,SKLPort01,SKLPort23]> { 1309 let Latency = 9; 1310 let NumMicroOps = 4; 1311 let ResourceCycles = [2,1,1]; 1312} 1313def: InstRW<[SKLWriteResGroup128], (instregex "(V?)PHADDSWrm", 1314 "(V?)PHSUBSWrm")>; 1315 1316def SKLWriteResGroup131 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort23,SKLPort0156]> { 1317 let Latency = 9; 1318 let NumMicroOps = 5; 1319 let ResourceCycles = [1,2,1,1]; 1320} 1321def: InstRW<[SKLWriteResGroup131], (instregex "LAR(16|32|64)rm", 1322 "LSL(16|32|64)rm")>; 1323 1324def SKLWriteResGroup133 : SchedWriteRes<[SKLPort5,SKLPort23]> { 1325 let Latency = 10; 1326 let NumMicroOps = 2; 1327 let ResourceCycles = [1,1]; 1328} 1329def: InstRW<[SKLWriteResGroup133], (instregex "(ADD|SUB|SUBR)_F(32|64)m", 1330 "ILD_F(16|32|64)m")>; 1331def: InstRW<[SKLWriteResGroup133], (instrs VPCMPGTQYrm)>; 1332 1333def SKLWriteResGroup134 : SchedWriteRes<[SKLPort01,SKLPort23]> { 1334 let Latency = 10; 1335 let NumMicroOps = 2; 1336 let ResourceCycles = [1,1]; 1337} 1338def: InstRW<[SKLWriteResGroup134], (instregex "(V?)CVTDQ2PSrm", 1339 "(V?)CVTPS2DQrm", 1340 "(V?)CVTSS2SDrm", 1341 "(V?)CVTTPS2DQrm")>; 1342 1343def SKLWriteResGroup138 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> { 1344 let Latency = 10; 1345 let NumMicroOps = 3; 1346 let ResourceCycles = [1,1,1]; 1347} 1348def: InstRW<[SKLWriteResGroup138], (instrs MMX_CVTPI2PDirm)>; 1349 1350def SKLWriteResGroup139 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort01]> { 1351 let Latency = 10; 1352 let NumMicroOps = 3; 1353 let ResourceCycles = [1,1,1]; 1354} 1355def: InstRW<[SKLWriteResGroup139], (instregex "(V?)CVTSD2SSrm")>; 1356 1357def SKLWriteResGroup140 : SchedWriteRes<[SKLPort5,SKLPort01,SKLPort23]> { 1358 let Latency = 10; 1359 let NumMicroOps = 4; 1360 let ResourceCycles = [2,1,1]; 1361} 1362def: InstRW<[SKLWriteResGroup140], (instrs VPHADDSWYrm, 1363 VPHSUBSWYrm)>; 1364 1365def SKLWriteResGroup143 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> { 1366 let Latency = 10; 1367 let NumMicroOps = 8; 1368 let ResourceCycles = [1,1,1,1,1,3]; 1369} 1370def: InstRW<[SKLWriteResGroup143], (instregex "XCHG(8|16|32|64)rm")>; 1371 1372def SKLWriteResGroup145 : SchedWriteRes<[SKLPort0,SKLFPDivider]> { 1373 let Latency = 11; 1374 let NumMicroOps = 1; 1375 let ResourceCycles = [1,3]; 1376} 1377def : SchedAlias<WriteFDivX, SKLWriteResGroup145>; // TODO - convert to ZnWriteResFpuPair 1378 1379def SKLWriteResGroup146 : SchedWriteRes<[SKLPort0,SKLPort23]> { 1380 let Latency = 11; 1381 let NumMicroOps = 2; 1382 let ResourceCycles = [1,1]; 1383} 1384def: InstRW<[SKLWriteResGroup146], (instregex "MUL_F(32|64)m")>; 1385 1386def SKLWriteResGroup147 : SchedWriteRes<[SKLPort01,SKLPort23]> { 1387 let Latency = 11; 1388 let NumMicroOps = 2; 1389 let ResourceCycles = [1,1]; 1390} 1391def: InstRW<[SKLWriteResGroup147], (instrs VCVTDQ2PSYrm, 1392 VCVTPS2PDYrm, 1393 VCVTPS2DQYrm, 1394 VCVTTPS2DQYrm)>; 1395 1396def SKLWriteResGroup149 : SchedWriteRes<[SKLPort5,SKLPort23]> { 1397 let Latency = 11; 1398 let NumMicroOps = 3; 1399 let ResourceCycles = [2,1]; 1400} 1401def: InstRW<[SKLWriteResGroup149], (instregex "FICOM(P?)(16|32)m")>; 1402 1403def SKLWriteResGroup150 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> { 1404 let Latency = 11; 1405 let NumMicroOps = 3; 1406 let ResourceCycles = [1,1,1]; 1407} 1408def: InstRW<[SKLWriteResGroup150], (instregex "(V?)CVTDQ2PDrm")>; 1409 1410def SKLWriteResGroup151 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort01]> { 1411 let Latency = 11; 1412 let NumMicroOps = 3; 1413 let ResourceCycles = [1,1,1]; 1414} 1415def: InstRW<[SKLWriteResGroup151], (instregex "(V?)CVTSS2SI64rm", 1416 "(V?)CVT(T?)SD2SI(64)?rm", 1417 "VCVTTSS2SI64rm", 1418 "(V?)CVT(T?)SS2SIrm")>; 1419 1420def SKLWriteResGroup152 : SchedWriteRes<[SKLPort5,SKLPort23,SKLPort01]> { 1421 let Latency = 11; 1422 let NumMicroOps = 3; 1423 let ResourceCycles = [1,1,1]; 1424} 1425def: InstRW<[SKLWriteResGroup152], (instrs CVTPD2PSrm, 1426 CVTPD2DQrm, 1427 CVTTPD2DQrm, 1428 MMX_CVTPD2PIirm, 1429 MMX_CVTTPD2PIirm)>; 1430 1431def SKLWriteResGroup154 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort0156]> { 1432 let Latency = 11; 1433 let NumMicroOps = 7; 1434 let ResourceCycles = [2,3,2]; 1435} 1436def: InstRW<[SKLWriteResGroup154], (instregex "RCL(16|32|64)rCL", 1437 "RCR(16|32|64)rCL")>; 1438 1439def SKLWriteResGroup155 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort15,SKLPort0156]> { 1440 let Latency = 11; 1441 let NumMicroOps = 9; 1442 let ResourceCycles = [1,5,1,2]; 1443} 1444def: InstRW<[SKLWriteResGroup155], (instrs RCL8rCL)>; 1445 1446def SKLWriteResGroup156 : SchedWriteRes<[SKLPort06,SKLPort0156]> { 1447 let Latency = 11; 1448 let NumMicroOps = 11; 1449 let ResourceCycles = [2,9]; 1450} 1451def: InstRW<[SKLWriteResGroup156], (instrs LOOPE, LOOPNE)>; 1452 1453def SKLWriteResGroup160 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23,SKLPort01]> { 1454 let Latency = 12; 1455 let NumMicroOps = 4; 1456 let ResourceCycles = [1,1,1,1]; 1457} 1458def: InstRW<[SKLWriteResGroup160], (instregex "CVTTSS2SI64rm")>; 1459 1460def SKLWriteResGroup162 : SchedWriteRes<[SKLPort5,SKLPort23]> { 1461 let Latency = 13; 1462 let NumMicroOps = 3; 1463 let ResourceCycles = [2,1]; 1464} 1465def: InstRW<[SKLWriteResGroup162], (instregex "(ADD|SUB|SUBR)_FI(16|32)m")>; 1466 1467def SKLWriteResGroup163 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> { 1468 let Latency = 13; 1469 let NumMicroOps = 3; 1470 let ResourceCycles = [1,1,1]; 1471} 1472def: InstRW<[SKLWriteResGroup163], (instrs VCVTDQ2PDYrm)>; 1473 1474def SKLWriteResGroup166 : SchedWriteRes<[SKLPort0,SKLFPDivider]> { 1475 let Latency = 14; 1476 let NumMicroOps = 1; 1477 let ResourceCycles = [1,3]; 1478} 1479def : SchedAlias<WriteFDiv64, SKLWriteResGroup166>; // TODO - convert to ZnWriteResFpuPair 1480def : SchedAlias<WriteFDiv64X, SKLWriteResGroup166>; // TODO - convert to ZnWriteResFpuPair 1481 1482def SKLWriteResGroup166_1 : SchedWriteRes<[SKLPort0,SKLFPDivider]> { 1483 let Latency = 14; 1484 let NumMicroOps = 1; 1485 let ResourceCycles = [1,5]; 1486} 1487def : SchedAlias<WriteFDiv64Y, SKLWriteResGroup166_1>; // TODO - convert to ZnWriteResFpuPair 1488 1489def SKLWriteResGroup169 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> { 1490 let Latency = 14; 1491 let NumMicroOps = 3; 1492 let ResourceCycles = [1,1,1]; 1493} 1494def: InstRW<[SKLWriteResGroup169], (instregex "MUL_FI(16|32)m")>; 1495 1496def SKLWriteResGroup170 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort15,SKLPort0156]> { 1497 let Latency = 14; 1498 let NumMicroOps = 10; 1499 let ResourceCycles = [2,4,1,3]; 1500} 1501def: InstRW<[SKLWriteResGroup170], (instrs RCR8rCL)>; 1502 1503def SKLWriteResGroup171 : SchedWriteRes<[SKLPort0]> { 1504 let Latency = 15; 1505 let NumMicroOps = 1; 1506 let ResourceCycles = [1]; 1507} 1508def: InstRW<[SKLWriteResGroup171], (instregex "DIVR_(FPrST0|FST0r|FrST0)")>; 1509 1510def SKLWriteResGroup174 : SchedWriteRes<[SKLPort1,SKLPort23,SKLPort237,SKLPort06,SKLPort15,SKLPort0156]> { 1511 let Latency = 15; 1512 let NumMicroOps = 10; 1513 let ResourceCycles = [1,1,1,5,1,1]; 1514} 1515def: InstRW<[SKLWriteResGroup174], (instregex "RCL(8|16|32|64)mCL")>; 1516 1517def SKLWriteResGroup177 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06,SKLPort15,SKLPort0156]> { 1518 let Latency = 16; 1519 let NumMicroOps = 14; 1520 let ResourceCycles = [1,1,1,4,2,5]; 1521} 1522def: InstRW<[SKLWriteResGroup177], (instrs CMPXCHG8B)>; 1523 1524def SKLWriteResGroup178 : SchedWriteRes<[SKLPort0156]> { 1525 let Latency = 16; 1526 let NumMicroOps = 16; 1527 let ResourceCycles = [16]; 1528} 1529def: InstRW<[SKLWriteResGroup178], (instrs VZEROALL)>; 1530 1531def SKLWriteResGroup179 : SchedWriteRes<[SKLPort0,SKLPort23,SKLFPDivider]> { 1532 let Latency = 17; 1533 let NumMicroOps = 2; 1534 let ResourceCycles = [1,1,5]; 1535} 1536def : SchedAlias<WriteFDivXLd, SKLWriteResGroup179>; // TODO - convert to ZnWriteResFpuPair 1537 1538def SKLWriteResGroup180 : SchedWriteRes<[SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort05,SKLPort0156]> { 1539 let Latency = 17; 1540 let NumMicroOps = 15; 1541 let ResourceCycles = [2,1,2,4,2,4]; 1542} 1543def: InstRW<[SKLWriteResGroup180], (instrs XCH_F)>; 1544 1545def SKLWriteResGroup184 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort06,SKLPort0156]> { 1546 let Latency = 18; 1547 let NumMicroOps = 8; 1548 let ResourceCycles = [1,1,1,5]; 1549} 1550def: InstRW<[SKLWriteResGroup184], (instrs CPUID, RDTSC)>; 1551 1552def SKLWriteResGroup185 : SchedWriteRes<[SKLPort1,SKLPort23,SKLPort237,SKLPort06,SKLPort15,SKLPort0156]> { 1553 let Latency = 18; 1554 let NumMicroOps = 11; 1555 let ResourceCycles = [2,1,1,4,1,2]; 1556} 1557def: InstRW<[SKLWriteResGroup185], (instregex "RCR(8|16|32|64)mCL")>; 1558 1559def SKLWriteResGroup186 : SchedWriteRes<[SKLPort0,SKLPort23,SKLFPDivider]> { 1560 let Latency = 19; 1561 let NumMicroOps = 2; 1562 let ResourceCycles = [1,1,4]; 1563} 1564def : SchedAlias<WriteFDiv64Ld, SKLWriteResGroup186>; // TODO - convert to ZnWriteResFpuPair 1565 1566def SKLWriteResGroup189 : SchedWriteRes<[SKLPort0]> { 1567 let Latency = 20; 1568 let NumMicroOps = 1; 1569 let ResourceCycles = [1]; 1570} 1571def: InstRW<[SKLWriteResGroup189], (instregex "DIV_(FPrST0|FST0r|FrST0)")>; 1572 1573def SKLWriteResGroup190 : SchedWriteRes<[SKLPort0,SKLPort23,SKLFPDivider]> { 1574 let Latency = 20; 1575 let NumMicroOps = 2; 1576 let ResourceCycles = [1,1,4]; 1577} 1578def : SchedAlias<WriteFDiv64XLd, SKLWriteResGroup190>; // TODO - convert to ZnWriteResFpuPair 1579 1580def SKLWriteResGroup192 : SchedWriteRes<[SKLPort4,SKLPort5,SKLPort6,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> { 1581 let Latency = 20; 1582 let NumMicroOps = 8; 1583 let ResourceCycles = [1,1,1,1,1,1,2]; 1584} 1585def: InstRW<[SKLWriteResGroup192], (instrs INSB, INSL, INSW)>; 1586 1587def SKLWriteResGroup193 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort0156]> { 1588 let Latency = 20; 1589 let NumMicroOps = 10; 1590 let ResourceCycles = [1,2,7]; 1591} 1592def: InstRW<[SKLWriteResGroup193], (instrs MWAITrr)>; 1593 1594def SKLWriteResGroup195 : SchedWriteRes<[SKLPort0,SKLPort23,SKLFPDivider]> { 1595 let Latency = 21; 1596 let NumMicroOps = 2; 1597 let ResourceCycles = [1,1,8]; 1598} 1599def : SchedAlias<WriteFDiv64YLd, SKLWriteResGroup195>; // TODO - convert to ZnWriteResFpuPair 1600 1601def SKLWriteResGroup196 : SchedWriteRes<[SKLPort0,SKLPort23]> { 1602 let Latency = 22; 1603 let NumMicroOps = 2; 1604 let ResourceCycles = [1,1]; 1605} 1606def: InstRW<[SKLWriteResGroup196], (instregex "DIV_F(32|64)m")>; 1607 1608def SKLWriteResGroupVEX2 : SchedWriteRes<[SKLPort0, SKLPort23, SKLPort5, SKLPort015]> { 1609 let Latency = 18; 1610 let NumMicroOps = 5; // 2 uops perform multiple loads 1611 let ResourceCycles = [1,2,1,1]; 1612} 1613def: InstRW<[SKLWriteResGroupVEX2], (instrs VGATHERDPDrm, VPGATHERDQrm, 1614 VGATHERQPDrm, VPGATHERQQrm, 1615 VGATHERQPSrm, VPGATHERQDrm)>; 1616 1617def SKLWriteResGroupVEX4 : SchedWriteRes<[SKLPort0, SKLPort23, SKLPort5, SKLPort015]> { 1618 let Latency = 20; 1619 let NumMicroOps = 5; // 2 uops peform multiple loads 1620 let ResourceCycles = [1,4,1,1]; 1621} 1622def: InstRW<[SKLWriteResGroupVEX4], (instrs VGATHERDPDYrm, VPGATHERDQYrm, 1623 VGATHERDPSrm, VPGATHERDDrm, 1624 VGATHERQPDYrm, VPGATHERQQYrm, 1625 VGATHERQPSYrm, VPGATHERQDYrm)>; 1626 1627def SKLWriteResGroupVEX8 : SchedWriteRes<[SKLPort0, SKLPort23, SKLPort5, SKLPort015]> { 1628 let Latency = 22; 1629 let NumMicroOps = 5; // 2 uops perform multiple loads 1630 let ResourceCycles = [1,8,1,1]; 1631} 1632def: InstRW<[SKLWriteResGroupVEX8], (instrs VGATHERDPSYrm, VPGATHERDDYrm)>; 1633 1634def SKLWriteResGroup198 : SchedWriteRes<[SKLPort0,SKLPort4,SKLPort5,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> { 1635 let Latency = 23; 1636 let NumMicroOps = 19; 1637 let ResourceCycles = [2,1,4,1,1,4,6]; 1638} 1639def: InstRW<[SKLWriteResGroup198], (instrs CMPXCHG16B)>; 1640 1641def SKLWriteResGroup202 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> { 1642 let Latency = 25; 1643 let NumMicroOps = 3; 1644 let ResourceCycles = [1,1,1]; 1645} 1646def: InstRW<[SKLWriteResGroup202], (instregex "DIV_FI(16|32)m")>; 1647 1648def SKLWriteResGroup206 : SchedWriteRes<[SKLPort0,SKLPort23]> { 1649 let Latency = 27; 1650 let NumMicroOps = 2; 1651 let ResourceCycles = [1,1]; 1652} 1653def: InstRW<[SKLWriteResGroup206], (instregex "DIVR_F(32|64)m")>; 1654 1655def SKLWriteResGroup208 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> { 1656 let Latency = 30; 1657 let NumMicroOps = 3; 1658 let ResourceCycles = [1,1,1]; 1659} 1660def: InstRW<[SKLWriteResGroup208], (instregex "DIVR_FI(16|32)m")>; 1661 1662def SKLWriteResGroup209 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort23,SKLPort06,SKLPort0156]> { 1663 let Latency = 35; 1664 let NumMicroOps = 23; 1665 let ResourceCycles = [1,5,3,4,10]; 1666} 1667def: InstRW<[SKLWriteResGroup209], (instregex "IN(8|16|32)ri", 1668 "IN(8|16|32)rr")>; 1669 1670def SKLWriteResGroup210 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> { 1671 let Latency = 35; 1672 let NumMicroOps = 23; 1673 let ResourceCycles = [1,5,2,1,4,10]; 1674} 1675def: InstRW<[SKLWriteResGroup210], (instregex "OUT(8|16|32)ir", 1676 "OUT(8|16|32)rr")>; 1677 1678def SKLWriteResGroup211 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort23,SKLPort0156]> { 1679 let Latency = 37; 1680 let NumMicroOps = 31; 1681 let ResourceCycles = [1,8,1,21]; 1682} 1683def: InstRW<[SKLWriteResGroup211], (instregex "XRSTOR(64)?")>; 1684 1685def SKLWriteResGroup212 : SchedWriteRes<[SKLPort1,SKLPort4,SKLPort5,SKLPort6,SKLPort23,SKLPort237,SKLPort15,SKLPort0156]> { 1686 let Latency = 40; 1687 let NumMicroOps = 18; 1688 let ResourceCycles = [1,1,2,3,1,1,1,8]; 1689} 1690def: InstRW<[SKLWriteResGroup212], (instrs VMCLEARm)>; 1691 1692def SKLWriteResGroup213 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> { 1693 let Latency = 41; 1694 let NumMicroOps = 39; 1695 let ResourceCycles = [1,10,1,1,26]; 1696} 1697def: InstRW<[SKLWriteResGroup213], (instrs XSAVE64)>; 1698 1699def SKLWriteResGroup214 : SchedWriteRes<[SKLPort5,SKLPort0156]> { 1700 let Latency = 42; 1701 let NumMicroOps = 22; 1702 let ResourceCycles = [2,20]; 1703} 1704def: InstRW<[SKLWriteResGroup214], (instrs RDTSCP)>; 1705 1706def SKLWriteResGroup215 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> { 1707 let Latency = 42; 1708 let NumMicroOps = 40; 1709 let ResourceCycles = [1,11,1,1,26]; 1710} 1711def: InstRW<[SKLWriteResGroup215], (instrs XSAVE)>; 1712def: InstRW<[SKLWriteResGroup215], (instregex "XSAVEC", "XSAVES")>; 1713 1714def SKLWriteResGroup216 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> { 1715 let Latency = 46; 1716 let NumMicroOps = 44; 1717 let ResourceCycles = [1,11,1,1,30]; 1718} 1719def: InstRW<[SKLWriteResGroup216], (instregex "XSAVEOPT")>; 1720 1721def SKLWriteResGroup217 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort05,SKLPort06,SKLPort0156]> { 1722 let Latency = 62; 1723 let NumMicroOps = 64; 1724 let ResourceCycles = [2,8,5,10,39]; 1725} 1726def: InstRW<[SKLWriteResGroup217], (instrs FLDENVm)>; 1727 1728def SKLWriteResGroup218 : SchedWriteRes<[SKLPort0,SKLPort6,SKLPort23,SKLPort05,SKLPort06,SKLPort15,SKLPort0156]> { 1729 let Latency = 63; 1730 let NumMicroOps = 88; 1731 let ResourceCycles = [4,4,31,1,2,1,45]; 1732} 1733def: InstRW<[SKLWriteResGroup218], (instrs FXRSTOR64)>; 1734 1735def SKLWriteResGroup219 : SchedWriteRes<[SKLPort0,SKLPort6,SKLPort23,SKLPort05,SKLPort06,SKLPort15,SKLPort0156]> { 1736 let Latency = 63; 1737 let NumMicroOps = 90; 1738 let ResourceCycles = [4,2,33,1,2,1,47]; 1739} 1740def: InstRW<[SKLWriteResGroup219], (instrs FXRSTOR)>; 1741 1742def SKLWriteResGroup220 : SchedWriteRes<[SKLPort5,SKLPort05,SKLPort0156]> { 1743 let Latency = 75; 1744 let NumMicroOps = 15; 1745 let ResourceCycles = [6,3,6]; 1746} 1747def: InstRW<[SKLWriteResGroup220], (instrs FNINIT)>; 1748 1749def SKLWriteResGroup223 : SchedWriteRes<[SKLPort0,SKLPort1,SKLPort4,SKLPort5,SKLPort6,SKLPort237,SKLPort06,SKLPort0156]> { 1750 let Latency = 106; 1751 let NumMicroOps = 100; 1752 let ResourceCycles = [9,1,11,16,1,11,21,30]; 1753} 1754def: InstRW<[SKLWriteResGroup223], (instrs FSTENVm)>; 1755 1756def: InstRW<[WriteZero], (instrs CLC)>; 1757 1758 1759// Instruction variants handled by the renamer. These might not need execution 1760// ports in certain conditions. 1761// See Agner's Fog "The microarchitecture of Intel, AMD and VIA CPUs", 1762// section "Skylake Pipeline" > "Register allocation and renaming". 1763// These can be investigated with llvm-exegesis, e.g. 1764// echo 'pxor %mm0, %mm0' | /tmp/llvm-exegesis -mode=uops -snippets-file=- 1765// echo 'vxorpd %xmm0, %xmm0, %xmm1' | /tmp/llvm-exegesis -mode=uops -snippets-file=- 1766 1767def SKLWriteZeroLatency : SchedWriteRes<[]> { 1768 let Latency = 0; 1769} 1770 1771def SKLWriteZeroIdiom : SchedWriteVariant<[ 1772 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>, 1773 SchedVar<NoSchedPred, [WriteALU]> 1774]>; 1775def : InstRW<[SKLWriteZeroIdiom], (instrs SUB32rr, SUB64rr, 1776 XOR32rr, XOR64rr)>; 1777 1778def SKLWriteFZeroIdiom : SchedWriteVariant<[ 1779 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>, 1780 SchedVar<NoSchedPred, [WriteFLogic]> 1781]>; 1782def : InstRW<[SKLWriteFZeroIdiom], (instrs XORPSrr, VXORPSrr, XORPDrr, 1783 VXORPDrr)>; 1784 1785def SKLWriteFZeroIdiomY : SchedWriteVariant<[ 1786 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>, 1787 SchedVar<NoSchedPred, [WriteFLogicY]> 1788]>; 1789def : InstRW<[SKLWriteFZeroIdiomY], (instrs VXORPSYrr, VXORPDYrr)>; 1790 1791def SKLWriteVZeroIdiomLogicX : SchedWriteVariant<[ 1792 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>, 1793 SchedVar<NoSchedPred, [WriteVecLogicX]> 1794]>; 1795def : InstRW<[SKLWriteVZeroIdiomLogicX], (instrs PXORrr, VPXORrr)>; 1796 1797def SKLWriteVZeroIdiomLogicY : SchedWriteVariant<[ 1798 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>, 1799 SchedVar<NoSchedPred, [WriteVecLogicY]> 1800]>; 1801def : InstRW<[SKLWriteVZeroIdiomLogicY], (instrs VPXORYrr)>; 1802 1803def SKLWriteVZeroIdiomALUX : SchedWriteVariant<[ 1804 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>, 1805 SchedVar<NoSchedPred, [WriteVecALUX]> 1806]>; 1807def : InstRW<[SKLWriteVZeroIdiomALUX], (instrs PCMPGTBrr, VPCMPGTBrr, 1808 PCMPGTDrr, VPCMPGTDrr, 1809 PCMPGTWrr, VPCMPGTWrr)>; 1810 1811def SKLWriteVZeroIdiomALUY : SchedWriteVariant<[ 1812 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>, 1813 SchedVar<NoSchedPred, [WriteVecALUY]> 1814]>; 1815def : InstRW<[SKLWriteVZeroIdiomALUY], (instrs VPCMPGTBYrr, 1816 VPCMPGTDYrr, 1817 VPCMPGTWYrr)>; 1818 1819def SKLWritePSUB : SchedWriteRes<[SKLPort015]> { 1820 let Latency = 1; 1821 let NumMicroOps = 1; 1822 let ResourceCycles = [1]; 1823} 1824 1825def SKLWriteVZeroIdiomPSUB : SchedWriteVariant<[ 1826 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>, 1827 SchedVar<NoSchedPred, [SKLWritePSUB]> 1828]>; 1829def : InstRW<[SKLWriteVZeroIdiomPSUB], (instrs PSUBBrr, VPSUBBrr, 1830 PSUBDrr, VPSUBDrr, 1831 PSUBQrr, VPSUBQrr, 1832 PSUBWrr, VPSUBWrr, 1833 VPSUBBYrr, 1834 VPSUBDYrr, 1835 VPSUBQYrr, 1836 VPSUBWYrr)>; 1837 1838def SKLWritePCMPGTQ : SchedWriteRes<[SKLPort5]> { 1839 let Latency = 3; 1840 let NumMicroOps = 1; 1841 let ResourceCycles = [1]; 1842} 1843 1844def SKLWriteVZeroIdiomPCMPGTQ : SchedWriteVariant<[ 1845 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>, 1846 SchedVar<NoSchedPred, [SKLWritePCMPGTQ]> 1847]>; 1848def : InstRW<[SKLWriteVZeroIdiomPCMPGTQ], (instrs PCMPGTQrr, VPCMPGTQrr, 1849 VPCMPGTQYrr)>; 1850 1851 1852// CMOVs that use both Z and C flag require an extra uop. 1853def SKLWriteCMOVA_CMOVBErr : SchedWriteRes<[SKLPort06]> { 1854 let Latency = 2; 1855 let ResourceCycles = [2]; 1856 let NumMicroOps = 2; 1857} 1858 1859def SKLWriteCMOVA_CMOVBErm : SchedWriteRes<[SKLPort23,SKLPort06]> { 1860 let Latency = 7; 1861 let ResourceCycles = [1,2]; 1862 let NumMicroOps = 3; 1863} 1864 1865def SKLCMOVA_CMOVBErr : SchedWriteVariant<[ 1866 SchedVar<MCSchedPredicate<IsCMOVArr_Or_CMOVBErr>, [SKLWriteCMOVA_CMOVBErr]>, 1867 SchedVar<NoSchedPred, [WriteCMOV]> 1868]>; 1869 1870def SKLCMOVA_CMOVBErm : SchedWriteVariant<[ 1871 SchedVar<MCSchedPredicate<IsCMOVArm_Or_CMOVBErm>, [SKLWriteCMOVA_CMOVBErm]>, 1872 SchedVar<NoSchedPred, [WriteCMOV.Folded]> 1873]>; 1874 1875def : InstRW<[SKLCMOVA_CMOVBErr], (instrs CMOV16rr, CMOV32rr, CMOV64rr)>; 1876def : InstRW<[SKLCMOVA_CMOVBErm], (instrs CMOV16rm, CMOV32rm, CMOV64rm)>; 1877 1878// SETCCs that use both Z and C flag require an extra uop. 1879def SKLWriteSETA_SETBEr : SchedWriteRes<[SKLPort06]> { 1880 let Latency = 2; 1881 let ResourceCycles = [2]; 1882 let NumMicroOps = 2; 1883} 1884 1885def SKLWriteSETA_SETBEm : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort06]> { 1886 let Latency = 3; 1887 let ResourceCycles = [1,1,2]; 1888 let NumMicroOps = 4; 1889} 1890 1891def SKLSETA_SETBErr : SchedWriteVariant<[ 1892 SchedVar<MCSchedPredicate<IsSETAr_Or_SETBEr>, [SKLWriteSETA_SETBEr]>, 1893 SchedVar<NoSchedPred, [WriteSETCC]> 1894]>; 1895 1896def SKLSETA_SETBErm : SchedWriteVariant<[ 1897 SchedVar<MCSchedPredicate<IsSETAm_Or_SETBEm>, [SKLWriteSETA_SETBEm]>, 1898 SchedVar<NoSchedPred, [WriteSETCCStore]> 1899]>; 1900 1901def : InstRW<[SKLSETA_SETBErr], (instrs SETCCr)>; 1902def : InstRW<[SKLSETA_SETBErm], (instrs SETCCm)>; 1903 1904} // SchedModel 1905