1//=- X86SchedSkylake.td - X86 Skylake Client Scheduling ------*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the machine model for Skylake Client to support 10// instruction scheduling and other instruction cost heuristics. 11// 12//===----------------------------------------------------------------------===// 13 14def SkylakeClientModel : SchedMachineModel { 15 // All x86 instructions are modeled as a single micro-op, and SKylake can 16 // decode 6 instructions per cycle. 17 let IssueWidth = 6; 18 let MicroOpBufferSize = 224; // Based on the reorder buffer. 19 let LoadLatency = 5; 20 let MispredictPenalty = 14; 21 22 // Based on the LSD (loop-stream detector) queue size and benchmarking data. 23 let LoopMicroOpBufferSize = 50; 24 25 // This flag is set to allow the scheduler to assign a default model to 26 // unrecognized opcodes. 27 let CompleteModel = 0; 28} 29 30let SchedModel = SkylakeClientModel in { 31 32// Skylake Client can issue micro-ops to 8 different ports in one cycle. 33 34// Ports 0, 1, 5, and 6 handle all computation. 35// Port 4 gets the data half of stores. Store data can be available later than 36// the store address, but since we don't model the latency of stores, we can 37// ignore that. 38// Ports 2 and 3 are identical. They handle loads and the address half of 39// stores. Port 7 can handle address calculations. 40def SKLPort0 : ProcResource<1>; 41def SKLPort1 : ProcResource<1>; 42def SKLPort2 : ProcResource<1>; 43def SKLPort3 : ProcResource<1>; 44def SKLPort4 : ProcResource<1>; 45def SKLPort5 : ProcResource<1>; 46def SKLPort6 : ProcResource<1>; 47def SKLPort7 : ProcResource<1>; 48 49// Many micro-ops are capable of issuing on multiple ports. 50def SKLPort01 : ProcResGroup<[SKLPort0, SKLPort1]>; 51def SKLPort23 : ProcResGroup<[SKLPort2, SKLPort3]>; 52def SKLPort237 : ProcResGroup<[SKLPort2, SKLPort3, SKLPort7]>; 53def SKLPort04 : ProcResGroup<[SKLPort0, SKLPort4]>; 54def SKLPort05 : ProcResGroup<[SKLPort0, SKLPort5]>; 55def SKLPort06 : ProcResGroup<[SKLPort0, SKLPort6]>; 56def SKLPort15 : ProcResGroup<[SKLPort1, SKLPort5]>; 57def SKLPort16 : ProcResGroup<[SKLPort1, SKLPort6]>; 58def SKLPort56 : ProcResGroup<[SKLPort5, SKLPort6]>; 59def SKLPort015 : ProcResGroup<[SKLPort0, SKLPort1, SKLPort5]>; 60def SKLPort056 : ProcResGroup<[SKLPort0, SKLPort5, SKLPort6]>; 61def SKLPort0156: ProcResGroup<[SKLPort0, SKLPort1, SKLPort5, SKLPort6]>; 62 63def SKLDivider : ProcResource<1>; // Integer division issued on port 0. 64// FP division and sqrt on port 0. 65def SKLFPDivider : ProcResource<1>; 66 67// 60 Entry Unified Scheduler 68def SKLPortAny : ProcResGroup<[SKLPort0, SKLPort1, SKLPort2, SKLPort3, SKLPort4, 69 SKLPort5, SKLPort6, SKLPort7]> { 70 let BufferSize=60; 71} 72 73// Integer loads are 5 cycles, so ReadAfterLd registers needn't be available until 5 74// cycles after the memory operand. 75def : ReadAdvance<ReadAfterLd, 5>; 76 77// Vector loads are 5/6/7 cycles, so ReadAfterVec*Ld registers needn't be available 78// until 5/6/7 cycles after the memory operand. 79def : ReadAdvance<ReadAfterVecLd, 5>; 80def : ReadAdvance<ReadAfterVecXLd, 6>; 81def : ReadAdvance<ReadAfterVecYLd, 7>; 82 83def : ReadAdvance<ReadInt2Fpu, 0>; 84 85// Many SchedWrites are defined in pairs with and without a folded load. 86// Instructions with folded loads are usually micro-fused, so they only appear 87// as two micro-ops when queued in the reservation station. 88// This multiclass defines the resource usage for variants with and without 89// folded loads. 90multiclass SKLWriteResPair<X86FoldableSchedWrite SchedRW, 91 list<ProcResourceKind> ExePorts, 92 int Lat, list<int> Res = [1], int UOps = 1, 93 int LoadLat = 5, int LoadUOps = 1> { 94 // Register variant is using a single cycle on ExePort. 95 def : WriteRes<SchedRW, ExePorts> { 96 let Latency = Lat; 97 let ReleaseAtCycles = Res; 98 let NumMicroOps = UOps; 99 } 100 101 // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to 102 // the latency (default = 5). 103 def : WriteRes<SchedRW.Folded, !listconcat([SKLPort23], ExePorts)> { 104 let Latency = !add(Lat, LoadLat); 105 let ReleaseAtCycles = !listconcat([1], Res); 106 let NumMicroOps = !add(UOps, LoadUOps); 107 } 108} 109 110// A folded store needs a cycle on port 4 for the store data, and an extra port 111// 2/3/7 cycle to recompute the address. 112def : WriteRes<WriteRMW, [SKLPort237,SKLPort4]>; 113 114// Arithmetic. 115defm : SKLWriteResPair<WriteALU, [SKLPort0156], 1>; // Simple integer ALU op. 116defm : SKLWriteResPair<WriteADC, [SKLPort06], 1>; // Integer ALU + flags op. 117 118// Integer multiplication. 119defm : SKLWriteResPair<WriteIMul8, [SKLPort1], 3>; 120defm : SKLWriteResPair<WriteIMul16, [SKLPort1,SKLPort06,SKLPort0156], 4, [1,1,2], 4>; 121defm : X86WriteRes<WriteIMul16Imm, [SKLPort1,SKLPort0156], 4, [1,1], 2>; 122defm : X86WriteRes<WriteIMul16ImmLd, [SKLPort1,SKLPort0156,SKLPort23], 8, [1,1,1], 3>; 123defm : SKLWriteResPair<WriteIMul16Reg, [SKLPort1], 3>; 124defm : SKLWriteResPair<WriteIMul32, [SKLPort1,SKLPort06,SKLPort0156], 4, [1,1,1], 3>; 125defm : SKLWriteResPair<WriteMULX32, [SKLPort1,SKLPort06,SKLPort0156], 3, [1,1,1], 3>; 126defm : SKLWriteResPair<WriteIMul32Imm, [SKLPort1], 3>; 127defm : SKLWriteResPair<WriteIMul32Reg, [SKLPort1], 3>; 128defm : SKLWriteResPair<WriteIMul64, [SKLPort1,SKLPort5], 4, [1,1], 2>; 129defm : SKLWriteResPair<WriteMULX64, [SKLPort1,SKLPort5], 3, [1,1], 2>; 130defm : SKLWriteResPair<WriteIMul64Imm, [SKLPort1], 3>; 131defm : SKLWriteResPair<WriteIMul64Reg, [SKLPort1], 3>; 132def SKLWriteIMulH : WriteRes<WriteIMulH, []> { let Latency = 4; } 133def : WriteRes<WriteIMulHLd, []> { 134 let Latency = !add(SKLWriteIMulH.Latency, SkylakeClientModel.LoadLatency); 135} 136 137defm : X86WriteRes<WriteBSWAP32, [SKLPort15], 1, [1], 1>; 138defm : X86WriteRes<WriteBSWAP64, [SKLPort06, SKLPort15], 2, [1,1], 2>; 139defm : X86WriteRes<WriteCMPXCHG,[SKLPort06, SKLPort0156], 5, [2,3], 5>; 140defm : X86WriteRes<WriteCMPXCHGRMW,[SKLPort23,SKLPort06,SKLPort0156,SKLPort237,SKLPort4], 8, [1,2,1,1,1], 6>; 141defm : X86WriteRes<WriteXCHG, [SKLPort0156], 2, [3], 3>; 142 143// TODO: Why isn't the SKLDivider used? 144defm : SKLWriteResPair<WriteDiv8, [SKLPort0,SKLDivider], 25, [1,10], 1, 4>; 145defm : X86WriteRes<WriteDiv16, [SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort05,SKLPort0156], 76, [7,2,8,3,1,11], 32>; 146defm : X86WriteRes<WriteDiv32, [SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort05,SKLPort0156], 76, [7,2,8,3,1,11], 32>; 147defm : X86WriteRes<WriteDiv64, [SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort05,SKLPort0156], 76, [7,2,8,3,1,11], 32>; 148defm : X86WriteRes<WriteDiv16Ld, [SKLPort0,SKLPort23,SKLDivider], 29, [1,1,10], 2>; 149defm : X86WriteRes<WriteDiv32Ld, [SKLPort0,SKLPort23,SKLDivider], 29, [1,1,10], 2>; 150defm : X86WriteRes<WriteDiv64Ld, [SKLPort0,SKLPort23,SKLDivider], 29, [1,1,10], 2>; 151 152defm : X86WriteRes<WriteIDiv8, [SKLPort0,SKLDivider], 25, [1,10], 1>; 153defm : X86WriteRes<WriteIDiv16, [SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort06,SKLPort0156], 102, [4,2,4,8,14,34], 66>; 154defm : X86WriteRes<WriteIDiv32, [SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort06,SKLPort0156], 102, [4,2,4,8,14,34], 66>; 155defm : X86WriteRes<WriteIDiv64, [SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort06,SKLPort0156], 102, [4,2,4,8,14,34], 66>; 156defm : X86WriteRes<WriteIDiv8Ld, [SKLPort0,SKLPort5,SKLPort23,SKLPort0156], 28, [2,4,1,1], 8>; 157defm : X86WriteRes<WriteIDiv16Ld, [SKLPort0,SKLPort5,SKLPort23,SKLPort0156], 28, [2,4,1,1], 8>; 158defm : X86WriteRes<WriteIDiv32Ld, [SKLPort0,SKLPort5,SKLPort23,SKLPort0156], 28, [2,4,1,1], 8>; 159defm : X86WriteRes<WriteIDiv64Ld, [SKLPort0,SKLPort5,SKLPort23,SKLPort0156], 28, [2,4,1,1], 8>; 160 161defm : SKLWriteResPair<WriteCRC32, [SKLPort1], 3>; 162 163def : WriteRes<WriteLEA, [SKLPort15]>; // LEA instructions can't fold loads. 164 165defm : SKLWriteResPair<WriteCMOV, [SKLPort06], 1, [1], 1>; // Conditional move. 166defm : X86WriteRes<WriteFCMOV, [SKLPort1], 3, [1], 1>; // x87 conditional move. 167def : WriteRes<WriteSETCC, [SKLPort06]>; // Setcc. 168def : WriteRes<WriteSETCCStore, [SKLPort06,SKLPort4,SKLPort237]> { 169 let Latency = 2; 170 let NumMicroOps = 3; 171} 172 173defm : X86WriteRes<WriteLAHFSAHF, [SKLPort06], 1, [1], 1>; 174defm : X86WriteRes<WriteBitTest, [SKLPort06], 1, [1], 1>; 175defm : X86WriteRes<WriteBitTestImmLd, [SKLPort06,SKLPort23], 6, [1,1], 2>; 176defm : X86WriteRes<WriteBitTestRegLd, [SKLPort0156,SKLPort23], 6, [1,1], 2>; 177defm : X86WriteRes<WriteBitTestSet, [SKLPort06], 1, [1], 1>; 178defm : X86WriteRes<WriteBitTestSetImmLd, [SKLPort06,SKLPort23], 5, [1,1], 3>; 179defm : X86WriteRes<WriteBitTestSetRegLd, [SKLPort0156,SKLPort23], 5, [1,1], 2>; 180 181// Bit counts. 182defm : SKLWriteResPair<WriteBSF, [SKLPort1], 3>; 183defm : SKLWriteResPair<WriteBSR, [SKLPort1], 3>; 184defm : SKLWriteResPair<WriteLZCNT, [SKLPort1], 3>; 185defm : SKLWriteResPair<WriteTZCNT, [SKLPort1], 3>; 186defm : SKLWriteResPair<WritePOPCNT, [SKLPort1], 3>; 187 188// Integer shifts and rotates. 189defm : SKLWriteResPair<WriteShift, [SKLPort06], 1>; 190defm : SKLWriteResPair<WriteShiftCL, [SKLPort06], 3, [3], 3>; 191defm : SKLWriteResPair<WriteRotate, [SKLPort06], 1, [1], 1>; 192defm : SKLWriteResPair<WriteRotateCL, [SKLPort06], 3, [3], 3>; 193 194// SHLD/SHRD. 195defm : X86WriteRes<WriteSHDrri, [SKLPort1], 3, [1], 1>; 196defm : X86WriteRes<WriteSHDrrcl,[SKLPort1,SKLPort06,SKLPort0156], 6, [1, 2, 1], 4>; 197defm : X86WriteRes<WriteSHDmri, [SKLPort1,SKLPort23,SKLPort237,SKLPort0156], 9, [1, 1, 1, 1], 4>; 198defm : X86WriteRes<WriteSHDmrcl,[SKLPort1,SKLPort23,SKLPort237,SKLPort06,SKLPort0156], 11, [1, 1, 1, 2, 1], 6>; 199 200// BMI1 BEXTR/BLS, BMI2 BZHI 201defm : SKLWriteResPair<WriteBEXTR, [SKLPort06,SKLPort15], 2, [1,1], 2>; 202defm : SKLWriteResPair<WriteBLS, [SKLPort15], 1>; 203defm : SKLWriteResPair<WriteBZHI, [SKLPort15], 1>; 204 205// Loads, stores, and moves, not folded with other operations. 206defm : X86WriteRes<WriteLoad, [SKLPort23], 5, [1], 1>; 207defm : X86WriteRes<WriteStore, [SKLPort237, SKLPort4], 1, [1,1], 1>; 208defm : X86WriteRes<WriteStoreNT, [SKLPort237, SKLPort4], 1, [1,1], 2>; 209defm : X86WriteRes<WriteMove, [SKLPort0156], 1, [1], 1>; 210 211// Model the effect of clobbering the read-write mask operand of the GATHER operation. 212// Does not cost anything by itself, only has latency, matching that of the WriteLoad, 213defm : X86WriteRes<WriteVecMaskedGatherWriteback, [], 5, [], 0>; 214 215// Idioms that clear a register, like xorps %xmm0, %xmm0. 216// These can often bypass execution ports completely. 217def : WriteRes<WriteZero, []>; 218 219// Branches don't produce values, so they have no latency, but they still 220// consume resources. Indirect branches can fold loads. 221defm : SKLWriteResPair<WriteJump, [SKLPort06], 1>; 222 223// Floating point. This covers both scalar and vector operations. 224defm : X86WriteRes<WriteFLD0, [SKLPort05], 1, [1], 1>; 225defm : X86WriteRes<WriteFLD1, [SKLPort05], 1, [2], 2>; 226defm : X86WriteRes<WriteFLDC, [SKLPort05], 1, [2], 2>; 227defm : X86WriteRes<WriteFLoad, [SKLPort23], 5, [1], 1>; 228defm : X86WriteRes<WriteFLoadX, [SKLPort23], 6, [1], 1>; 229defm : X86WriteRes<WriteFLoadY, [SKLPort23], 7, [1], 1>; 230defm : X86WriteRes<WriteFMaskedLoad, [SKLPort23,SKLPort015], 7, [1,1], 2>; 231defm : X86WriteRes<WriteFMaskedLoadY, [SKLPort23,SKLPort015], 8, [1,1], 2>; 232defm : X86WriteRes<WriteFStore, [SKLPort237,SKLPort4], 1, [1,1], 2>; 233defm : X86WriteRes<WriteFStoreX, [SKLPort237,SKLPort4], 1, [1,1], 2>; 234defm : X86WriteRes<WriteFStoreY, [SKLPort237,SKLPort4], 1, [1,1], 2>; 235defm : X86WriteRes<WriteFStoreNT, [SKLPort237,SKLPort4], 1, [1,1], 2>; 236defm : X86WriteRes<WriteFStoreNTX, [SKLPort237,SKLPort4], 1, [1,1], 2>; 237defm : X86WriteRes<WriteFStoreNTY, [SKLPort237,SKLPort4], 1, [1,1], 2>; 238 239defm : X86WriteRes<WriteFMaskedStore32, [SKLPort23,SKLPort0,SKLPort4], 2, [1,1,1], 2>; 240defm : X86WriteRes<WriteFMaskedStore32Y, [SKLPort23,SKLPort0,SKLPort4], 2, [1,1,1], 2>; 241defm : X86WriteRes<WriteFMaskedStore64, [SKLPort23,SKLPort0,SKLPort4], 2, [1,1,1], 2>; 242defm : X86WriteRes<WriteFMaskedStore64Y, [SKLPort23,SKLPort0,SKLPort4], 2, [1,1,1], 2>; 243 244defm : X86WriteRes<WriteFMove, [SKLPort015], 1, [1], 1>; 245defm : X86WriteRes<WriteFMoveX, [SKLPort015], 1, [1], 1>; 246defm : X86WriteRes<WriteFMoveY, [SKLPort015], 1, [1], 1>; 247defm : X86WriteResUnsupported<WriteFMoveZ>; 248defm : X86WriteRes<WriteEMMS, [SKLPort05,SKLPort0156], 10, [9,1], 10>; 249 250defm : SKLWriteResPair<WriteFAdd, [SKLPort01], 4, [1], 1, 5>; // Floating point add/sub. 251defm : SKLWriteResPair<WriteFAddX, [SKLPort01], 4, [1], 1, 6>; 252defm : SKLWriteResPair<WriteFAddY, [SKLPort01], 4, [1], 1, 7>; 253defm : X86WriteResPairUnsupported<WriteFAddZ>; 254defm : SKLWriteResPair<WriteFAdd64, [SKLPort01], 4, [1], 1, 5>; // Floating point double add/sub. 255defm : SKLWriteResPair<WriteFAdd64X, [SKLPort01], 4, [1], 1, 6>; 256defm : SKLWriteResPair<WriteFAdd64Y, [SKLPort01], 4, [1], 1, 7>; 257defm : X86WriteResPairUnsupported<WriteFAdd64Z>; 258 259defm : SKLWriteResPair<WriteFCmp, [SKLPort01], 4, [1], 1, 5>; // Floating point compare. 260defm : SKLWriteResPair<WriteFCmpX, [SKLPort01], 4, [1], 1, 6>; 261defm : SKLWriteResPair<WriteFCmpY, [SKLPort01], 4, [1], 1, 7>; 262defm : X86WriteResPairUnsupported<WriteFCmpZ>; 263defm : SKLWriteResPair<WriteFCmp64, [SKLPort01], 4, [1], 1, 5>; // Floating point double compare. 264defm : SKLWriteResPair<WriteFCmp64X, [SKLPort01], 4, [1], 1, 6>; 265defm : SKLWriteResPair<WriteFCmp64Y, [SKLPort01], 4, [1], 1, 7>; 266defm : X86WriteResPairUnsupported<WriteFCmp64Z>; 267 268defm : SKLWriteResPair<WriteFCom, [SKLPort0], 2>; // Floating point compare to flags (X87). 269defm : SKLWriteResPair<WriteFComX, [SKLPort0], 2>; // Floating point compare to flags (SSE). 270 271defm : SKLWriteResPair<WriteFMul, [SKLPort01], 4, [1], 1, 5>; // Floating point multiplication. 272defm : SKLWriteResPair<WriteFMulX, [SKLPort01], 4, [1], 1, 6>; 273defm : SKLWriteResPair<WriteFMulY, [SKLPort01], 4, [1], 1, 7>; 274defm : X86WriteResPairUnsupported<WriteFMulZ>; 275defm : SKLWriteResPair<WriteFMul64, [SKLPort01], 4, [1], 1, 5>; // Floating point double multiplication. 276defm : SKLWriteResPair<WriteFMul64X, [SKLPort01], 4, [1], 1, 6>; 277defm : SKLWriteResPair<WriteFMul64Y, [SKLPort01], 4, [1], 1, 7>; 278defm : X86WriteResPairUnsupported<WriteFMul64Z>; 279 280defm : SKLWriteResPair<WriteFDiv, [SKLPort0,SKLFPDivider], 11, [1,3], 1, 5>; // Floating point division. 281defm : SKLWriteResPair<WriteFDivX, [SKLPort0,SKLFPDivider], 11, [1,3], 1, 6>; 282defm : SKLWriteResPair<WriteFDivY, [SKLPort0,SKLFPDivider], 11, [1,5], 1, 7>; 283defm : X86WriteResPairUnsupported<WriteFDivZ>; 284defm : SKLWriteResPair<WriteFDiv64, [SKLPort0,SKLFPDivider], 14, [1,4], 1, 5>; // Floating point double division. 285defm : SKLWriteResPair<WriteFDiv64X, [SKLPort0,SKLFPDivider], 14, [1,4], 1, 6>; 286defm : SKLWriteResPair<WriteFDiv64Y, [SKLPort0,SKLFPDivider], 14, [1,8], 1, 7>; 287defm : X86WriteResPairUnsupported<WriteFDiv64Z>; 288 289defm : SKLWriteResPair<WriteFSqrt, [SKLPort0,SKLFPDivider], 12, [1,3], 1, 5>; // Floating point square root. 290defm : SKLWriteResPair<WriteFSqrtX, [SKLPort0,SKLFPDivider], 12, [1,3], 1, 6>; 291defm : SKLWriteResPair<WriteFSqrtY, [SKLPort0,SKLFPDivider], 12, [1,6], 1, 7>; 292defm : X86WriteResPairUnsupported<WriteFSqrtZ>; 293defm : SKLWriteResPair<WriteFSqrt64, [SKLPort0,SKLFPDivider], 18, [1,6], 1, 5>; // Floating point double square root. 294defm : SKLWriteResPair<WriteFSqrt64X, [SKLPort0,SKLFPDivider], 18, [1,6], 1, 6>; 295defm : SKLWriteResPair<WriteFSqrt64Y, [SKLPort0,SKLFPDivider], 18, [1,12],1, 7>; 296defm : X86WriteResPairUnsupported<WriteFSqrt64Z>; 297defm : SKLWriteResPair<WriteFSqrt80, [SKLPort0,SKLFPDivider], 21, [1,7]>; // Floating point long double square root. 298 299defm : SKLWriteResPair<WriteFRcp, [SKLPort0], 4, [1], 1, 5>; // Floating point reciprocal estimate. 300defm : SKLWriteResPair<WriteFRcpX, [SKLPort0], 4, [1], 1, 6>; 301defm : SKLWriteResPair<WriteFRcpY, [SKLPort0], 4, [1], 1, 7>; 302defm : X86WriteResPairUnsupported<WriteFRcpZ>; 303 304defm : SKLWriteResPair<WriteFRsqrt, [SKLPort0], 4, [1], 1, 5>; // Floating point reciprocal square root estimate. 305defm : SKLWriteResPair<WriteFRsqrtX,[SKLPort0], 4, [1], 1, 6>; 306defm : SKLWriteResPair<WriteFRsqrtY,[SKLPort0], 4, [1], 1, 7>; 307defm : X86WriteResPairUnsupported<WriteFRsqrtZ>; 308 309defm : SKLWriteResPair<WriteFMA, [SKLPort01], 4, [1], 1, 5>; // Fused Multiply Add. 310defm : SKLWriteResPair<WriteFMAX, [SKLPort01], 4, [1], 1, 6>; 311defm : SKLWriteResPair<WriteFMAY, [SKLPort01], 4, [1], 1, 7>; 312defm : X86WriteResPairUnsupported<WriteFMAZ>; 313defm : SKLWriteResPair<WriteDPPD, [SKLPort5,SKLPort01], 9, [1,2], 3, 6>; // Floating point double dot product. 314defm : SKLWriteResPair<WriteDPPS, [SKLPort5,SKLPort01], 13, [1,3], 4, 6>; 315defm : SKLWriteResPair<WriteDPPSY, [SKLPort5,SKLPort01], 13, [1,3], 4, 7>; 316defm : SKLWriteResPair<WriteFSign, [SKLPort0], 1>; // Floating point fabs/fchs. 317defm : SKLWriteResPair<WriteFRnd, [SKLPort01], 8, [2], 2, 6>; // Floating point rounding. 318defm : SKLWriteResPair<WriteFRndY, [SKLPort01], 8, [2], 2, 7>; 319defm : X86WriteResPairUnsupported<WriteFRndZ>; 320defm : SKLWriteResPair<WriteFLogic, [SKLPort015], 1, [1], 1, 6>; // Floating point and/or/xor logicals. 321defm : SKLWriteResPair<WriteFLogicY, [SKLPort015], 1, [1], 1, 7>; 322defm : X86WriteResPairUnsupported<WriteFLogicZ>; 323defm : SKLWriteResPair<WriteFTest, [SKLPort0], 2, [1], 1, 6>; // Floating point TEST instructions. 324defm : SKLWriteResPair<WriteFTestY, [SKLPort0], 2, [1], 1, 7>; 325defm : X86WriteResPairUnsupported<WriteFTestZ>; 326defm : SKLWriteResPair<WriteFShuffle, [SKLPort5], 1, [1], 1, 6>; // Floating point vector shuffles. 327defm : SKLWriteResPair<WriteFShuffleY, [SKLPort5], 1, [1], 1, 7>; 328defm : X86WriteResPairUnsupported<WriteFShuffleZ>; 329defm : SKLWriteResPair<WriteFVarShuffle, [SKLPort5], 1, [1], 1, 6>; // Floating point vector shuffles. 330defm : SKLWriteResPair<WriteFVarShuffleY, [SKLPort5], 1, [1], 1, 7>; 331defm : X86WriteResPairUnsupported<WriteFVarShuffleZ>; 332defm : SKLWriteResPair<WriteFBlend, [SKLPort015], 1, [1], 1, 6>; // Floating point vector blends. 333defm : SKLWriteResPair<WriteFBlendY, [SKLPort015], 1, [1], 1, 7>; 334defm : X86WriteResPairUnsupported<WriteFBlendZ>; 335defm : SKLWriteResPair<WriteFVarBlend, [SKLPort015], 2, [2], 2, 6>; // Fp vector variable blends. 336defm : SKLWriteResPair<WriteFVarBlendY,[SKLPort015], 2, [2], 2, 7>; 337defm : X86WriteResPairUnsupported<WriteFVarBlendZ>; 338 339// FMA Scheduling helper class. 340// class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; } 341 342// Vector integer operations. 343defm : X86WriteRes<WriteVecLoad, [SKLPort23], 5, [1], 1>; 344defm : X86WriteRes<WriteVecLoadX, [SKLPort23], 6, [1], 1>; 345defm : X86WriteRes<WriteVecLoadY, [SKLPort23], 7, [1], 1>; 346defm : X86WriteRes<WriteVecLoadNT, [SKLPort23], 6, [1], 1>; 347defm : X86WriteRes<WriteVecLoadNTY, [SKLPort23], 7, [1], 1>; 348defm : X86WriteRes<WriteVecMaskedLoad, [SKLPort23,SKLPort015], 7, [1,1], 2>; 349defm : X86WriteRes<WriteVecMaskedLoadY, [SKLPort23,SKLPort015], 8, [1,1], 2>; 350defm : X86WriteRes<WriteVecStore, [SKLPort237,SKLPort4], 1, [1,1], 2>; 351defm : X86WriteRes<WriteVecStoreX, [SKLPort237,SKLPort4], 1, [1,1], 2>; 352defm : X86WriteRes<WriteVecStoreY, [SKLPort237,SKLPort4], 1, [1,1], 2>; 353defm : X86WriteRes<WriteVecStoreNT, [SKLPort237,SKLPort4], 1, [1,1], 2>; 354defm : X86WriteRes<WriteVecStoreNTY, [SKLPort237,SKLPort4], 1, [1,1], 2>; 355defm : X86WriteRes<WriteVecMaskedStore32, [SKLPort23,SKLPort0,SKLPort4], 2, [1,1,1], 2>; 356defm : X86WriteRes<WriteVecMaskedStore32Y, [SKLPort23,SKLPort0,SKLPort4], 2, [1,1,1], 2>; 357defm : X86WriteRes<WriteVecMaskedStore64, [SKLPort23,SKLPort0,SKLPort4], 2, [1,1,1], 2>; 358defm : X86WriteRes<WriteVecMaskedStore64Y, [SKLPort23,SKLPort0,SKLPort4], 2, [1,1,1], 2>; 359defm : X86WriteRes<WriteVecMove, [SKLPort05], 1, [1], 1>; 360defm : X86WriteRes<WriteVecMoveX, [SKLPort015], 1, [1], 1>; 361defm : X86WriteRes<WriteVecMoveY, [SKLPort015], 1, [1], 1>; 362defm : X86WriteResUnsupported<WriteVecMoveZ>; 363defm : X86WriteRes<WriteVecMoveToGpr, [SKLPort0], 2, [1], 1>; 364defm : X86WriteRes<WriteVecMoveFromGpr, [SKLPort5], 1, [1], 1>; 365 366defm : SKLWriteResPair<WriteVecALU, [SKLPort05], 1, [1], 1, 5>; // Vector integer ALU op, no logicals. 367defm : SKLWriteResPair<WriteVecALUX, [SKLPort01], 1, [1], 1, 6>; 368defm : SKLWriteResPair<WriteVecALUY, [SKLPort01], 1, [1], 1, 7>; 369defm : X86WriteResPairUnsupported<WriteVecALUZ>; 370defm : SKLWriteResPair<WriteVecLogic, [SKLPort05], 1, [1], 1, 5>; // Vector integer and/or/xor. 371defm : SKLWriteResPair<WriteVecLogicX,[SKLPort015], 1, [1], 1, 6>; 372defm : SKLWriteResPair<WriteVecLogicY,[SKLPort015], 1, [1], 1, 7>; 373defm : X86WriteResPairUnsupported<WriteVecLogicZ>; 374defm : SKLWriteResPair<WriteVecTest, [SKLPort0,SKLPort5], 3, [1,1], 2, 6>; // Vector integer TEST instructions. 375defm : SKLWriteResPair<WriteVecTestY, [SKLPort0,SKLPort5], 3, [1,1], 2, 7>; 376defm : X86WriteResPairUnsupported<WriteVecTestZ>; 377defm : SKLWriteResPair<WriteVecIMul, [SKLPort0] , 5, [1], 1, 5>; // Vector integer multiply. 378defm : SKLWriteResPair<WriteVecIMulX, [SKLPort01], 5, [1], 1, 6>; 379defm : SKLWriteResPair<WriteVecIMulY, [SKLPort01], 5, [1], 1, 7>; 380defm : X86WriteResPairUnsupported<WriteVecIMulZ>; 381defm : SKLWriteResPair<WritePMULLD, [SKLPort01], 10, [2], 2, 6>; // Vector PMULLD. 382defm : SKLWriteResPair<WritePMULLDY, [SKLPort01], 10, [2], 2, 7>; 383defm : X86WriteResPairUnsupported<WritePMULLDZ>; 384defm : SKLWriteResPair<WriteShuffle, [SKLPort5], 1, [1], 1, 5>; // Vector shuffles. 385defm : SKLWriteResPair<WriteShuffleX, [SKLPort5], 1, [1], 1, 6>; 386defm : SKLWriteResPair<WriteShuffleY, [SKLPort5], 1, [1], 1, 7>; 387defm : X86WriteResPairUnsupported<WriteShuffleZ>; 388defm : SKLWriteResPair<WriteVarShuffle, [SKLPort5], 1, [1], 1, 5>; // Vector shuffles. 389defm : SKLWriteResPair<WriteVarShuffleX, [SKLPort5], 1, [1], 1, 6>; 390defm : SKLWriteResPair<WriteVarShuffleY, [SKLPort5], 1, [1], 1, 7>; 391defm : X86WriteResPairUnsupported<WriteVarShuffleZ>; 392defm : SKLWriteResPair<WriteBlend, [SKLPort5], 1, [1], 1, 6>; // Vector blends. 393defm : SKLWriteResPair<WriteBlendY, [SKLPort5], 1, [1], 1, 7>; 394defm : X86WriteResPairUnsupported<WriteBlendZ>; 395defm : SKLWriteResPair<WriteVarBlend, [SKLPort015], 2, [2], 2, 6>; // Vector variable blends. 396defm : SKLWriteResPair<WriteVarBlendY, [SKLPort015], 2, [2], 2, 6>; 397defm : X86WriteResPairUnsupported<WriteVarBlendZ>; 398defm : SKLWriteResPair<WriteMPSAD, [SKLPort5], 4, [2], 2, 6>; // Vector MPSAD. 399defm : SKLWriteResPair<WriteMPSADY, [SKLPort5], 4, [2], 2, 7>; 400defm : X86WriteResPairUnsupported<WriteMPSADZ>; 401defm : SKLWriteResPair<WritePSADBW, [SKLPort5], 3, [1], 1, 5>; // Vector PSADBW. 402defm : SKLWriteResPair<WritePSADBWX, [SKLPort5], 3, [1], 1, 6>; 403defm : SKLWriteResPair<WritePSADBWY, [SKLPort5], 3, [1], 1, 7>; 404defm : X86WriteResPairUnsupported<WritePSADBWZ>; 405defm : SKLWriteResPair<WritePHMINPOS, [SKLPort01], 4, [1], 1, 6>; // Vector PHMINPOS. 406 407// Vector integer shifts. 408defm : SKLWriteResPair<WriteVecShift, [SKLPort0], 1, [1], 1, 5>; 409defm : X86WriteRes<WriteVecShiftX, [SKLPort5,SKLPort01], 2, [1,1], 2>; 410defm : X86WriteRes<WriteVecShiftY, [SKLPort5,SKLPort01], 4, [1,1], 2>; 411defm : X86WriteRes<WriteVecShiftXLd, [SKLPort01,SKLPort23], 7, [1,1], 2>; 412defm : X86WriteRes<WriteVecShiftYLd, [SKLPort01,SKLPort23], 8, [1,1], 2>; 413defm : X86WriteResPairUnsupported<WriteVecShiftZ>; 414 415defm : SKLWriteResPair<WriteVecShiftImm, [SKLPort0], 1, [1], 1, 5>; // Vector integer immediate shifts. 416defm : SKLWriteResPair<WriteVecShiftImmX, [SKLPort01], 1, [1], 1, 6>; 417defm : SKLWriteResPair<WriteVecShiftImmY, [SKLPort01], 1, [1], 1, 7>; 418defm : X86WriteResPairUnsupported<WriteVecShiftImmZ>; 419defm : SKLWriteResPair<WriteVarVecShift, [SKLPort01], 1, [1], 1, 6>; // Variable vector shifts. 420defm : SKLWriteResPair<WriteVarVecShiftY, [SKLPort01], 1, [1], 1, 7>; 421defm : X86WriteResPairUnsupported<WriteVarVecShiftZ>; 422 423// Vector insert/extract operations. 424def : WriteRes<WriteVecInsert, [SKLPort5]> { 425 let Latency = 2; 426 let NumMicroOps = 2; 427 let ReleaseAtCycles = [2]; 428} 429def : WriteRes<WriteVecInsertLd, [SKLPort5,SKLPort23]> { 430 let Latency = 6; 431 let NumMicroOps = 2; 432} 433def: InstRW<[WriteVecInsertLd], (instregex "(V?)MOV(H|L)(PD|PS)rm")>; 434 435def : WriteRes<WriteVecExtract, [SKLPort0,SKLPort5]> { 436 let Latency = 3; 437 let NumMicroOps = 2; 438} 439def : WriteRes<WriteVecExtractSt, [SKLPort4,SKLPort5,SKLPort237]> { 440 let Latency = 2; 441 let NumMicroOps = 3; 442} 443 444// Conversion between integer and float. 445defm : SKLWriteResPair<WriteCvtSS2I, [SKLPort0,SKLPort01], 6, [1,1], 2, 5>; 446defm : SKLWriteResPair<WriteCvtPS2I, [SKLPort01], 4, [1], 1, 6>; 447defm : SKLWriteResPair<WriteCvtPS2IY, [SKLPort01], 4, [1], 1, 7>; 448defm : X86WriteResPairUnsupported<WriteCvtPS2IZ>; 449defm : SKLWriteResPair<WriteCvtSD2I, [SKLPort0,SKLPort01], 6, [1,1], 2, 5>; 450defm : SKLWriteResPair<WriteCvtPD2I, [SKLPort5,SKLPort01], 5, [1,1], 2, 6>; 451defm : SKLWriteResPair<WriteCvtPD2IY, [SKLPort5,SKLPort01], 7, [1,1], 2, 6>; 452defm : X86WriteResPairUnsupported<WriteCvtPD2IZ>; 453 454defm : X86WriteRes<WriteCvtI2SS, [SKLPort5,SKLPort01], 5, [1,1], 2>; 455defm : X86WriteRes<WriteCvtI2SSLd, [SKLPort23,SKLPort01], 10, [1,1], 2>; 456defm : SKLWriteResPair<WriteCvtI2PS, [SKLPort01], 4, [1], 1, 6>; 457defm : SKLWriteResPair<WriteCvtI2PSY, [SKLPort01], 4, [1], 1, 7>; 458defm : X86WriteResPairUnsupported<WriteCvtI2PSZ>; 459defm : X86WriteRes<WriteCvtI2SD, [SKLPort5,SKLPort01], 5, [1,1], 2>; 460defm : X86WriteRes<WriteCvtI2SDLd, [SKLPort23,SKLPort01], 10, [1,1], 2>; 461defm : SKLWriteResPair<WriteCvtI2PD, [SKLPort0,SKLPort5], 5, [1,1], 2, 6>; 462defm : SKLWriteResPair<WriteCvtI2PDY, [SKLPort0,SKLPort5], 7, [1,1], 2, 6>; 463defm : X86WriteResPairUnsupported<WriteCvtI2PDZ>; 464 465defm : X86WriteRes<WriteCvtSS2SD, [SKLPort5,SKLPort01], 5, [1,1], 2>; 466defm : X86WriteRes<WriteCvtSS2SDLd, [SKLPort23,SKLPort01], 10, [1,1], 2>; 467defm : X86WriteRes<WriteCvtPS2PD, [SKLPort5,SKLPort01], 5, [1,1], 2>; 468defm : X86WriteRes<WriteCvtPS2PDLd, [SKLPort23,SKLPort01], 9, [1,1], 2>; 469defm : X86WriteRes<WriteCvtPS2PDY, [SKLPort5,SKLPort01], 7, [1,1], 2>; 470defm : X86WriteRes<WriteCvtPS2PDYLd, [SKLPort23,SKLPort01], 11, [1,1], 2>; 471defm : X86WriteResPairUnsupported<WriteCvtPS2PDZ>; 472defm : SKLWriteResPair<WriteCvtSD2SS, [SKLPort5,SKLPort01], 5, [1,1], 2, 5>; 473defm : SKLWriteResPair<WriteCvtPD2PS, [SKLPort5,SKLPort01], 5, [1,1], 2, 6>; 474defm : SKLWriteResPair<WriteCvtPD2PSY, [SKLPort5,SKLPort01], 7, [1,1], 2, 6>; 475defm : X86WriteResPairUnsupported<WriteCvtPD2PSZ>; 476 477defm : X86WriteRes<WriteCvtPH2PS, [SKLPort5,SKLPort01], 5, [1,1], 2>; 478defm : X86WriteRes<WriteCvtPH2PSY, [SKLPort5,SKLPort01], 7, [1,1], 2>; 479defm : X86WriteResUnsupported<WriteCvtPH2PSZ>; 480defm : X86WriteRes<WriteCvtPH2PSLd, [SKLPort23,SKLPort01], 9, [1,1], 2>; 481defm : X86WriteRes<WriteCvtPH2PSYLd, [SKLPort23,SKLPort01], 10, [1,1], 2>; 482defm : X86WriteResUnsupported<WriteCvtPH2PSZLd>; 483 484defm : X86WriteRes<WriteCvtPS2PH, [SKLPort5,SKLPort01], 5, [1,1], 2>; 485defm : X86WriteRes<WriteCvtPS2PHY, [SKLPort5,SKLPort01], 7, [1,1], 2>; 486defm : X86WriteResUnsupported<WriteCvtPS2PHZ>; 487defm : X86WriteRes<WriteCvtPS2PHSt, [SKLPort4,SKLPort5,SKLPort237,SKLPort01], 6, [1,1,1,1], 4>; 488defm : X86WriteRes<WriteCvtPS2PHYSt, [SKLPort4,SKLPort5,SKLPort237,SKLPort01], 8, [1,1,1,1], 4>; 489defm : X86WriteResUnsupported<WriteCvtPS2PHZSt>; 490 491// Strings instructions. 492 493// Packed Compare Implicit Length Strings, Return Mask 494def : WriteRes<WritePCmpIStrM, [SKLPort0]> { 495 let Latency = 10; 496 let NumMicroOps = 3; 497 let ReleaseAtCycles = [3]; 498} 499def : WriteRes<WritePCmpIStrMLd, [SKLPort0, SKLPort23]> { 500 let Latency = 16; 501 let NumMicroOps = 4; 502 let ReleaseAtCycles = [3,1]; 503} 504 505// Packed Compare Explicit Length Strings, Return Mask 506def : WriteRes<WritePCmpEStrM, [SKLPort0, SKLPort5, SKLPort015, SKLPort0156]> { 507 let Latency = 19; 508 let NumMicroOps = 9; 509 let ReleaseAtCycles = [4,3,1,1]; 510} 511def : WriteRes<WritePCmpEStrMLd, [SKLPort0, SKLPort5,SKLPort23, SKLPort015, SKLPort0156]> { 512 let Latency = 25; 513 let NumMicroOps = 10; 514 let ReleaseAtCycles = [4,3,1,1,1]; 515} 516 517// Packed Compare Implicit Length Strings, Return Index 518def : WriteRes<WritePCmpIStrI, [SKLPort0]> { 519 let Latency = 10; 520 let NumMicroOps = 3; 521 let ReleaseAtCycles = [3]; 522} 523def : WriteRes<WritePCmpIStrILd, [SKLPort0, SKLPort23]> { 524 let Latency = 16; 525 let NumMicroOps = 4; 526 let ReleaseAtCycles = [3,1]; 527} 528 529// Packed Compare Explicit Length Strings, Return Index 530def : WriteRes<WritePCmpEStrI, [SKLPort0, SKLPort5, SKLPort0156]> { 531 let Latency = 18; 532 let NumMicroOps = 8; 533 let ReleaseAtCycles = [4,3,1]; 534} 535def : WriteRes<WritePCmpEStrILd, [SKLPort0, SKLPort5, SKLPort23, SKLPort0156]> { 536 let Latency = 24; 537 let NumMicroOps = 9; 538 let ReleaseAtCycles = [4,3,1,1]; 539} 540 541// MOVMSK Instructions. 542def : WriteRes<WriteFMOVMSK, [SKLPort0]> { let Latency = 2; } 543def : WriteRes<WriteVecMOVMSK, [SKLPort0]> { let Latency = 2; } 544def : WriteRes<WriteVecMOVMSKY, [SKLPort0]> { let Latency = 2; } 545def : WriteRes<WriteMMXMOVMSK, [SKLPort0]> { let Latency = 2; } 546 547// AES instructions. 548def : WriteRes<WriteAESDecEnc, [SKLPort0]> { // Decryption, encryption. 549 let Latency = 4; 550 let NumMicroOps = 1; 551 let ReleaseAtCycles = [1]; 552} 553def : WriteRes<WriteAESDecEncLd, [SKLPort0, SKLPort23]> { 554 let Latency = 10; 555 let NumMicroOps = 2; 556 let ReleaseAtCycles = [1,1]; 557} 558 559def : WriteRes<WriteAESIMC, [SKLPort0]> { // InvMixColumn. 560 let Latency = 8; 561 let NumMicroOps = 2; 562 let ReleaseAtCycles = [2]; 563} 564def : WriteRes<WriteAESIMCLd, [SKLPort0, SKLPort23]> { 565 let Latency = 14; 566 let NumMicroOps = 3; 567 let ReleaseAtCycles = [2,1]; 568} 569 570def : WriteRes<WriteAESKeyGen, [SKLPort0, SKLPort5, SKLPort015]> { // Key Generation. 571 let Latency = 20; 572 let NumMicroOps = 11; 573 let ReleaseAtCycles = [3,6,2]; 574} 575def : WriteRes<WriteAESKeyGenLd, [SKLPort0, SKLPort5, SKLPort23, SKLPort015]> { 576 let Latency = 25; 577 let NumMicroOps = 11; 578 let ReleaseAtCycles = [3,6,1,1]; 579} 580 581// Carry-less multiplication instructions. 582def : WriteRes<WriteCLMul, [SKLPort5]> { 583 let Latency = 6; 584 let NumMicroOps = 1; 585 let ReleaseAtCycles = [1]; 586} 587def : WriteRes<WriteCLMulLd, [SKLPort5, SKLPort23]> { 588 let Latency = 12; 589 let NumMicroOps = 2; 590 let ReleaseAtCycles = [1,1]; 591} 592 593// Catch-all for expensive system instructions. 594def : WriteRes<WriteSystem, [SKLPort0156]> { let Latency = 100; } // def WriteSystem : SchedWrite; 595 596// AVX2. 597defm : SKLWriteResPair<WriteFShuffle256, [SKLPort5], 3, [1], 1, 7>; // Fp 256-bit width vector shuffles. 598defm : SKLWriteResPair<WriteFVarShuffle256, [SKLPort5], 3, [1], 1, 7>; // Fp 256-bit width vector variable shuffles. 599defm : SKLWriteResPair<WriteShuffle256, [SKLPort5], 3, [1], 1, 7>; // 256-bit width vector shuffles. 600defm : SKLWriteResPair<WriteVPMOV256, [SKLPort5], 3, [1], 1, 7>; // 256-bit width packed vector width-changing move. 601defm : SKLWriteResPair<WriteVarShuffle256, [SKLPort5], 3, [1], 1, 7>; // 256-bit width vector variable shuffles. 602 603// Old microcoded instructions that nobody use. 604def : WriteRes<WriteMicrocoded, [SKLPort0156]> { let Latency = 100; } // def WriteMicrocoded : SchedWrite; 605 606// Fence instructions. 607def : WriteRes<WriteFence, [SKLPort23, SKLPort4]>; 608 609// Load/store MXCSR. 610def : WriteRes<WriteLDMXCSR, [SKLPort0,SKLPort23,SKLPort0156]> { let Latency = 7; let NumMicroOps = 3; let ReleaseAtCycles = [1,1,1]; } 611def : WriteRes<WriteSTMXCSR, [SKLPort4,SKLPort5,SKLPort237]> { let Latency = 2; let NumMicroOps = 3; let ReleaseAtCycles = [1,1,1]; } 612 613// Nop, not very useful expect it provides a model for nops! 614def : WriteRes<WriteNop, []>; 615 616//////////////////////////////////////////////////////////////////////////////// 617// Horizontal add/sub instructions. 618//////////////////////////////////////////////////////////////////////////////// 619 620defm : SKLWriteResPair<WriteFHAdd, [SKLPort5,SKLPort01], 6, [2,1], 3, 6>; 621defm : SKLWriteResPair<WriteFHAddY, [SKLPort5,SKLPort01], 6, [2,1], 3, 7>; 622defm : SKLWriteResPair<WritePHAdd, [SKLPort5,SKLPort05], 3, [2,1], 3, 5>; 623defm : SKLWriteResPair<WritePHAddX, [SKLPort5,SKLPort015], 3, [2,1], 3, 6>; 624defm : SKLWriteResPair<WritePHAddY, [SKLPort5,SKLPort015], 3, [2,1], 3, 7>; 625 626// Remaining instrs. 627 628def SKLWriteResGroup1 : SchedWriteRes<[SKLPort0]> { 629 let Latency = 1; 630 let NumMicroOps = 1; 631 let ReleaseAtCycles = [1]; 632} 633def: InstRW<[SKLWriteResGroup1], (instregex "MMX_PADDS(B|W)rr", 634 "MMX_PADDUS(B|W)rr", 635 "MMX_PAVG(B|W)rr", 636 "MMX_PCMPEQ(B|D|W)rr", 637 "MMX_PCMPGT(B|D|W)rr", 638 "MMX_P(MAX|MIN)SWrr", 639 "MMX_P(MAX|MIN)UBrr", 640 "MMX_PSUBS(B|W)rr", 641 "MMX_PSUBUS(B|W)rr")>; 642 643def SKLWriteResGroup3 : SchedWriteRes<[SKLPort5]> { 644 let Latency = 1; 645 let NumMicroOps = 1; 646 let ReleaseAtCycles = [1]; 647} 648def: InstRW<[SKLWriteResGroup3], (instregex "COM(P?)_FST0r", 649 "UCOM_F(P?)r")>; 650 651def SKLWriteResGroup4 : SchedWriteRes<[SKLPort6]> { 652 let Latency = 1; 653 let NumMicroOps = 1; 654 let ReleaseAtCycles = [1]; 655} 656def: InstRW<[SKLWriteResGroup4], (instregex "JMP(16|32|64)r")>; 657 658def SKLWriteResGroup6 : SchedWriteRes<[SKLPort05]> { 659 let Latency = 1; 660 let NumMicroOps = 1; 661 let ReleaseAtCycles = [1]; 662} 663def: InstRW<[SKLWriteResGroup6], (instrs FINCSTP, FNOP)>; 664 665def SKLWriteResGroup7 : SchedWriteRes<[SKLPort06]> { 666 let Latency = 1; 667 let NumMicroOps = 1; 668 let ReleaseAtCycles = [1]; 669} 670def: InstRW<[SKLWriteResGroup7], (instrs CDQ, CQO, CLAC, STAC)>; 671 672def SKLWriteResGroup8 : SchedWriteRes<[SKLPort15]> { 673 let Latency = 1; 674 let NumMicroOps = 1; 675 let ReleaseAtCycles = [1]; 676} 677def: InstRW<[SKLWriteResGroup8], (instregex "ANDN(32|64)rr")>; 678 679def SKLWriteResGroup9 : SchedWriteRes<[SKLPort015]> { 680 let Latency = 1; 681 let NumMicroOps = 1; 682 let ReleaseAtCycles = [1]; 683} 684def: InstRW<[SKLWriteResGroup9], (instregex "(V?)PADD(B|D|Q|W)(Y?)rr", 685 "VPBLENDD(Y?)rri")>; 686 687def SKLWriteResGroup10 : SchedWriteRes<[SKLPort0156]> { 688 let Latency = 1; 689 let NumMicroOps = 1; 690 let ReleaseAtCycles = [1]; 691} 692def: InstRW<[SKLWriteResGroup10], (instrs SGDT64m, 693 SIDT64m, 694 SMSW16m, 695 STRm, 696 SYSCALL)>; 697 698def SKLWriteResGroup11 : SchedWriteRes<[SKLPort4,SKLPort237]> { 699 let Latency = 1; 700 let NumMicroOps = 2; 701 let ReleaseAtCycles = [1,1]; 702} 703def: InstRW<[SKLWriteResGroup11], (instrs FBSTPm, VMPTRSTm)>; 704def: InstRW<[SKLWriteResGroup11], (instregex "ST_FP(32|64|80)m")>; 705 706def SKLWriteResGroup13 : SchedWriteRes<[SKLPort5]> { 707 let Latency = 2; 708 let NumMicroOps = 2; 709 let ReleaseAtCycles = [2]; 710} 711def: InstRW<[SKLWriteResGroup13], (instrs MMX_MOVQ2DQrr)>; 712 713def SKLWriteResGroup14 : SchedWriteRes<[SKLPort05]> { 714 let Latency = 2; 715 let NumMicroOps = 2; 716 let ReleaseAtCycles = [2]; 717} 718def: InstRW<[SKLWriteResGroup14], (instrs FDECSTP, 719 MMX_MOVDQ2Qrr)>; 720 721def SKLWriteResGroup17 : SchedWriteRes<[SKLPort0156]> { 722 let Latency = 2; 723 let NumMicroOps = 2; 724 let ReleaseAtCycles = [2]; 725} 726def: InstRW<[SKLWriteResGroup17], (instrs LFENCE, 727 WAIT, 728 XGETBV)>; 729 730def SKLWriteResGroup20 : SchedWriteRes<[SKLPort6,SKLPort0156]> { 731 let Latency = 2; 732 let NumMicroOps = 2; 733 let ReleaseAtCycles = [1,1]; 734} 735def: InstRW<[SKLWriteResGroup20], (instregex "CLFLUSH")>; 736 737def SKLWriteResGroup21 : SchedWriteRes<[SKLPort237,SKLPort0156]> { 738 let Latency = 2; 739 let NumMicroOps = 2; 740 let ReleaseAtCycles = [1,1]; 741} 742def: InstRW<[SKLWriteResGroup21], (instrs SFENCE)>; 743 744def SKLWriteResGroup23 : SchedWriteRes<[SKLPort06,SKLPort0156]> { 745 let Latency = 2; 746 let NumMicroOps = 2; 747 let ReleaseAtCycles = [1,1]; 748} 749def: InstRW<[SKLWriteResGroup23], (instrs CWD, 750 JCXZ, JECXZ, JRCXZ, 751 ADC8i8, SBB8i8, 752 ADC16i16, SBB16i16, 753 ADC32i32, SBB32i32, 754 ADC64i32, SBB64i32)>; 755 756def SKLWriteResGroup25 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort237]> { 757 let Latency = 2; 758 let NumMicroOps = 3; 759 let ReleaseAtCycles = [1,1,1]; 760} 761def: InstRW<[SKLWriteResGroup25], (instrs FNSTCW16m)>; 762 763def SKLWriteResGroup27 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort15]> { 764 let Latency = 2; 765 let NumMicroOps = 3; 766 let ReleaseAtCycles = [1,1,1]; 767} 768def: InstRW<[SKLWriteResGroup27], (instregex "MOVBE(16|32|64)mr")>; 769 770def SKLWriteResGroup28 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort0156]> { 771 let Latency = 2; 772 let NumMicroOps = 3; 773 let ReleaseAtCycles = [1,1,1]; 774} 775def: InstRW<[SKLWriteResGroup28], (instrs PUSH16r, PUSH32r, PUSH64r, PUSH64i8, 776 STOSB, STOSL, STOSQ, STOSW)>; 777def: InstRW<[SKLWriteResGroup28], (instregex "PUSH(16|32|64)rmr")>; 778 779def SKLWriteResGroup29 : SchedWriteRes<[SKLPort1]> { 780 let Latency = 3; 781 let NumMicroOps = 1; 782 let ReleaseAtCycles = [1]; 783} 784def: InstRW<[SKLWriteResGroup29], (instregex "PDEP(32|64)rr", 785 "PEXT(32|64)rr")>; 786 787def SKLWriteResGroup30 : SchedWriteRes<[SKLPort5]> { 788 let Latency = 3; 789 let NumMicroOps = 1; 790 let ReleaseAtCycles = [1]; 791} 792def: InstRW<[SKLWriteResGroup30], (instregex "(ADD|SUB|SUBR)_(FPrST0|FST0r|FrST0)", 793 "VPBROADCAST(B|W)rr")>; 794 795def SKLWriteResGroup32 : SchedWriteRes<[SKLPort0,SKLPort0156]> { 796 let Latency = 3; 797 let NumMicroOps = 2; 798 let ReleaseAtCycles = [1,1]; 799} 800def: InstRW<[SKLWriteResGroup32], (instrs FNSTSW16r)>; 801 802def SKLWriteResGroup35 : SchedWriteRes<[SKLPort0,SKLPort5]> { 803 let Latency = 3; 804 let NumMicroOps = 3; 805 let ReleaseAtCycles = [1,2]; 806} 807def: InstRW<[SKLWriteResGroup35], (instregex "MMX_PH(ADD|SUB)SWrr")>; 808 809def SKLWriteResGroup36 : SchedWriteRes<[SKLPort5,SKLPort01]> { 810 let Latency = 3; 811 let NumMicroOps = 3; 812 let ReleaseAtCycles = [2,1]; 813} 814def: InstRW<[SKLWriteResGroup36], (instregex "(V?)PHADDSW(Y?)rr", 815 "(V?)PHSUBSW(Y?)rr")>; 816 817def SKLWriteResGroup39 : SchedWriteRes<[SKLPort5,SKLPort0156]> { 818 let Latency = 3; 819 let NumMicroOps = 3; 820 let ReleaseAtCycles = [2,1]; 821} 822def: InstRW<[SKLWriteResGroup39], (instrs MMX_PACKSSDWrr, 823 MMX_PACKSSWBrr, 824 MMX_PACKUSWBrr)>; 825 826def SKLWriteResGroup40 : SchedWriteRes<[SKLPort6,SKLPort0156]> { 827 let Latency = 3; 828 let NumMicroOps = 3; 829 let ReleaseAtCycles = [1,2]; 830} 831def: InstRW<[SKLWriteResGroup40], (instregex "CLD")>; 832 833def SKLWriteResGroup41 : SchedWriteRes<[SKLPort237,SKLPort0156]> { 834 let Latency = 3; 835 let NumMicroOps = 3; 836 let ReleaseAtCycles = [1,2]; 837} 838def: InstRW<[SKLWriteResGroup41], (instrs MFENCE)>; 839 840def SKLWriteResGroup42 : SchedWriteRes<[SKLPort06,SKLPort0156]> { 841 let Latency = 2; 842 let NumMicroOps = 3; 843 let ReleaseAtCycles = [1,2]; 844} 845def: InstRW<[SKLWriteResGroup42], (instrs RCL8r1, RCL16r1, RCL32r1, RCL64r1, 846 RCR8r1, RCR16r1, RCR32r1, RCR64r1)>; 847 848def SKLWriteResGroup42b : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort0156]> { 849 let Latency = 5; 850 let NumMicroOps = 8; 851 let ReleaseAtCycles = [2,4,2]; 852} 853def: InstRW<[SKLWriteResGroup42b], (instrs RCR8ri, RCR16ri, RCR32ri, RCR64ri)>; 854 855def SKLWriteResGroup42c : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort0156]> { 856 let Latency = 6; 857 let NumMicroOps = 8; 858 let ReleaseAtCycles = [2,4,2]; 859} 860def: InstRW<[SKLWriteResGroup42c], (instrs RCL8ri, RCL16ri, RCL32ri, RCL64ri)>; 861 862def SKLWriteResGroup43 : SchedWriteRes<[SKLPort0,SKLPort4,SKLPort237]> { 863 let Latency = 3; 864 let NumMicroOps = 3; 865 let ReleaseAtCycles = [1,1,1]; 866} 867def: InstRW<[SKLWriteResGroup43], (instrs FNSTSWm)>; 868 869def SKLWriteResGroup45 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort237,SKLPort0156]> { 870 let Latency = 3; 871 let NumMicroOps = 4; 872 let ReleaseAtCycles = [1,1,1,1]; 873} 874def: InstRW<[SKLWriteResGroup45], (instregex "CALL(16|32|64)r")>; 875 876def SKLWriteResGroup46 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort06,SKLPort0156]> { 877 let Latency = 3; 878 let NumMicroOps = 4; 879 let ReleaseAtCycles = [1,1,1,1]; 880} 881def: InstRW<[SKLWriteResGroup46], (instrs CALL64pcrel32)>; 882 883def SKLWriteResGroup47 : SchedWriteRes<[SKLPort0]> { 884 let Latency = 4; 885 let NumMicroOps = 1; 886 let ReleaseAtCycles = [1]; 887} 888def: InstRW<[SKLWriteResGroup47], (instregex "MUL_(FPrST0|FST0r|FrST0)")>; 889 890def SKLWriteResGroup53 : SchedWriteRes<[SKLPort4,SKLPort5,SKLPort237]> { 891 let Latency = 4; 892 let NumMicroOps = 3; 893 let ReleaseAtCycles = [1,1,1]; 894} 895def: InstRW<[SKLWriteResGroup53], (instregex "IST(T?)_FP(16|32|64)m", 896 "IST_F(16|32)m")>; 897 898def SKLWriteResGroup54 : SchedWriteRes<[SKLPort0156]> { 899 let Latency = 4; 900 let NumMicroOps = 4; 901 let ReleaseAtCycles = [4]; 902} 903def: InstRW<[SKLWriteResGroup54], (instrs FNCLEX)>; 904 905def SKLWriteResGroup55 : SchedWriteRes<[SKLPort6,SKLPort0156]> { 906 let Latency = 4; 907 let NumMicroOps = 4; 908 let ReleaseAtCycles = [1,3]; 909} 910def: InstRW<[SKLWriteResGroup55], (instrs PAUSE)>; 911 912def SKLWriteResGroup56 : SchedWriteRes<[]> { 913 let Latency = 0; 914 let NumMicroOps = 4; 915 let ReleaseAtCycles = []; 916} 917def: InstRW<[SKLWriteResGroup56], (instrs VZEROUPPER)>; 918 919def SKLWriteResGroup57 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort0156]> { 920 let Latency = 4; 921 let NumMicroOps = 4; 922 let ReleaseAtCycles = [1,1,2]; 923} 924def: InstRW<[SKLWriteResGroup57], (instregex "LAR(16|32|64)rr")>; 925 926def SKLWriteResGroup60 : SchedWriteRes<[SKLPort5,SKLPort01]> { 927 let Latency = 5; 928 let NumMicroOps = 2; 929 let ReleaseAtCycles = [1,1]; 930} 931def: InstRW<[SKLWriteResGroup60], (instregex "MMX_CVT(T?)PS2PIrr")>; 932 933def SKLWriteResGroup61 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort06]> { 934 let Latency = 5; 935 let NumMicroOps = 3; 936 let ReleaseAtCycles = [1,1,1]; 937} 938def: InstRW<[SKLWriteResGroup61], (instregex "STR(16|32|64)r")>; 939 940def SKLWriteResGroup63 : SchedWriteRes<[SKLPort06,SKLPort0156]> { 941 let Latency = 5; 942 let NumMicroOps = 5; 943 let ReleaseAtCycles = [1,4]; 944} 945def: InstRW<[SKLWriteResGroup63], (instrs XSETBV)>; 946 947def SKLWriteResGroup65 : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort0156]> { 948 let Latency = 5; 949 let NumMicroOps = 6; 950 let ReleaseAtCycles = [1,1,4]; 951} 952def: InstRW<[SKLWriteResGroup65], (instregex "PUSHF(16|64)")>; 953 954def SKLWriteResGroup67 : SchedWriteRes<[SKLPort23]> { 955 let Latency = 6; 956 let NumMicroOps = 1; 957 let ReleaseAtCycles = [1]; 958} 959def: InstRW<[SKLWriteResGroup67], (instrs VBROADCASTSSrm, 960 VPBROADCASTDrm, 961 VPBROADCASTQrm)>; 962def: InstRW<[SKLWriteResGroup67], (instregex "(V?)MOVSHDUPrm", 963 "(V?)MOVSLDUPrm", 964 "(V?)MOVDDUPrm")>; 965 966def SKLWriteResGroup68 : SchedWriteRes<[SKLPort0]> { 967 let Latency = 6; 968 let NumMicroOps = 2; 969 let ReleaseAtCycles = [2]; 970} 971def: InstRW<[SKLWriteResGroup68], (instrs MMX_CVTPI2PSrr)>; 972 973def SKLWriteResGroup69 : SchedWriteRes<[SKLPort0,SKLPort23]> { 974 let Latency = 6; 975 let NumMicroOps = 2; 976 let ReleaseAtCycles = [1,1]; 977} 978def: InstRW<[SKLWriteResGroup69], (instrs MMX_PADDSBrm, 979 MMX_PADDSWrm, 980 MMX_PADDUSBrm, 981 MMX_PADDUSWrm, 982 MMX_PAVGBrm, 983 MMX_PAVGWrm, 984 MMX_PCMPEQBrm, 985 MMX_PCMPEQDrm, 986 MMX_PCMPEQWrm, 987 MMX_PCMPGTBrm, 988 MMX_PCMPGTDrm, 989 MMX_PCMPGTWrm, 990 MMX_PMAXSWrm, 991 MMX_PMAXUBrm, 992 MMX_PMINSWrm, 993 MMX_PMINUBrm, 994 MMX_PSUBSBrm, 995 MMX_PSUBSWrm, 996 MMX_PSUBUSBrm, 997 MMX_PSUBUSWrm)>; 998 999def SKLWriteResGroup72 : SchedWriteRes<[SKLPort6,SKLPort23]> { 1000 let Latency = 6; 1001 let NumMicroOps = 2; 1002 let ReleaseAtCycles = [1,1]; 1003} 1004def: InstRW<[SKLWriteResGroup72], (instrs FARJMP64m)>; 1005def: InstRW<[SKLWriteResGroup72], (instregex "JMP(16|32|64)m")>; 1006 1007def SKLWriteResGroup75 : SchedWriteRes<[SKLPort23,SKLPort15]> { 1008 let Latency = 6; 1009 let NumMicroOps = 2; 1010 let ReleaseAtCycles = [1,1]; 1011} 1012def: InstRW<[SKLWriteResGroup75], (instregex "ANDN(32|64)rm", 1013 "MOVBE(16|32|64)rm")>; 1014 1015def SKLWriteResGroup76 : SchedWriteRes<[SKLPort23,SKLPort0156]> { 1016 let Latency = 6; 1017 let NumMicroOps = 2; 1018 let ReleaseAtCycles = [1,1]; 1019} 1020def: InstRW<[SKLWriteResGroup76], (instrs POP16r, POP32r, POP64r)>; 1021def: InstRW<[SKLWriteResGroup76], (instregex "POP(16|32|64)rmr")>; 1022 1023def SKLWriteResGroup78 : SchedWriteRes<[SKLPort5,SKLPort01]> { 1024 let Latency = 6; 1025 let NumMicroOps = 3; 1026 let ReleaseAtCycles = [2,1]; 1027} 1028def: InstRW<[SKLWriteResGroup78], (instregex "(V?)CVTSI642SSrr")>; 1029 1030def SKLWriteResGroup80 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort06,SKLPort0156]> { 1031 let Latency = 6; 1032 let NumMicroOps = 4; 1033 let ReleaseAtCycles = [1,1,1,1]; 1034} 1035def: InstRW<[SKLWriteResGroup80], (instregex "SLDT(16|32|64)r")>; 1036 1037def SKLWriteResGroup82 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> { 1038 let Latency = 6; 1039 let NumMicroOps = 4; 1040 let ReleaseAtCycles = [1,1,1,1]; 1041} 1042def: InstRW<[SKLWriteResGroup82], (instregex "SAR(8|16|32|64)m(1|i)", 1043 "SHL(8|16|32|64)m(1|i)", 1044 "SHR(8|16|32|64)m(1|i)")>; 1045 1046def SKLWriteResGroup83 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort0156]> { 1047 let Latency = 6; 1048 let NumMicroOps = 4; 1049 let ReleaseAtCycles = [1,1,1,1]; 1050} 1051def: InstRW<[SKLWriteResGroup83], (instregex "POP(16|32|64)rmm", 1052 "PUSH(16|32|64)rmm")>; 1053 1054def SKLWriteResGroup84 : SchedWriteRes<[SKLPort6,SKLPort0156]> { 1055 let Latency = 6; 1056 let NumMicroOps = 6; 1057 let ReleaseAtCycles = [1,5]; 1058} 1059def: InstRW<[SKLWriteResGroup84], (instrs STD)>; 1060 1061def SKLWriteResGroup85 : SchedWriteRes<[SKLPort23]> { 1062 let Latency = 7; 1063 let NumMicroOps = 1; 1064 let ReleaseAtCycles = [1]; 1065} 1066def: InstRW<[SKLWriteResGroup85], (instregex "LD_F(32|64|80)m")>; 1067def: InstRW<[SKLWriteResGroup85], (instrs VBROADCASTF128rm, 1068 VBROADCASTI128rm, 1069 VBROADCASTSDYrm, 1070 VBROADCASTSSYrm, 1071 VMOVDDUPYrm, 1072 VMOVSHDUPYrm, 1073 VMOVSLDUPYrm, 1074 VPBROADCASTDYrm, 1075 VPBROADCASTQYrm)>; 1076 1077def SKLWriteResGroup88 : SchedWriteRes<[SKLPort5,SKLPort23]> { 1078 let Latency = 6; 1079 let NumMicroOps = 2; 1080 let ReleaseAtCycles = [1,1]; 1081} 1082def: InstRW<[SKLWriteResGroup88], (instregex "(V?)PMOV(SX|ZX)BDrm", 1083 "(V?)PMOV(SX|ZX)BQrm", 1084 "(V?)PMOV(SX|ZX)BWrm", 1085 "(V?)PMOV(SX|ZX)DQrm", 1086 "(V?)PMOV(SX|ZX)WDrm", 1087 "(V?)PMOV(SX|ZX)WQrm")>; 1088 1089def SKLWriteResGroup91 : SchedWriteRes<[SKLPort23,SKLPort015]> { 1090 let Latency = 7; 1091 let NumMicroOps = 2; 1092 let ReleaseAtCycles = [1,1]; 1093} 1094def: InstRW<[SKLWriteResGroup91], (instrs VINSERTF128rm, 1095 VINSERTI128rm, 1096 VPBLENDDrmi)>; 1097def: InstRW<[SKLWriteResGroup91, ReadAfterVecXLd], 1098 (instregex "(V?)PADD(B|D|Q|W)rm", 1099 "(V?)PSUB(B|D|Q|W)rm")>; 1100 1101def SKLWriteResGroup92 : SchedWriteRes<[SKLPort5,SKLPort23]> { 1102 let Latency = 7; 1103 let NumMicroOps = 3; 1104 let ReleaseAtCycles = [2,1]; 1105} 1106def: InstRW<[SKLWriteResGroup92], (instrs MMX_PACKSSDWrm, 1107 MMX_PACKSSWBrm, 1108 MMX_PACKUSWBrm)>; 1109 1110def SKLWriteResGroup94 : SchedWriteRes<[SKLPort23,SKLPort0156]> { 1111 let Latency = 7; 1112 let NumMicroOps = 3; 1113 let ReleaseAtCycles = [1,2]; 1114} 1115def: InstRW<[SKLWriteResGroup94], (instrs LEAVE, LEAVE64, 1116 SCASB, SCASL, SCASQ, SCASW)>; 1117 1118def SKLWriteResGroup95 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort01]> { 1119 let Latency = 7; 1120 let NumMicroOps = 3; 1121 let ReleaseAtCycles = [1,1,1]; 1122} 1123def: InstRW<[SKLWriteResGroup95], (instregex "(V?)CVT(T?)SS2SI64rr")>; 1124 1125def SKLWriteResGroup96 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort05]> { 1126 let Latency = 7; 1127 let NumMicroOps = 3; 1128 let ReleaseAtCycles = [1,1,1]; 1129} 1130def: InstRW<[SKLWriteResGroup96], (instrs FLDCW16m)>; 1131 1132def SKLWriteResGroup98 : SchedWriteRes<[SKLPort6,SKLPort23,SKLPort0156]> { 1133 let Latency = 7; 1134 let NumMicroOps = 3; 1135 let ReleaseAtCycles = [1,1,1]; 1136} 1137def: InstRW<[SKLWriteResGroup98], (instrs LRET64, RET64)>; 1138 1139def SKLWriteResGroup100 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> { 1140 let Latency = 7; 1141 let NumMicroOps = 5; 1142 let ReleaseAtCycles = [1,1,1,2]; 1143} 1144def: InstRW<[SKLWriteResGroup100], (instregex "ROL(8|16|32|64)m(1|i)", 1145 "ROR(8|16|32|64)m(1|i)")>; 1146 1147def SKLWriteResGroup100_1 : SchedWriteRes<[SKLPort06]> { 1148 let Latency = 2; 1149 let NumMicroOps = 2; 1150 let ReleaseAtCycles = [2]; 1151} 1152def: InstRW<[SKLWriteResGroup100_1], (instrs ROL8r1, ROL16r1, ROL32r1, ROL64r1, 1153 ROR8r1, ROR16r1, ROR32r1, ROR64r1)>; 1154 1155def SKLWriteResGroup101 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort0156]> { 1156 let Latency = 7; 1157 let NumMicroOps = 5; 1158 let ReleaseAtCycles = [1,1,1,2]; 1159} 1160def: InstRW<[SKLWriteResGroup101], (instregex "XADD(8|16|32|64)rm")>; 1161 1162def SKLWriteResGroup102 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> { 1163 let Latency = 7; 1164 let NumMicroOps = 5; 1165 let ReleaseAtCycles = [1,1,1,1,1]; 1166} 1167def: InstRW<[SKLWriteResGroup102], (instregex "CALL(16|32|64)m")>; 1168def: InstRW<[SKLWriteResGroup102], (instrs FARCALL64m)>; 1169 1170def SKLWriteResGroup103 : SchedWriteRes<[SKLPort6,SKLPort06,SKLPort15,SKLPort0156]> { 1171 let Latency = 7; 1172 let NumMicroOps = 7; 1173 let ReleaseAtCycles = [1,3,1,2]; 1174} 1175def: InstRW<[SKLWriteResGroup103], (instrs LOOP)>; 1176 1177def SKLWriteResGroup107 : SchedWriteRes<[SKLPort1,SKLPort23]> { 1178 let Latency = 8; 1179 let NumMicroOps = 2; 1180 let ReleaseAtCycles = [1,1]; 1181} 1182def: InstRW<[SKLWriteResGroup107], (instregex "PDEP(32|64)rm", 1183 "PEXT(32|64)rm")>; 1184 1185def SKLWriteResGroup108 : SchedWriteRes<[SKLPort5,SKLPort23]> { 1186 let Latency = 8; 1187 let NumMicroOps = 2; 1188 let ReleaseAtCycles = [1,1]; 1189} 1190def: InstRW<[SKLWriteResGroup108], (instregex "FCOM(P?)(32|64)m")>; 1191def: InstRW<[SKLWriteResGroup108], (instrs VPBROADCASTBYrm, 1192 VPBROADCASTWYrm, 1193 VPMOVSXBDYrm, 1194 VPMOVSXBQYrm, 1195 VPMOVSXWQYrm)>; 1196 1197def SKLWriteResGroup110 : SchedWriteRes<[SKLPort23,SKLPort015]> { 1198 let Latency = 8; 1199 let NumMicroOps = 2; 1200 let ReleaseAtCycles = [1,1]; 1201} 1202def: InstRW<[SKLWriteResGroup110], (instrs VPBLENDDYrmi)>; 1203def: InstRW<[SKLWriteResGroup110, ReadAfterVecYLd], 1204 (instregex "VPADD(B|D|Q|W)Yrm", 1205 "VPSUB(B|D|Q|W)Yrm")>; 1206 1207def SKLWriteResGroup112 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> { 1208 let Latency = 8; 1209 let NumMicroOps = 4; 1210 let ReleaseAtCycles = [1,2,1]; 1211} 1212def: InstRW<[SKLWriteResGroup112], (instregex "MMX_PH(ADD|SUB)SWrm")>; 1213 1214def SKLWriteResGroup116 : SchedWriteRes<[SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> { 1215 let Latency = 8; 1216 let NumMicroOps = 5; 1217 let ReleaseAtCycles = [1,1,1,2]; 1218} 1219def: InstRW<[SKLWriteResGroup116], (instregex "RCL(8|16|32|64)m(1|i)", 1220 "RCR(8|16|32|64)m(1|i)")>; 1221 1222def SKLWriteResGroup117 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06]> { 1223 let Latency = 8; 1224 let NumMicroOps = 6; 1225 let ReleaseAtCycles = [1,1,1,3]; 1226} 1227def: InstRW<[SKLWriteResGroup117], (instregex "ROL(8|16|32|64)mCL", 1228 "ROR(8|16|32|64)mCL", 1229 "SAR(8|16|32|64)mCL", 1230 "SHL(8|16|32|64)mCL", 1231 "SHR(8|16|32|64)mCL")>; 1232 1233def SKLWriteResGroup119 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> { 1234 let Latency = 8; 1235 let NumMicroOps = 6; 1236 let ReleaseAtCycles = [1,1,1,2,1]; 1237} 1238def: SchedAlias<WriteADCRMW, SKLWriteResGroup119>; 1239 1240def SKLWriteResGroup120 : SchedWriteRes<[SKLPort0,SKLPort23]> { 1241 let Latency = 9; 1242 let NumMicroOps = 2; 1243 let ReleaseAtCycles = [1,1]; 1244} 1245def: InstRW<[SKLWriteResGroup120], (instrs MMX_CVTPI2PSrm)>; 1246 1247def SKLWriteResGroup121 : SchedWriteRes<[SKLPort5,SKLPort23]> { 1248 let Latency = 9; 1249 let NumMicroOps = 2; 1250 let ReleaseAtCycles = [1,1]; 1251} 1252def: InstRW<[SKLWriteResGroup121], (instrs PCMPGTQrm, 1253 VPCMPGTQrm, 1254 VPMOVSXBWYrm, 1255 VPMOVSXDQYrm, 1256 VPMOVSXWDYrm, 1257 VPMOVZXWDYrm)>; 1258 1259def SKLWriteResGroup123 : SchedWriteRes<[SKLPort23,SKLPort01]> { 1260 let Latency = 9; 1261 let NumMicroOps = 2; 1262 let ReleaseAtCycles = [1,1]; 1263} 1264def: InstRW<[SKLWriteResGroup123], (instregex "MMX_CVT(T?)PS2PIrm")>; 1265 1266def SKLWriteResGroup128 : SchedWriteRes<[SKLPort5,SKLPort01,SKLPort23]> { 1267 let Latency = 9; 1268 let NumMicroOps = 4; 1269 let ReleaseAtCycles = [2,1,1]; 1270} 1271def: InstRW<[SKLWriteResGroup128], (instregex "(V?)PHADDSWrm", 1272 "(V?)PHSUBSWrm")>; 1273 1274def SKLWriteResGroup131 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort23,SKLPort0156]> { 1275 let Latency = 9; 1276 let NumMicroOps = 5; 1277 let ReleaseAtCycles = [1,2,1,1]; 1278} 1279def: InstRW<[SKLWriteResGroup131], (instregex "LAR(16|32|64)rm", 1280 "LSL(16|32|64)rm")>; 1281 1282def SKLWriteResGroup133 : SchedWriteRes<[SKLPort5,SKLPort23]> { 1283 let Latency = 10; 1284 let NumMicroOps = 2; 1285 let ReleaseAtCycles = [1,1]; 1286} 1287def: InstRW<[SKLWriteResGroup133], (instregex "(ADD|SUB|SUBR)_F(32|64)m", 1288 "ILD_F(16|32|64)m")>; 1289def: InstRW<[SKLWriteResGroup133], (instrs VPCMPGTQYrm)>; 1290 1291def SKLWriteResGroup138 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> { 1292 let Latency = 10; 1293 let NumMicroOps = 3; 1294 let ReleaseAtCycles = [1,1,1]; 1295} 1296def: InstRW<[SKLWriteResGroup138], (instrs MMX_CVTPI2PDrm)>; 1297 1298def SKLWriteResGroup140 : SchedWriteRes<[SKLPort5,SKLPort01,SKLPort23]> { 1299 let Latency = 10; 1300 let NumMicroOps = 4; 1301 let ReleaseAtCycles = [2,1,1]; 1302} 1303def: InstRW<[SKLWriteResGroup140], (instrs VPHADDSWYrm, 1304 VPHSUBSWYrm)>; 1305 1306def SKLWriteResGroup143 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> { 1307 let Latency = 10; 1308 let NumMicroOps = 8; 1309 let ReleaseAtCycles = [1,1,1,1,1,3]; 1310} 1311def: InstRW<[SKLWriteResGroup143], (instregex "XCHG(8|16|32|64)rm")>; 1312 1313def SKLWriteResGroup146 : SchedWriteRes<[SKLPort0,SKLPort23]> { 1314 let Latency = 11; 1315 let NumMicroOps = 2; 1316 let ReleaseAtCycles = [1,1]; 1317} 1318def: InstRW<[SKLWriteResGroup146], (instregex "MUL_F(32|64)m")>; 1319 1320def SKLWriteResGroup149 : SchedWriteRes<[SKLPort5,SKLPort23]> { 1321 let Latency = 11; 1322 let NumMicroOps = 3; 1323 let ReleaseAtCycles = [2,1]; 1324} 1325def: InstRW<[SKLWriteResGroup149], (instregex "FICOM(P?)(16|32)m")>; 1326 1327def SKLWriteResGroup154 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort0156]> { 1328 let Latency = 11; 1329 let NumMicroOps = 7; 1330 let ReleaseAtCycles = [2,3,2]; 1331} 1332def: InstRW<[SKLWriteResGroup154], (instregex "RCL(16|32|64)rCL", 1333 "RCR(16|32|64)rCL")>; 1334 1335def SKLWriteResGroup155 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort15,SKLPort0156]> { 1336 let Latency = 11; 1337 let NumMicroOps = 9; 1338 let ReleaseAtCycles = [1,5,1,2]; 1339} 1340def: InstRW<[SKLWriteResGroup155], (instrs RCL8rCL)>; 1341 1342def SKLWriteResGroup156 : SchedWriteRes<[SKLPort06,SKLPort0156]> { 1343 let Latency = 11; 1344 let NumMicroOps = 11; 1345 let ReleaseAtCycles = [2,9]; 1346} 1347def: InstRW<[SKLWriteResGroup156], (instrs LOOPE, LOOPNE)>; 1348 1349def SKLWriteResGroup162 : SchedWriteRes<[SKLPort5,SKLPort23]> { 1350 let Latency = 13; 1351 let NumMicroOps = 3; 1352 let ReleaseAtCycles = [2,1]; 1353} 1354def: InstRW<[SKLWriteResGroup162], (instregex "(ADD|SUB|SUBR)_FI(16|32)m")>; 1355 1356def SKLWriteResGroup169 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> { 1357 let Latency = 14; 1358 let NumMicroOps = 3; 1359 let ReleaseAtCycles = [1,1,1]; 1360} 1361def: InstRW<[SKLWriteResGroup169], (instregex "MUL_FI(16|32)m")>; 1362 1363def SKLWriteResGroup170 : SchedWriteRes<[SKLPort1,SKLPort06,SKLPort15,SKLPort0156]> { 1364 let Latency = 14; 1365 let NumMicroOps = 10; 1366 let ReleaseAtCycles = [2,4,1,3]; 1367} 1368def: InstRW<[SKLWriteResGroup170], (instrs RCR8rCL)>; 1369 1370def SKLWriteResGroup171 : SchedWriteRes<[SKLPort0]> { 1371 let Latency = 15; 1372 let NumMicroOps = 1; 1373 let ReleaseAtCycles = [1]; 1374} 1375def: InstRW<[SKLWriteResGroup171], (instregex "DIVR_(FPrST0|FST0r|FrST0)")>; 1376 1377def SKLWriteResGroup174 : SchedWriteRes<[SKLPort1,SKLPort23,SKLPort237,SKLPort06,SKLPort15,SKLPort0156]> { 1378 let Latency = 15; 1379 let NumMicroOps = 10; 1380 let ReleaseAtCycles = [1,1,1,5,1,1]; 1381} 1382def: InstRW<[SKLWriteResGroup174], (instregex "RCL(8|16|32|64)mCL")>; 1383 1384def SKLWriteResGroup177 : SchedWriteRes<[SKLPort4,SKLPort23,SKLPort237,SKLPort06,SKLPort15,SKLPort0156]> { 1385 let Latency = 16; 1386 let NumMicroOps = 14; 1387 let ReleaseAtCycles = [1,1,1,4,2,5]; 1388} 1389def: InstRW<[SKLWriteResGroup177], (instrs CMPXCHG8B)>; 1390 1391def SKLWriteResGroup178 : SchedWriteRes<[SKLPort0156]> { 1392 let Latency = 16; 1393 let NumMicroOps = 16; 1394 let ReleaseAtCycles = [16]; 1395} 1396def: InstRW<[SKLWriteResGroup178], (instrs VZEROALL)>; 1397 1398def SKLWriteResGroup180 : SchedWriteRes<[SKLPort0,SKLPort1,SKLPort5,SKLPort6,SKLPort05,SKLPort0156]> { 1399 let Latency = 17; 1400 let NumMicroOps = 15; 1401 let ReleaseAtCycles = [2,1,2,4,2,4]; 1402} 1403def: InstRW<[SKLWriteResGroup180], (instrs XCH_F)>; 1404 1405def SKLWriteResGroup184 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort06,SKLPort0156]> { 1406 let Latency = 18; 1407 let NumMicroOps = 8; 1408 let ReleaseAtCycles = [1,1,1,5]; 1409} 1410def: InstRW<[SKLWriteResGroup184], (instrs CPUID, RDTSC)>; 1411 1412def SKLWriteResGroup185 : SchedWriteRes<[SKLPort1,SKLPort23,SKLPort237,SKLPort06,SKLPort15,SKLPort0156]> { 1413 let Latency = 18; 1414 let NumMicroOps = 11; 1415 let ReleaseAtCycles = [2,1,1,4,1,2]; 1416} 1417def: InstRW<[SKLWriteResGroup185], (instregex "RCR(8|16|32|64)mCL")>; 1418 1419def SKLWriteResGroup189 : SchedWriteRes<[SKLPort0]> { 1420 let Latency = 20; 1421 let NumMicroOps = 1; 1422 let ReleaseAtCycles = [1]; 1423} 1424def: InstRW<[SKLWriteResGroup189], (instregex "DIV_(FPrST0|FST0r|FrST0)")>; 1425 1426def SKLWriteResGroup192 : SchedWriteRes<[SKLPort4,SKLPort5,SKLPort6,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> { 1427 let Latency = 20; 1428 let NumMicroOps = 8; 1429 let ReleaseAtCycles = [1,1,1,1,1,1,2]; 1430} 1431def: InstRW<[SKLWriteResGroup192], (instrs INSB, INSL, INSW)>; 1432 1433def SKLWriteResGroup193 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort0156]> { 1434 let Latency = 20; 1435 let NumMicroOps = 10; 1436 let ReleaseAtCycles = [1,2,7]; 1437} 1438def: InstRW<[SKLWriteResGroup193], (instrs MWAITrr)>; 1439 1440def SKLWriteResGroup196 : SchedWriteRes<[SKLPort0,SKLPort23]> { 1441 let Latency = 22; 1442 let NumMicroOps = 2; 1443 let ReleaseAtCycles = [1,1]; 1444} 1445def: InstRW<[SKLWriteResGroup196], (instregex "DIV_F(32|64)m")>; 1446 1447def SKLWriteResGroupVEX2 : SchedWriteRes<[SKLPort0, SKLPort23, SKLPort5, SKLPort015]> { 1448 let Latency = 18; 1449 let NumMicroOps = 5; // 2 uops perform multiple loads 1450 let ReleaseAtCycles = [1,2,1,1]; 1451} 1452def: InstRW<[SKLWriteResGroupVEX2], (instrs VGATHERDPDrm, VPGATHERDQrm, 1453 VGATHERQPDrm, VPGATHERQQrm, 1454 VGATHERQPSrm, VPGATHERQDrm)>; 1455 1456def SKLWriteResGroupVEX4 : SchedWriteRes<[SKLPort0, SKLPort23, SKLPort5, SKLPort015]> { 1457 let Latency = 20; 1458 let NumMicroOps = 5; // 2 uops peform multiple loads 1459 let ReleaseAtCycles = [1,4,1,1]; 1460} 1461def: InstRW<[SKLWriteResGroupVEX4], (instrs VGATHERDPDYrm, VPGATHERDQYrm, 1462 VGATHERDPSrm, VPGATHERDDrm, 1463 VGATHERQPDYrm, VPGATHERQQYrm, 1464 VGATHERQPSYrm, VPGATHERQDYrm)>; 1465 1466def SKLWriteResGroupVEX8 : SchedWriteRes<[SKLPort0, SKLPort23, SKLPort5, SKLPort015]> { 1467 let Latency = 22; 1468 let NumMicroOps = 5; // 2 uops perform multiple loads 1469 let ReleaseAtCycles = [1,8,1,1]; 1470} 1471def: InstRW<[SKLWriteResGroupVEX8], (instrs VGATHERDPSYrm, VPGATHERDDYrm)>; 1472 1473def SKLWriteResGroup198 : SchedWriteRes<[SKLPort0,SKLPort4,SKLPort5,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> { 1474 let Latency = 23; 1475 let NumMicroOps = 19; 1476 let ReleaseAtCycles = [2,1,4,1,1,4,6]; 1477} 1478def: InstRW<[SKLWriteResGroup198], (instrs CMPXCHG16B)>; 1479 1480def SKLWriteResGroup202 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> { 1481 let Latency = 25; 1482 let NumMicroOps = 3; 1483 let ReleaseAtCycles = [1,1,1]; 1484} 1485def: InstRW<[SKLWriteResGroup202], (instregex "DIV_FI(16|32)m")>; 1486 1487def SKLWriteResGroup206 : SchedWriteRes<[SKLPort0,SKLPort23]> { 1488 let Latency = 27; 1489 let NumMicroOps = 2; 1490 let ReleaseAtCycles = [1,1]; 1491} 1492def: InstRW<[SKLWriteResGroup206], (instregex "DIVR_F(32|64)m")>; 1493 1494def SKLWriteResGroup208 : SchedWriteRes<[SKLPort0,SKLPort5,SKLPort23]> { 1495 let Latency = 30; 1496 let NumMicroOps = 3; 1497 let ReleaseAtCycles = [1,1,1]; 1498} 1499def: InstRW<[SKLWriteResGroup208], (instregex "DIVR_FI(16|32)m")>; 1500 1501def SKLWriteResGroup209 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort23,SKLPort06,SKLPort0156]> { 1502 let Latency = 35; 1503 let NumMicroOps = 23; 1504 let ReleaseAtCycles = [1,5,3,4,10]; 1505} 1506def: InstRW<[SKLWriteResGroup209], (instregex "IN(8|16|32)ri", 1507 "IN(8|16|32)rr")>; 1508 1509def SKLWriteResGroup210 : SchedWriteRes<[SKLPort5,SKLPort6,SKLPort23,SKLPort237,SKLPort06,SKLPort0156]> { 1510 let Latency = 35; 1511 let NumMicroOps = 23; 1512 let ReleaseAtCycles = [1,5,2,1,4,10]; 1513} 1514def: InstRW<[SKLWriteResGroup210], (instregex "OUT(8|16|32)ir", 1515 "OUT(8|16|32)rr")>; 1516 1517def SKLWriteResGroup211 : SchedWriteRes<[SKLPort1,SKLPort6,SKLPort23,SKLPort0156]> { 1518 let Latency = 37; 1519 let NumMicroOps = 31; 1520 let ReleaseAtCycles = [1,8,1,21]; 1521} 1522def: InstRW<[SKLWriteResGroup211], (instregex "XRSTOR(64)?")>; 1523 1524def SKLWriteResGroup212 : SchedWriteRes<[SKLPort1,SKLPort4,SKLPort5,SKLPort6,SKLPort23,SKLPort237,SKLPort15,SKLPort0156]> { 1525 let Latency = 40; 1526 let NumMicroOps = 18; 1527 let ReleaseAtCycles = [1,1,2,3,1,1,1,8]; 1528} 1529def: InstRW<[SKLWriteResGroup212], (instrs VMCLEARm)>; 1530 1531def SKLWriteResGroup213 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> { 1532 let Latency = 41; 1533 let NumMicroOps = 39; 1534 let ReleaseAtCycles = [1,10,1,1,26]; 1535} 1536def: InstRW<[SKLWriteResGroup213], (instrs XSAVE64)>; 1537 1538def SKLWriteResGroup214 : SchedWriteRes<[SKLPort5,SKLPort0156]> { 1539 let Latency = 42; 1540 let NumMicroOps = 22; 1541 let ReleaseAtCycles = [2,20]; 1542} 1543def: InstRW<[SKLWriteResGroup214], (instrs RDTSCP)>; 1544 1545def SKLWriteResGroup215 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> { 1546 let Latency = 42; 1547 let NumMicroOps = 40; 1548 let ReleaseAtCycles = [1,11,1,1,26]; 1549} 1550def: InstRW<[SKLWriteResGroup215], (instrs XSAVE)>; 1551def: InstRW<[SKLWriteResGroup215], (instregex "XSAVEC", "XSAVES")>; 1552 1553def SKLWriteResGroup216 : SchedWriteRes<[SKLPort4,SKLPort6,SKLPort23,SKLPort237,SKLPort0156]> { 1554 let Latency = 46; 1555 let NumMicroOps = 44; 1556 let ReleaseAtCycles = [1,11,1,1,30]; 1557} 1558def: InstRW<[SKLWriteResGroup216], (instregex "XSAVEOPT")>; 1559 1560def SKLWriteResGroup217 : SchedWriteRes<[SKLPort0,SKLPort23,SKLPort05,SKLPort06,SKLPort0156]> { 1561 let Latency = 62; 1562 let NumMicroOps = 64; 1563 let ReleaseAtCycles = [2,8,5,10,39]; 1564} 1565def: InstRW<[SKLWriteResGroup217], (instrs FLDENVm)>; 1566 1567def SKLWriteResGroup218 : SchedWriteRes<[SKLPort0,SKLPort6,SKLPort23,SKLPort05,SKLPort06,SKLPort15,SKLPort0156]> { 1568 let Latency = 63; 1569 let NumMicroOps = 88; 1570 let ReleaseAtCycles = [4,4,31,1,2,1,45]; 1571} 1572def: InstRW<[SKLWriteResGroup218], (instrs FXRSTOR64)>; 1573 1574def SKLWriteResGroup219 : SchedWriteRes<[SKLPort0,SKLPort6,SKLPort23,SKLPort05,SKLPort06,SKLPort15,SKLPort0156]> { 1575 let Latency = 63; 1576 let NumMicroOps = 90; 1577 let ReleaseAtCycles = [4,2,33,1,2,1,47]; 1578} 1579def: InstRW<[SKLWriteResGroup219], (instrs FXRSTOR)>; 1580 1581def SKLWriteResGroup220 : SchedWriteRes<[SKLPort5,SKLPort05,SKLPort0156]> { 1582 let Latency = 75; 1583 let NumMicroOps = 15; 1584 let ReleaseAtCycles = [6,3,6]; 1585} 1586def: InstRW<[SKLWriteResGroup220], (instrs FNINIT)>; 1587 1588def SKLWriteResGroup223 : SchedWriteRes<[SKLPort0,SKLPort1,SKLPort4,SKLPort5,SKLPort6,SKLPort237,SKLPort06,SKLPort0156]> { 1589 let Latency = 106; 1590 let NumMicroOps = 100; 1591 let ReleaseAtCycles = [9,1,11,16,1,11,21,30]; 1592} 1593def: InstRW<[SKLWriteResGroup223], (instrs FSTENVm)>; 1594 1595def: InstRW<[WriteZero], (instrs CLC)>; 1596 1597 1598// Instruction variants handled by the renamer. These might not need execution 1599// ports in certain conditions. 1600// See Agner's Fog "The microarchitecture of Intel, AMD and VIA CPUs", 1601// section "Skylake Pipeline" > "Register allocation and renaming". 1602// These can be investigated with llvm-exegesis, e.g. 1603// echo 'pxor %mm0, %mm0' | /tmp/llvm-exegesis -mode=uops -snippets-file=- 1604// echo 'vxorpd %xmm0, %xmm0, %xmm1' | /tmp/llvm-exegesis -mode=uops -snippets-file=- 1605 1606def SKLWriteZeroLatency : SchedWriteRes<[]> { 1607 let Latency = 0; 1608} 1609 1610def SKLWriteZeroIdiom : SchedWriteVariant<[ 1611 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>, 1612 SchedVar<NoSchedPred, [WriteALU]> 1613]>; 1614def : InstRW<[SKLWriteZeroIdiom], (instrs SUB32rr, SUB64rr, 1615 XOR32rr, XOR64rr)>; 1616 1617def SKLWriteFZeroIdiom : SchedWriteVariant<[ 1618 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>, 1619 SchedVar<NoSchedPred, [WriteFLogic]> 1620]>; 1621def : InstRW<[SKLWriteFZeroIdiom], (instrs XORPSrr, VXORPSrr, XORPDrr, 1622 VXORPDrr)>; 1623 1624def SKLWriteFZeroIdiomY : SchedWriteVariant<[ 1625 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>, 1626 SchedVar<NoSchedPred, [WriteFLogicY]> 1627]>; 1628def : InstRW<[SKLWriteFZeroIdiomY], (instrs VXORPSYrr, VXORPDYrr)>; 1629 1630def SKLWriteVZeroIdiomLogicX : SchedWriteVariant<[ 1631 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>, 1632 SchedVar<NoSchedPred, [WriteVecLogicX]> 1633]>; 1634def : InstRW<[SKLWriteVZeroIdiomLogicX], (instrs PXORrr, VPXORrr)>; 1635 1636def SKLWriteVZeroIdiomLogicY : SchedWriteVariant<[ 1637 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>, 1638 SchedVar<NoSchedPred, [WriteVecLogicY]> 1639]>; 1640def : InstRW<[SKLWriteVZeroIdiomLogicY], (instrs VPXORYrr)>; 1641 1642def SKLWriteVZeroIdiomALUX : SchedWriteVariant<[ 1643 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>, 1644 SchedVar<NoSchedPred, [WriteVecALUX]> 1645]>; 1646def : InstRW<[SKLWriteVZeroIdiomALUX], (instrs PCMPGTBrr, VPCMPGTBrr, 1647 PCMPGTDrr, VPCMPGTDrr, 1648 PCMPGTWrr, VPCMPGTWrr)>; 1649 1650def SKLWriteVZeroIdiomALUY : SchedWriteVariant<[ 1651 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>, 1652 SchedVar<NoSchedPred, [WriteVecALUY]> 1653]>; 1654def : InstRW<[SKLWriteVZeroIdiomALUY], (instrs VPCMPGTBYrr, 1655 VPCMPGTDYrr, 1656 VPCMPGTWYrr)>; 1657 1658def SKLWritePSUB : SchedWriteRes<[SKLPort015]> { 1659 let Latency = 1; 1660 let NumMicroOps = 1; 1661 let ReleaseAtCycles = [1]; 1662} 1663 1664def SKLWriteVZeroIdiomPSUB : SchedWriteVariant<[ 1665 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>, 1666 SchedVar<NoSchedPred, [SKLWritePSUB]> 1667]>; 1668def : InstRW<[SKLWriteVZeroIdiomPSUB], (instrs PSUBBrr, VPSUBBrr, 1669 PSUBDrr, VPSUBDrr, 1670 PSUBQrr, VPSUBQrr, 1671 PSUBWrr, VPSUBWrr, 1672 VPSUBBYrr, 1673 VPSUBDYrr, 1674 VPSUBQYrr, 1675 VPSUBWYrr)>; 1676 1677def SKLWritePCMPGTQ : SchedWriteRes<[SKLPort5]> { 1678 let Latency = 3; 1679 let NumMicroOps = 1; 1680 let ReleaseAtCycles = [1]; 1681} 1682 1683def SKLWriteVZeroIdiomPCMPGTQ : SchedWriteVariant<[ 1684 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SKLWriteZeroLatency]>, 1685 SchedVar<NoSchedPred, [SKLWritePCMPGTQ]> 1686]>; 1687def : InstRW<[SKLWriteVZeroIdiomPCMPGTQ], (instrs PCMPGTQrr, VPCMPGTQrr, 1688 VPCMPGTQYrr)>; 1689 1690 1691// CMOVs that use both Z and C flag require an extra uop. 1692def SKLWriteCMOVA_CMOVBErr : SchedWriteRes<[SKLPort06]> { 1693 let Latency = 2; 1694 let ReleaseAtCycles = [2]; 1695 let NumMicroOps = 2; 1696} 1697 1698def SKLWriteCMOVA_CMOVBErm : SchedWriteRes<[SKLPort23,SKLPort06]> { 1699 let Latency = 7; 1700 let ReleaseAtCycles = [1,2]; 1701 let NumMicroOps = 3; 1702} 1703 1704def SKLCMOVA_CMOVBErr : SchedWriteVariant<[ 1705 SchedVar<MCSchedPredicate<IsCMOVArr_Or_CMOVBErr>, [SKLWriteCMOVA_CMOVBErr]>, 1706 SchedVar<NoSchedPred, [WriteCMOV]> 1707]>; 1708 1709def SKLCMOVA_CMOVBErm : SchedWriteVariant<[ 1710 SchedVar<MCSchedPredicate<IsCMOVArm_Or_CMOVBErm>, [SKLWriteCMOVA_CMOVBErm]>, 1711 SchedVar<NoSchedPred, [WriteCMOV.Folded]> 1712]>; 1713 1714def : InstRW<[SKLCMOVA_CMOVBErr], (instrs CMOV16rr, CMOV32rr, CMOV64rr)>; 1715def : InstRW<[SKLCMOVA_CMOVBErm], (instrs CMOV16rm, CMOV32rm, CMOV64rm)>; 1716 1717// SETCCs that use both Z and C flag require an extra uop. 1718def SKLWriteSETA_SETBEr : SchedWriteRes<[SKLPort06]> { 1719 let Latency = 2; 1720 let ReleaseAtCycles = [2]; 1721 let NumMicroOps = 2; 1722} 1723 1724def SKLWriteSETA_SETBEm : SchedWriteRes<[SKLPort4,SKLPort237,SKLPort06]> { 1725 let Latency = 3; 1726 let ReleaseAtCycles = [1,1,2]; 1727 let NumMicroOps = 4; 1728} 1729 1730def SKLSETA_SETBErr : SchedWriteVariant<[ 1731 SchedVar<MCSchedPredicate<IsSETAr_Or_SETBEr>, [SKLWriteSETA_SETBEr]>, 1732 SchedVar<NoSchedPred, [WriteSETCC]> 1733]>; 1734 1735def SKLSETA_SETBErm : SchedWriteVariant<[ 1736 SchedVar<MCSchedPredicate<IsSETAm_Or_SETBEm>, [SKLWriteSETA_SETBEm]>, 1737 SchedVar<NoSchedPred, [WriteSETCCStore]> 1738]>; 1739 1740def : InstRW<[SKLSETA_SETBErr], (instrs SETCCr)>; 1741def : InstRW<[SKLSETA_SETBErm], (instrs SETCCm)>; 1742 1743/////////////////////////////////////////////////////////////////////////////// 1744// Dependency breaking instructions. 1745/////////////////////////////////////////////////////////////////////////////// 1746 1747def : IsZeroIdiomFunction<[ 1748 // GPR Zero-idioms. 1749 DepBreakingClass<[ SUB32rr, SUB64rr, XOR32rr, XOR64rr ], ZeroIdiomPredicate>, 1750 1751 // SSE Zero-idioms. 1752 DepBreakingClass<[ 1753 // fp variants. 1754 XORPSrr, XORPDrr, 1755 1756 // int variants. 1757 PXORrr, 1758 PSUBBrr, PSUBWrr, PSUBDrr, PSUBQrr, 1759 PCMPGTBrr, PCMPGTDrr, PCMPGTQrr, PCMPGTWrr 1760 ], ZeroIdiomPredicate>, 1761 1762 // AVX Zero-idioms. 1763 DepBreakingClass<[ 1764 // xmm fp variants. 1765 VXORPSrr, VXORPDrr, 1766 1767 // xmm int variants. 1768 VPXORrr, 1769 VPSUBBrr, VPSUBWrr, VPSUBDrr, VPSUBQrr, 1770 VPCMPGTBrr, VPCMPGTWrr, VPCMPGTDrr, VPCMPGTQrr, 1771 1772 // ymm variants. 1773 VXORPSYrr, VXORPDYrr, VPXORYrr, 1774 VPSUBBYrr, VPSUBWYrr, VPSUBDYrr, VPSUBQYrr, 1775 VPCMPGTBYrr, VPCMPGTWYrr, VPCMPGTDYrr, VPCMPGTQYrr 1776 ], ZeroIdiomPredicate>, 1777]>; 1778 1779} // SchedModel 1780