xref: /freebsd/contrib/llvm-project/llvm/lib/Target/X86/X86SchedSapphireRapids.td (revision cb14a3fe5122c879eae1fb480ed7ce82a699ddb6) 
1//=- X86SchedSapphireRapids.td - X86 SapphireRapids Scheduling *- tablegen -*=//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the machine model for SapphireRapids to support instruction
10// scheduling and other instruction cost heuristics.
11//
12//===----------------------------------------------------------------------===//
13
14def SapphireRapidsModel : SchedMachineModel {
15  // SapphireRapids can allocate 6 uops per cycle.
16  let IssueWidth = 6; // Based on allocator width.
17  let MicroOpBufferSize = 512; // Based on the reorder buffer.
18  let LoadLatency = 5;
19  let MispredictPenalty = 14;
20
21  // Latency for microcoded instructions or instructions without latency info.
22  int MaxLatency = 100;
23
24  // Based on the LSD (loop-stream detector) queue size (ST).
25  let LoopMicroOpBufferSize = 72;
26
27  // This flag is set to allow the scheduler to assign a default model to
28  // unrecognized opcodes.
29  let CompleteModel = 0;
30}
31
32let SchedModel = SapphireRapidsModel in {
33
34// SapphireRapids can issue micro-ops to 12 different ports in one cycle.
35def SPRPort00 : ProcResource<1>;
36def SPRPort01 : ProcResource<1>;
37def SPRPort02 : ProcResource<1>;
38def SPRPort03 : ProcResource<1>;
39def SPRPort04 : ProcResource<1>;
40def SPRPort05 : ProcResource<1>;
41def SPRPort06 : ProcResource<1>;
42def SPRPort07 : ProcResource<1>;
43def SPRPort08 : ProcResource<1>;
44def SPRPort09 : ProcResource<1>;
45def SPRPort10 : ProcResource<1>;
46def SPRPort11 : ProcResource<1>;
47
48// Workaround to represent invalid ports. WriteRes shouldn't use this resource.
49def SPRPortInvalid :ProcResource<1>;
50
51// Many micro-ops are capable of issuing on multiple ports.
52def SPRPort00_01          : ProcResGroup<[SPRPort00, SPRPort01]>;
53def SPRPort00_01_05       : ProcResGroup<[SPRPort00, SPRPort01, SPRPort05]>;
54def SPRPort00_01_05_06    : ProcResGroup<[SPRPort00, SPRPort01, SPRPort05, SPRPort06]>;
55def SPRPort00_05          : ProcResGroup<[SPRPort00, SPRPort05]>;
56def SPRPort00_05_06       : ProcResGroup<[SPRPort00, SPRPort05, SPRPort06]>;
57def SPRPort00_06          : ProcResGroup<[SPRPort00, SPRPort06]>;
58def SPRPort01_05          : ProcResGroup<[SPRPort01, SPRPort05]>;
59def SPRPort01_05_10       : ProcResGroup<[SPRPort01, SPRPort05, SPRPort10]>;
60def SPRPort02_03          : ProcResGroup<[SPRPort02, SPRPort03]>;
61def SPRPort02_03_11       : ProcResGroup<[SPRPort02, SPRPort03, SPRPort11]>;
62def SPRPort07_08          : ProcResGroup<[SPRPort07, SPRPort08]>;
63
64// EU has 112 reservation stations.
65def SPRPort00_01_05_06_10 : ProcResGroup<[SPRPort00, SPRPort01, SPRPort05,
66                                          SPRPort06, SPRPort10]> {
67  let BufferSize = 112;
68}
69
70// STD has 48 reservation stations.
71def SPRPort04_09          : ProcResGroup<[SPRPort04, SPRPort09]> {
72  let BufferSize = 48;
73}
74
75// MEM has 72 reservation stations.
76def SPRPort02_03_07_08_11 : ProcResGroup<[SPRPort02, SPRPort03, SPRPort07,
77                                          SPRPort08, SPRPort11]> {
78  let BufferSize = 72;
79}
80
81// Integer loads are 5 cycles, so ReadAfterLd registers needn't be available
82// until 5 cycles after the memory operand.
83def : ReadAdvance<ReadAfterLd, 5>;
84
85// Vector loads are 6 cycles, so ReadAfterVec*Ld registers needn't be available
86// until 6 cycles after the memory operand.
87def : ReadAdvance<ReadAfterVecLd, 6>;
88def : ReadAdvance<ReadAfterVecXLd, 6>;
89def : ReadAdvance<ReadAfterVecYLd, 6>;
90
91def : ReadAdvance<ReadInt2Fpu, 0>;
92
93// Many SchedWrites are defined in pairs with and without a folded load.
94// Instructions with folded loads are usually micro-fused, so they only appear
95// as two micro-ops when queued in the reservation station.
96// This multiclass defines the resource usage for variants with and without
97// folded loads.
98multiclass SPRWriteResPair<X86FoldableSchedWrite SchedRW,
99                           list<ProcResourceKind> ExePorts,
100                           int Lat, list<int> Res = [1], int UOps = 1,
101                           int LoadLat = 5, int LoadUOps = 1> {
102  // Register variant is using a single cycle on ExePort.
103  def : WriteRes<SchedRW, ExePorts> {
104    let Latency = Lat;
105    let ReleaseAtCycles = Res;
106    let NumMicroOps = UOps;
107  }
108
109  // Memory variant also uses a cycle on port 2/3/11 and adds LoadLat cycles to
110  // the latency (default = 5).
111  def : WriteRes<SchedRW.Folded, !listconcat([SPRPort02_03_11], ExePorts)> {
112    let Latency = !add(Lat, LoadLat);
113    let ReleaseAtCycles = !listconcat([1], Res);
114    let NumMicroOps = !add(UOps, LoadUOps);
115  }
116}
117
118//===----------------------------------------------------------------------===//
119// The following definitons are infered by smg.
120//===----------------------------------------------------------------------===//
121
122// Infered SchedWrite definition.
123def : WriteRes<WriteADC, [SPRPort00_06]>;
124defm : X86WriteRes<WriteADCLd, [SPRPort00_01_05_06_10, SPRPort00_06], 11, [1, 1], 2>;
125defm : SPRWriteResPair<WriteAESDecEnc, [SPRPort00_01], 5, [1], 1, 7>;
126defm : SPRWriteResPair<WriteAESIMC, [SPRPort00_01], 8, [2], 2, 7>;
127defm : X86WriteRes<WriteAESKeyGen, [SPRPort00, SPRPort00_01, SPRPort00_01_05, SPRPort00_06, SPRPort01_05, SPRPort05], 7, [4, 1, 1, 2, 3, 3], 14>;
128defm : X86WriteRes<WriteAESKeyGenLd, [SPRPort00, SPRPort00_01, SPRPort00_06, SPRPort01_05, SPRPort02_03_11, SPRPort05], 12, [4, 1, 2, 3, 1, 3], 14>;
129def : WriteRes<WriteALU, [SPRPort00_01_05_06_10]>;
130def : WriteRes<WriteALULd, [SPRPort00_01_05_06_10]> {
131  let Latency = 11;
132}
133defm : SPRWriteResPair<WriteBEXTR, [SPRPort00_06, SPRPort01], 6, [1, 1], 2>;
134defm : SPRWriteResPair<WriteBLS, [SPRPort01_05_10], 2, [1]>;
135defm : SPRWriteResPair<WriteBSF, [SPRPort01], 3, [1]>;
136defm : SPRWriteResPair<WriteBSR, [SPRPort01], 3, [1]>;
137def : WriteRes<WriteBSWAP32, [SPRPort01]>;
138defm : X86WriteRes<WriteBSWAP64, [SPRPort00_06, SPRPort01], 2, [1, 1], 2>;
139defm : SPRWriteResPair<WriteBZHI, [SPRPort01], 3, [1]>;
140def : WriteRes<WriteBitTest, [SPRPort01]>;
141defm : X86WriteRes<WriteBitTestImmLd, [SPRPort01, SPRPort02_03_11], 6, [1, 1], 2>;
142defm : X86WriteRes<WriteBitTestRegLd, [SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort01_05_10, SPRPort02_03_11], 11, [4, 2, 1, 2, 1], 10>;
143def : WriteRes<WriteBitTestSet, [SPRPort01]>;
144def : WriteRes<WriteBitTestSetImmLd, [SPRPort01]> {
145  let Latency = 11;
146}
147defm : X86WriteRes<WriteBitTestSetRegLd, [SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort01_05_10], 17, [3, 2, 1, 2], 8>;
148defm : SPRWriteResPair<WriteBlend, [SPRPort01_05], 1, [1], 1, 7>;
149defm : SPRWriteResPair<WriteBlendY, [SPRPort00_01_05], 1, [1], 1, 8>;
150defm : SPRWriteResPair<WriteCLMul, [SPRPort05], 3, [1], 1, 7>;
151defm : SPRWriteResPair<WriteCMOV, [SPRPort00_06], 1, [1], 1, 6>;
152defm : X86WriteRes<WriteCMPXCHG, [SPRPort00_01_05_06_10, SPRPort00_06], 3, [3, 2], 5>;
153defm : X86WriteRes<WriteCMPXCHGRMW, [SPRPort00_01_05_06_10, SPRPort00_06, SPRPort02_03_11, SPRPort04_09, SPRPort07_08], 12, [1, 2, 1, 1, 1], 6>;
154defm : SPRWriteResPair<WriteCRC32, [SPRPort01], 3, [1]>;
155defm : X86WriteRes<WriteCvtI2PD, [SPRPort00_01, SPRPort05], 5, [1, 1], 2>;
156defm : X86WriteRes<WriteCvtI2PDLd, [SPRPort00_01, SPRPort02_03_11], 11, [1, 1], 2>;
157defm : X86WriteRes<WriteCvtI2PDY, [SPRPort00_01, SPRPort05], 7, [1, 1], 2>;
158defm : X86WriteRes<WriteCvtI2PDYLd, [SPRPort00_01, SPRPort02_03_11], 12, [1, 1], 2>;
159defm : SPRWriteResPair<WriteCvtI2PDZ, [SPRPort00], 4, [1], 1, 8>;
160defm : SPRWriteResPair<WriteCvtI2PS, [SPRPort00_01], 4, [1], 1, 7>;
161defm : SPRWriteResPair<WriteCvtI2PSY, [SPRPort00_01], 4, [1], 1, 8>;
162defm : SPRWriteResPair<WriteCvtI2PSZ, [SPRPort00], 4, [1], 1, 8>;
163defm : X86WriteRes<WriteCvtI2SD, [SPRPort00_01, SPRPort05], 7, [1, 1], 2>;
164defm : X86WriteRes<WriteCvtI2SDLd, [SPRPort00_01, SPRPort02_03_11], 11, [1, 1], 2>;
165defm : X86WriteRes<WriteCvtI2SS, [SPRPort00_01, SPRPort00_01_05, SPRPort05], 9, [1, 1, 1], 3>;
166defm : X86WriteRes<WriteCvtI2SSLd, [SPRPort00_01, SPRPort02_03_11], 11, [1, 1], 2>;
167defm : X86WriteRes<WriteCvtPD2I, [SPRPort00_01, SPRPort05], 5, [1, 1], 2>;
168defm : X86WriteRes<WriteCvtPD2ILd, [SPRPort00_01, SPRPort02_03_11], 12, [1, 1], 2>;
169defm : X86WriteRes<WriteCvtPD2IY, [SPRPort00_01, SPRPort05], 7, [1, 1], 2>;
170defm : X86WriteRes<WriteCvtPD2IYLd, [SPRPort00_01, SPRPort02_03_11], 12, [1, 1], 2>;
171defm : X86WriteRes<WriteCvtPD2IZ, [SPRPort00, SPRPort05], 7, [1, 1], 2>;
172defm : X86WriteRes<WriteCvtPD2IZLd, [SPRPort00, SPRPort02_03_11], 12, [1, 1], 2>;
173defm : SPRWriteResPair<WriteCvtPD2PS, [SPRPort00_01, SPRPort05], 5, [1, 1], 2, 7>;
174defm : SPRWriteResPair<WriteCvtPD2PSY, [SPRPort00_01, SPRPort05], 7, [1, 1], 2, 8>;
175defm : SPRWriteResPair<WriteCvtPD2PSZ, [SPRPort00, SPRPort05], 7, [1, 1], 2, 8>;
176defm : X86WriteRes<WriteCvtPH2PS, [SPRPort00_01, SPRPort05], 6, [1, 1], 2>;
177defm : X86WriteRes<WriteCvtPH2PSLd, [SPRPort00_01, SPRPort02_03_11], 12, [1, 1], 2>;
178defm : X86WriteRes<WriteCvtPH2PSY, [SPRPort00_01, SPRPort05], 8, [1, 1], 2>;
179defm : X86WriteRes<WriteCvtPH2PSYLd, [SPRPort00_01, SPRPort02_03_11], 12, [1, 1], 2>;
180defm : SPRWriteResPair<WriteCvtPH2PSZ, [SPRPort00, SPRPort05], 11, [1, 1], 2>;
181defm : SPRWriteResPair<WriteCvtPS2I, [SPRPort00_01], 4, [1], 1, 7>;
182defm : SPRWriteResPair<WriteCvtPS2IY, [SPRPort00_01], 4, [1], 1, 8>;
183defm : X86WriteRes<WriteCvtPS2IZ, [SPRPort00, SPRPort00_05, SPRPort05], 10, [1, 2, 1], 4>;
184defm : X86WriteRes<WriteCvtPS2IZLd, [SPRPort00, SPRPort00_05, SPRPort00_06, SPRPort02_03_11, SPRPort05], 18, [1, 2, 1, 1, 1], 6>;
185defm : X86WriteRes<WriteCvtPS2PD, [SPRPort00_01, SPRPort05], 5, [1, 1], 2>;
186defm : X86WriteRes<WriteCvtPS2PDLd, [SPRPort00_01, SPRPort02_03_11], 11, [1, 1], 2>;
187defm : X86WriteRes<WriteCvtPS2PDY, [SPRPort00_01, SPRPort05], 7, [1, 1], 2>;
188defm : X86WriteRes<WriteCvtPS2PDYLd, [SPRPort00_01, SPRPort02_03_11], 12, [1, 1], 2>;
189defm : SPRWriteResPair<WriteCvtPS2PDZ, [SPRPort00, SPRPort05], 7, [1, 1], 2, 6>;
190defm : X86WriteRes<WriteCvtPS2PH, [SPRPort00_01, SPRPort05], 6, [1, 1], 2>;
191defm : X86WriteRes<WriteCvtPS2PHSt, [SPRPort00_01, SPRPort04_09, SPRPort07_08], 12, [1, 1, 1], 3>;
192defm : X86WriteRes<WriteCvtPS2PHY, [SPRPort00_01, SPRPort05], 8, [1, 1], 2>;
193defm : X86WriteRes<WriteCvtPS2PHYSt, [SPRPort00_01, SPRPort04_09, SPRPort07_08], 12, [1, 1, 1], 3>;
194defm : X86WriteRes<WriteCvtPS2PHZ, [SPRPort00, SPRPort05], 11, [1, 1], 2>;
195defm : X86WriteRes<WriteCvtPS2PHZSt, [SPRPort00, SPRPort04_09, SPRPort07_08], 12, [1, 1, 1], 3>;
196defm : SPRWriteResPair<WriteCvtSD2I, [SPRPort00, SPRPort00_01], 7, [1, 1], 2>;
197defm : SPRWriteResPair<WriteCvtSD2SS, [SPRPort00_01, SPRPort05], 5, [1, 1], 2, 7>;
198defm : SPRWriteResPair<WriteCvtSS2I, [SPRPort00, SPRPort00_01], 7, [1, 1], 2>;
199defm : X86WriteRes<WriteCvtSS2SD, [SPRPort00_01, SPRPort05], 5, [1, 1], 2>;
200defm : X86WriteRes<WriteCvtSS2SDLd, [SPRPort00_01, SPRPort02_03_11], 11, [1, 1], 2>;
201defm : SPRWriteResPair<WriteDPPD, [SPRPort00_01, SPRPort01_05], 9, [2, 1], 3, 7>;
202defm : SPRWriteResPair<WriteDPPS, [SPRPort00_01, SPRPort00_06, SPRPort01_05, SPRPort05], 14, [2, 1, 2, 1], 6, 7>;
203defm : SPRWriteResPair<WriteDPPSY, [SPRPort00_01, SPRPort00_06, SPRPort01_05, SPRPort05], 14, [2, 1, 2, 1], 6, 8>;
204defm : SPRWriteResPair<WriteDiv16, [SPRPort00_01_05_06_10, SPRPort01], 16, [1, 3], 4, 4>;
205defm : SPRWriteResPair<WriteDiv32, [SPRPort00_01_05_06_10, SPRPort01], 15, [1, 3], 4, 4>;
206defm : SPRWriteResPair<WriteDiv64, [SPRPort01], 18, [3], 3>;
207defm : X86WriteRes<WriteDiv8, [SPRPort01], 17, [3], 3>;
208defm : X86WriteRes<WriteDiv8Ld, [SPRPort01], 22, [3], 3>;
209defm : X86WriteRes<WriteEMMS, [SPRPort00, SPRPort00_05, SPRPort00_06], 10, [1, 8, 1], 10>;
210defm : SPRWriteResPair<WriteFAdd, [SPRPort01_05], 3, [1], 1, 7>;
211defm : SPRWriteResPair<WriteFAdd64, [SPRPort01_05], 3, [1], 1, 7>;
212defm : SPRWriteResPair<WriteFAdd64X, [SPRPort01_05], 3, [1], 1, 7>;
213defm : SPRWriteResPair<WriteFAdd64Y, [SPRPort01_05], 3, [1], 1, 8>;
214defm : SPRWriteResPair<WriteFAdd64Z, [SPRPort00_05], 4, [1], 1, 7>;
215defm : SPRWriteResPair<WriteFAddX, [SPRPort00_01], 4, [1], 1, 7>;
216defm : SPRWriteResPair<WriteFAddY, [SPRPort00_01], 4, [1], 1, 8>;
217defm : SPRWriteResPair<WriteFAddZ, [SPRPort00], 4, [1], 1, 8>;
218defm : SPRWriteResPair<WriteFBlend, [SPRPort00_01_05], 1, [1], 1, 7>;
219defm : SPRWriteResPair<WriteFBlendY, [SPRPort00_01_05], 1, [1], 1, 8>;
220def : WriteRes<WriteFCMOV, [SPRPort01]> {
221  let Latency = 3;
222}
223defm : SPRWriteResPair<WriteFCmp, [SPRPort00_01], 4, [1], 1, 7>;
224defm : SPRWriteResPair<WriteFCmp64, [SPRPort00_01], 4, [1], 1, 7>;
225defm : SPRWriteResPair<WriteFCmp64X, [SPRPort00_01], 4, [1], 1, 7>;
226defm : SPRWriteResPair<WriteFCmp64Y, [SPRPort00_01], 4, [1], 1, 8>;
227defm : SPRWriteResPair<WriteFCmp64Z, [SPRPort00], 4, [1], 1, 8>;
228defm : SPRWriteResPair<WriteFCmpX, [SPRPort00_01], 4, [1], 1, 7>;
229defm : SPRWriteResPair<WriteFCmpY, [SPRPort00_01], 4, [1], 1, 8>;
230def : WriteRes<WriteFCmpZ, [SPRPort05]> {
231  let Latency = 3;
232}
233defm : X86WriteRes<WriteFCmpZLd, [SPRPort00, SPRPort02_03_11], 12, [1, 1], 2>;
234defm : SPRWriteResPair<WriteFCom, [SPRPort05], 1, [1], 1, 7>;
235defm : SPRWriteResPair<WriteFComX, [SPRPort00], 3, [1]>;
236defm : SPRWriteResPair<WriteFDiv, [SPRPort00], 11, [1], 1, 7>;
237defm : SPRWriteResPair<WriteFDiv64, [SPRPort00], 14, [1], 1, 6>;
238defm : SPRWriteResPair<WriteFDiv64X, [SPRPort00], 14, [1], 1, 6>;
239defm : SPRWriteResPair<WriteFDiv64Y, [SPRPort00], 14, [1], 1, 7>;
240defm : SPRWriteResPair<WriteFDiv64Z, [SPRPort00, SPRPort00_05], 23, [2, 1], 3, 7>;
241defm : SPRWriteResPair<WriteFDivX, [SPRPort00], 11, [1], 1, 7>;
242defm : SPRWriteResPair<WriteFDivY, [SPRPort00], 11, [1], 1, 8>;
243defm : SPRWriteResPair<WriteFDivZ, [SPRPort00, SPRPort00_05], 18, [2, 1], 3, 7>;
244defm : SPRWriteResPair<WriteFHAdd, [SPRPort01_05, SPRPort05], 6, [1, 2], 3, 6>;
245defm : SPRWriteResPair<WriteFHAddY, [SPRPort01_05, SPRPort05], 5, [1, 2], 3, 8>;
246def : WriteRes<WriteFLD0, [SPRPort00_05]>;
247defm : X86WriteRes<WriteFLD1, [SPRPort00_05], 1, [2], 2>;
248defm : X86WriteRes<WriteFLDC, [SPRPort00_05], 1, [2], 2>;
249def : WriteRes<WriteFLoad, [SPRPort02_03_11]> {
250  let Latency = 7;
251}
252def : WriteRes<WriteFLoadX, [SPRPort02_03_11]> {
253  let Latency = 7;
254}
255def : WriteRes<WriteFLoadY, [SPRPort02_03_11]> {
256  let Latency = 8;
257}
258defm : SPRWriteResPair<WriteFLogic, [SPRPort00_01_05], 1, [1], 1, 7>;
259defm : SPRWriteResPair<WriteFLogicY, [SPRPort00_01_05], 1, [1], 1, 8>;
260defm : SPRWriteResPair<WriteFLogicZ, [SPRPort00_05], 1, [1], 1, 8>;
261defm : SPRWriteResPair<WriteFMA, [SPRPort00_01], 4, [1], 1, 7>;
262defm : SPRWriteResPair<WriteFMAX, [SPRPort00_01], 4, [1], 1, 7>;
263defm : SPRWriteResPair<WriteFMAY, [SPRPort00_01], 4, [1], 1, 8>;
264defm : SPRWriteResPair<WriteFMAZ, [SPRPort00], 4, [1], 1, 8>;
265def : WriteRes<WriteFMOVMSK, [SPRPort00]> {
266  let Latency = 3;
267}
268defm : X86WriteRes<WriteFMaskedLoad, [SPRPort00_01_05, SPRPort02_03_11], 8, [1, 1], 2>;
269defm : X86WriteRes<WriteFMaskedLoadY, [SPRPort00_01_05, SPRPort02_03_11], 9, [1, 1], 2>;
270defm : X86WriteRes<WriteFMaskedStore32, [SPRPort00, SPRPort04_09, SPRPort07_08], 14, [1, 1, 1], 3>;
271defm : X86WriteRes<WriteFMaskedStore32Y, [SPRPort00, SPRPort04_09, SPRPort07_08], 14, [1, 1, 1], 3>;
272defm : X86WriteRes<WriteFMaskedStore64, [SPRPort00, SPRPort04_09, SPRPort07_08], 14, [1, 1, 1], 3>;
273defm : X86WriteRes<WriteFMaskedStore64Y, [SPRPort00, SPRPort04_09, SPRPort07_08], 14, [1, 1, 1], 3>;
274defm : X86WriteRes<WriteFMoveX, [], 1, [], 0>;
275defm : X86WriteRes<WriteFMoveY, [], 1, [], 0>;
276def : WriteRes<WriteFMoveZ, [SPRPort00_05]>;
277defm : SPRWriteResPair<WriteFMul, [SPRPort00_01], 4, [1], 1, 7>;
278defm : SPRWriteResPair<WriteFMul64, [SPRPort00_01], 4, [1], 1, 7>;
279defm : SPRWriteResPair<WriteFMul64X, [SPRPort00_01], 4, [1], 1, 7>;
280defm : SPRWriteResPair<WriteFMul64Y, [SPRPort00_01], 4, [1], 1, 8>;
281defm : SPRWriteResPair<WriteFMul64Z, [SPRPort00], 4, [1], 1, 8>;
282defm : SPRWriteResPair<WriteFMulX, [SPRPort00_01], 4, [1], 1, 7>;
283defm : SPRWriteResPair<WriteFMulY, [SPRPort00_01], 4, [1], 1, 8>;
284defm : SPRWriteResPair<WriteFMulZ, [SPRPort00], 4, [1], 1, 8>;
285defm : SPRWriteResPair<WriteFRcp, [SPRPort00], 4, [1], 1, 7>;
286defm : SPRWriteResPair<WriteFRcpX, [SPRPort00], 4, [1], 1, 7>;
287defm : SPRWriteResPair<WriteFRcpY, [SPRPort00], 4, [1], 1, 8>;
288defm : SPRWriteResPair<WriteFRcpZ, [SPRPort00, SPRPort00_05], 7, [2, 1], 3, 7>;
289defm : SPRWriteResPair<WriteFRnd, [SPRPort00_01], 4, [1], 1, 7>;
290defm : SPRWriteResPair<WriteFRndY, [SPRPort00_01], 4, [1], 1, 8>;
291defm : SPRWriteResPair<WriteFRndZ, [SPRPort00], 4, [1], 1, 8>;
292defm : SPRWriteResPair<WriteFRsqrt, [SPRPort00], 4, [1], 1, 7>;
293defm : SPRWriteResPair<WriteFRsqrtX, [SPRPort00], 4, [1], 1, 7>;
294defm : SPRWriteResPair<WriteFRsqrtY, [SPRPort00], 4, [1], 1, 8>;
295defm : SPRWriteResPair<WriteFRsqrtZ, [SPRPort00, SPRPort00_05], 9, [2, 1], 3>;
296defm : SPRWriteResPair<WriteFShuffle, [SPRPort05], 1, [1], 1, 7>;
297defm : SPRWriteResPair<WriteFShuffle256, [SPRPort05], 3, [1], 1, 8>;
298defm : SPRWriteResPair<WriteFShuffleY, [SPRPort05], 1, [1], 1, 8>;
299defm : SPRWriteResPair<WriteFShuffleZ, [SPRPort05], 1, [1], 1, 8>;
300def : WriteRes<WriteFSign, [SPRPort00]>;
301defm : SPRWriteResPair<WriteFSqrt, [SPRPort00], 12, [1], 1, 7>;
302defm : SPRWriteResPair<WriteFSqrt64, [SPRPort00], 18, [1]>;
303defm : SPRWriteResPair<WriteFSqrt64X, [SPRPort00], 18, [1], 1, 6>;
304defm : SPRWriteResPair<WriteFSqrt64Y, [SPRPort00], 18, [1], 1, 3>;
305// Warning: negtive load latency.
306defm : SPRWriteResPair<WriteFSqrt64Z, [SPRPort00, SPRPort00_05], 32, [2, 1], 3, -1>;
307def : WriteRes<WriteFSqrt80, [SPRPortInvalid, SPRPort00]> {
308  let ReleaseAtCycles = [7, 1];
309  let Latency = 21;
310}
311defm : SPRWriteResPair<WriteFSqrtX, [SPRPort00], 12, [1], 1, 7>;
312defm : SPRWriteResPair<WriteFSqrtY, [SPRPort00], 12, [1], 1, 8>;
313defm : SPRWriteResPair<WriteFSqrtZ, [SPRPort00, SPRPort00_05], 20, [2, 1], 3, 7>;
314defm : X86WriteRes<WriteFStore, [SPRPort04_09, SPRPort07_08], 12, [1, 1], 2>;
315defm : X86WriteResUnsupported<WriteFStoreNT>;
316defm : X86WriteRes<WriteFStoreNTX, [SPRPort04_09, SPRPort07_08], 518, [1, 1], 2>;
317defm : X86WriteRes<WriteFStoreNTY, [SPRPort04_09, SPRPort07_08], 542, [1, 1], 2>;
318defm : X86WriteRes<WriteFStoreX, [SPRPort04_09, SPRPort07_08], 12, [1, 1], 2>;
319defm : X86WriteRes<WriteFStoreY, [SPRPort04_09, SPRPort07_08], 12, [1, 1], 2>;
320defm : SPRWriteResPair<WriteFTest, [SPRPort00], 3, [1]>;
321defm : SPRWriteResPair<WriteFTestY, [SPRPort00], 5, [1], 1, 6>;
322defm : SPRWriteResPair<WriteFVarBlend, [SPRPort00_01_05], 1, [1], 1, 7>;
323defm : SPRWriteResPair<WriteFVarBlendY, [SPRPort00_01_05], 1, [1], 1, 8>;
324defm : SPRWriteResPair<WriteFVarBlendZ, [SPRPort00_05], 1, [1], 1, 8>;
325defm : SPRWriteResPair<WriteFVarShuffle, [SPRPort05], 1, [1], 1, 7>;
326defm : SPRWriteResPair<WriteFVarShuffle256, [SPRPort05], 3, [1], 1, 8>;
327defm : SPRWriteResPair<WriteFVarShuffleY, [SPRPort05], 1, [1], 1, 8>;
328defm : SPRWriteResPair<WriteFVarShuffleZ, [SPRPort05], 1, [1], 1, 8>;
329def : WriteRes<WriteFence, [SPRPort00_06]> {
330  let Latency = 2;
331}
332defm : SPRWriteResPair<WriteIDiv16, [SPRPort00_01_05_06_10, SPRPort01], 16, [1, 3], 4, 4>;
333defm : SPRWriteResPair<WriteIDiv32, [SPRPort00_01_05_06_10, SPRPort01], 15, [1, 3], 4, 4>;
334defm : SPRWriteResPair<WriteIDiv64, [SPRPort01], 18, [3], 3>;
335defm : X86WriteRes<WriteIDiv8, [SPRPort01], 17, [3], 3>;
336defm : X86WriteRes<WriteIDiv8Ld, [SPRPort01], 22, [3], 3>;
337defm : SPRWriteResPair<WriteIMul16, [SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01], 5, [2, 1, 1], 4>;
338defm : SPRWriteResPair<WriteIMul16Imm, [SPRPort00_01_05_06_10, SPRPort01], 4, [1, 1], 2>;
339defm : SPRWriteResPair<WriteIMul16Reg, [SPRPort01], 3, [1]>;
340defm : SPRWriteResPair<WriteIMul32, [SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01], 4, [1, 1, 1], 3>;
341defm : SPRWriteResPair<WriteIMul32Imm, [SPRPort01], 3, [1]>;
342defm : SPRWriteResPair<WriteIMul32Reg, [SPRPort01], 3, [1]>;
343defm : SPRWriteResPair<WriteIMul64, [SPRPort01, SPRPort05], 4, [1, 1], 2>;
344defm : SPRWriteResPair<WriteIMul64Imm, [SPRPort01], 3, [1]>;
345defm : SPRWriteResPair<WriteIMul64Reg, [SPRPort01], 3, [1]>;
346defm : SPRWriteResPair<WriteIMul8, [SPRPort01], 3, [1]>;
347def : WriteRes<WriteIMulH, []> {
348  let Latency = 3;
349}
350def : WriteRes<WriteIMulHLd, []> {
351  let Latency = 3;
352}
353defm : SPRWriteResPair<WriteJump, [SPRPort00_06], 1, [1]>;
354def : WriteRes<WriteLAHFSAHF, [SPRPort00_06]> {
355  let Latency = 3;
356}
357defm : X86WriteRes<WriteLDMXCSR, [SPRPort00, SPRPort00_01_05, SPRPort00_06, SPRPort02_03_11], 7, [1, 1, 1, 1], 4>;
358def : WriteRes<WriteLEA, [SPRPort01]>;
359defm : SPRWriteResPair<WriteLZCNT, [SPRPort01], 3, [1]>;
360def : WriteRes<WriteLoad, [SPRPort02_03_11]> {
361  let Latency = 5;
362}
363def : WriteRes<WriteMMXMOVMSK, [SPRPort00]> {
364  let Latency = 3;
365}
366defm : SPRWriteResPair<WriteMPSAD, [SPRPort01_05, SPRPort05], 4, [1, 1], 2, 7>;
367defm : SPRWriteResPair<WriteMPSADY, [SPRPort01_05, SPRPort05], 4, [1, 1], 2, 8>;
368defm : SPRWriteResPair<WriteMULX32, [SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01], 4, [1, 1, 1], 2>;
369defm : SPRWriteResPair<WriteMULX64, [SPRPort01, SPRPort05], 4, [1, 1]>;
370def : WriteRes<WriteMicrocoded, [SPRPort00_01_05_06]> {
371  let Latency = SapphireRapidsModel.MaxLatency;
372}
373def : WriteRes<WriteMove, [SPRPort00]> {
374  let Latency = 3;
375}
376defm : X86WriteRes<WriteNop, [], 1, [], 0>;
377defm : X86WriteRes<WritePCmpEStrI, [SPRPort00, SPRPort00_01_05, SPRPort00_06, SPRPort01, SPRPort05], 16, [3, 2, 1, 1, 1], 8>;
378defm : X86WriteRes<WritePCmpEStrILd, [SPRPort00, SPRPort00_01_05, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort05], 31, [3, 1, 1, 1, 1, 1], 8>;
379defm : X86WriteRes<WritePCmpEStrM, [SPRPort00, SPRPort00_01_05, SPRPort00_06, SPRPort01, SPRPort05], 16, [3, 3, 1, 1, 1], 9>;
380defm : X86WriteRes<WritePCmpEStrMLd, [SPRPort00, SPRPort00_01_05, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort05], 17, [3, 2, 1, 1, 1, 1], 9>;
381defm : SPRWriteResPair<WritePCmpIStrI, [SPRPort00], 11, [3], 3, 20>;
382defm : SPRWriteResPair<WritePCmpIStrM, [SPRPort00], 11, [3], 3>;
383defm : SPRWriteResPair<WritePHAdd, [SPRPort00_05, SPRPort05], 3, [1, 2], 3, 8>;
384defm : SPRWriteResPair<WritePHAddX, [SPRPort00_01_05, SPRPort01_05], 2, [1, 2], 3, 7>;
385defm : SPRWriteResPair<WritePHAddY, [SPRPort00_01_05, SPRPort01_05], 2, [1, 2], 3, 8>;
386defm : SPRWriteResPair<WritePHMINPOS, [SPRPort00], 4, [1], 1, 7>;
387defm : SPRWriteResPair<WritePMULLD, [SPRPort00_01], 10, [2], 2, 8>;
388defm : SPRWriteResPair<WritePMULLDY, [SPRPort00_01], 10, [2], 2, 8>;
389defm : SPRWriteResPair<WritePMULLDZ, [SPRPort00], 10, [2], 2, 8>;
390defm : SPRWriteResPair<WritePOPCNT, [SPRPort01], 3, [1]>;
391defm : SPRWriteResPair<WritePSADBW, [SPRPort05], 3, [1], 1, 8>;
392defm : SPRWriteResPair<WritePSADBWX, [SPRPort05], 3, [1], 1, 7>;
393defm : SPRWriteResPair<WritePSADBWY, [SPRPort05], 3, [1], 1, 8>;
394defm : SPRWriteResPair<WritePSADBWZ, [SPRPort05], 3, [1], 1, 8>;
395defm : X86WriteRes<WriteRMW, [SPRPort02_03_11, SPRPort04_09, SPRPort07_08], 1, [1, 1, 1], 3>;
396defm : X86WriteRes<WriteRotate, [SPRPort00_01_05_06_10, SPRPort00_06], 2, [1, 2], 3>;
397defm : X86WriteRes<WriteRotateLd, [SPRPort00_01_05_06_10, SPRPort00_06], 12, [1, 2], 3>;
398defm : X86WriteRes<WriteRotateCL, [SPRPort00_06], 2, [2], 2>;
399defm : X86WriteRes<WriteRotateCLLd, [SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01], 19, [2, 3, 2], 7>;
400defm : X86WriteRes<WriteSETCC, [SPRPort00_06], 2, [2], 2>;
401defm : X86WriteRes<WriteSETCCStore, [SPRPort00_06, SPRPort04_09, SPRPort07_08], 13, [2, 1, 1], 4>;
402defm : X86WriteRes<WriteSHDmrcl, [SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort04_09, SPRPort07_08], 12, [1, 1, 1, 1, 1, 1], 6>;
403defm : X86WriteRes<WriteSHDmri, [SPRPort00_01_05_06_10, SPRPort01, SPRPort02_03_11, SPRPort04_09, SPRPort07_08], 12, [1, 1, 1, 1, 1], 5>;
404defm : X86WriteRes<WriteSHDrrcl, [SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01], 5, [1, 1, 1], 3>;
405def : WriteRes<WriteSHDrri, [SPRPort01]> {
406  let Latency = 3;
407}
408defm : X86WriteRes<WriteSTMXCSR, [SPRPort00, SPRPort00_06, SPRPort04_09, SPRPort07_08], 12, [1, 1, 1, 1], 4>;
409def : WriteRes<WriteShift, [SPRPort00_06]>;
410def : WriteRes<WriteShiftLd, [SPRPort00_06]> {
411  let Latency = 12;
412}
413defm : X86WriteRes<WriteShiftCL, [SPRPort00_06], 2, [2], 2>;
414defm : X86WriteRes<WriteShiftCLLd, [SPRPort00_06], 12, [2], 2>;
415defm : SPRWriteResPair<WriteShuffle, [SPRPort05], 1, [1], 1, 8>;
416defm : SPRWriteResPair<WriteShuffle256, [SPRPort05], 3, [1], 1, 8>;
417defm : SPRWriteResPair<WriteShuffleX, [SPRPort01_05], 1, [1], 1, 7>;
418defm : SPRWriteResPair<WriteShuffleY, [SPRPort01_05], 1, [1], 1, 8>;
419defm : SPRWriteResPair<WriteShuffleZ, [SPRPort05], 3, [1], 1, 6>;
420defm : X86WriteRes<WriteStore, [SPRPort04_09, SPRPort07_08], 12, [1, 1], 2>;
421defm : X86WriteRes<WriteStoreNT, [SPRPort04_09, SPRPort07_08], 512, [1, 1], 2>;
422def : WriteRes<WriteSystem, [SPRPort00_01_05_06]> {
423  let Latency = SapphireRapidsModel.MaxLatency;
424}
425defm : SPRWriteResPair<WriteTZCNT, [SPRPort01], 3, [1]>;
426defm : SPRWriteResPair<WriteVPMOV256, [SPRPort05], 3, [1], 1, 8>;
427defm : SPRWriteResPair<WriteVarBlend, [SPRPort00_01_05], 1, [1], 1, 7>;
428defm : SPRWriteResPair<WriteVarBlendY, [SPRPort00_01_05], 1, [1], 1, 8>;
429defm : SPRWriteResPair<WriteVarBlendZ, [SPRPort00_05], 1, [1], 1, 8>;
430defm : SPRWriteResPair<WriteVarShuffle, [SPRPort00, SPRPort05], 3, [1, 1], 2, 8>;
431defm : X86WriteRes<WriteVarShuffle256, [SPRPort05], 6, [2], 2>;
432defm : X86WriteRes<WriteVarShuffle256Ld, [SPRPort02_03_11, SPRPort05], 11, [1, 1], 2>;
433defm : SPRWriteResPair<WriteVarShuffleX, [SPRPort01_05], 1, [1], 1, 7>;
434defm : SPRWriteResPair<WriteVarShuffleY, [SPRPort01_05], 1, [1], 1, 8>;
435defm : SPRWriteResPair<WriteVarShuffleZ, [SPRPort05], 3, [1], 1, 8>;
436defm : SPRWriteResPair<WriteVarVecShift, [SPRPort00_01], 1, [1], 1, 7>;
437defm : SPRWriteResPair<WriteVarVecShiftY, [SPRPort00_01], 1, [1], 1, 8>;
438defm : SPRWriteResPair<WriteVarVecShiftZ, [SPRPort00], 1, [1], 1, 8>;
439defm : SPRWriteResPair<WriteVecALU, [SPRPort00], 1, [1], 1, 8>;
440defm : SPRWriteResPair<WriteVecALUX, [SPRPort00_01], 1, [1], 1, 7>;
441defm : SPRWriteResPair<WriteVecALUY, [SPRPort00_01], 1, [1], 1, 8>;
442def : WriteRes<WriteVecALUZ, [SPRPort05]> {
443  let Latency = 3;
444}
445defm : X86WriteRes<WriteVecALUZLd, [SPRPort00, SPRPort02_03_11], 9, [1, 1], 2>;
446defm : X86WriteRes<WriteVecExtract, [SPRPort00, SPRPort01_05], 4, [1, 1], 2>;
447defm : X86WriteRes<WriteVecExtractSt, [SPRPort01_05, SPRPort04_09, SPRPort07_08], 19, [1, 1, 1], 3>;
448defm : SPRWriteResPair<WriteVecIMul, [SPRPort00], 5, [1], 1, 8>;
449defm : SPRWriteResPair<WriteVecIMulX, [SPRPort00_01], 5, [1], 1, 8>;
450defm : SPRWriteResPair<WriteVecIMulY, [SPRPort00_01], 5, [1], 1, 8>;
451defm : SPRWriteResPair<WriteVecIMulZ, [SPRPort00], 5, [1], 1, 8>;
452defm : X86WriteRes<WriteVecInsert, [SPRPort01_05, SPRPort05], 4, [1, 1], 2>;
453defm : X86WriteRes<WriteVecInsertLd, [SPRPort01_05, SPRPort02_03_11], 8, [1, 1], 2>;
454def : WriteRes<WriteVecLoad, [SPRPort02_03_11]> {
455  let Latency = 7;
456}
457def : WriteRes<WriteVecLoadNT, [SPRPort02_03_11]> {
458  let Latency = 7;
459}
460def : WriteRes<WriteVecLoadNTY, [SPRPort02_03_11]> {
461  let Latency = 8;
462}
463def : WriteRes<WriteVecLoadX, [SPRPort02_03_11]> {
464  let Latency = 7;
465}
466def : WriteRes<WriteVecLoadY, [SPRPort02_03_11]> {
467  let Latency = 8;
468}
469defm : SPRWriteResPair<WriteVecLogic, [SPRPort00_05], 1, [1], 1, 8>;
470defm : SPRWriteResPair<WriteVecLogicX, [SPRPort00_01_05], 1, [1], 1, 7>;
471defm : SPRWriteResPair<WriteVecLogicY, [SPRPort00_01_05], 1, [1], 1, 8>;
472defm : SPRWriteResPair<WriteVecLogicZ, [SPRPort00_05], 1, [1], 1, 8>;
473def : WriteRes<WriteVecMOVMSK, [SPRPort00]> {
474  let Latency = 3;
475}
476def : WriteRes<WriteVecMOVMSKY, [SPRPort00]> {
477  let Latency = 4;
478}
479defm : X86WriteRes<WriteVecMaskedGatherWriteback, [], 5, [], 0>;
480defm : X86WriteRes<WriteVecMaskedLoad, [SPRPort00_01_05, SPRPort02_03_11], 8, [1, 1], 2>;
481defm : X86WriteRes<WriteVecMaskedLoadY, [SPRPort00_01_05, SPRPort02_03_11], 9, [1, 1], 2>;
482defm : X86WriteRes<WriteVecMaskedStore32, [SPRPort00, SPRPort04_09, SPRPort07_08], 14, [1, 1, 1], 3>;
483defm : X86WriteRes<WriteVecMaskedStore32Y, [SPRPort00, SPRPort04_09, SPRPort07_08], 14, [1, 1, 1], 3>;
484defm : X86WriteRes<WriteVecMaskedStore64, [SPRPort00, SPRPort04_09, SPRPort07_08], 14, [1, 1, 1], 3>;
485defm : X86WriteRes<WriteVecMaskedStore64Y, [SPRPort00, SPRPort04_09, SPRPort07_08], 14, [1, 1, 1], 3>;
486def : WriteRes<WriteVecMove, [SPRPort00_05]>;
487def : WriteRes<WriteVecMoveFromGpr, [SPRPort05]> {
488  let Latency = 3;
489}
490def : WriteRes<WriteVecMoveToGpr, [SPRPort00]> {
491  let Latency = 3;
492}
493defm : X86WriteRes<WriteVecMoveX, [], 1, [], 0>;
494def : WriteRes<WriteVecMoveY, [SPRPort00_01_05]>;
495def : WriteRes<WriteVecMoveZ, [SPRPort00_05]>;
496defm : SPRWriteResPair<WriteVecShift, [SPRPort00], 1, [1], 1, 8>;
497def : WriteRes<WriteVecShiftImm, [SPRPort00]>;
498defm : SPRWriteResPair<WriteVecShiftImmX, [SPRPort00_01], 1, [1], 1, 7>;
499defm : SPRWriteResPair<WriteVecShiftImmY, [SPRPort00_01], 1, [1], 1, 8>;
500defm : SPRWriteResPair<WriteVecShiftImmZ, [SPRPort00], 1, [1], 1, 8>;
501defm : X86WriteRes<WriteVecShiftX, [SPRPort00_01, SPRPort01_05], 2, [1, 1], 2>;
502defm : X86WriteRes<WriteVecShiftXLd, [SPRPort00_01, SPRPort02_03_11], 8, [1, 1], 2>;
503defm : X86WriteRes<WriteVecShiftY, [SPRPort00_01, SPRPort05], 4, [1, 1], 2>;
504defm : X86WriteRes<WriteVecShiftYLd, [SPRPort00_01, SPRPort02_03_11], 9, [1, 1], 2>;
505defm : X86WriteRes<WriteVecShiftZ, [SPRPort00, SPRPort05], 4, [1, 1], 2>;
506defm : X86WriteRes<WriteVecShiftZLd, [SPRPort00, SPRPort02_03_11], 9, [1, 1], 2>;
507defm : X86WriteRes<WriteVecStore, [SPRPort04_09, SPRPort07_08], 12, [1, 1], 2>;
508defm : X86WriteRes<WriteVecStoreNT, [SPRPort04_09, SPRPort07_08], 511, [1, 1], 2>;
509defm : X86WriteRes<WriteVecStoreNTY, [SPRPort04_09, SPRPort07_08], 507, [1, 1], 2>;
510defm : X86WriteRes<WriteVecStoreX, [SPRPort04_09, SPRPort07_08], 12, [1, 1], 2>;
511defm : X86WriteRes<WriteVecStoreY, [SPRPort04_09, SPRPort07_08], 12, [1, 1], 2>;
512defm : SPRWriteResPair<WriteVecTest, [SPRPort00, SPRPort05], 4, [1, 1], 2>;
513defm : SPRWriteResPair<WriteVecTestY, [SPRPort00, SPRPort05], 6, [1, 1], 2, 6>;
514defm : X86WriteRes<WriteXCHG, [SPRPort00_01_05_06_10], 2, [3], 3>;
515def : WriteRes<WriteZero, []>;
516
517// Infered SchedWriteRes and InstRW definition.
518
519def SPRWriteResGroup0 : SchedWriteRes<[SPRPort02_03, SPRPort02_03_11, SPRPort04, SPRPort04_09]> {
520  let Latency = 7;
521  let NumMicroOps = 3;
522}
523def : InstRW<[SPRWriteResGroup0], (instregex "^AA(D|N)D64mr$",
524                                             "^A(X?)OR64mr$")>;
525
526def SPRWriteResGroup1 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06, SPRPort02_03_11, SPRPort04_09, SPRPort07_08]> {
527  let ReleaseAtCycles = [2, 1, 1, 1, 1];
528  let Latency = 12;
529  let NumMicroOps = 6;
530}
531def : InstRW<[SPRWriteResGroup1, ReadAfterLd, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^(ADC|SBB)(16|32|64)mr$")>;
532
533def SPRWriteResGroup2 : SchedWriteRes<[SPRPort00_06, SPRPort02_03_11]> {
534  let Latency = 6;
535  let NumMicroOps = 2;
536}
537def : InstRW<[SPRWriteResGroup2], (instregex "^RORX(32|64)mi$")>;
538def : InstRW<[SPRWriteResGroup2, ReadAfterLd, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^(ADC|SBB)(8|16|32|64)rm$",
539                                                                                                                                        "^AD(C|O)X(32|64)rm$")>;
540
541def SPRWriteResGroup3 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06, SPRPort02_03_11, SPRPort04_09, SPRPort07_08]> {
542  let Latency = 13;
543  let NumMicroOps = 5;
544}
545def : InstRW<[SPRWriteResGroup3], (instregex "^(ADC|SBB)8mi(8?)$")>;
546
547def SPRWriteResGroup4 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06, SPRPort02_03_11, SPRPort04_09, SPRPort07_08]> {
548  let ReleaseAtCycles = [2, 1, 1, 1, 1];
549  let Latency = 13;
550  let NumMicroOps = 6;
551}
552def : InstRW<[SPRWriteResGroup4, ReadAfterLd, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^(ADC|SBB)8mr$")>;
553
554def SPRWriteResGroup5 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort02_03_11]> {
555  let Latency = 6;
556  let NumMicroOps = 2;
557}
558def : InstRW<[SPRWriteResGroup5], (instregex "^CMP(8|16|32)mi$",
559                                             "^CMP(8|16|32|64)mi8$",
560                                             "^MOV(8|16)rm$",
561                                             "^POP(16|32)r((mr)?)$")>;
562def : InstRW<[SPRWriteResGroup5], (instrs CMP64mi32,
563                                          MOV8rm_NOREX,
564                                          MOVZX16rm8)>;
565def : InstRW<[SPRWriteResGroup5, ReadAfterLd], (instregex "^(ADD|CMP|SUB)(8|16|32|64)rm$",
566                                                          "^AND(8|16|32)rm$",
567                                                          "^(X?)OR(8|16|32)rm$")>;
568def : InstRW<[SPRWriteResGroup5, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^CMP(8|16|32|64)mr$")>;
569
570def SPRWriteResGroup6 : SchedWriteRes<[]> {
571  let NumMicroOps = 0;
572}
573def : InstRW<[SPRWriteResGroup6], (instregex "^(ADD|SUB)64ri8$",
574                                             "^(DE|IN)C64r$",
575                                             "^MOV64rr((_REV)?)$",
576                                             "^VMOV(A|U)P(D|S)Zrr((_REV)?)$",
577                                             "^VMOVDQA(32|64)Z((256)?)rr((_REV)?)$",
578                                             "^VMOVDQ(A|U)Yrr((_REV)?)$",
579                                             "^VMOVDQU(8|16|32|64)Z((256)?)rr((_REV)?)$")>;
580def : InstRW<[SPRWriteResGroup6], (instrs CLC,
581                                          JMP_2)>;
582
583def SPRWriteResGroup7 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort02_03_11, SPRPort04_09, SPRPort07_08]> {
584  let Latency = 13;
585  let NumMicroOps = 4;
586}
587def : InstRW<[SPRWriteResGroup7], (instregex "^A(D|N)D8mi(8?)$",
588                                             "^(DE|IN)C8m$",
589                                             "^N(EG|OT)8m$",
590                                             "^(X?)OR8mi(8?)$",
591                                             "^SUB8mi(8?)$")>;
592def : InstRW<[SPRWriteResGroup7, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^A(D|N)D8mr$",
593                                                                                                                           "^(X?)OR8mr$")>;
594def : InstRW<[SPRWriteResGroup7, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instrs SUB8mr)>;
595
596def SPRWriteResGroup8 : SchedWriteRes<[SPRPort01_05, SPRPort02_03_11]> {
597  let Latency = 10;
598  let NumMicroOps = 2;
599}
600def : InstRW<[SPRWriteResGroup8, ReadAfterVecXLd], (instregex "^(V?)(ADD|SUB)PSrm$",
601                                                              "^(V?)ADDSUBPSrm$",
602                                                              "^V(ADD|SUB)PSZ128rm((b|k|bk|kz)?)$",
603                                                              "^V(ADD|SUB)PSZ128rmbkz$")>;
604
605def SPRWriteResGroup9 : SchedWriteRes<[SPRPort01_05]> {
606  let Latency = 3;
607}
608def : InstRW<[SPRWriteResGroup9], (instregex "^(V?)(ADD|SUB)PSrr$",
609                                             "^(V?)ADDSUBPSrr$",
610                                             "^V(ADD|SUB)PSYrr$",
611                                             "^V(ADD|SUB)PSZ(128|256)rr(k?)$",
612                                             "^VPMOV(S|Z)XBWZ128rrk(z?)$",
613                                             "^VPSHUFBZ(128|256)rrk(z?)$",
614                                             "^VPSHUF(H|L)WZ(128|256)rik(z?)$",
615                                             "^VPUNPCK(H|L)(BW|WD)Z(128|256)rrk(z?)$")>;
616def : InstRW<[SPRWriteResGroup9], (instrs VADDSUBPSYrr)>;
617
618def SPRWriteResGroup10 : SchedWriteRes<[SPRPort02_03_11, SPRPort05]> {
619  let Latency = 10;
620  let NumMicroOps = 2;
621}
622def : InstRW<[SPRWriteResGroup10], (instregex "^ADD_F(32|64)m$",
623                                              "^ILD_F(16|32|64)m$",
624                                              "^SUB(R?)_F(32|64)m$",
625                                              "^VPOPCNT(B|D|Q|W)Z128rm$",
626                                              "^VPOPCNT(D|Q)Z128rm(b|k|kz)$",
627                                              "^VPOPCNT(D|Q)Z128rmbk(z?)$")>;
628def : InstRW<[SPRWriteResGroup10, ReadAfterVecXLd], (instregex "^(V?)PACK(S|U)S(DW|WB)rm$",
629                                                               "^(V?)PCMPGTQrm$",
630                                                               "^VFPCLASSP(D|H|S)Z128rmb$",
631                                                               "^VPACK(S|U)S(DW|WB)Z128rm$",
632                                                               "^VPACK(S|U)SDWZ128rmb$",
633                                                               "^VPM(AX|IN)(S|U)QZ128rm((b|k|bk|kz)?)$",
634                                                               "^VPM(AX|IN)(S|U)QZ128rmbkz$",
635                                                               "^VPMULTISHIFTQBZ128rm(b?)$")>;
636def : InstRW<[SPRWriteResGroup10, ReadAfterVecXLd], (instrs VFPCLASSPHZ128rm)>;
637def : InstRW<[SPRWriteResGroup10, ReadAfterVecYLd], (instregex "^VFPCLASSP(D|H|S)Z((256)?)rm$",
638                                                               "^VPERM(I|T)2(D|Q|PS)Z128rm((b|k|bk|kz)?)$",
639                                                               "^VPERM(I|T)2(D|Q|PS)Z128rmbkz$",
640                                                               "^VPERM(I|T)2PDZ128rm((b|k|bk|kz)?)$",
641                                                               "^VPERM(I|T)2PDZ128rmbkz$")>;
642def : InstRW<[SPRWriteResGroup10, ReadAfterVecYLd], (instrs VPERMBZ128rm)>;
643
644def SPRWriteResGroup11 : SchedWriteRes<[SPRPort02_03_11, SPRPort05]> {
645  let ReleaseAtCycles = [1, 2];
646  let Latency = 13;
647  let NumMicroOps = 3;
648}
649def : InstRW<[SPRWriteResGroup11], (instregex "^ADD_FI(16|32)m$",
650                                              "^SUB(R?)_FI(16|32)m$")>;
651def : InstRW<[SPRWriteResGroup11, ReadAfterVecXLd], (instrs SHA256MSG2rm)>;
652def : InstRW<[SPRWriteResGroup11, ReadAfterVecYLd], (instregex "^VPEXPAND(B|W)Z(128|256)rmk(z?)$",
653                                                               "^VPEXPAND(B|W)Zrmk(z?)$")>;
654
655def SPRWriteResGroup12 : SchedWriteRes<[SPRPort05]> {
656  let Latency = 3;
657}
658def : InstRW<[SPRWriteResGroup12], (instregex "^ADD_F(P?)rST0$",
659                                              "^KMOV(B|D|W)kr$",
660                                              "^(V?)PACK(S|U)S(DW|WB)rr$",
661                                              "^(V?)PCMPGTQrr$",
662                                              "^SUB(R?)_F(P?)rST0$",
663                                              "^SUB(R?)_FST0r$",
664                                              "^VALIGN(D|Q)Z256rri((k|kz)?)$",
665                                              "^VCMPP(D|H|S)Z(128|256)rri(k?)$",
666                                              "^VCMPS(D|H|S)Zrr$",
667                                              "^VCMPS(D|H|S)Zrr(b?)_Int(k?)$",
668                                              "^VFPCLASSP(D|H|S)Z(128|256)rr(k?)$",
669                                              "^VFPCLASSS(D|H|S)Zrr(k?)$",
670                                              "^VPACK(S|U)S(DW|WB)Yrr$",
671                                              "^VPACK(S|U)S(DW|WB)Z(128|256)rr$",
672                                              "^VPALIGNRZ(128|256)rrik(z?)$",
673                                              "^VPBROADCAST(B|W)Z128rrk(z?)$",
674                                              "^VPCMP(B|D|Q|W|UD|UQ|UW)Z(128|256)rri(k?)$",
675                                              "^VPCMP(EQ|GT)(B|D|Q|W)Z(128|256)rr(k?)$",
676                                              "^VPCMPUBZ(128|256)rri(k?)$",
677                                              "^VPERMBZ(128|256)rr$",
678                                              "^VPERM(B|D|Q)Zrr$",
679                                              "^VPERM(D|Q)Z256rr((k|kz)?)$",
680                                              "^VPERM(D|Q)Zrrk(z?)$",
681                                              "^VPERM(I|T)2(D|Q)Z(128|256)rr((k|kz)?)$",
682                                              "^VPERM(I|T)2(D|Q)Zrr((k|kz)?)$",
683                                              "^VPM(AX|IN)(S|U)QZ(128|256)rr((k|kz)?)$",
684                                              "^VPMULTISHIFTQBZ(128|256)rr$",
685                                              "^VPOPCNT(B|D|Q|W)Z(128|256)rr$",
686                                              "^VPOPCNT(D|Q)Z(128|256)rrk(z?)$",
687                                              "^VPTEST(N?)M(B|D|Q|W)Z(128|256)rr(k?)$",
688                                              "^VPTEST(N?)M(B|D|Q|W)Zrr(k?)$")>;
689def : InstRW<[SPRWriteResGroup12], (instrs ADD_FST0r,
690                                           VPCMPGTQYrr,
691                                           VPERMDYrr)>;
692
693def SPRWriteResGroup13 : SchedWriteRes<[SPRPort00_01_05_06_10]> {
694  let Latency = 2;
695}
696def : InstRW<[SPRWriteResGroup13], (instregex "^AND(8|16|32|64)r(r|i8)$",
697                                              "^AND(8|16|32|64)rr_REV$",
698                                              "^(AND|TEST)(32|64)i32$",
699                                              "^(AND|TEST)(8|32)ri$",
700                                              "^(AND|TEST)64ri32$",
701                                              "^(AND|TEST)8i8$",
702                                              "^(X?)OR(8|16|32|64)r(r|i8)$",
703                                              "^(X?)OR(8|16|32|64)rr_REV$",
704                                              "^(X?)OR(32|64)i32$",
705                                              "^(X?)OR(8|32)ri$",
706                                              "^(X?)OR64ri32$",
707                                              "^(X?)OR8i8$",
708                                              "^TEST(8|16|32|64)rr$")>;
709def : InstRW<[SPRWriteResGroup13], (instrs XOR8rr_NOREX)>;
710
711def SPRWriteResGroup14 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort02_03_11]> {
712  let Latency = 7;
713  let NumMicroOps = 2;
714}
715def : InstRW<[SPRWriteResGroup14], (instregex "^TEST(8|16|32)mi$")>;
716def : InstRW<[SPRWriteResGroup14], (instrs TEST64mi32)>;
717def : InstRW<[SPRWriteResGroup14, ReadAfterLd], (instregex "^(X?)OR64rm$")>;
718def : InstRW<[SPRWriteResGroup14, ReadAfterLd], (instrs AND64rm)>;
719def : InstRW<[SPRWriteResGroup14, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^TEST(8|16|32|64)mr$")>;
720
721def SPRWriteResGroup15 : SchedWriteRes<[SPRPort01_05_10, SPRPort02_03_11]> {
722  let Latency = 7;
723  let NumMicroOps = 2;
724}
725def : InstRW<[SPRWriteResGroup15, ReadAfterLd], (instregex "^ANDN(32|64)rm$")>;
726
727def SPRWriteResGroup16 : SchedWriteRes<[SPRPort01_05_10]> {
728  let Latency = 2;
729}
730def : InstRW<[SPRWriteResGroup16], (instregex "^ANDN(32|64)rr$")>;
731
732def SPRWriteResGroup17 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort02_03_11]> {
733  let ReleaseAtCycles = [5, 2, 1, 1];
734  let Latency = 10;
735  let NumMicroOps = 9;
736}
737def : InstRW<[SPRWriteResGroup17], (instrs BT64mr)>;
738
739def SPRWriteResGroup18 : SchedWriteRes<[SPRPort01]> {
740  let Latency = 3;
741}
742def : InstRW<[SPRWriteResGroup18], (instregex "^BT((C|R|S)?)64rr$",
743                                              "^P(DEP|EXT)(32|64)rr$")>;
744
745def SPRWriteResGroup19 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort04_09, SPRPort07_08]> {
746  let ReleaseAtCycles = [4, 2, 1, 1, 1, 1];
747  let Latency = 17;
748  let NumMicroOps = 10;
749}
750def : InstRW<[SPRWriteResGroup19], (instregex "^BT(C|R|S)64mr$")>;
751
752def SPRWriteResGroup20 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06, SPRPort02_03_11, SPRPort04_09, SPRPort07_08]> {
753  let Latency = 7;
754  let NumMicroOps = 5;
755}
756def : InstRW<[SPRWriteResGroup20], (instregex "^CALL(16|32|64)m((_NT)?)$")>;
757
758def SPRWriteResGroup21 : SchedWriteRes<[SPRPort00_06, SPRPort04_09, SPRPort07_08]> {
759  let Latency = 3;
760  let NumMicroOps = 3;
761}
762def : InstRW<[SPRWriteResGroup21], (instregex "^CALL(16|32|64)r((_NT)?)$")>;
763
764def SPRWriteResGroup22 : SchedWriteRes<[SPRPort04_09, SPRPort07_08]> {
765  let Latency = 3;
766  let NumMicroOps = 2;
767}
768def : InstRW<[SPRWriteResGroup22], (instrs CALL64pcrel32,
769                                           MFENCE)>;
770
771def SPRWriteResGroup23 : SchedWriteRes<[SPRPort01_05]>;
772def : InstRW<[SPRWriteResGroup23], (instregex "^C(DQ|WD)E$",
773                                              "^(V?)MOVS(H|L)DUPrr$",
774                                              "^(V?)SHUFP(D|S)rri$",
775                                              "^VMOVS(H|L)DUPYrr$",
776                                              "^VMOVS(H|L)DUPZ(128|256)rr((k|kz)?)$",
777                                              "^VPMOVQDZ128rr((k|kz)?)$",
778                                              "^VSHUFP(D|S)Yrri$",
779                                              "^VSHUFP(D|S)Z(128|256)rri((k|kz)?)$")>;
780def : InstRW<[SPRWriteResGroup23], (instrs CBW,
781                                           VPBLENDWYrri)>;
782
783def SPRWriteResGroup24 : SchedWriteRes<[SPRPort00_06]>;
784def : InstRW<[SPRWriteResGroup24], (instregex "^C(DQ|QO)$",
785                                              "^(CL|ST)AC$")>;
786
787def SPRWriteResGroup25 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06]> {
788  let Latency = 3;
789  let NumMicroOps = 2;
790}
791def : InstRW<[SPRWriteResGroup25], (instrs CLD)>;
792
793def SPRWriteResGroup26 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort04_09, SPRPort07_08]> {
794  let Latency = 3;
795  let NumMicroOps = 3;
796}
797def : InstRW<[SPRWriteResGroup26], (instrs CLDEMOTE)>;
798
799def SPRWriteResGroup27 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06, SPRPort04_09, SPRPort07_08]> {
800  let Latency = 2;
801  let NumMicroOps = 4;
802}
803def : InstRW<[SPRWriteResGroup27], (instrs CLFLUSH)>;
804
805def SPRWriteResGroup28 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort04_09, SPRPort07_08]> {
806  let Latency = 2;
807  let NumMicroOps = 3;
808}
809def : InstRW<[SPRWriteResGroup28], (instrs CLFLUSHOPT)>;
810
811def SPRWriteResGroup29 : SchedWriteRes<[SPRPort00_06, SPRPort01]> {
812  let ReleaseAtCycles = [2, 1];
813  let Latency = SapphireRapidsModel.MaxLatency;
814  let NumMicroOps = 3;
815}
816def : InstRW<[SPRWriteResGroup29], (instrs CLI)>;
817
818def SPRWriteResGroup30 : SchedWriteRes<[SPRPort00_06, SPRPort01, SPRPort05]> {
819  let ReleaseAtCycles = [6, 1, 3];
820  let Latency = SapphireRapidsModel.MaxLatency;
821  let NumMicroOps = 10;
822}
823def : InstRW<[SPRWriteResGroup30], (instrs CLTS)>;
824
825def SPRWriteResGroup31 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort04_09, SPRPort07_08]> {
826  let Latency = 5;
827  let NumMicroOps = 3;
828}
829def : InstRW<[SPRWriteResGroup31], (instregex "^MOV16o(16|32|64)a$")>;
830def : InstRW<[SPRWriteResGroup31], (instrs CLWB)>;
831
832def SPRWriteResGroup32 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort02_03_11]> {
833  let ReleaseAtCycles = [5, 2];
834  let Latency = 6;
835  let NumMicroOps = 7;
836}
837def : InstRW<[SPRWriteResGroup32], (instregex "^CMPS(B|L|Q|W)$")>;
838
839def SPRWriteResGroup33 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01_05, SPRPort02_03_11, SPRPort04_09, SPRPort05, SPRPort07_08]> {
840  let ReleaseAtCycles = [2, 7, 6, 2, 1, 1, 2, 1];
841  let Latency = 32;
842  let NumMicroOps = 22;
843}
844def : InstRW<[SPRWriteResGroup33], (instrs CMPXCHG16B)>;
845
846def SPRWriteResGroup34 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort04_09, SPRPort07_08]> {
847  let ReleaseAtCycles = [4, 7, 2, 1, 1, 1];
848  let Latency = 25;
849  let NumMicroOps = 16;
850}
851def : InstRW<[SPRWriteResGroup34], (instrs CMPXCHG8B)>;
852
853def SPRWriteResGroup35 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06, SPRPort02_03_11, SPRPort04_09, SPRPort07_08]> {
854  let ReleaseAtCycles = [1, 2, 1, 1, 1];
855  let Latency = 13;
856  let NumMicroOps = 6;
857}
858def : InstRW<[SPRWriteResGroup35], (instrs CMPXCHG8rm)>;
859
860def SPRWriteResGroup36 : SchedWriteRes<[SPRPort00, SPRPort00_01, SPRPort00_06, SPRPort01, SPRPort04_09, SPRPort05, SPRPort07_08]> {
861  let ReleaseAtCycles = [2, 1, 10, 6, 1, 5, 1];
862  let Latency = 18;
863  let NumMicroOps = 26;
864}
865def : InstRW<[SPRWriteResGroup36], (instrs CPUID)>;
866
867def SPRWriteResGroup37 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_11, SPRPort05]> {
868  let Latency = 12;
869  let NumMicroOps = 3;
870}
871def : InstRW<[SPRWriteResGroup37], (instregex "^(V?)CVT(T?)PD2DQrm$",
872                                              "^VCVT(T?)PD2(U?)DQZ128rm((b|k|bk|kz)?)$",
873                                              "^VCVT(T?)PD2(U?)DQZ128rmbkz$",
874                                              "^VCVTPH2PSXZ128rm(b?)$",
875                                              "^VCVT(U?)QQ2PSZ128rm((b|k|bk|kz)?)$",
876                                              "^VCVT(U?)QQ2PSZ128rmbkz$")>;
877def : InstRW<[SPRWriteResGroup37], (instrs CVTSI642SSrm)>;
878def : InstRW<[SPRWriteResGroup37, ReadAfterVecLd], (instregex "^(V?)CVTSI642SSrm_Int$",
879                                                              "^VCVT(U?)SI642SSZrm((_Int)?)$")>;
880def : InstRW<[SPRWriteResGroup37, ReadAfterVecLd], (instrs VCVTSI642SSrm)>;
881
882def SPRWriteResGroup38 : SchedWriteRes<[SPRPort00, SPRPort00_01, SPRPort02_03_11]> {
883  let Latency = 26;
884  let NumMicroOps = 3;
885}
886def : InstRW<[SPRWriteResGroup38], (instregex "^(V?)CVT(T?)SD2SIrm((_Int)?)$")>;
887def : InstRW<[SPRWriteResGroup38, ReadAfterVecLd], (instregex "^VCVT(T?)SD2SIZrm$",
888                                                              "^VCVT(T?)SD2(U?)SIZrm_Int$")>;
889def : InstRW<[SPRWriteResGroup38, ReadAfterVecLd], (instrs VCVTTSD2USIZrm)>;
890
891def SPRWriteResGroup39 : SchedWriteRes<[SPRPort00_01, SPRPort05]> {
892  let Latency = 7;
893  let NumMicroOps = 2;
894}
895def : InstRW<[SPRWriteResGroup39], (instregex "^VCVT(T?)PS2(U?)QQZ256rr((k|kz)?)$",
896                                              "^VCVT(U?)QQ2PSZ256rr((k|kz)?)$")>;
897def : InstRW<[SPRWriteResGroup39, ReadInt2Fpu], (instrs CVTSI2SSrr)>;
898def : InstRW<[SPRWriteResGroup39, ReadDefault, ReadInt2Fpu], (instregex "^(V?)CVTSI2SSrr_Int$",
899                                                                        "^VCVT(U?)SI2SSZrr$",
900                                                                        "^VCVT(U?)SI2SSZrr(b?)_Int$")>;
901def : InstRW<[SPRWriteResGroup39, ReadDefault, ReadInt2Fpu], (instrs VCVTSI2SSrr)>;
902
903def SPRWriteResGroup40 : SchedWriteRes<[SPRPort00_01, SPRPort05]> {
904  let ReleaseAtCycles = [1, 2];
905  let Latency = 8;
906  let NumMicroOps = 3;
907}
908def : InstRW<[SPRWriteResGroup40, ReadInt2Fpu], (instrs CVTSI642SSrr)>;
909def : InstRW<[SPRWriteResGroup40, ReadDefault, ReadInt2Fpu], (instregex "^(V?)CVTSI642SSrr_Int$",
910                                                                        "^VCVT(U?)SI642SSZrr$",
911                                                                        "^VCVT(U?)SI642SSZrr(b?)_Int$")>;
912def : InstRW<[SPRWriteResGroup40, ReadDefault, ReadInt2Fpu], (instrs VCVTSI642SSrr)>;
913
914def SPRWriteResGroup41 : SchedWriteRes<[SPRPort00, SPRPort00_01, SPRPort05]> {
915  let Latency = 8;
916  let NumMicroOps = 3;
917}
918def : InstRW<[SPRWriteResGroup41], (instregex "^(V?)CVT(T?)SS2SI64rr_Int$",
919                                              "^VCVT(T?)SS2SI64Zrr$",
920                                              "^VCVT(T?)SS2(U?)SI64Zrr(b?)_Int$")>;
921def : InstRW<[SPRWriteResGroup41], (instrs VCVTTSS2USI64Zrr)>;
922def : InstRW<[SPRWriteResGroup41, ReadDefault], (instregex "^(V?)CVT(T?)SS2SI64rr$")>;
923
924def SPRWriteResGroup42 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06]> {
925  let Latency = 2;
926  let NumMicroOps = 2;
927}
928def : InstRW<[SPRWriteResGroup42], (instregex "^J(E|R)CXZ$")>;
929def : InstRW<[SPRWriteResGroup42], (instrs CWD)>;
930
931def SPRWriteResGroup43 : SchedWriteRes<[SPRPort00_01_05_06]>;
932def : InstRW<[SPRWriteResGroup43], (instregex "^(LD|ST)_Frr$",
933                                              "^MOV16s(m|r)$",
934                                              "^MOV(32|64)sr$")>;
935def : InstRW<[SPRWriteResGroup43], (instrs DEC16r_alt,
936                                           SALC,
937                                           ST_FPrr,
938                                           SYSCALL)>;
939
940def SPRWriteResGroup44 : SchedWriteRes<[SPRPort00_06, SPRPort02_03_11, SPRPort04_09, SPRPort07_08]> {
941  let Latency = 7;
942}
943def : InstRW<[SPRWriteResGroup44], (instrs DEC32r_alt)>;
944
945def SPRWriteResGroup45 : SchedWriteRes<[SPRPort00, SPRPort02_03_11]> {
946  let Latency = 27;
947  let NumMicroOps = 2;
948}
949def : InstRW<[SPRWriteResGroup45], (instregex "^DIVR_F(32|64)m$")>;
950
951def SPRWriteResGroup46 : SchedWriteRes<[SPRPort00, SPRPort02_03_11, SPRPort05]> {
952  let Latency = 30;
953  let NumMicroOps = 3;
954}
955def : InstRW<[SPRWriteResGroup46], (instregex "^DIVR_FI(16|32)m$")>;
956
957def SPRWriteResGroup47 : SchedWriteRes<[SPRPort00]> {
958  let Latency = 15;
959}
960def : InstRW<[SPRWriteResGroup47], (instregex "^DIVR_F(P?)rST0$")>;
961def : InstRW<[SPRWriteResGroup47], (instrs DIVR_FST0r)>;
962
963def SPRWriteResGroup48 : SchedWriteRes<[SPRPort00, SPRPort02_03_11]> {
964  let Latency = 19;
965  let NumMicroOps = 2;
966}
967def : InstRW<[SPRWriteResGroup48, ReadAfterVecLd], (instregex "^(V?)DIVSDrm$")>;
968def : InstRW<[SPRWriteResGroup48, ReadAfterVecLd], (instrs VDIVSDZrm)>;
969
970def SPRWriteResGroup49 : SchedWriteRes<[SPRPort00, SPRPort02_03_11]> {
971  let Latency = 22;
972  let NumMicroOps = 2;
973}
974def : InstRW<[SPRWriteResGroup49], (instregex "^DIV_F(32|64)m$")>;
975def : InstRW<[SPRWriteResGroup49, ReadAfterVecLd], (instregex "^VSQRTSHZm_Int((k|kz)?)$")>;
976def : InstRW<[SPRWriteResGroup49, ReadAfterVecLd], (instrs VSQRTSHZm)>;
977
978def SPRWriteResGroup50 : SchedWriteRes<[SPRPort00, SPRPort02_03_11, SPRPort05]> {
979  let Latency = 25;
980  let NumMicroOps = 3;
981}
982def : InstRW<[SPRWriteResGroup50], (instregex "^DIV_FI(16|32)m$")>;
983
984def SPRWriteResGroup51 : SchedWriteRes<[SPRPort00]> {
985  let Latency = 20;
986}
987def : InstRW<[SPRWriteResGroup51], (instregex "^DIV_F(P?)rST0$")>;
988def : InstRW<[SPRWriteResGroup51], (instrs DIV_FST0r)>;
989
990def SPRWriteResGroup52 : SchedWriteRes<[SPRPort04, SPRPort04_09]>;
991def : InstRW<[SPRWriteResGroup52], (instregex "^ENQCMD(S?)(16|32|64)$",
992                                              "^PUSHA(16|32)$",
993                                              "^ST_F(32|64)m$")>;
994def : InstRW<[SPRWriteResGroup52], (instrs PUSHF32)>;
995
996def SPRWriteResGroup53 : SchedWriteRes<[SPRPort00, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort04_09, SPRPort05, SPRPort07_08]> {
997  let ReleaseAtCycles = [2, 21, 2, 14, 4, 9, 5];
998  let Latency = 126;
999  let NumMicroOps = 57;
1000}
1001def : InstRW<[SPRWriteResGroup53], (instrs ENTER)>;
1002
1003def SPRWriteResGroup54 : SchedWriteRes<[SPRPort04_09, SPRPort05, SPRPort07_08]> {
1004  let Latency = 12;
1005  let NumMicroOps = 3;
1006}
1007def : InstRW<[SPRWriteResGroup54], (instregex "^(V?)EXTRACTPSmr$",
1008                                              "^VPMOVQDZ((256)?)mr$")>;
1009def : InstRW<[SPRWriteResGroup54], (instrs SMSW16m,
1010                                           VEXTRACTPSZmr)>;
1011
1012def SPRWriteResGroup55 : SchedWriteRes<[SPRPort00, SPRPort05]> {
1013  let Latency = 4;
1014  let NumMicroOps = 2;
1015}
1016def : InstRW<[SPRWriteResGroup55], (instregex "^(V?)EXTRACTPSrr$")>;
1017def : InstRW<[SPRWriteResGroup55], (instrs MMX_PEXTRWrr,
1018                                           VEXTRACTPSZrr,
1019                                           VPERMWZrr)>;
1020
1021def SPRWriteResGroup56 : SchedWriteRes<[SPRPort02_03, SPRPort02_03_11, SPRPort04, SPRPort04_09, SPRPort06]> {
1022  let Latency = 7;
1023  let NumMicroOps = 5;
1024}
1025def : InstRW<[SPRWriteResGroup56], (instrs FARCALL64m)>;
1026
1027def SPRWriteResGroup57 : SchedWriteRes<[SPRPort02_03_11, SPRPort06]> {
1028  let Latency = 6;
1029  let NumMicroOps = 2;
1030}
1031def : InstRW<[SPRWriteResGroup57], (instrs FARJMP64m,
1032                                           JMP64m_REX)>;
1033
1034def SPRWriteResGroup58 : SchedWriteRes<[SPRPort04, SPRPort04_09]> {
1035  let NumMicroOps = 2;
1036}
1037def : InstRW<[SPRWriteResGroup58], (instregex "^(V?)MASKMOVDQU((64)?)$",
1038                                              "^ST_FP(32|64|80)m$")>;
1039def : InstRW<[SPRWriteResGroup58], (instrs FBSTPm,
1040                                           VMPTRSTm)>;
1041
1042def SPRWriteResGroup59 : SchedWriteRes<[SPRPort00_05]> {
1043  let ReleaseAtCycles = [2];
1044  let Latency = 2;
1045  let NumMicroOps = 2;
1046}
1047def : InstRW<[SPRWriteResGroup59], (instrs FDECSTP)>;
1048
1049def SPRWriteResGroup60 : SchedWriteRes<[SPRPort02_03_11, SPRPort05]> {
1050  let ReleaseAtCycles = [1, 2];
1051  let Latency = 11;
1052  let NumMicroOps = 3;
1053}
1054def : InstRW<[SPRWriteResGroup60], (instregex "^FICOM(P?)(16|32)m$")>;
1055def : InstRW<[SPRWriteResGroup60, ReadAfterVecYLd], (instregex "^VEXPANDP(D|S)Z((256)?)rm((k|kz)?)$",
1056                                                               "^VPEXPAND(B|D|Q|W)Z((256)?)rm$",
1057                                                               "^VPEXPAND(D|Q)Z((256)?)rmk(z?)$")>;
1058
1059def SPRWriteResGroup61 : SchedWriteRes<[SPRPort00_05]>;
1060def : InstRW<[SPRWriteResGroup61], (instregex "^MMX_P(ADD|SUB)(B|D|Q|W)rr$",
1061                                              "^VP(ADD|SUB)(B|D|Q|W)Zrr$",
1062                                              "^VP(ADD|SUB)(D|Q)Zrrk(z?)$",
1063                                              "^VPTERNLOG(D|Q)Zrri((k|kz)?)$")>;
1064def : InstRW<[SPRWriteResGroup61], (instrs FINCSTP,
1065                                           FNOP)>;
1066
1067def SPRWriteResGroup62 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort02_03_11]> {
1068  let Latency = 7;
1069  let NumMicroOps = 3;
1070}
1071def : InstRW<[SPRWriteResGroup62], (instrs FLDCW16m)>;
1072
1073def SPRWriteResGroup63 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort00_06, SPRPort02_03, SPRPort02_03_11]> {
1074  let ReleaseAtCycles = [2, 5, 10, 39, 8];
1075  let Latency = 62;
1076  let NumMicroOps = 64;
1077}
1078def : InstRW<[SPRWriteResGroup63], (instrs FLDENVm)>;
1079
1080def SPRWriteResGroup64 : SchedWriteRes<[SPRPort00_01_05_06]> {
1081  let ReleaseAtCycles = [4];
1082  let Latency = 4;
1083  let NumMicroOps = 4;
1084}
1085def : InstRW<[SPRWriteResGroup64], (instrs FNCLEX)>;
1086
1087def SPRWriteResGroup65 : SchedWriteRes<[SPRPort00_01_05_06, SPRPort00_05, SPRPort05]> {
1088  let ReleaseAtCycles = [6, 3, 6];
1089  let Latency = 75;
1090  let NumMicroOps = 15;
1091}
1092def : InstRW<[SPRWriteResGroup65], (instrs FNINIT)>;
1093
1094def SPRWriteResGroup66 : SchedWriteRes<[SPRPort04, SPRPort04_09, SPRPort06]> {
1095  let Latency = 2;
1096  let NumMicroOps = 3;
1097}
1098def : InstRW<[SPRWriteResGroup66], (instrs FNSTCW16m)>;
1099
1100def SPRWriteResGroup67 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06]> {
1101  let Latency = 3;
1102  let NumMicroOps = 2;
1103}
1104def : InstRW<[SPRWriteResGroup67], (instrs FNSTSW16r)>;
1105
1106def SPRWriteResGroup68 : SchedWriteRes<[SPRPort00, SPRPort04, SPRPort04_09]> {
1107  let Latency = 3;
1108  let NumMicroOps = 3;
1109}
1110def : InstRW<[SPRWriteResGroup68], (instrs FNSTSWm)>;
1111
1112def SPRWriteResGroup69 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06, SPRPort00_06, SPRPort01, SPRPort04, SPRPort04_09, SPRPort05, SPRPort06]> {
1113  let ReleaseAtCycles = [9, 11, 21, 1, 30, 11, 16, 1];
1114  let Latency = 106;
1115  let NumMicroOps = 100;
1116}
1117def : InstRW<[SPRWriteResGroup69], (instrs FSTENVm)>;
1118
1119def SPRWriteResGroup70 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort00_06, SPRPort01_05, SPRPort02_03, SPRPort02_03_11, SPRPort06]> {
1120  let ReleaseAtCycles = [4, 1, 2, 1, 47, 33, 2];
1121  let Latency = 63;
1122  let NumMicroOps = 90;
1123}
1124def : InstRW<[SPRWriteResGroup70], (instrs FXRSTOR)>;
1125
1126def SPRWriteResGroup71 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort00_06, SPRPort01_05, SPRPort02_03, SPRPort02_03_11, SPRPort06]> {
1127  let ReleaseAtCycles = [4, 1, 2, 1, 45, 31, 4];
1128  let Latency = 63;
1129  let NumMicroOps = 88;
1130}
1131def : InstRW<[SPRWriteResGroup71], (instrs FXRSTOR64)>;
1132
1133def SPRWriteResGroup72 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort04_09, SPRPort05, SPRPort07_08]> {
1134  let ReleaseAtCycles = [2, 5, 10, 10, 2, 38, 5, 38];
1135  let Latency = SapphireRapidsModel.MaxLatency;
1136  let NumMicroOps = 110;
1137}
1138def : InstRW<[SPRWriteResGroup72], (instregex "^FXSAVE((64)?)$")>;
1139
1140def SPRWriteResGroup73 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_11]> {
1141  let Latency = 12;
1142  let NumMicroOps = 2;
1143}
1144def : InstRW<[SPRWriteResGroup73], (instregex "^VPLZCNT(D|Q)Z256rm((b|k|bk|kz)?)$",
1145                                              "^VPLZCNT(D|Q)Z256rmbkz$")>;
1146def : InstRW<[SPRWriteResGroup73, ReadAfterVecXLd], (instregex "^(V?)GF2P8AFFINE((INV)?)QBrmi$",
1147                                                               "^(V?)GF2P8MULBrm$",
1148                                                               "^V(ADD|SUB)PHZ128rm((b|k|bk|kz)?)$",
1149                                                               "^V(ADD|SUB)PHZ128rmbkz$",
1150                                                               "^VGETEXPPHZ128m((b|k|bk|kz)?)$",
1151                                                               "^VGETEXPSHZm((k|kz)?)$",
1152                                                               "^VGETMANTPHZ128rm(bi|ik)$",
1153                                                               "^VGETMANTPHZ128rmbik(z?)$",
1154                                                               "^VGETMANTPHZ128rmi((kz)?)$",
1155                                                               "^VGETMANTSHZrmi((k|kz)?)$",
1156                                                               "^VGF2P8AFFINE((INV)?)QBZ128rm(b?)i$",
1157                                                               "^VM(AX|IN)CPHZ128rm((b|k|bk|kz)?)$",
1158                                                               "^VM(AX|IN)CPHZ128rmbkz$",
1159                                                               "^VM(AX|IN|UL)PHZ128rm((b|k|bk|kz)?)$",
1160                                                               "^VM(AX|IN|UL)PHZ128rmbkz$")>;
1161def : InstRW<[SPRWriteResGroup73, ReadAfterVecXLd], (instrs VGETEXPPHZ128mbkz,
1162                                                            VGF2P8MULBZ128rm)>;
1163def : InstRW<[SPRWriteResGroup73, ReadAfterVecLd], (instregex "^V(ADD|SUB)SHZrm$",
1164                                                              "^V(ADD|SUB)SHZrm_Int((k|kz)?)$",
1165                                                              "^VCVTSH2SSZrm((_Int)?)$",
1166                                                              "^VM(AX|IN)CSHZrm$",
1167                                                              "^VM(AX|IN|UL)SHZrm$",
1168                                                              "^VM(AX|IN|UL)SHZrm_Int((k|kz)?)$")>;
1169def : InstRW<[SPRWriteResGroup73, ReadAfterVecYLd], (instregex "^VGF2P8AFFINE((INV)?)QBYrmi$",
1170                                                               "^VGF2P8AFFINE((INV)?)QBZ256rm(b?)i$",
1171                                                               "^VGF2P8MULB(Y|Z256)rm$")>;
1172def : InstRW<[SPRWriteResGroup73, ReadAfterVecXLd, ReadAfterVecXLd], (instregex "^VF(N?)M(ADD|SUB)(132|213|231)PHZ128m((b|k|bk|kz)?)$",
1173                                                                                "^VF(N?)M(ADD|SUB)(132|213|231)PHZ128mbkz$",
1174                                                                                "^VFMADDSUB(132|213|231)PHZ128m((b|k|bk|kz)?)$",
1175                                                                                "^VFMADDSUB(132|213|231)PHZ128mbkz$",
1176                                                                                "^VFMSUBADD(132|213|231)PHZ128m((b|k|bk|kz)?)$",
1177                                                                                "^VFMSUBADD(132|213|231)PHZ128mbkz$")>;
1178def : InstRW<[SPRWriteResGroup73, ReadAfterVecLd, ReadAfterVecLd], (instregex "^VF(N?)M(ADD|SUB)(132|213|231)SHZm$",
1179                                                                              "^VF(N?)M(ADD|SUB)(132|213|231)SHZm_Int((k|kz)?)$")>;
1180def : InstRW<[SPRWriteResGroup73, ReadAfterVecYLd, ReadAfterVecYLd], (instregex "^VPMADD52(H|L)UQZ256m((b|k|bk|kz)?)$",
1181                                                                                "^VPMADD52(H|L)UQZ256mbkz$")>;
1182
1183def SPRWriteResGroup74 : SchedWriteRes<[SPRPort00_01]> {
1184  let Latency = 5;
1185}
1186def : InstRW<[SPRWriteResGroup74], (instregex "^(V?)GF2P8MULBrr$",
1187                                              "^V(ADD|SUB)PHZ(128|256)rr$",
1188                                              "^V(ADD|SUB)SHZrr$",
1189                                              "^V(ADD|SUB)SHZrr(b?)_Int$",
1190                                              "^VCVT(T?)PH2(U?)WZ(128|256)rr$",
1191                                              "^VCVTSH2SSZrr(b?)_Int$",
1192                                              "^VCVT(U?)W2PHZ(128|256)rr$",
1193                                              "^VF(N?)M(ADD|SUB)(132|213|231)PHZ(128|256)r$",
1194                                              "^VF(N?)M(ADD|SUB)(132|213|231)SHZr(b?)((_Int)?)$",
1195                                              "^VFMADDSUB(132|213|231)PHZ(128|256)r$",
1196                                              "^VFMSUBADD(132|213|231)PHZ(128|256)r$",
1197                                              "^VGETEXPPHZ(128|256)r$",
1198                                              "^VGETEXPSHZr(b?)$",
1199                                              "^VGETMANTPHZ(128|256)rri$",
1200                                              "^VGETMANTSHZrri(b?)$",
1201                                              "^VGF2P8MULBZ(128|256)rr$",
1202                                              "^VM(AX|IN)CPHZ(128|256)rr$",
1203                                              "^VM(AX|IN)CSHZrr$",
1204                                              "^VM(AX|IN|UL)PHZ(128|256)rr$",
1205                                              "^VM(AX|IN|UL)SHZrr$",
1206                                              "^VM(AX|IN|UL)SHZrr(b?)_Int$")>;
1207def : InstRW<[SPRWriteResGroup74], (instrs VCVTSH2SSZrr,
1208                                           VGF2P8MULBYrr)>;
1209
1210def SPRWriteResGroup75 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort01_05_10, SPRPort02_03_11, SPRPort05]> {
1211  let ReleaseAtCycles = [7, 5, 26, 19, 2, 7, 21];
1212  let Latency = 35;
1213  let NumMicroOps = 87;
1214}
1215def : InstRW<[SPRWriteResGroup75], (instrs IN16ri)>;
1216
1217def SPRWriteResGroup76 : SchedWriteRes<[SPRPort00, SPRPort00_01, SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort01_05_10, SPRPort02_03_11, SPRPort05]> {
1218  let ReleaseAtCycles = [7, 1, 4, 26, 19, 3, 7, 20];
1219  let Latency = 35;
1220  let NumMicroOps = 87;
1221}
1222def : InstRW<[SPRWriteResGroup76], (instrs IN16rr)>;
1223
1224def SPRWriteResGroup77 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort01_05_10, SPRPort02_03_11, SPRPort05]> {
1225  let ReleaseAtCycles = [7, 6, 28, 21, 2, 10, 20];
1226  let Latency = 35;
1227  let NumMicroOps = 94;
1228}
1229def : InstRW<[SPRWriteResGroup77], (instrs IN32ri)>;
1230
1231def SPRWriteResGroup78 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort01_05_10, SPRPort02_03_11, SPRPort05]> {
1232  let ReleaseAtCycles = [7, 9, 28, 21, 2, 11, 21];
1233  let NumMicroOps = 99;
1234}
1235def : InstRW<[SPRWriteResGroup78], (instrs IN32rr)>;
1236
1237def SPRWriteResGroup79 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort01_05_10, SPRPort02_03_11, SPRPort05]> {
1238  let ReleaseAtCycles = [7, 6, 25, 19, 2, 8, 20];
1239  let Latency = 35;
1240  let NumMicroOps = 87;
1241}
1242def : InstRW<[SPRWriteResGroup79], (instrs IN8ri)>;
1243
1244def SPRWriteResGroup80 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort01_05_10, SPRPort02_03_11, SPRPort05]> {
1245  let ReleaseAtCycles = [7, 6, 25, 19, 2, 7, 20];
1246  let Latency = 35;
1247  let NumMicroOps = 86;
1248}
1249def : InstRW<[SPRWriteResGroup80], (instrs IN8rr)>;
1250
1251def SPRWriteResGroup81 : SchedWriteRes<[SPRPort00_06]> {
1252  let NumMicroOps = 4;
1253}
1254def : InstRW<[SPRWriteResGroup81], (instrs INC16r_alt)>;
1255
1256def SPRWriteResGroup82 : SchedWriteRes<[SPRPort02_03_11]> {
1257  let Latency = 7;
1258}
1259def : InstRW<[SPRWriteResGroup82], (instregex "^LD_F(32|64|80)m$",
1260                                              "^(V?)MOV(D|SH|SL)DUPrm$",
1261                                              "^VBROADCASTSS((Z128)?)rm$",
1262                                              "^VMOV(D|SH|SL)DUPZ128rm$",
1263                                              "^VPBROADCAST(D|Q)((Z128)?)rm$")>;
1264def : InstRW<[SPRWriteResGroup82], (instrs INC32r_alt,
1265                                           VBROADCASTI32X2Z128rm)>;
1266
1267def SPRWriteResGroup83 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort04_09, SPRPort05, SPRPort07_08]> {
1268  let ReleaseAtCycles = [7, 6, 24, 17, 8, 1, 19, 1];
1269  let Latency = 20;
1270  let NumMicroOps = 83;
1271}
1272def : InstRW<[SPRWriteResGroup83], (instrs INSB)>;
1273
1274def SPRWriteResGroup84 : SchedWriteRes<[SPRPort00, SPRPort00_01_05, SPRPort00_01_05_06_10, SPRPort00_05_06, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort04_09, SPRPort05, SPRPort07_08]> {
1275  let ReleaseAtCycles = [7, 1, 5, 1, 27, 17, 11, 1, 21, 1];
1276  let Latency = 20;
1277  let NumMicroOps = 92;
1278}
1279def : InstRW<[SPRWriteResGroup84], (instrs INSL)>;
1280
1281def SPRWriteResGroup85 : SchedWriteRes<[SPRPort00, SPRPort00_01_05, SPRPort00_01_05_06_10, SPRPort00_05_06, SPRPort00_06, SPRPort01, SPRPort01_05_10, SPRPort02_03_11, SPRPort04_09, SPRPort05, SPRPort07_08]> {
1282  let ReleaseAtCycles = [7, 1, 4, 1, 25, 17, 1, 9, 1, 19, 1];
1283  let Latency = 20;
1284  let NumMicroOps = 86;
1285}
1286def : InstRW<[SPRWriteResGroup85], (instrs INSW)>;
1287
1288def SPRWriteResGroup86 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort01_05_10, SPRPort04_09, SPRPort05, SPRPort07_08]> {
1289  let ReleaseAtCycles = [5, 4, 8, 6, 2, 5, 7, 5];
1290  let Latency = SapphireRapidsModel.MaxLatency;
1291  let NumMicroOps = 42;
1292}
1293def : InstRW<[SPRWriteResGroup86], (instrs INVLPG)>;
1294
1295def SPRWriteResGroup87 : SchedWriteRes<[SPRPort04, SPRPort04_09, SPRPort05]> {
1296  let Latency = 4;
1297  let NumMicroOps = 3;
1298}
1299def : InstRW<[SPRWriteResGroup87], (instregex "^IST(T?)_FP(16|32|64)m$",
1300                                              "^IST_F(16|32)m$")>;
1301
1302def SPRWriteResGroup88 : SchedWriteRes<[SPRPort00_01_05_06, SPRPort00_06]> {
1303  let Latency = 2;
1304  let NumMicroOps = 2;
1305}
1306def : InstRW<[SPRWriteResGroup88], (instrs JCXZ)>;
1307
1308def SPRWriteResGroup89 : SchedWriteRes<[SPRPort06]>;
1309def : InstRW<[SPRWriteResGroup89], (instrs JMP64r_REX)>;
1310
1311def SPRWriteResGroup90 : SchedWriteRes<[]> {
1312  let Latency = 0;
1313  let NumMicroOps = 0;
1314}
1315def : InstRW<[SPRWriteResGroup90], (instregex "^JMP_(1|4)$")>;
1316def : InstRW<[SPRWriteResGroup90], (instrs VZEROUPPER)>;
1317
1318def SPRWriteResGroup91 : SchedWriteRes<[SPRPort05]> {
1319  let Latency = 4;
1320}
1321def : InstRW<[SPRWriteResGroup91], (instregex "^KADD(B|D|Q|W)rr$",
1322                                              "^KSHIFT(LB|RD|RQ|RW)ri$",
1323                                              "^KSHIFT(LD|RB)ri$",
1324                                              "^KSHIFTL(Q|W)ri$",
1325                                              "^KUNPCK(BW|DQ|WD)rr$")>;
1326
1327def SPRWriteResGroup92 : SchedWriteRes<[SPRPort00]>;
1328def : InstRW<[SPRWriteResGroup92], (instregex "^KAND(B|D|Q|W|ND|NQ|NW)rr$",
1329                                              "^KMOV(B|D|Q|W)kk$",
1330                                              "^KNOT(B|D|Q|W)rr$",
1331                                              "^K((X|XN)?)OR(B|D|Q|W)rr$",
1332                                              "^VP(A|SU)BSBZrr$",
1333                                              "^VPABS(D|Q|W)Zrr$",
1334                                              "^VPABS(D|Q)Zrrk(z?)$",
1335                                              "^VPADD(U?)S(B|W)Zrr$",
1336                                              "^VPAVG(B|W)Zrr$",
1337                                              "^VPM(AX|IN)(SB|UD|UW)Zrr$",
1338                                              "^VPM(AX|IN)(SD|UB)Zrr$",
1339                                              "^VPM(AX|IN)(S|U)DZrrk(z?)$",
1340                                              "^VPM(AX|IN)SWZrr$",
1341                                              "^VPSH(L|R)D(D|Q|W)Zrri$",
1342                                              "^VPSH(L|R)DV(D|Q|W)Zr$",
1343                                              "^VPSH(L|R)DV(D|Q)Zrk(z?)$",
1344                                              "^VPSUB(U?)SWZrr$")>;
1345def : InstRW<[SPRWriteResGroup92], (instrs KANDNBrr,
1346                                           VPSUBUSBZrr)>;
1347
1348def SPRWriteResGroup93 : SchedWriteRes<[SPRPort02_03_11, SPRPort05]> {
1349  let Latency = 7;
1350  let NumMicroOps = 2;
1351}
1352def : InstRW<[SPRWriteResGroup93], (instregex "^KMOV(B|D|Q|W)km$")>;
1353
1354def SPRWriteResGroup94 : SchedWriteRes<[SPRPort04_09, SPRPort07_08]> {
1355  let Latency = 13;
1356  let NumMicroOps = 2;
1357}
1358def : InstRW<[SPRWriteResGroup94], (instregex "^MOV8m(i|r)$")>;
1359def : InstRW<[SPRWriteResGroup94], (instrs KMOVBmk,
1360                                           MOV8mr_NOREX)>;
1361
1362def SPRWriteResGroup95 : SchedWriteRes<[SPRPort05]>;
1363def : InstRW<[SPRWriteResGroup95], (instregex "^(V?)PALIGNRrri$",
1364                                              "^VALIGN(D|Q)Z128rri((k|kz)?)$",
1365                                              "^VBROADCASTSSZ128rr((k|kz)?)$",
1366                                              "^VPALIGNR(Y|Z)rri$",
1367                                              "^VPALIGNRZ(128|256)rri$",
1368                                              "^VPBROADCAST(B|D|Q|W)rr$",
1369                                              "^VPSHUF(D|HW|LW)Zri$",
1370                                              "^VPSHUFDZrik(z?)$",
1371                                              "^VPS(L|R)LDQZri$",
1372                                              "^VPUNPCK(H|L)(BW|WD)Zrr$",
1373                                              "^VPUNPCK(H|L|LQ)DQZrr((k|kz)?)$",
1374                                              "^VPUNPCKHQDQZrr((k|kz)?)$")>;
1375def : InstRW<[SPRWriteResGroup95], (instrs KMOVQkr,
1376                                           VPSHUFBZrr)>;
1377
1378def SPRWriteResGroup96 : SchedWriteRes<[SPRPort00]> {
1379  let Latency = 3;
1380}
1381def : InstRW<[SPRWriteResGroup96], (instregex "^K((OR)?)TEST(B|D|Q|W)rr$",
1382                                              "^VP(A|SU)BS(B|W)Zrrk(z?)$",
1383                                              "^VPADD(U?)S(B|W)Zrrk(z?)$",
1384                                              "^VPAVG(B|W)Zrrk(z?)$",
1385                                              "^VPM(AX|IN)(SB|UW)Zrrk(z?)$",
1386                                              "^VPM(AX|IN)(SW|UB)Zrrk(z?)$",
1387                                              "^VPSH(L|R)DVWZrk(z?)$",
1388                                              "^VPS(L|R)LVWZrrk(z?)$",
1389                                              "^VPS(L|R)LWZrik(z?)$",
1390                                              "^VPSRAVWZrrk(z?)$",
1391                                              "^VPSRAWZrik(z?)$",
1392                                              "^VPSUBUS(B|W)Zrrk(z?)$")>;
1393def : InstRW<[SPRWriteResGroup96], (instrs VMOVSDto64Zrr)>;
1394
1395def SPRWriteResGroup97 : SchedWriteRes<[SPRPort00, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort05]> {
1396  let ReleaseAtCycles = [8, 2, 14, 3, 1];
1397  let Latency = 198;
1398  let NumMicroOps = 81;
1399}
1400def : InstRW<[SPRWriteResGroup97], (instrs LAR16rm)>;
1401
1402def SPRWriteResGroup98 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort00_05_06, SPRPort00_06, SPRPort01, SPRPort01_05, SPRPort02_03_11, SPRPort05]> {
1403  let ReleaseAtCycles = [1, 3, 1, 8, 5, 1, 2, 1];
1404  let Latency = 66;
1405  let NumMicroOps = 22;
1406}
1407def : InstRW<[SPRWriteResGroup98], (instrs LAR16rr)>;
1408
1409def SPRWriteResGroup99 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort00_05, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort05]> {
1410  let ReleaseAtCycles = [1, 2, 2, 9, 5, 3, 1];
1411  let Latency = 71;
1412  let NumMicroOps = 85;
1413}
1414def : InstRW<[SPRWriteResGroup99], (instrs LAR32rm)>;
1415
1416def SPRWriteResGroup100 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort00_05_06, SPRPort00_06, SPRPort01, SPRPort01_05, SPRPort02_03_11, SPRPort05]> {
1417  let ReleaseAtCycles = [1, 3, 1, 8, 5, 1, 2, 1];
1418  let Latency = 65;
1419  let NumMicroOps = 22;
1420}
1421def : InstRW<[SPRWriteResGroup100], (instregex "^LAR(32|64)rr$")>;
1422
1423def SPRWriteResGroup101 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort00_05, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort05]> {
1424  let ReleaseAtCycles = [1, 2, 2, 9, 5, 3, 1];
1425  let Latency = 71;
1426  let NumMicroOps = 87;
1427}
1428def : InstRW<[SPRWriteResGroup101], (instrs LAR64rm)>;
1429
1430def SPRWriteResGroup102 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort01]> {
1431  let Latency = 2;
1432  let NumMicroOps = 2;
1433}
1434def : InstRW<[SPRWriteResGroup102], (instrs LEA16r)>;
1435
1436def SPRWriteResGroup103 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort02_03_11]> {
1437  let ReleaseAtCycles = [3, 1];
1438  let Latency = 6;
1439  let NumMicroOps = 4;
1440}
1441def : InstRW<[SPRWriteResGroup103], (instregex "^LODS(B|W)$",
1442                                               "^SCAS(B|L|Q|W)$")>;
1443def : InstRW<[SPRWriteResGroup103], (instrs LEAVE)>;
1444
1445def SPRWriteResGroup104 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort02_03_11]> {
1446  let ReleaseAtCycles = [2, 1];
1447  let Latency = 6;
1448  let NumMicroOps = 3;
1449}
1450def : InstRW<[SPRWriteResGroup104], (instrs LEAVE64)>;
1451
1452def SPRWriteResGroup105 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort04_09, SPRPort07_08]> {
1453  let ReleaseAtCycles = [1, 2, 4, 3, 2, 1, 1];
1454  let Latency = SapphireRapidsModel.MaxLatency;
1455  let NumMicroOps = 14;
1456}
1457def : InstRW<[SPRWriteResGroup105], (instrs LGDT64m)>;
1458
1459def SPRWriteResGroup106 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_05, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort04_09, SPRPort07_08]> {
1460  let ReleaseAtCycles = [1, 1, 5, 3, 2, 1, 1];
1461  let Latency = SapphireRapidsModel.MaxLatency;
1462  let NumMicroOps = 14;
1463}
1464def : InstRW<[SPRWriteResGroup106], (instrs LIDT64m)>;
1465
1466def SPRWriteResGroup107 : SchedWriteRes<[SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort04_09, SPRPort07_08]> {
1467  let ReleaseAtCycles = [5, 3, 2, 1, 1];
1468  let Latency = SapphireRapidsModel.MaxLatency;
1469  let NumMicroOps = 12;
1470}
1471def : InstRW<[SPRWriteResGroup107], (instrs LLDT16m)>;
1472
1473def SPRWriteResGroup108 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort04_09, SPRPort07_08]> {
1474  let ReleaseAtCycles = [1, 4, 3, 1, 1, 1];
1475  let Latency = SapphireRapidsModel.MaxLatency;
1476  let NumMicroOps = 11;
1477}
1478def : InstRW<[SPRWriteResGroup108], (instrs LLDT16r)>;
1479
1480def SPRWriteResGroup109 : SchedWriteRes<[SPRPort00, SPRPort00_01_05, SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort04_09, SPRPort05, SPRPort07_08]> {
1481  let ReleaseAtCycles = [1, 1, 2, 8, 3, 1, 2, 7, 2];
1482  let Latency = SapphireRapidsModel.MaxLatency;
1483  let NumMicroOps = 27;
1484}
1485def : InstRW<[SPRWriteResGroup109], (instrs LMSW16m)>;
1486
1487def SPRWriteResGroup110 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort04_09, SPRPort05, SPRPort07_08]> {
1488  let ReleaseAtCycles = [5, 7, 1, 2, 5, 2];
1489  let Latency = SapphireRapidsModel.MaxLatency;
1490  let NumMicroOps = 22;
1491}
1492def : InstRW<[SPRWriteResGroup110], (instrs LMSW16r)>;
1493
1494def SPRWriteResGroup111 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort02_03_11]> {
1495  let ReleaseAtCycles = [2, 1];
1496  let Latency = 5;
1497  let NumMicroOps = 3;
1498}
1499def : InstRW<[SPRWriteResGroup111], (instregex "^LODS(L|Q)$")>;
1500
1501def SPRWriteResGroup112 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01]> {
1502  let ReleaseAtCycles = [2, 4, 1];
1503  let Latency = 3;
1504  let NumMicroOps = 7;
1505}
1506def : InstRW<[SPRWriteResGroup112], (instrs LOOP)>;
1507
1508def SPRWriteResGroup113 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01]> {
1509  let ReleaseAtCycles = [4, 6, 1];
1510  let Latency = 3;
1511  let NumMicroOps = 11;
1512}
1513def : InstRW<[SPRWriteResGroup113], (instrs LOOPE)>;
1514
1515def SPRWriteResGroup114 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01]> {
1516  let ReleaseAtCycles = [4, 6, 1];
1517  let Latency = 2;
1518  let NumMicroOps = 11;
1519}
1520def : InstRW<[SPRWriteResGroup114], (instrs LOOPNE)>;
1521
1522def SPRWriteResGroup115 : SchedWriteRes<[SPRPort02_03, SPRPort02_03_11, SPRPort06]> {
1523  let Latency = 7;
1524  let NumMicroOps = 3;
1525}
1526def : InstRW<[SPRWriteResGroup115], (instrs LRET64)>;
1527
1528def SPRWriteResGroup116 : SchedWriteRes<[SPRPort00, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort05]> {
1529  let ReleaseAtCycles = [1, 5, 3, 3, 1];
1530  let Latency = 70;
1531  let NumMicroOps = 13;
1532}
1533def : InstRW<[SPRWriteResGroup116], (instregex "^LSL(16|32|64)rm$")>;
1534
1535def SPRWriteResGroup117 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort05]> {
1536  let ReleaseAtCycles = [1, 4, 4, 3, 2, 1];
1537  let Latency = 63;
1538  let NumMicroOps = 15;
1539}
1540def : InstRW<[SPRWriteResGroup117], (instregex "^LSL(16|32|64)rr$")>;
1541
1542def SPRWriteResGroup118 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_11, SPRPort05]> {
1543  let Latency = 24;
1544  let NumMicroOps = 3;
1545}
1546def : InstRW<[SPRWriteResGroup118], (instregex "^MMX_CVT(T?)PD2PIrm$")>;
1547
1548def SPRWriteResGroup119 : SchedWriteRes<[SPRPort00_01, SPRPort05]> {
1549  let Latency = 8;
1550  let NumMicroOps = 2;
1551}
1552def : InstRW<[SPRWriteResGroup119], (instregex "^MMX_CVT(T?)PD2PIrr$",
1553                                               "^VCVT(T?)PH2(U?)DQZ(128|256)rr$",
1554                                               "^VCVTP(H2PS|S2PH)XZ256rr$")>;
1555
1556def SPRWriteResGroup120 : SchedWriteRes<[SPRPort00_01, SPRPort05]> {
1557  let Latency = 6;
1558  let NumMicroOps = 2;
1559}
1560def : InstRW<[SPRWriteResGroup120], (instregex "^VCVTP(H2PS|S2PH)XZ128rr$",
1561                                               "^VPERMWZ(128|256)rrk(z?)$",
1562                                               "^VPS(L|R)LWZ256rrk(z?)$",
1563                                               "^VPSRAWZ256rrk(z?)$")>;
1564def : InstRW<[SPRWriteResGroup120], (instrs MMX_CVTPI2PDrr)>;
1565
1566def SPRWriteResGroup121 : SchedWriteRes<[SPRPort00, SPRPort00_01]> {
1567  let Latency = 7;
1568  let NumMicroOps = 2;
1569}
1570def : InstRW<[SPRWriteResGroup121], (instrs MMX_CVTPI2PSrr)>;
1571
1572def SPRWriteResGroup122 : SchedWriteRes<[SPRPort00, SPRPort02_03_11]> {
1573  let Latency = 13;
1574  let NumMicroOps = 2;
1575}
1576def : InstRW<[SPRWriteResGroup122], (instregex "^MMX_CVT(T?)PS2PIrm$")>;
1577
1578def SPRWriteResGroup123 : SchedWriteRes<[SPRPort00, SPRPort00_01_05]> {
1579  let Latency = 9;
1580  let NumMicroOps = 2;
1581}
1582def : InstRW<[SPRWriteResGroup123], (instregex "^MMX_CVT(T?)PS2PIrr$")>;
1583
1584def SPRWriteResGroup124 : SchedWriteRes<[SPRPort00, SPRPort04_09, SPRPort07_08]> {
1585  let ReleaseAtCycles = [2, 1, 1];
1586  let Latency = 12;
1587  let NumMicroOps = 4;
1588}
1589def : InstRW<[SPRWriteResGroup124], (instregex "^MMX_MASKMOVQ((64)?)$")>;
1590
1591def SPRWriteResGroup125 : SchedWriteRes<[SPRPort04_09, SPRPort07_08]> {
1592  let Latency = 18;
1593  let NumMicroOps = 2;
1594}
1595def : InstRW<[SPRWriteResGroup125], (instregex "^VMOV(W|SHZ)mr$")>;
1596def : InstRW<[SPRWriteResGroup125], (instrs MMX_MOVD64mr)>;
1597
1598def SPRWriteResGroup126 : SchedWriteRes<[SPRPort02_03_11]> {
1599  let Latency = 8;
1600}
1601def : InstRW<[SPRWriteResGroup126], (instregex "^MMX_MOV(D|Q)64rm$",
1602                                               "^VBROADCAST(F|I)128rm$",
1603                                               "^VBROADCAST(F|I)32X(2|4)Z256rm$",
1604                                               "^VBROADCAST(F|I)32X(8|2Z)rm$",
1605                                               "^VBROADCAST(F|I)(32|64)X4rm$",
1606                                               "^VBROADCAST(F|I)64X2((Z128)?)rm$",
1607                                               "^VBROADCASTS(DY|SZ)rm$",
1608                                               "^VBROADCASTS(D|S)Z256rm$",
1609                                               "^VBROADCASTS(DZ|SY)rm$",
1610                                               "^VMOV(D|SH|SL)DUP(Y|Z)rm$",
1611                                               "^VMOV(D|SH|SL)DUPZ256rm$",
1612                                               "^VPBROADCAST(DY|QZ)rm$",
1613                                               "^VPBROADCAST(D|Q)Z256rm$",
1614                                               "^VPBROADCAST(DZ|QY)rm$")>;
1615def : InstRW<[SPRWriteResGroup126], (instrs MMX_MOVD64to64rm)>;
1616
1617def SPRWriteResGroup127 : SchedWriteRes<[SPRPort00_01_05, SPRPort00_05]> {
1618  let Latency = 3;
1619  let NumMicroOps = 2;
1620}
1621def : InstRW<[SPRWriteResGroup127], (instregex "^MMX_MOV(DQ|FR64)2Qrr$")>;
1622
1623def SPRWriteResGroup128 : SchedWriteRes<[SPRPort00, SPRPort00_01_05]> {
1624  let Latency = 3;
1625  let NumMicroOps = 2;
1626}
1627def : InstRW<[SPRWriteResGroup128], (instregex "^MMX_MOVQ2(DQ|FR64)rr$")>;
1628
1629def SPRWriteResGroup129 : SchedWriteRes<[SPRPort02_03_11, SPRPort05]> {
1630  let ReleaseAtCycles = [1, 2];
1631  let Latency = 12;
1632  let NumMicroOps = 3;
1633}
1634def : InstRW<[SPRWriteResGroup129, ReadAfterVecLd], (instregex "^MMX_PACKSS(DW|WB)rm$")>;
1635def : InstRW<[SPRWriteResGroup129, ReadAfterVecLd], (instrs MMX_PACKUSWBrm)>;
1636
1637def SPRWriteResGroup130 : SchedWriteRes<[SPRPort05]> {
1638  let ReleaseAtCycles = [2];
1639  let Latency = 4;
1640  let NumMicroOps = 2;
1641}
1642def : InstRW<[SPRWriteResGroup130], (instregex "^MMX_PACKSS(DW|WB)rr$",
1643                                               "^VPMOV(D|Q|W|SQ|SW)BZrr$",
1644                                               "^VPMOV((S|US)?)(D|Q)WZrr$",
1645                                               "^VPMOV(U?)S(DB|QD)Zrr$",
1646                                               "^VPMOV(U?)SQDZrrk(z?)$",
1647                                               "^VPMOVUS(Q|W)BZrr$")>;
1648def : InstRW<[SPRWriteResGroup130], (instrs MMX_PACKUSWBrr)>;
1649def : InstRW<[SPRWriteResGroup130, ReadDefault, ReadInt2Fpu], (instrs MMX_PINSRWrr)>;
1650
1651def SPRWriteResGroup131 : SchedWriteRes<[SPRPort00_05, SPRPort02_03_11]> {
1652  let Latency = 9;
1653  let NumMicroOps = 2;
1654}
1655def : InstRW<[SPRWriteResGroup131], (instregex "^VBROADCAST(F|I)32X(8|2Z)rmk(z?)$",
1656                                               "^VBROADCAST(F|I)(32|64)X4rmk(z?)$",
1657                                               "^VBROADCAST(F|I)64X2rmk(z?)$",
1658                                               "^VBROADCASTS(D|S)Zrmk(z?)$",
1659                                               "^VMOV(A|U)P(D|S)Zrmk(z?)$",
1660                                               "^VMOV(D|SH|SL)DUPZrmk(z?)$",
1661                                               "^VMOVDQ(A|U)(32|64)Zrmk(z?)$",
1662                                               "^VPBROADCAST(D|Q)Zrmk(z?)$")>;
1663def : InstRW<[SPRWriteResGroup131, ReadAfterVecLd], (instregex "^MMX_P(ADD|SUB)(B|D|Q|W)rm$")>;
1664def : InstRW<[SPRWriteResGroup131, ReadAfterVecYLd], (instregex "^VINSERT(F|I)(32|64)x4Zrm((k|kz)?)$",
1665                                                                "^VINSERT(F|I)(32x8|64x2)Zrm((k|kz)?)$",
1666                                                                "^VP(ADD|SUB)(B|D|Q|W)Zrm$",
1667                                                                "^VP(ADD|SUB)(D|Q)Zrm(b|k|kz)$",
1668                                                                "^VP(ADD|SUB)(D|Q)Zrmbk(z?)$",
1669                                                                "^VPTERNLOG(D|Q)Zrm(bi|ik)$",
1670                                                                "^VPTERNLOG(D|Q)Zrmbik(z?)$",
1671                                                                "^VPTERNLOG(D|Q)Zrmi((kz)?)$")>;
1672
1673def SPRWriteResGroup132 : SchedWriteRes<[SPRPort00, SPRPort02_03_11, SPRPort05]> {
1674  let ReleaseAtCycles = [1, 1, 2];
1675  let Latency = 11;
1676  let NumMicroOps = 4;
1677}
1678def : InstRW<[SPRWriteResGroup132, ReadAfterVecLd], (instregex "^MMX_PH(ADD|SUB)SWrm$")>;
1679
1680def SPRWriteResGroup133 : SchedWriteRes<[SPRPort00, SPRPort05]> {
1681  let ReleaseAtCycles = [1, 2];
1682  let Latency = 3;
1683  let NumMicroOps = 3;
1684}
1685def : InstRW<[SPRWriteResGroup133], (instregex "^MMX_PH(ADD|SUB)SWrr$")>;
1686
1687def SPRWriteResGroup134 : SchedWriteRes<[SPRPort02_03_11, SPRPort05]> {
1688  let Latency = 9;
1689  let NumMicroOps = 2;
1690}
1691def : InstRW<[SPRWriteResGroup134], (instregex "^VPBROADCAST(BY|WZ)rm$",
1692                                               "^VPBROADCAST(B|W)Z256rm$",
1693                                               "^VPBROADCAST(BZ|WY)rm$")>;
1694def : InstRW<[SPRWriteResGroup134, ReadAfterLd], (instrs MMX_PINSRWrm)>;
1695def : InstRW<[SPRWriteResGroup134, ReadAfterVecXLd], (instregex "^VFPCLASSP(D|S)Z128rm$")>;
1696def : InstRW<[SPRWriteResGroup134, ReadAfterVecLd], (instregex "^VFPCLASSS(D|H|S)Zrm$")>;
1697def : InstRW<[SPRWriteResGroup134, ReadAfterVecYLd], (instregex "^VPALIGNR(Y|Z256)rmi$")>;
1698def : InstRW<[SPRWriteResGroup134, ReadAfterVecYLd], (instrs VPSHUFBZrm)>;
1699
1700def SPRWriteResGroup135 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort02_03_11]> {
1701  let Latency = 5;
1702  let NumMicroOps = 2;
1703}
1704def : InstRW<[SPRWriteResGroup135], (instregex "^MOV16ao(16|32|64)$")>;
1705
1706def SPRWriteResGroup136 : SchedWriteRes<[SPRPort01, SPRPort04_09, SPRPort07_08]> {
1707  let Latency = 12;
1708  let NumMicroOps = 3;
1709}
1710def : InstRW<[SPRWriteResGroup136], (instregex "^PUSH(F|G)S(16|32)$")>;
1711def : InstRW<[SPRWriteResGroup136], (instrs MOV16ms,
1712                                            MOVBE32mr)>;
1713
1714def SPRWriteResGroup137 : SchedWriteRes<[SPRPort00_01_05_06_10]>;
1715def : InstRW<[SPRWriteResGroup137], (instregex "^MOV(8|16|32|64)ri$",
1716                                               "^MOV(8|16|32)ri_alt$",
1717                                               "^MOV(8|16)rr((_REV)?)$")>;
1718def : InstRW<[SPRWriteResGroup137], (instrs MOV64ri32,
1719                                            MOV8rr_NOREX)>;
1720
1721def SPRWriteResGroup138 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort01]> {
1722  let NumMicroOps = 2;
1723}
1724def : InstRW<[SPRWriteResGroup138], (instregex "^MOV(16|32|64)rs$",
1725                                               "^S(TR|LDT)16r$")>;
1726
1727def SPRWriteResGroup139 : SchedWriteRes<[SPRPort02_03_11]>;
1728def : InstRW<[SPRWriteResGroup139], (instregex "^MOV32ao(16|32|64)$")>;
1729def : InstRW<[SPRWriteResGroup139], (instrs MOV64ao64)>;
1730
1731def SPRWriteResGroup140 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort04_09, SPRPort07_08]> {
1732  let NumMicroOps = 3;
1733}
1734def : InstRW<[SPRWriteResGroup140], (instregex "^MOV(8|32)o(16|32)a$",
1735                                               "^MOV(8|32|64)o64a$")>;
1736
1737def SPRWriteResGroup141 : SchedWriteRes<[SPRPort00_01_05_06_10]> {
1738  let Latency = 0;
1739}
1740def : InstRW<[SPRWriteResGroup141], (instregex "^MOV32rr((_REV)?)$",
1741                                               "^MOVZX(32|64)rr8$")>;
1742def : InstRW<[SPRWriteResGroup141], (instrs MOVZX32rr8_NOREX)>;
1743
1744def SPRWriteResGroup142 : SchedWriteRes<[SPRPort02_03_11]> {
1745  let Latency = 5;
1746}
1747def : InstRW<[SPRWriteResGroup142], (instrs MOV64ao32)>;
1748
1749def SPRWriteResGroup143 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort01_05_10, SPRPort04_09, SPRPort05, SPRPort07_08]> {
1750  let ReleaseAtCycles = [1, 2, 4, 16, 7, 2, 2, 12, 2];
1751  let Latency = 217;
1752  let NumMicroOps = 48;
1753}
1754def : InstRW<[SPRWriteResGroup143], (instrs MOV64dr)>;
1755
1756def SPRWriteResGroup144 : SchedWriteRes<[SPRPort04_09, SPRPort07_08]> {
1757  let Latency = 12;
1758  let NumMicroOps = 2;
1759}
1760def : InstRW<[SPRWriteResGroup144], (instrs MOV64o32a)>;
1761
1762def SPRWriteResGroup145 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06, SPRPort05]> {
1763  let Latency = SapphireRapidsModel.MaxLatency;
1764  let NumMicroOps = 3;
1765}
1766def : InstRW<[SPRWriteResGroup145], (instrs MOV64rc)>;
1767
1768def SPRWriteResGroup146 : SchedWriteRes<[SPRPort00_01_05, SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort01_05_10, SPRPort05]> {
1769  let ReleaseAtCycles = [3, 4, 8, 4, 2, 3];
1770  let Latency = 181;
1771  let NumMicroOps = 24;
1772}
1773def : InstRW<[SPRWriteResGroup146], (instrs MOV64rd)>;
1774
1775def SPRWriteResGroup147 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort02_03_11]> {
1776  let NumMicroOps = 2;
1777}
1778def : InstRW<[SPRWriteResGroup147], (instregex "^MOV8ao(16|32|64)$")>;
1779
1780def SPRWriteResGroup148 : SchedWriteRes<[SPRPort00_06, SPRPort04_09, SPRPort07_08]> {
1781  let Latency = 12;
1782  let NumMicroOps = 3;
1783}
1784def : InstRW<[SPRWriteResGroup148], (instrs MOVBE16mr)>;
1785
1786def SPRWriteResGroup149 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06, SPRPort02_03_11]> {
1787  let Latency = 7;
1788  let NumMicroOps = 3;
1789}
1790def : InstRW<[SPRWriteResGroup149], (instrs MOVBE16rm)>;
1791
1792def SPRWriteResGroup150 : SchedWriteRes<[SPRPort01, SPRPort02_03_11]> {
1793  let Latency = 6;
1794  let NumMicroOps = 2;
1795}
1796def : InstRW<[SPRWriteResGroup150], (instrs MOVBE32rm)>;
1797
1798def SPRWriteResGroup151 : SchedWriteRes<[SPRPort00_06, SPRPort01, SPRPort04_09, SPRPort07_08]> {
1799  let Latency = 12;
1800  let NumMicroOps = 4;
1801}
1802def : InstRW<[SPRWriteResGroup151], (instrs MOVBE64mr,
1803                                            PUSHF16,
1804                                            SLDT16m,
1805                                            STRm)>;
1806
1807def SPRWriteResGroup152 : SchedWriteRes<[SPRPort00_06, SPRPort01, SPRPort02_03_11]> {
1808  let Latency = 7;
1809  let NumMicroOps = 3;
1810}
1811def : InstRW<[SPRWriteResGroup152], (instrs MOVBE64rm)>;
1812
1813def SPRWriteResGroup153 : SchedWriteRes<[SPRPort00_06, SPRPort02_03_11, SPRPort04_09, SPRPort07_08]> {
1814  let NumMicroOps = 4;
1815}
1816def : InstRW<[SPRWriteResGroup153], (instregex "^MOVDIR64B(16|32|64)$")>;
1817
1818def SPRWriteResGroup154 : SchedWriteRes<[SPRPort04_09, SPRPort07_08]> {
1819  let Latency = 511;
1820  let NumMicroOps = 2;
1821}
1822def : InstRW<[SPRWriteResGroup154], (instrs MOVDIRI32)>;
1823
1824def SPRWriteResGroup155 : SchedWriteRes<[SPRPort04_09, SPRPort07_08]> {
1825  let Latency = 514;
1826  let NumMicroOps = 2;
1827}
1828def : InstRW<[SPRWriteResGroup155], (instrs MOVDIRI64)>;
1829
1830def SPRWriteResGroup156 : SchedWriteRes<[SPRPort01_05, SPRPort02_03_11]> {
1831  let Latency = 8;
1832  let NumMicroOps = 2;
1833}
1834def : InstRW<[SPRWriteResGroup156, ReadAfterVecXLd], (instregex "^(V?)MOVLP(D|S)rm$",
1835                                                                "^(V?)SHUFP(D|S)rmi$",
1836                                                                "^VMOVLP(D|S)Z128rm$",
1837                                                                "^VSHUFP(D|S)Z128rm(bi|ik)$",
1838                                                                "^VSHUFP(D|S)Z128rmbik(z?)$",
1839                                                                "^VSHUFP(D|S)Z128rmi((kz)?)$")>;
1840
1841def SPRWriteResGroup157 : SchedWriteRes<[SPRPort04_09, SPRPort07_08]> {
1842  let Latency = 512;
1843  let NumMicroOps = 2;
1844}
1845def : InstRW<[SPRWriteResGroup157], (instrs MOVNTDQmr)>;
1846
1847def SPRWriteResGroup158 : SchedWriteRes<[SPRPort04_09, SPRPort07_08]> {
1848  let Latency = 518;
1849  let NumMicroOps = 2;
1850}
1851def : InstRW<[SPRWriteResGroup158], (instrs MOVNTImr)>;
1852
1853def SPRWriteResGroup159 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort02_03_11, SPRPort04_09, SPRPort07_08]> {
1854  let ReleaseAtCycles = [4, 1, 1, 1];
1855  let Latency = 8;
1856  let NumMicroOps = 7;
1857}
1858def : InstRW<[SPRWriteResGroup159], (instrs MOVSB)>;
1859
1860def SPRWriteResGroup160 : SchedWriteRes<[SPRPort00_01_05]>;
1861def : InstRW<[SPRWriteResGroup160], (instregex "^(V?)MOVS(D|S)rr((_REV)?)$",
1862                                               "^(V?)P(ADD|SUB)(B|D|Q|W)rr$",
1863                                               "^VMOV(A|U)P(D|S)Z(128|256)rrk(z?)((_REV)?)$",
1864                                               "^VMOVDQ(A|U)(32|64)Z128rrk(z?)((_REV)?)$",
1865                                               "^VMOVS(D|H|S)Zrr((_REV)?)$",
1866                                               "^VMOVS(D|S)Zrrk(z?)((_REV)?)$",
1867                                               "^VP(ADD|SUB)(B|D|Q|W)Yrr$",
1868                                               "^VP(ADD|SUB)(B|D|Q|W)Z(128|256)rr$",
1869                                               "^VP(ADD|SUB)(D|Q)Z(128|256)rrk(z?)$",
1870                                               "^VPMOVM2(D|Q)Z128rr$",
1871                                               "^VPTERNLOG(D|Q)Z(128|256)rri((k|kz)?)$")>;
1872def : InstRW<[SPRWriteResGroup160], (instrs VPBLENDDrri)>;
1873
1874def SPRWriteResGroup161 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort02_03_11, SPRPort04_09, SPRPort07_08]> {
1875  let ReleaseAtCycles = [4, 1, 1, 1];
1876  let Latency = 7;
1877  let NumMicroOps = 7;
1878}
1879def : InstRW<[SPRWriteResGroup161], (instregex "^MOVS(L|Q|W)$")>;
1880
1881def SPRWriteResGroup162 : SchedWriteRes<[SPRPort02_03_11]> {
1882  let Latency = 6;
1883}
1884def : InstRW<[SPRWriteResGroup162], (instregex "^MOVSX(16|32|64)rm(16|32)$",
1885                                               "^MOVSX(32|64)rm8$")>;
1886def : InstRW<[SPRWriteResGroup162], (instrs MOVSX32rm8_NOREX)>;
1887
1888def SPRWriteResGroup163 : SchedWriteRes<[SPRPort01_05_10, SPRPort02_03_11]> {
1889  let Latency = 6;
1890  let NumMicroOps = 2;
1891}
1892def : InstRW<[SPRWriteResGroup163], (instrs MOVSX16rm8)>;
1893
1894def SPRWriteResGroup164 : SchedWriteRes<[SPRPort01_05_10]>;
1895def : InstRW<[SPRWriteResGroup164], (instregex "^MOVSX(16|32|64)rr(8|16|32)$")>;
1896def : InstRW<[SPRWriteResGroup164], (instrs MOVSX32rr8_NOREX)>;
1897
1898def SPRWriteResGroup165 : SchedWriteRes<[SPRPort00, SPRPort02_03_11]> {
1899  let Latency = 11;
1900  let NumMicroOps = 2;
1901}
1902def : InstRW<[SPRWriteResGroup165], (instregex "^MUL_F(32|64)m$",
1903                                               "^VPABS(B|W)Zrmk(z?)$",
1904                                               "^VPS(L|R)LWZmik(z?)$",
1905                                               "^VPSRAWZmik(z?)$")>;
1906def : InstRW<[SPRWriteResGroup165, ReadAfterVecYLd], (instregex "^VP(ADD|SUB)(U?)S(B|W)Zrmk(z?)$",
1907                                                                "^VPAVG(B|W)Zrmk(z?)$",
1908                                                                "^VPM(AX|IN)(SB|UW)Zrmk(z?)$",
1909                                                                "^VPM(AX|IN)(SW|UB)Zrmk(z?)$",
1910                                                                "^VPSH(L|R)DVWZmk(z?)$",
1911                                                                "^VPS(L|R)L(V?)WZrmk(z?)$",
1912                                                                "^VPSRA(V?)WZrmk(z?)$")>;
1913
1914def SPRWriteResGroup166 : SchedWriteRes<[SPRPort00, SPRPort02_03_11, SPRPort05]> {
1915  let Latency = 14;
1916  let NumMicroOps = 3;
1917}
1918def : InstRW<[SPRWriteResGroup166], (instregex "^MUL_FI(16|32)m$")>;
1919
1920def SPRWriteResGroup167 : SchedWriteRes<[SPRPort00]> {
1921  let Latency = 4;
1922}
1923def : InstRW<[SPRWriteResGroup167], (instregex "^MUL_F(P?)rST0$",
1924                                               "^V(U?)COMISHZrr(b?)$",
1925                                               "^V(U?)COMISHZrr_Int$",
1926                                               "^VCVT(T?)PD2(U?)QQZrr((b|k|bk|kz)?)$",
1927                                               "^VCVT(T?)PD2(U?)QQZrrbkz$",
1928                                               "^VCVT(T?)PS2(U?)DQZrr((b|k|bk|kz)?)$",
1929                                               "^VCVT(T?)PS2(U?)DQZrrbkz$",
1930                                               "^VM(AX|IN)(C?)PSZrr((k|kz)?)$",
1931                                               "^VM(AX|IN)PSZrrb((k|kz)?)$",
1932                                               "^VPLZCNT(D|Q)Zrr((k|kz)?)$",
1933                                               "^VPMADD52(H|L)UQZr((k|kz)?)$")>;
1934def : InstRW<[SPRWriteResGroup167], (instrs MUL_FST0r)>;
1935
1936def SPRWriteResGroup168 : SchedWriteRes<[SPRPort00_01_05_06, SPRPort05, SPRPort06]> {
1937  let ReleaseAtCycles = [7, 1, 2];
1938  let Latency = 20;
1939  let NumMicroOps = 10;
1940}
1941def : InstRW<[SPRWriteResGroup168], (instrs MWAITrr)>;
1942
1943def SPRWriteResGroup169 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort00_05, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort04_09, SPRPort05, SPRPort07_08]> {
1944  let ReleaseAtCycles = [6, 4, 1, 28, 15, 7, 1, 16, 1];
1945  let Latency = 35;
1946  let NumMicroOps = 79;
1947}
1948def : InstRW<[SPRWriteResGroup169], (instrs OUT16ir)>;
1949
1950def SPRWriteResGroup170 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort04_09, SPRPort05, SPRPort07_08]> {
1951  let ReleaseAtCycles = [6, 6, 27, 15, 7, 1, 16, 1];
1952  let Latency = 35;
1953  let NumMicroOps = 79;
1954}
1955def : InstRW<[SPRWriteResGroup170], (instrs OUT16rr)>;
1956
1957def SPRWriteResGroup171 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort00_05, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort04_09, SPRPort05, SPRPort07_08]> {
1958  let ReleaseAtCycles = [6, 4, 1, 30, 15, 9, 1, 18, 1];
1959  let Latency = 35;
1960  let NumMicroOps = 85;
1961}
1962def : InstRW<[SPRWriteResGroup171], (instrs OUT32ir)>;
1963
1964def SPRWriteResGroup172 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort04_09, SPRPort05, SPRPort07_08]> {
1965  let ReleaseAtCycles = [6, 6, 29, 15, 9, 1, 18, 1];
1966  let Latency = 35;
1967  let NumMicroOps = 85;
1968}
1969def : InstRW<[SPRWriteResGroup172], (instrs OUT32rr)>;
1970
1971def SPRWriteResGroup173 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort00_05, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort04_09, SPRPort05, SPRPort07_08]> {
1972  let ReleaseAtCycles = [5, 5, 1, 25, 15, 5, 1, 15, 1];
1973  let Latency = 35;
1974  let NumMicroOps = 73;
1975}
1976def : InstRW<[SPRWriteResGroup173], (instrs OUT8ir)>;
1977
1978def SPRWriteResGroup174 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort04_09, SPRPort05, SPRPort07_08]> {
1979  let ReleaseAtCycles = [5, 5, 26, 15, 5, 1, 15, 1];
1980  let Latency = 35;
1981  let NumMicroOps = 73;
1982}
1983def : InstRW<[SPRWriteResGroup174], (instrs OUT8rr)>;
1984
1985def SPRWriteResGroup175 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort04_09, SPRPort05, SPRPort07_08]> {
1986  let ReleaseAtCycles = [7, 6, 25, 16, 7, 1, 17, 1];
1987  let Latency = SapphireRapidsModel.MaxLatency;
1988  let NumMicroOps = 80;
1989}
1990def : InstRW<[SPRWriteResGroup175], (instrs OUTSB)>;
1991
1992def SPRWriteResGroup176 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort04_09, SPRPort05, SPRPort07_08]> {
1993  let ReleaseAtCycles = [7, 6, 28, 16, 10, 1, 20, 1];
1994  let Latency = SapphireRapidsModel.MaxLatency;
1995  let NumMicroOps = 89;
1996}
1997def : InstRW<[SPRWriteResGroup176], (instrs OUTSL)>;
1998
1999def SPRWriteResGroup177 : SchedWriteRes<[SPRPort00, SPRPort00_01, SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort04_09, SPRPort05, SPRPort07_08]> {
2000  let ReleaseAtCycles = [6, 1, 5, 27, 16, 8, 1, 18, 1];
2001  let Latency = SapphireRapidsModel.MaxLatency;
2002  let NumMicroOps = 83;
2003}
2004def : InstRW<[SPRWriteResGroup177], (instrs OUTSW)>;
2005
2006def SPRWriteResGroup178 : SchedWriteRes<[SPRPort00_01_05, SPRPort02_03_11]> {
2007  let Latency = 8;
2008  let NumMicroOps = 2;
2009}
2010def : InstRW<[SPRWriteResGroup178], (instregex "^VBROADCASTI32X2Z128rmk(z?)$",
2011                                               "^VBROADCASTSSZ128rmk(z?)$",
2012                                               "^VMOV(A|U)P(D|S)Z128rmk(z?)$",
2013                                               "^VMOV(D|SH|SL)DUPZ128rmk(z?)$",
2014                                               "^VMOVDQ(A|U)(32|64)Z128rmk(z?)$",
2015                                               "^VMOVS(D|S)Zrmk(z?)$",
2016                                               "^VPBROADCAST(D|Q)Z128rmk(z?)$")>;
2017def : InstRW<[SPRWriteResGroup178, ReadAfterVecXLd], (instregex "^(V?)P(ADD|SUB)(B|D|Q|W)rm$",
2018                                                                "^VP(ADD|SUB)(B|D|Q|W)Z128rm$",
2019                                                                "^VP(ADD|SUB)(D|Q)Z128rm(b|k|kz)$",
2020                                                                "^VP(ADD|SUB)(D|Q)Z128rmbk(z?)$",
2021                                                                "^VPTERNLOG(D|Q)Z128rm(bi|ik)$",
2022                                                                "^VPTERNLOG(D|Q)Z128rmbik(z?)$",
2023                                                                "^VPTERNLOG(D|Q)Z128rmi((kz)?)$")>;
2024def : InstRW<[SPRWriteResGroup178, ReadAfterVecXLd], (instrs VPBLENDDrmi)>;
2025
2026def SPRWriteResGroup179 : SchedWriteRes<[SPRPort02_03_11, SPRPort05]> {
2027  let Latency = 8;
2028  let NumMicroOps = 2;
2029}
2030def : InstRW<[SPRWriteResGroup179], (instregex "^VPBROADCAST(B|W)((Z128)?)rm$")>;
2031def : InstRW<[SPRWriteResGroup179, ReadAfterVecXLd], (instregex "^(V?)PALIGNRrmi$",
2032                                                                "^VALIGN(D|Q)Z128rm(bi|ik)$",
2033                                                                "^VALIGN(D|Q)Z128rmbik(z?)$",
2034                                                                "^VALIGN(D|Q)Z128rmi((kz)?)$")>;
2035def : InstRW<[SPRWriteResGroup179, ReadAfterVecXLd], (instrs VPALIGNRZ128rmi)>;
2036
2037def SPRWriteResGroup180 : SchedWriteRes<[SPRPort00_06, SPRPort05]> {
2038  let Latency = 140;
2039  let NumMicroOps = 2;
2040}
2041def : InstRW<[SPRWriteResGroup180], (instrs PAUSE)>;
2042
2043def SPRWriteResGroup181 : SchedWriteRes<[SPRPort01, SPRPort02_03_11]> {
2044  let Latency = 8;
2045  let NumMicroOps = 2;
2046}
2047def : InstRW<[SPRWriteResGroup181, ReadAfterLd], (instregex "^P(DEP|EXT)(32|64)rm$")>;
2048
2049def SPRWriteResGroup182 : SchedWriteRes<[SPRPort01_05, SPRPort04_09, SPRPort07_08]> {
2050  let Latency = 12;
2051  let NumMicroOps = 3;
2052}
2053def : InstRW<[SPRWriteResGroup182], (instregex "^(V?)PEXTR(D|Q)mr$",
2054                                               "^VPEXTR(D|Q)Zmr$",
2055                                               "^VPMOVQDZ128mr(k?)$")>;
2056
2057def SPRWriteResGroup183 : SchedWriteRes<[SPRPort00_01, SPRPort01_05, SPRPort02_03_11]> {
2058  let ReleaseAtCycles = [1, 2, 1];
2059  let Latency = 9;
2060  let NumMicroOps = 4;
2061}
2062def : InstRW<[SPRWriteResGroup183, ReadAfterVecXLd], (instregex "^(V?)PH(ADD|SUB)SWrm$")>;
2063
2064def SPRWriteResGroup184 : SchedWriteRes<[SPRPort00_01, SPRPort01_05]> {
2065  let ReleaseAtCycles = [1, 2];
2066  let Latency = 2;
2067  let NumMicroOps = 3;
2068}
2069def : InstRW<[SPRWriteResGroup184], (instregex "^(V?)PH(ADD|SUB)SWrr$",
2070                                               "^VPH(ADD|SUB)SWYrr$")>;
2071
2072def SPRWriteResGroup185 : SchedWriteRes<[SPRPort02_03_11, SPRPort04_09, SPRPort07_08]> {
2073  let Latency = 12;
2074  let NumMicroOps = 3;
2075}
2076def : InstRW<[SPRWriteResGroup185], (instregex "^POP(16|32|64)rmm$",
2077                                               "^PUSH(16|32)rmm$")>;
2078
2079def SPRWriteResGroup186 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort02_03_11]> {
2080  let ReleaseAtCycles = [6, 2, 1, 1];
2081  let Latency = 5;
2082  let NumMicroOps = 10;
2083}
2084def : InstRW<[SPRWriteResGroup186], (instrs POPF16)>;
2085
2086def SPRWriteResGroup187 : SchedWriteRes<[SPRPort00_06, SPRPort01, SPRPort02_03_11]> {
2087  let ReleaseAtCycles = [2, 1, 1];
2088  let Latency = 5;
2089  let NumMicroOps = 7;
2090}
2091def : InstRW<[SPRWriteResGroup187], (instrs POPF64)>;
2092
2093def SPRWriteResGroup188 : SchedWriteRes<[SPRPort02_03_11]> {
2094  let Latency = 0;
2095}
2096def : InstRW<[SPRWriteResGroup188], (instregex "^PREFETCHT(0|1|2)$")>;
2097def : InstRW<[SPRWriteResGroup188], (instrs PREFETCHNTA)>;
2098
2099def SPRWriteResGroup189 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort02_03_11, SPRPort06]> {
2100  let ReleaseAtCycles = [1, 1, 2];
2101  let Latency = SapphireRapidsModel.MaxLatency;
2102  let NumMicroOps = 4;
2103}
2104def : InstRW<[SPRWriteResGroup189], (instregex "^PTWRITE((64)?)m$")>;
2105
2106def SPRWriteResGroup190 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort06]> {
2107  let ReleaseAtCycles = [1, 2];
2108  let Latency = SapphireRapidsModel.MaxLatency;
2109  let NumMicroOps = 3;
2110}
2111def : InstRW<[SPRWriteResGroup190], (instrs PTWRITE64r)>;
2112
2113def SPRWriteResGroup191 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort06]> {
2114  let ReleaseAtCycles = [2, 2];
2115  let Latency = SapphireRapidsModel.MaxLatency;
2116  let NumMicroOps = 4;
2117}
2118def : InstRW<[SPRWriteResGroup191], (instrs PTWRITEr)>;
2119
2120def SPRWriteResGroup192 : SchedWriteRes<[SPRPort04_09, SPRPort07_08]> {
2121  let NumMicroOps = 2;
2122}
2123def : InstRW<[SPRWriteResGroup192], (instregex "^PUSH64r((mr)?)$")>;
2124
2125def SPRWriteResGroup193 : SchedWriteRes<[SPRPort02_03_11, SPRPort04_09, SPRPort07_08]> {
2126  let NumMicroOps = 3;
2127}
2128def : InstRW<[SPRWriteResGroup193], (instrs PUSH64rmm)>;
2129
2130def SPRWriteResGroup194 : SchedWriteRes<[SPRPort00_06, SPRPort01, SPRPort04_09, SPRPort07_08]> {
2131  let Latency = 4;
2132  let NumMicroOps = 4;
2133}
2134def : InstRW<[SPRWriteResGroup194], (instrs PUSHF64)>;
2135
2136def SPRWriteResGroup195 : SchedWriteRes<[SPRPort01, SPRPort04_09, SPRPort07_08]> {
2137  let NumMicroOps = 3;
2138}
2139def : InstRW<[SPRWriteResGroup195], (instregex "^PUSH(F|G)S64$")>;
2140
2141def SPRWriteResGroup196 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01]> {
2142  let ReleaseAtCycles = [2, 3, 2];
2143  let Latency = 8;
2144  let NumMicroOps = 7;
2145}
2146def : InstRW<[SPRWriteResGroup196], (instregex "^RC(L|R)(16|32|64)rCL$")>;
2147
2148def SPRWriteResGroup197 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06]> {
2149  let ReleaseAtCycles = [1, 2];
2150  let Latency = 13;
2151  let NumMicroOps = 3;
2152}
2153def : InstRW<[SPRWriteResGroup197, WriteRMW], (instregex "^RC(L|R)8m(1|i)$")>;
2154
2155def SPRWriteResGroup198 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01]> {
2156  let ReleaseAtCycles = [1, 5, 2];
2157  let Latency = 20;
2158  let NumMicroOps = 8;
2159}
2160def : InstRW<[SPRWriteResGroup198, WriteRMW], (instrs RCL8mCL)>;
2161
2162def SPRWriteResGroup199 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01]> {
2163  let ReleaseAtCycles = [2, 5, 2];
2164  let Latency = 7;
2165  let NumMicroOps = 9;
2166}
2167def : InstRW<[SPRWriteResGroup199], (instrs RCL8rCL)>;
2168
2169def SPRWriteResGroup200 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01]> {
2170  let ReleaseAtCycles = [2, 4, 3];
2171  let Latency = 20;
2172  let NumMicroOps = 9;
2173}
2174def : InstRW<[SPRWriteResGroup200, WriteRMW], (instrs RCR8mCL)>;
2175
2176def SPRWriteResGroup201 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01]> {
2177  let ReleaseAtCycles = [3, 4, 3];
2178  let Latency = 9;
2179  let NumMicroOps = 10;
2180}
2181def : InstRW<[SPRWriteResGroup201], (instrs RCR8rCL)>;
2182
2183def SPRWriteResGroup202 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_05, SPRPort00_05_06, SPRPort00_06, SPRPort01, SPRPort01_05, SPRPort01_05_10, SPRPort05]> {
2184  let ReleaseAtCycles = [1, 6, 1, 10, 20, 8, 5, 1, 2];
2185  let Latency = SapphireRapidsModel.MaxLatency;
2186  let NumMicroOps = 54;
2187}
2188def : InstRW<[SPRWriteResGroup202], (instrs RDMSR)>;
2189
2190def SPRWriteResGroup203 : SchedWriteRes<[SPRPort01]> {
2191  let Latency = SapphireRapidsModel.MaxLatency;
2192}
2193def : InstRW<[SPRWriteResGroup203], (instrs RDPID64)>;
2194
2195def SPRWriteResGroup204 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01]> {
2196  let Latency = SapphireRapidsModel.MaxLatency;
2197  let NumMicroOps = 3;
2198}
2199def : InstRW<[SPRWriteResGroup204], (instrs RDPKRUr)>;
2200
2201def SPRWriteResGroup205 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort05]> {
2202  let ReleaseAtCycles = [9, 6, 2, 1];
2203  let Latency = SapphireRapidsModel.MaxLatency;
2204  let NumMicroOps = 18;
2205}
2206def : InstRW<[SPRWriteResGroup205], (instrs RDPMC)>;
2207
2208def SPRWriteResGroup206 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort00_05_06, SPRPort00_06, SPRPort01, SPRPort01_05, SPRPort02_03_11, SPRPort05]> {
2209  let ReleaseAtCycles = [2, 3, 2, 5, 7, 3, 1, 2];
2210  let Latency = 1386;
2211  let NumMicroOps = 25;
2212}
2213def : InstRW<[SPRWriteResGroup206], (instrs RDRAND16r)>;
2214
2215def SPRWriteResGroup207 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort00_05_06, SPRPort00_06, SPRPort01, SPRPort01_05, SPRPort02_03_11, SPRPort05]> {
2216  let ReleaseAtCycles = [2, 3, 2, 5, 7, 3, 1, 2];
2217  let Latency = SapphireRapidsModel.MaxLatency;
2218  let NumMicroOps = 25;
2219}
2220def : InstRW<[SPRWriteResGroup207], (instregex "^RDRAND(32|64)r$")>;
2221
2222def SPRWriteResGroup208 : SchedWriteRes<[SPRPort00, SPRPort00_01_05, SPRPort00_05_06, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort05]> {
2223  let ReleaseAtCycles = [2, 3, 3, 5, 7, 1, 4];
2224  let Latency = 1381;
2225  let NumMicroOps = 25;
2226}
2227def : InstRW<[SPRWriteResGroup208], (instrs RDSEED16r)>;
2228
2229def SPRWriteResGroup209 : SchedWriteRes<[SPRPort00, SPRPort00_01_05, SPRPort00_05_06, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort05]> {
2230  let ReleaseAtCycles = [2, 3, 3, 5, 7, 1, 4];
2231  let Latency = SapphireRapidsModel.MaxLatency;
2232  let NumMicroOps = 25;
2233}
2234def : InstRW<[SPRWriteResGroup209], (instregex "^RDSEED(32|64)r$")>;
2235
2236def SPRWriteResGroup210 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort05]> {
2237  let ReleaseAtCycles = [5, 6, 3, 1];
2238  let Latency = 18;
2239  let NumMicroOps = 15;
2240}
2241def : InstRW<[SPRWriteResGroup210], (instrs RDTSC)>;
2242
2243def SPRWriteResGroup211 : SchedWriteRes<[SPRPort00, SPRPort00_01, SPRPort00_01_05, SPRPort00_05_06, SPRPort00_06, SPRPort01, SPRPort05]> {
2244  let ReleaseAtCycles = [2, 2, 1, 2, 7, 4, 3];
2245  let Latency = 42;
2246  let NumMicroOps = 21;
2247}
2248def : InstRW<[SPRWriteResGroup211], (instrs RDTSCP)>;
2249
2250def SPRWriteResGroup212 : SchedWriteRes<[SPRPort00_06, SPRPort02_03_11]> {
2251  let Latency = 7;
2252  let NumMicroOps = 2;
2253}
2254def : InstRW<[SPRWriteResGroup212], (instrs RET64)>;
2255
2256def SPRWriteResGroup213 : SchedWriteRes<[SPRPort00_06, SPRPort02_03_11]> {
2257  let ReleaseAtCycles = [2, 1];
2258  let Latency = 6;
2259  let NumMicroOps = 3;
2260}
2261def : InstRW<[SPRWriteResGroup213], (instregex "^RETI(16|32|64)$")>;
2262
2263def SPRWriteResGroup214 : SchedWriteRes<[]>;
2264def : InstRW<[SPRWriteResGroup214], (instrs REX64_PREFIX)>;
2265
2266def SPRWriteResGroup215 : SchedWriteRes<[SPRPort00_06]> {
2267  let ReleaseAtCycles = [2];
2268  let Latency = 12;
2269  let NumMicroOps = 2;
2270}
2271def : InstRW<[SPRWriteResGroup215, WriteRMW], (instregex "^RO(L|R)(16|32|64)m(1|i|CL)$")>;
2272
2273def SPRWriteResGroup216 : SchedWriteRes<[SPRPort00_06]> {
2274  let ReleaseAtCycles = [2];
2275  let NumMicroOps = 2;
2276}
2277def : InstRW<[SPRWriteResGroup216], (instregex "^RO(L|R)(8|16|32|64)r(1|i)$")>;
2278
2279def SPRWriteResGroup217 : SchedWriteRes<[SPRPort00_06]> {
2280  let ReleaseAtCycles = [2];
2281  let Latency = 13;
2282  let NumMicroOps = 2;
2283}
2284def : InstRW<[SPRWriteResGroup217, WriteRMW], (instregex "^RO(L|R)8m(1|i)$",
2285                                                         "^(RO|SH)L8mCL$",
2286                                                         "^(RO|SA|SH)R8mCL$")>;
2287
2288def SPRWriteResGroup218 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_11]> {
2289  let ReleaseAtCycles = [2, 1];
2290  let Latency = 15;
2291  let NumMicroOps = 3;
2292}
2293def : InstRW<[SPRWriteResGroup218], (instregex "^(V?)ROUNDP(D|S)m$")>;
2294def : InstRW<[SPRWriteResGroup218, ReadAfterVecXLd], (instregex "^(V?)ROUNDS(D|S)m((_Int)?)$",
2295                                                                "^VRNDSCALEP(D|S)Z128rm(bi|ik)$",
2296                                                                "^VRNDSCALEP(D|S)Z128rmbik(z?)$",
2297                                                                "^VRNDSCALEP(D|S)Z128rmi((kz)?)$",
2298                                                                "^VRNDSCALES(D|S)Zm$",
2299                                                                "^VRNDSCALES(D|S)Zm_Int((k|kz)?)$")>;
2300
2301def SPRWriteResGroup219 : SchedWriteRes<[SPRPort00_01]> {
2302  let ReleaseAtCycles = [2];
2303  let Latency = 8;
2304  let NumMicroOps = 2;
2305}
2306def : InstRW<[SPRWriteResGroup219], (instregex "^(V?)ROUND(PD|SS)r$",
2307                                               "^(V?)ROUND(PS|SD)r$",
2308                                               "^(V?)ROUNDS(D|S)r_Int$",
2309                                               "^VRNDSCALEP(D|S)Z(128|256)rri((k|kz)?)$",
2310                                               "^VRNDSCALES(D|S)Zr$",
2311                                               "^VRNDSCALES(D|S)Zr(b?)_Int((k|kz)?)$",
2312                                               "^VROUNDP(D|S)Yr$")>;
2313
2314def SPRWriteResGroup220 : SchedWriteRes<[SPRPort00_06]> {
2315  let ReleaseAtCycles = [2];
2316  let Latency = 4;
2317  let NumMicroOps = 2;
2318}
2319def : InstRW<[SPRWriteResGroup220], (instrs SAHF)>;
2320
2321def SPRWriteResGroup221 : SchedWriteRes<[SPRPort00_06]> {
2322  let Latency = 13;
2323}
2324def : InstRW<[SPRWriteResGroup221, WriteRMW], (instregex "^S(A|H)R8m(1|i)$",
2325                                                         "^SHL8m(1|i)$")>;
2326
2327def SPRWriteResGroup222 : SchedWriteRes<[SPRPort00_06, SPRPort02_03_11]> {
2328  let Latency = 8;
2329  let NumMicroOps = 2;
2330}
2331def : InstRW<[SPRWriteResGroup222, ReadAfterLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^S(A|H)RX(32|64)rm$",
2332                                                                                                                             "^SHLX(32|64)rm$")>;
2333
2334def SPRWriteResGroup223 : SchedWriteRes<[SPRPort00_06]> {
2335  let Latency = 3;
2336}
2337def : InstRW<[SPRWriteResGroup223], (instregex "^S(A|H)RX(32|64)rr$",
2338                                               "^SHLX(32|64)rr$")>;
2339
2340def SPRWriteResGroup224 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort04_09, SPRPort07_08]> {
2341  let ReleaseAtCycles = [2, 2, 1, 1, 1];
2342  let Latency = SapphireRapidsModel.MaxLatency;
2343  let NumMicroOps = 7;
2344}
2345def : InstRW<[SPRWriteResGroup224], (instrs SERIALIZE)>;
2346
2347def SPRWriteResGroup225 : SchedWriteRes<[SPRPort04_09, SPRPort07_08]> {
2348  let Latency = 2;
2349  let NumMicroOps = 2;
2350}
2351def : InstRW<[SPRWriteResGroup225], (instrs SFENCE)>;
2352
2353def SPRWriteResGroup226 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort01, SPRPort04_09, SPRPort07_08]> {
2354  let ReleaseAtCycles = [1, 2, 2, 2];
2355  let Latency = 21;
2356  let NumMicroOps = 7;
2357}
2358def : InstRW<[SPRWriteResGroup226], (instregex "^S(G|I)DT64m$")>;
2359
2360def SPRWriteResGroup227 : SchedWriteRes<[SPRPort00_01_05, SPRPort02_03_11, SPRPort05]> {
2361  let Latency = 9;
2362  let NumMicroOps = 3;
2363}
2364def : InstRW<[SPRWriteResGroup227, ReadAfterVecXLd], (instrs SHA1MSG1rm)>;
2365
2366def SPRWriteResGroup228 : SchedWriteRes<[SPRPort00_01_05, SPRPort05]> {
2367  let Latency = 2;
2368  let NumMicroOps = 2;
2369}
2370def : InstRW<[SPRWriteResGroup228], (instrs SHA1MSG1rr)>;
2371
2372def SPRWriteResGroup229 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_06, SPRPort01_05, SPRPort02_03_11]> {
2373  let ReleaseAtCycles = [2, 2, 1, 2, 1];
2374  let Latency = 13;
2375  let NumMicroOps = 8;
2376}
2377def : InstRW<[SPRWriteResGroup229, ReadAfterVecXLd], (instrs SHA1MSG2rm)>;
2378
2379def SPRWriteResGroup230 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_06, SPRPort01_05]> {
2380  let ReleaseAtCycles = [2, 2, 1, 2];
2381  let Latency = 6;
2382  let NumMicroOps = 7;
2383}
2384def : InstRW<[SPRWriteResGroup230], (instrs SHA1MSG2rr)>;
2385
2386def SPRWriteResGroup231 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort01_05, SPRPort02_03_11]> {
2387  let Latency = 8;
2388  let NumMicroOps = 4;
2389}
2390def : InstRW<[SPRWriteResGroup231, ReadAfterVecXLd], (instrs SHA1NEXTErm)>;
2391
2392def SPRWriteResGroup232 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort01_05]> {
2393  let Latency = 3;
2394  let NumMicroOps = 3;
2395}
2396def : InstRW<[SPRWriteResGroup232], (instrs SHA1NEXTErr)>;
2397
2398def SPRWriteResGroup233 : SchedWriteRes<[SPRPort02_03_11, SPRPort05]> {
2399  let Latency = 13;
2400  let NumMicroOps = 2;
2401}
2402def : InstRW<[SPRWriteResGroup233], (instregex "^VPMOV(S|Z)XBWZ((256)?)rmk(z?)$",
2403                                               "^VPOPCNT(B|W)Z(128|256)rmk(z?)$",
2404                                               "^VPOPCNT(B|W)Zrmk(z?)$")>;
2405def : InstRW<[SPRWriteResGroup233, ReadAfterVecXLd], (instregex "^VDBPSADBWZ128rmik(z?)$",
2406                                                                "^VPACK(S|U)SDWZ128rm(bk|kz)$",
2407                                                                "^VPACK(S|U)SDWZ128rmbkz$",
2408                                                                "^VPACK(S|U)S(DW|WB)Z128rmk$",
2409                                                                "^VPACK(S|U)SWBZ128rmkz$",
2410                                                                "^VPMULTISHIFTQBZ128rm(bk|kz)$",
2411                                                                "^VPMULTISHIFTQBZ128rm(k|bkz)$")>;
2412def : InstRW<[SPRWriteResGroup233, ReadAfterVecXLd], (instrs SHA1RNDS4rmi,
2413                                                             SHA256RNDS2rm)>;
2414def : InstRW<[SPRWriteResGroup233, ReadAfterVecYLd], (instregex "^VDBPSADBWZ((256)?)rmik(z?)$",
2415                                                                "^VPACK(S|U)SDWZ((256)?)rm(bk|kz)$",
2416                                                                "^VPACK(S|U)SDWZ((256)?)rmbkz$",
2417                                                                "^VPACK(S|U)S(DW|WB)Z((256)?)rmk$",
2418                                                                "^VPACK(S|U)SWBZ((256)?)rmkz$",
2419                                                                "^VPERMBZ(128|256)rmk(z?)$",
2420                                                                "^VPERMBZrmk(z?)$",
2421                                                                "^VPMULTISHIFTQBZ((256)?)rm(bk|kz)$",
2422                                                                "^VPMULTISHIFTQBZ((256)?)rm(k|bkz)$")>;
2423
2424def SPRWriteResGroup234 : SchedWriteRes<[SPRPort05]> {
2425  let Latency = 6;
2426}
2427def : InstRW<[SPRWriteResGroup234], (instrs SHA1RNDS4rri,
2428                                            SHA256RNDS2rr)>;
2429
2430def SPRWriteResGroup235 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_06, SPRPort02_03_11, SPRPort05]> {
2431  let ReleaseAtCycles = [3, 2, 1, 1, 1];
2432  let Latency = 12;
2433  let NumMicroOps = 8;
2434}
2435def : InstRW<[SPRWriteResGroup235, ReadAfterVecXLd], (instrs SHA256MSG1rm)>;
2436
2437def SPRWriteResGroup236 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_06, SPRPort05]> {
2438  let ReleaseAtCycles = [3, 2, 1, 1];
2439  let Latency = 5;
2440  let NumMicroOps = 7;
2441}
2442def : InstRW<[SPRWriteResGroup236], (instrs SHA256MSG1rr)>;
2443
2444def SPRWriteResGroup237 : SchedWriteRes<[SPRPort05]> {
2445  let ReleaseAtCycles = [2];
2446  let Latency = 6;
2447  let NumMicroOps = 2;
2448}
2449def : InstRW<[SPRWriteResGroup237], (instregex "^VPMOV(D|Q|W|SQ|SW)BZrrk(z?)$",
2450                                               "^VPMOV((S|US)?)(D|Q)WZrrk(z?)$",
2451                                               "^VPMOV(U?)SDBZrrk(z?)$",
2452                                               "^VPMOVUS(Q|W)BZrrk(z?)$")>;
2453def : InstRW<[SPRWriteResGroup237], (instrs SHA256MSG2rr)>;
2454
2455def SPRWriteResGroup238 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort01, SPRPort02_03_11, SPRPort04_09, SPRPort07_08]> {
2456  let Latency = 13;
2457  let NumMicroOps = 5;
2458}
2459def : InstRW<[SPRWriteResGroup238], (instrs SHRD16mri8)>;
2460
2461def SPRWriteResGroup239 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort01]> {
2462  let Latency = 6;
2463  let NumMicroOps = 2;
2464}
2465def : InstRW<[SPRWriteResGroup239], (instregex "^SLDT(32|64)r$")>;
2466
2467def SPRWriteResGroup240 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort05]> {
2468  let NumMicroOps = 2;
2469}
2470def : InstRW<[SPRWriteResGroup240], (instrs SMSW16r)>;
2471
2472def SPRWriteResGroup241 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort05]> {
2473  let Latency = SapphireRapidsModel.MaxLatency;
2474  let NumMicroOps = 2;
2475}
2476def : InstRW<[SPRWriteResGroup241], (instregex "^SMSW(32|64)r$")>;
2477
2478def SPRWriteResGroup242 : SchedWriteRes<[SPRPort00, SPRPort02_03_11]> {
2479  let Latency = 24;
2480  let NumMicroOps = 2;
2481}
2482def : InstRW<[SPRWriteResGroup242, ReadAfterVecLd], (instregex "^(V?)SQRTSDm_Int$")>;
2483def : InstRW<[SPRWriteResGroup242, ReadAfterVecLd], (instrs VSQRTSDZm_Int)>;
2484
2485def SPRWriteResGroup243 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06]> {
2486  let Latency = 6;
2487  let NumMicroOps = 2;
2488}
2489def : InstRW<[SPRWriteResGroup243], (instrs STD)>;
2490
2491def SPRWriteResGroup244 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01]> {
2492  let ReleaseAtCycles = [1, 4, 1];
2493  let Latency = SapphireRapidsModel.MaxLatency;
2494  let NumMicroOps = 6;
2495}
2496def : InstRW<[SPRWriteResGroup244], (instrs STI)>;
2497
2498def SPRWriteResGroup245 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort04_09, SPRPort07_08]> {
2499  let ReleaseAtCycles = [2, 1, 1];
2500  let Latency = 8;
2501  let NumMicroOps = 4;
2502}
2503def : InstRW<[SPRWriteResGroup245], (instrs STOSB)>;
2504
2505def SPRWriteResGroup246 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort04_09, SPRPort07_08]> {
2506  let ReleaseAtCycles = [2, 1, 1];
2507  let Latency = 7;
2508  let NumMicroOps = 4;
2509}
2510def : InstRW<[SPRWriteResGroup246], (instregex "^STOS(L|Q|W)$")>;
2511
2512def SPRWriteResGroup247 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort01]> {
2513  let Latency = 5;
2514  let NumMicroOps = 2;
2515}
2516def : InstRW<[SPRWriteResGroup247], (instregex "^STR(32|64)r$")>;
2517
2518def SPRWriteResGroup248 : SchedWriteRes<[SPRPort00]> {
2519  let Latency = 2;
2520}
2521def : InstRW<[SPRWriteResGroup248], (instregex "^(TST|XAM)_F$")>;
2522def : InstRW<[SPRWriteResGroup248], (instrs UCOM_FPPr)>;
2523
2524def SPRWriteResGroup249 : SchedWriteRes<[SPRPort01_05]> {
2525  let Latency = 4;
2526}
2527def : InstRW<[SPRWriteResGroup249], (instregex "^V(ADD|SUB)P(D|S)Z(128|256)rrkz$",
2528                                               "^V(ADD|SUB)S(D|S)Zrr(b?)_Intkz$")>;
2529
2530def SPRWriteResGroup250 : SchedWriteRes<[SPRPort00_05]> {
2531  let Latency = 3;
2532}
2533def : InstRW<[SPRWriteResGroup250], (instregex "^V(ADD|SUB)P(D|S)Zrr(b?)$",
2534                                               "^VMOVDQU(8|16)Zrrk(z?)((_REV)?)$",
2535                                               "^VP(ADD|SUB)(B|W)Zrrk(z?)$",
2536                                               "^VPBLENDM(B|W)Zrrk(z?)$",
2537                                               "^VPMOVM2(B|W)Zrr$")>;
2538
2539def SPRWriteResGroup251 : SchedWriteRes<[SPRPort00_01]> {
2540  let Latency = 6;
2541}
2542def : InstRW<[SPRWriteResGroup251], (instregex "^V(ADD|SUB)PHZ(128|256)rrk(z?)$",
2543                                               "^V(ADD|SUB)SHZrr(b?)_Intk(z?)$",
2544                                               "^VCVT(T?)PH2(U?)WZ(128|256)rrk(z?)$",
2545                                               "^VCVT(U?)W2PHZ(128|256)rrk(z?)$",
2546                                               "^VF(N?)M(ADD|SUB)(132|213|231)PHZ(128|256)rk(z?)$",
2547                                               "^VF(N?)M(ADD|SUB)(132|213|231)SHZr(b?)_Intk(z?)$",
2548                                               "^VFMADDSUB(132|213|231)PHZ(128|256)rk(z?)$",
2549                                               "^VFMSUBADD(132|213|231)PHZ(128|256)rk(z?)$",
2550                                               "^VGETEXPPHZ(128|256)rk(z?)$",
2551                                               "^VGETEXPSHZr(bk|kz)$",
2552                                               "^VGETEXPSHZr(k|bkz)$",
2553                                               "^VGETMANTPHZ(128|256)rrik(z?)$",
2554                                               "^VGETMANTSHZrri(bk|kz)$",
2555                                               "^VGETMANTSHZrri(k|bkz)$",
2556                                               "^VM(AX|IN)CPHZ(128|256)rrk(z?)$",
2557                                               "^VM(AX|IN|UL)PHZ(128|256)rrk(z?)$",
2558                                               "^VM(AX|IN|UL)SHZrr(b?)_Intk(z?)$")>;
2559
2560def SPRWriteResGroup252 : SchedWriteRes<[SPRPort00]> {
2561  let Latency = 5;
2562}
2563def : InstRW<[SPRWriteResGroup252], (instregex "^V(ADD|SUB)PHZrr(b?)$",
2564                                               "^VAES(DE|EN)C((LAST)?)Zrr$",
2565                                               "^VCVT(T?)PH2(U?)WZrr(b?)$",
2566                                               "^VCVT(U?)W2PHZrr(b?)$",
2567                                               "^VF(N?)M(ADD|SUB)(132|213|231)PHZr(b?)$",
2568                                               "^VFMADDSUB(132|213|231)PHZr(b?)$",
2569                                               "^VFMSUBADD(132|213|231)PHZr(b?)$",
2570                                               "^VGETEXPPHZr(b?)$",
2571                                               "^VGETMANTPHZrri(b?)$",
2572                                               "^VM(AX|IN)CPHZrr$",
2573                                               "^VM(AX|IN|UL)PHZrr(b?)$",
2574                                               "^VMOVMSKP(D|S)Yrr$")>;
2575def : InstRW<[SPRWriteResGroup252], (instrs VGF2P8MULBZrr)>;
2576
2577def SPRWriteResGroup253 : SchedWriteRes<[SPRPort00]> {
2578  let Latency = 6;
2579}
2580def : InstRW<[SPRWriteResGroup253], (instregex "^V(ADD|SUB)PHZrr(bk|kz)$",
2581                                               "^V(ADD|SUB)PHZrr(k|bkz)$",
2582                                               "^VCVT(T?)PH2(U?)WZrr(bk|kz)$",
2583                                               "^VCVT(T?)PH2(U?)WZrr(k|bkz)$",
2584                                               "^VCVT(U?)W2PHZrr(bk|kz)$",
2585                                               "^VCVT(U?)W2PHZrr(k|bkz)$",
2586                                               "^VF(N?)M(ADD|SUB)(132|213|231)PHZr(bk|kz)$",
2587                                               "^VF(N?)M(ADD|SUB)(132|213|231)PHZr(k|bkz)$",
2588                                               "^VFMADDSUB(132|213|231)PHZr(bk|kz)$",
2589                                               "^VFMADDSUB(132|213|231)PHZr(k|bkz)$",
2590                                               "^VFMSUBADD(132|213|231)PHZr(bk|kz)$",
2591                                               "^VFMSUBADD(132|213|231)PHZr(k|bkz)$",
2592                                               "^VGETEXPPHZr(bk|kz)$",
2593                                               "^VGETEXPPHZr(k|bkz)$",
2594                                               "^VGETMANTPHZrri(bk|kz)$",
2595                                               "^VGETMANTPHZrri(k|bkz)$",
2596                                               "^VM(AX|IN)CPHZrrk(z?)$",
2597                                               "^VM(AX|IN|UL)PHZrr(bk|kz)$",
2598                                               "^VM(AX|IN|UL)PHZrr(k|bkz)$")>;
2599
2600def SPRWriteResGroup254 : SchedWriteRes<[SPRPort01_05, SPRPort02_03_11]> {
2601  let Latency = 11;
2602  let NumMicroOps = 2;
2603}
2604def : InstRW<[SPRWriteResGroup254], (instregex "^VPMOV(S|Z)XBWZ128rmk(z?)$",
2605                                               "^VPSHUF(H|L)WZ(128|256)mik(z?)$")>;
2606def : InstRW<[SPRWriteResGroup254, ReadAfterVecYLd], (instregex "^V(ADD|SUB)PSYrm$",
2607                                                                "^V(ADD|SUB)PSZ256rm((b|k|bk|kz)?)$",
2608                                                                "^V(ADD|SUB)PSZ256rmbkz$",
2609                                                                "^VPSHUFBZ256rmk(z?)$",
2610                                                                "^VPUNPCK(H|L)(BW|WD)Z256rmk(z?)$")>;
2611def : InstRW<[SPRWriteResGroup254, ReadAfterVecYLd], (instrs VADDSUBPSYrm)>;
2612def : InstRW<[SPRWriteResGroup254, ReadAfterVecXLd], (instregex "^VPSHUFBZ128rmk(z?)$",
2613                                                                "^VPUNPCK(H|L)(BW|WD)Z128rmk(z?)$")>;
2614
2615def SPRWriteResGroup255 : SchedWriteRes<[SPRPort00_05, SPRPort02_03_11]> {
2616  let Latency = 11;
2617  let NumMicroOps = 2;
2618}
2619def : InstRW<[SPRWriteResGroup255], (instregex "^VMOVDQU(8|16)Zrmk(z?)$")>;
2620def : InstRW<[SPRWriteResGroup255, ReadAfterVecYLd], (instregex "^V(ADD|SUB)PSZrm((b|k|bk|kz)?)$",
2621                                                                "^V(ADD|SUB)PSZrmbkz$",
2622                                                                "^VP(ADD|SUB)(B|W)Zrmk(z?)$",
2623                                                                "^VPBLENDM(B|W)Zrmk(z?)$")>;
2624
2625def SPRWriteResGroup256 : SchedWriteRes<[SPRPort00_05]> {
2626  let Latency = 4;
2627}
2628def : InstRW<[SPRWriteResGroup256], (instregex "^V(ADD|SUB)PSZrr(bk|kz)$",
2629                                               "^V(ADD|SUB)PSZrr(k|bkz)$")>;
2630
2631def SPRWriteResGroup257 : SchedWriteRes<[SPRPort00, SPRPort02_03_11]> {
2632  let Latency = 12;
2633  let NumMicroOps = 2;
2634}
2635def : InstRW<[SPRWriteResGroup257], (instregex "^VCVT(T?)PS2(U?)DQZrm((b|k|bk|kz)?)$",
2636                                               "^VCVT(T?)PS2(U?)DQZrmbkz$",
2637                                               "^VPLZCNT(D|Q)Zrm((b|k|bk|kz)?)$",
2638                                               "^VPLZCNT(D|Q)Zrmbkz$")>;
2639def : InstRW<[SPRWriteResGroup257, ReadAfterVecXLd], (instregex "^VAES(DE|EN)C((LAST)?)Zrm$")>;
2640def : InstRW<[SPRWriteResGroup257, ReadAfterVecYLd], (instregex "^VGF2P8AFFINE((INV)?)QBZrm(b?)i$")>;
2641def : InstRW<[SPRWriteResGroup257, ReadAfterVecYLd], (instrs VGF2P8MULBZrm)>;
2642def : InstRW<[SPRWriteResGroup257, ReadAfterVecYLd, ReadAfterVecYLd], (instregex "^VPMADD52(H|L)UQZm((b|k|bk|kz)?)$",
2643                                                                                 "^VPMADD52(H|L)UQZmbkz$")>;
2644
2645def SPRWriteResGroup258 : SchedWriteRes<[SPRPort02_03_11, SPRPort05]> {
2646  let Latency = 11;
2647  let NumMicroOps = 2;
2648}
2649def : InstRW<[SPRWriteResGroup258], (instregex "^VPBROADCAST(B|W)Z128rmk(z?)$",
2650                                               "^VPOPCNT(B|D|Q|W)Z((256)?)rm$",
2651                                               "^VPOPCNT(D|Q)Z((256)?)rm(b|k|kz)$",
2652                                               "^VPOPCNT(D|Q)Z((256)?)rmbk(z?)$",
2653                                               "^VPSHUF(H|L)WZmik(z?)$")>;
2654def : InstRW<[SPRWriteResGroup258, ReadAfterVecYLd], (instregex "^VALIGN(D|Q)Z((256)?)rm(bi|ik)$",
2655                                                                "^VALIGN(D|Q)Z((256)?)rmbik(z?)$",
2656                                                                "^VALIGN(D|Q)Z((256)?)rmi((kz)?)$",
2657                                                                "^VFPCLASSP(D|H|S)Z((256)?)rmb$",
2658                                                                "^VPACK(S|U)S(DW|WB)(Y|Z)rm$",
2659                                                                "^VPACK(S|U)S(DW|WB)Z256rm$",
2660                                                                "^VPACK(S|U)SDWZ((256)?)rmb$",
2661                                                                "^VPALIGNRZ((256)?)rmik(z?)$",
2662                                                                "^VPM(AX|IN)(S|U)QZ((256)?)rm((b|k|bk|kz)?)$",
2663                                                                "^VPM(AX|IN)(S|U)QZ((256)?)rmbkz$",
2664                                                                "^VPMULTISHIFTQBZ((256)?)rm(b?)$",
2665                                                                "^VPUNPCK(H|L)(BW|WD)Zrmk(z?)$")>;
2666def : InstRW<[SPRWriteResGroup258, ReadAfterVecYLd], (instrs VPCMPGTQYrm)>;
2667def : InstRW<[SPRWriteResGroup258, ReadAfterVecXLd], (instregex "^VPALIGNRZ128rmik(z?)$",
2668                                                                "^VPCLMULQDQ(Y|Z)rm$")>;
2669def : InstRW<[SPRWriteResGroup258, ReadAfterVecXLd], (instrs VPCLMULQDQZ256rm)>;
2670
2671def SPRWriteResGroup259 : SchedWriteRes<[SPRPort00_01_05, SPRPort02_03_11]> {
2672  let ReleaseAtCycles = [3, 1];
2673  let Latency = 10;
2674  let NumMicroOps = 4;
2675}
2676def : InstRW<[SPRWriteResGroup259, ReadAfterVecYLd, ReadAfterVecYLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^VBLENDVP(D|S)Yrm$")>;
2677def : InstRW<[SPRWriteResGroup259, ReadAfterVecYLd, ReadAfterVecYLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instrs VPBLENDVBYrm)>;
2678
2679def SPRWriteResGroup260 : SchedWriteRes<[SPRPort00_01_05]> {
2680  let ReleaseAtCycles = [3];
2681  let Latency = 3;
2682  let NumMicroOps = 3;
2683}
2684def : InstRW<[SPRWriteResGroup260], (instregex "^VBLENDVP(S|DY)rr$",
2685                                               "^VBLENDVP(D|SY)rr$",
2686                                               "^VPBLENDVB(Y?)rr$")>;
2687
2688def SPRWriteResGroup261 : SchedWriteRes<[SPRPort00_01_05, SPRPort02_03_11]> {
2689  let ReleaseAtCycles = [3, 1];
2690  let Latency = 9;
2691  let NumMicroOps = 4;
2692}
2693def : InstRW<[SPRWriteResGroup261, ReadAfterVecXLd, ReadAfterVecXLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instregex "^VBLENDVP(D|S)rm$")>;
2694def : InstRW<[SPRWriteResGroup261, ReadAfterVecXLd, ReadAfterVecXLd, ReadDefault, ReadDefault, ReadDefault, ReadDefault, ReadDefault], (instrs VPBLENDVBrm)>;
2695
2696def SPRWriteResGroup262 : SchedWriteRes<[SPRPort00_01_05, SPRPort02_03_11]> {
2697  let Latency = 9;
2698  let NumMicroOps = 2;
2699}
2700def : InstRW<[SPRWriteResGroup262], (instregex "^VBROADCAST(F|I)32X(2|4)Z256rmk(z?)$",
2701                                               "^VBROADCAST(F|I)64X2Z128rmk(z?)$",
2702                                               "^VBROADCASTS(D|S)Z256rmk(z?)$",
2703                                               "^VMOV(A|U)P(D|S)Z256rmk(z?)$",
2704                                               "^VMOV(D|SH|SL)DUPZ256rmk(z?)$",
2705                                               "^VMOVDQ(A|U)(32|64)Z256rmk(z?)$",
2706                                               "^VPBROADCAST(D|Q)Z256rmk(z?)$")>;
2707def : InstRW<[SPRWriteResGroup262, ReadAfterVecYLd], (instregex "^VINSERT(F|I)128rm$",
2708                                                                "^VINSERT(F|I)(32x4|64x2)Z256rm((k|kz)?)$",
2709                                                                "^VP(ADD|SUB)(B|D|Q|W)(Y|Z256)rm$",
2710                                                                "^VP(ADD|SUB)(D|Q)Z256rm(b|k|kz)$",
2711                                                                "^VP(ADD|SUB)(D|Q)Z256rmbk(z?)$",
2712                                                                "^VPTERNLOG(D|Q)Z256rm(bi|ik)$",
2713                                                                "^VPTERNLOG(D|Q)Z256rmbik(z?)$",
2714                                                                "^VPTERNLOG(D|Q)Z256rmi((kz)?)$")>;
2715
2716def SPRWriteResGroup263 : SchedWriteRes<[SPRPort02_03_11, SPRPort05]> {
2717  let Latency = 3;
2718  let NumMicroOps = 2;
2719}
2720def : InstRW<[SPRWriteResGroup263, ReadAfterVecXLd], (instregex "^VCMPP(D|H|S)Z128rm(bi|ik)$",
2721                                                                "^VCMPP(D|H|S)Z128rm(i|bik)$",
2722                                                                "^VFPCLASSP(D|H|S)Z128rm(b?)k$",
2723                                                                "^VPCMP(B|D|Q|W|UD|UQ|UW)Z128rmi(k?)$",
2724                                                                "^VPCMP(D|Q|UQ)Z128rmib(k?)$",
2725                                                                "^VPCMP(EQ|GT)(B|D|Q|W)Z128rm(k?)$",
2726                                                                "^VPCMP(EQ|GT)(D|Q)Z128rmb(k?)$",
2727                                                                "^VPCMPUBZ128rmi(k?)$",
2728                                                                "^VPCMPUDZ128rmib(k?)$",
2729                                                                "^VPTEST(N?)M(B|D|Q|W)Z128rm(k?)$",
2730                                                                "^VPTEST(N?)M(D|Q)Z128rmb(k?)$")>;
2731def : InstRW<[SPRWriteResGroup263, ReadAfterVecYLd], (instregex "^VCMPP(D|H|S)Z((256)?)rm(bi|ik)$",
2732                                                                "^VCMPP(D|H|S)Z((256)?)rm(i|bik)$",
2733                                                                "^VFPCLASSP(D|H|S)Z((256)?)rm(b?)k$",
2734                                                                "^VPCMP(B|D|Q|W|UD|UQ|UW)Z((256)?)rmi(k?)$",
2735                                                                "^VPCMP(D|Q|UQ)Z((256)?)rmib(k?)$",
2736                                                                "^VPCMP(EQ|GT)(B|D|Q|W)Z((256)?)rm(k?)$",
2737                                                                "^VPCMP(EQ|GT)(D|Q)Z((256)?)rmb(k?)$",
2738                                                                "^VPCMPUBZ((256)?)rmi(k?)$",
2739                                                                "^VPCMPUDZ((256)?)rmib(k?)$",
2740                                                                "^VPTEST(N?)M(B|D|Q|W)Z((256)?)rm(k?)$",
2741                                                                "^VPTEST(N?)M(D|Q)Z((256)?)rmb(k?)$")>;
2742def : InstRW<[SPRWriteResGroup263, ReadAfterVecLd], (instregex "^VCMPS(D|H|S)Zrm$",
2743                                                               "^VCMPS(D|H|S)Zrm_Int(k?)$",
2744                                                               "^VFPCLASSS(D|H|S)Zrmk$")>;
2745
2746def SPRWriteResGroup264 : SchedWriteRes<[SPRPort00, SPRPort02_03_11]> {
2747  let Latency = 10;
2748  let NumMicroOps = 2;
2749}
2750def : InstRW<[SPRWriteResGroup264, ReadAfterVecLd], (instregex "^V(U?)COMISHZrm((_Int)?)$")>;
2751
2752def SPRWriteResGroup265 : SchedWriteRes<[SPRPort04_09, SPRPort05, SPRPort07_08]> {
2753  let ReleaseAtCycles = [1, 2, 1];
2754  let Latency = 12;
2755  let NumMicroOps = 4;
2756}
2757def : InstRW<[SPRWriteResGroup265], (instregex "^VCOMPRESSP(D|S)Z(128|256)mr$",
2758                                               "^VCOMPRESSP(D|S)Zmr$",
2759                                               "^VPCOMPRESS(D|Q)Z(128|256)mr$",
2760                                               "^VPCOMPRESS(D|Q)Zmr$",
2761                                               "^VPMOV(D|Q|W|SQ|SW)BZmr$",
2762                                               "^VPMOV((S|US)?)(D|Q)WZmr$",
2763                                               "^VPMOV(U?)S(DB|QD)Zmr$",
2764                                               "^VPMOVUS(Q|W)BZmr$")>;
2765
2766def SPRWriteResGroup266 : SchedWriteRes<[SPRPort04_09, SPRPort05, SPRPort07_08]> {
2767  let ReleaseAtCycles = [1, 2, 1];
2768  let Latency = 15;
2769  let NumMicroOps = 4;
2770}
2771def : InstRW<[SPRWriteResGroup266], (instregex "^VCOMPRESSP(D|S)Z(128|256)mrk$",
2772                                               "^VCOMPRESSP(D|S)Zmrk$",
2773                                               "^VPCOMPRESS(D|Q)Z(128|256)mrk$",
2774                                               "^VPCOMPRESS(D|Q)Zmrk$",
2775                                               "^VPMOV(D|Q|W|SQ|SW)BZmrk$",
2776                                               "^VPMOV((S|US)?)(D|Q)WZmrk$",
2777                                               "^VPMOV(U?)S(DB|QD)Zmrk$",
2778                                               "^VPMOVUS(Q|W)BZmrk$")>;
2779
2780def SPRWriteResGroup267 : SchedWriteRes<[SPRPort05]> {
2781  let ReleaseAtCycles = [2];
2782  let Latency = 3;
2783  let NumMicroOps = 2;
2784}
2785def : InstRW<[SPRWriteResGroup267], (instregex "^VCOMPRESSP(D|S)Z(128|256)rr$",
2786                                               "^VCOMPRESSP(D|S)Zrr$",
2787                                               "^VEXPANDP(D|S)Z(128|256)rr$",
2788                                               "^VEXPANDP(D|S)Zrr$",
2789                                               "^VPCOMPRESS(B|D|Q|W)Z(128|256)rr$",
2790                                               "^VPCOMPRESS(B|D|Q|W)Zrr$",
2791                                               "^VPEXPAND(B|D|Q|W)Z(128|256)rr$",
2792                                               "^VPEXPAND(B|D|Q|W)Zrr$")>;
2793
2794def SPRWriteResGroup268 : SchedWriteRes<[SPRPort00, SPRPort05]> {
2795  let Latency = 7;
2796  let NumMicroOps = 2;
2797}
2798def : InstRW<[SPRWriteResGroup268], (instregex "^VCVT(U?)DQ2PDZrr((k|kz)?)$",
2799                                               "^VCVT(T?)PS2(U?)QQZrr((b|k|bk|kz)?)$",
2800                                               "^VCVT(T?)PS2(U?)QQZrrbkz$",
2801                                               "^VCVT(U?)QQ2PSZrr((b|k|bk|kz)?)$",
2802                                               "^VCVT(U?)QQ2PSZrrbkz$")>;
2803
2804def SPRWriteResGroup269 : SchedWriteRes<[SPRPort00_01, SPRPort01_05, SPRPort02_03_11, SPRPort05]> {
2805  let Latency = 15;
2806  let NumMicroOps = 4;
2807}
2808def : InstRW<[SPRWriteResGroup269], (instregex "^VCVT(U?)DQ2PHZ128rm(b?)$",
2809                                               "^VCVTNEPS2BF16Z128rm(b?)$")>;
2810
2811def SPRWriteResGroup270 : SchedWriteRes<[SPRPort00_01, SPRPort01_05, SPRPort02_03_11, SPRPort05]> {
2812  let Latency = 19;
2813  let NumMicroOps = 4;
2814}
2815def : InstRW<[SPRWriteResGroup270], (instregex "^VCVT(U?)DQ2PHZ128rm(bk|kz)$",
2816                                               "^VCVT(U?)DQ2PHZ128rm(k|bkz)$")>;
2817
2818def SPRWriteResGroup271 : SchedWriteRes<[SPRPort00_01, SPRPort01_05, SPRPort05]> {
2819  let Latency = 7;
2820  let NumMicroOps = 3;
2821}
2822def : InstRW<[SPRWriteResGroup271], (instregex "^VCVT(U?)DQ2PHZ128rr$")>;
2823
2824def SPRWriteResGroup272 : SchedWriteRes<[SPRPort00_01, SPRPort01_05, SPRPort05]> {
2825  let Latency = 12;
2826  let NumMicroOps = 3;
2827}
2828def : InstRW<[SPRWriteResGroup272], (instregex "^VCVT(U?)DQ2PHZ128rrk(z?)$")>;
2829
2830def SPRWriteResGroup273 : SchedWriteRes<[SPRPort00_01, SPRPort01_05, SPRPort02_03_11, SPRPort05]> {
2831  let Latency = 17;
2832  let NumMicroOps = 4;
2833}
2834def : InstRW<[SPRWriteResGroup273], (instregex "^VCVT(U?)DQ2PHZ256rm(b?)$",
2835                                               "^VCVTNEPS2BF16Z128rm(bk|kz)$",
2836                                               "^VCVTNEPS2BF16Z128rm(k|bkz)$")>;
2837
2838def SPRWriteResGroup274 : SchedWriteRes<[SPRPort00_01, SPRPort01_05, SPRPort02_03_11, SPRPort05]> {
2839  let Latency = 21;
2840  let NumMicroOps = 4;
2841}
2842def : InstRW<[SPRWriteResGroup274], (instregex "^VCVT(U?)DQ2PHZ256rm(bk|kz)$",
2843                                               "^VCVT(U?)DQ2PHZ256rm(k|bkz)$")>;
2844
2845def SPRWriteResGroup275 : SchedWriteRes<[SPRPort00_01, SPRPort01_05, SPRPort05]> {
2846  let Latency = 9;
2847  let NumMicroOps = 3;
2848}
2849def : InstRW<[SPRWriteResGroup275], (instregex "^VCVT(U?)DQ2PHZ256rr$")>;
2850
2851def SPRWriteResGroup276 : SchedWriteRes<[SPRPort00_01, SPRPort01_05, SPRPort05]> {
2852  let Latency = 14;
2853  let NumMicroOps = 3;
2854}
2855def : InstRW<[SPRWriteResGroup276], (instregex "^VCVT(U?)DQ2PHZ256rrk(z?)$")>;
2856
2857def SPRWriteResGroup277 : SchedWriteRes<[SPRPort00, SPRPort02_03_11, SPRPort05]> {
2858  let ReleaseAtCycles = [1, 1, 2];
2859  let Latency = 17;
2860  let NumMicroOps = 4;
2861}
2862def : InstRW<[SPRWriteResGroup277], (instregex "^VCVT(U?)DQ2PHZrm(b?)$")>;
2863
2864def SPRWriteResGroup278 : SchedWriteRes<[SPRPort00, SPRPort02_03_11, SPRPort05]> {
2865  let ReleaseAtCycles = [1, 1, 2];
2866  let Latency = 21;
2867  let NumMicroOps = 4;
2868}
2869def : InstRW<[SPRWriteResGroup278], (instregex "^VCVT(U?)DQ2PHZrm(bk|kz)$",
2870                                               "^VCVT(U?)DQ2PHZrm(k|bkz)$")>;
2871
2872def SPRWriteResGroup279 : SchedWriteRes<[SPRPort00, SPRPort05]> {
2873  let ReleaseAtCycles = [1, 2];
2874  let Latency = 9;
2875  let NumMicroOps = 3;
2876}
2877def : InstRW<[SPRWriteResGroup279], (instregex "^VCVT(U?)DQ2PHZrr(b?)$")>;
2878
2879def SPRWriteResGroup280 : SchedWriteRes<[SPRPort00, SPRPort05]> {
2880  let ReleaseAtCycles = [1, 2];
2881  let Latency = 14;
2882  let NumMicroOps = 3;
2883}
2884def : InstRW<[SPRWriteResGroup280], (instregex "^VCVT(U?)DQ2PHZrr(bk|kz)$",
2885                                               "^VCVT(U?)DQ2PHZrr(k|bkz)$")>;
2886
2887def SPRWriteResGroup281 : SchedWriteRes<[SPRPort00_01, SPRPort01_05, SPRPort02_03_11, SPRPort05]> {
2888  let ReleaseAtCycles = [2, 1, 1, 1];
2889  let Latency = 15;
2890  let NumMicroOps = 5;
2891}
2892def : InstRW<[SPRWriteResGroup281, ReadAfterVecXLd], (instregex "^VCVTNE2PS2BF16Z128rm(b?)$")>;
2893
2894def SPRWriteResGroup282 : SchedWriteRes<[SPRPort00_01, SPRPort01_05, SPRPort02_03_11, SPRPort05]> {
2895  let ReleaseAtCycles = [2, 1, 1, 1];
2896  let Latency = 17;
2897  let NumMicroOps = 5;
2898}
2899def : InstRW<[SPRWriteResGroup282, ReadAfterVecXLd], (instregex "^VCVTNE2PS2BF16Z128rm(bk|kz)$",
2900                                                                "^VCVTNE2PS2BF16Z128rm(k|bkz)$")>;
2901
2902def SPRWriteResGroup283 : SchedWriteRes<[SPRPort00_01, SPRPort01_05, SPRPort05]> {
2903  let ReleaseAtCycles = [2, 1, 1];
2904  let Latency = 8;
2905  let NumMicroOps = 4;
2906}
2907def : InstRW<[SPRWriteResGroup283], (instregex "^VCVTNE2PS2BF16Z(128|256)rr$")>;
2908
2909def SPRWriteResGroup284 : SchedWriteRes<[SPRPort00_01, SPRPort01_05, SPRPort05]> {
2910  let ReleaseAtCycles = [2, 1, 1];
2911  let Latency = 10;
2912  let NumMicroOps = 4;
2913}
2914def : InstRW<[SPRWriteResGroup284], (instregex "^VCVTNE2PS2BF16Z(128|256)rrk(z?)$")>;
2915
2916def SPRWriteResGroup285 : SchedWriteRes<[SPRPort00_01, SPRPort01_05, SPRPort02_03_11, SPRPort05]> {
2917  let ReleaseAtCycles = [2, 1, 1, 1];
2918  let Latency = 16;
2919  let NumMicroOps = 5;
2920}
2921def : InstRW<[SPRWriteResGroup285, ReadAfterVecYLd], (instregex "^VCVTNE2PS2BF16Z256rm(b?)$")>;
2922
2923def SPRWriteResGroup286 : SchedWriteRes<[SPRPort00_01, SPRPort01_05, SPRPort02_03_11, SPRPort05]> {
2924  let ReleaseAtCycles = [2, 1, 1, 1];
2925  let Latency = 18;
2926  let NumMicroOps = 5;
2927}
2928def : InstRW<[SPRWriteResGroup286, ReadAfterVecYLd], (instregex "^VCVTNE2PS2BF16Z256rm(bk|kz)$",
2929                                                                "^VCVTNE2PS2BF16Z256rm(k|bkz)$")>;
2930
2931def SPRWriteResGroup287 : SchedWriteRes<[SPRPort00, SPRPort02_03_11, SPRPort05]> {
2932  let ReleaseAtCycles = [2, 1, 2];
2933  let Latency = 16;
2934  let NumMicroOps = 5;
2935}
2936def : InstRW<[SPRWriteResGroup287, ReadAfterVecYLd], (instregex "^VCVTNE2PS2BF16Zrm(b?)$",
2937                                                                "^VDPBF16PSZm((b|k|bk|kz)?)$")>;
2938def : InstRW<[SPRWriteResGroup287, ReadAfterVecYLd], (instrs VDPBF16PSZmbkz)>;
2939
2940def SPRWriteResGroup288 : SchedWriteRes<[SPRPort00, SPRPort02_03_11, SPRPort05]> {
2941  let ReleaseAtCycles = [2, 1, 2];
2942  let Latency = 18;
2943  let NumMicroOps = 5;
2944}
2945def : InstRW<[SPRWriteResGroup288, ReadAfterVecYLd], (instregex "^VCVTNE2PS2BF16Zrm(bk|kz)$",
2946                                                                "^VCVTNE2PS2BF16Zrm(k|bkz)$")>;
2947
2948def SPRWriteResGroup289 : SchedWriteRes<[SPRPort00, SPRPort05]> {
2949  let ReleaseAtCycles = [2, 2];
2950  let Latency = 8;
2951  let NumMicroOps = 4;
2952}
2953def : InstRW<[SPRWriteResGroup289], (instregex "^VDPBF16PSZr((k|kz)?)$")>;
2954def : InstRW<[SPRWriteResGroup289], (instrs VCVTNE2PS2BF16Zrr)>;
2955
2956def SPRWriteResGroup290 : SchedWriteRes<[SPRPort00, SPRPort05]> {
2957  let ReleaseAtCycles = [2, 2];
2958  let Latency = 10;
2959  let NumMicroOps = 4;
2960}
2961def : InstRW<[SPRWriteResGroup290], (instregex "^VCVTNE2PS2BF16Zrrk(z?)$")>;
2962
2963def SPRWriteResGroup291 : SchedWriteRes<[SPRPort00_01, SPRPort01_05, SPRPort05]> {
2964  let Latency = 8;
2965  let NumMicroOps = 3;
2966}
2967def : InstRW<[SPRWriteResGroup291], (instregex "^VCVTNEPS2BF16Z(128|256)rr$")>;
2968
2969def SPRWriteResGroup292 : SchedWriteRes<[SPRPort00_01, SPRPort01_05, SPRPort05]> {
2970  let Latency = 10;
2971  let NumMicroOps = 3;
2972}
2973def : InstRW<[SPRWriteResGroup292], (instregex "^VCVTNEPS2BF16Z(128|256)rrk(z?)$")>;
2974
2975def SPRWriteResGroup293 : SchedWriteRes<[SPRPort00_01, SPRPort01_05, SPRPort02_03_11, SPRPort05]> {
2976  let Latency = 16;
2977  let NumMicroOps = 4;
2978}
2979def : InstRW<[SPRWriteResGroup293], (instregex "^VCVTNEPS2BF16Z256rm(b?)$")>;
2980
2981def SPRWriteResGroup294 : SchedWriteRes<[SPRPort00_01, SPRPort01_05, SPRPort02_03_11, SPRPort05]> {
2982  let Latency = 18;
2983  let NumMicroOps = 4;
2984}
2985def : InstRW<[SPRWriteResGroup294], (instregex "^VCVTNEPS2BF16Z256rm(bk|kz)$",
2986                                               "^VCVTNEPS2BF16Z256rm(k|bkz)$")>;
2987
2988def SPRWriteResGroup295 : SchedWriteRes<[SPRPort00, SPRPort02_03_11, SPRPort05]> {
2989  let ReleaseAtCycles = [1, 1, 2];
2990  let Latency = 16;
2991  let NumMicroOps = 4;
2992}
2993def : InstRW<[SPRWriteResGroup295], (instregex "^VCVTNEPS2BF16Zrm(b?)$")>;
2994
2995def SPRWriteResGroup296 : SchedWriteRes<[SPRPort00, SPRPort02_03_11, SPRPort05]> {
2996  let ReleaseAtCycles = [1, 1, 2];
2997  let Latency = 18;
2998  let NumMicroOps = 4;
2999}
3000def : InstRW<[SPRWriteResGroup296], (instregex "^VCVTNEPS2BF16Zrm(bk|kz)$",
3001                                               "^VCVTNEPS2BF16Zrm(k|bkz)$")>;
3002
3003def SPRWriteResGroup297 : SchedWriteRes<[SPRPort00, SPRPort05]> {
3004  let ReleaseAtCycles = [1, 2];
3005  let Latency = 8;
3006  let NumMicroOps = 3;
3007}
3008def : InstRW<[SPRWriteResGroup297], (instrs VCVTNEPS2BF16Zrr)>;
3009
3010def SPRWriteResGroup298 : SchedWriteRes<[SPRPort00, SPRPort05]> {
3011  let ReleaseAtCycles = [1, 2];
3012  let Latency = 10;
3013  let NumMicroOps = 3;
3014}
3015def : InstRW<[SPRWriteResGroup298], (instregex "^VCVTNEPS2BF16Zrrk(z?)$")>;
3016
3017def SPRWriteResGroup299 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_11, SPRPort05]> {
3018  let Latency = 15;
3019  let NumMicroOps = 3;
3020}
3021def : InstRW<[SPRWriteResGroup299], (instregex "^VCVT(T?)PD2DQYrm$",
3022                                               "^VCVT(T?)P(D|H)2(U?)DQZ256rm(b?)$",
3023                                               "^VCVT(T?)PD2(U?)DQZ256rm(bk|kz)$",
3024                                               "^VCVT(T?)PD2(U?)DQZ256rm(k|bkz)$",
3025                                               "^VCVTPH2PSXZ128rm(bk|kz)$",
3026                                               "^VCVTPH2PSXZ128rm(k|bkz)$",
3027                                               "^VCVTPH2PSXZ256rm(b?)$",
3028                                               "^VCVT(U?)QQ2PSZ256rm((b|k|bk|kz)?)$",
3029                                               "^VCVT(U?)QQ2PSZ256rmbkz$")>;
3030
3031def SPRWriteResGroup300 : SchedWriteRes<[SPRPort00, SPRPort02_03_11, SPRPort05]> {
3032  let Latency = 15;
3033  let NumMicroOps = 3;
3034}
3035def : InstRW<[SPRWriteResGroup300], (instregex "^VCVT(T?)P(D|H)2(U?)DQZrm(b?)$",
3036                                               "^VCVT(T?)PD2(U?)DQZrm(bk|kz)$",
3037                                               "^VCVT(T?)PD2(U?)DQZrm(k|bkz)$",
3038                                               "^VCVTPH2PSXZrm(b?)$",
3039                                               "^VCVT(U?)QQ2PSZrm((b|k|bk|kz)?)$",
3040                                               "^VCVT(U?)QQ2PSZrmbkz$")>;
3041
3042def SPRWriteResGroup301 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_06, SPRPort02_03_11, SPRPort05]> {
3043  let ReleaseAtCycles = [2, 1, 1, 1, 2];
3044  let Latency = 19;
3045  let NumMicroOps = 7;
3046}
3047def : InstRW<[SPRWriteResGroup301], (instregex "^VCVTPD2PHZ128rm(b?)$")>;
3048
3049def SPRWriteResGroup302 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_06, SPRPort02_03_11, SPRPort05]> {
3050  let ReleaseAtCycles = [2, 1, 1, 1, 2];
3051  let Latency = 22;
3052  let NumMicroOps = 7;
3053}
3054def : InstRW<[SPRWriteResGroup302], (instregex "^VCVTPD2PHZ128rm(bk|kz)$",
3055                                               "^VCVTPD2PHZ128rm(k|bkz)$")>;
3056
3057def SPRWriteResGroup303 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort05]> {
3058  let ReleaseAtCycles = [2, 1, 2];
3059  let Latency = 12;
3060  let NumMicroOps = 5;
3061}
3062def : InstRW<[SPRWriteResGroup303], (instrs VCVTPD2PHZ128rr)>;
3063
3064def SPRWriteResGroup304 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort05]> {
3065  let ReleaseAtCycles = [2, 1, 2];
3066  let Latency = 15;
3067  let NumMicroOps = 5;
3068}
3069def : InstRW<[SPRWriteResGroup304], (instregex "^VCVTPD2PHZ128rrk(z?)$")>;
3070
3071def SPRWriteResGroup305 : SchedWriteRes<[SPRPort00_01, SPRPort00_06, SPRPort02_03_11, SPRPort05]> {
3072  let ReleaseAtCycles = [2, 1, 1, 2];
3073  let Latency = 21;
3074  let NumMicroOps = 6;
3075}
3076def : InstRW<[SPRWriteResGroup305], (instregex "^VCVTPD2PHZ256rm(b?)$")>;
3077
3078def SPRWriteResGroup306 : SchedWriteRes<[SPRPort00_01, SPRPort00_06, SPRPort02_03_11, SPRPort05]> {
3079  let ReleaseAtCycles = [2, 1, 1, 2];
3080  let Latency = 24;
3081  let NumMicroOps = 6;
3082}
3083def : InstRW<[SPRWriteResGroup306], (instregex "^VCVTPD2PHZ256rm(bk|kz)$",
3084                                               "^VCVTPD2PHZ256rm(k|bkz)$")>;
3085
3086def SPRWriteResGroup307 : SchedWriteRes<[SPRPort00_01, SPRPort05]> {
3087  let ReleaseAtCycles = [2, 2];
3088  let Latency = 13;
3089  let NumMicroOps = 4;
3090}
3091def : InstRW<[SPRWriteResGroup307], (instrs VCVTPD2PHZ256rr)>;
3092
3093def SPRWriteResGroup308 : SchedWriteRes<[SPRPort00_01, SPRPort05]> {
3094  let ReleaseAtCycles = [2, 2];
3095  let Latency = 16;
3096  let NumMicroOps = 4;
3097}
3098def : InstRW<[SPRWriteResGroup308], (instregex "^VCVTPD2PHZ256rrk(z?)$")>;
3099
3100def SPRWriteResGroup309 : SchedWriteRes<[SPRPort00, SPRPort00_06, SPRPort02_03_11, SPRPort05]> {
3101  let ReleaseAtCycles = [2, 1, 1, 2];
3102  let Latency = 23;
3103  let NumMicroOps = 6;
3104}
3105def : InstRW<[SPRWriteResGroup309], (instregex "^VCVTP(D2PH|H2PD)Zrm(b?)$")>;
3106
3107def SPRWriteResGroup310 : SchedWriteRes<[SPRPort00, SPRPort00_06, SPRPort02_03_11, SPRPort05]> {
3108  let ReleaseAtCycles = [2, 1, 1, 2];
3109  let Latency = 26;
3110  let NumMicroOps = 6;
3111}
3112def : InstRW<[SPRWriteResGroup310], (instregex "^VCVTP(D2PH|H2PD)Zrm(bk|kz)$",
3113                                               "^VCVTP(D2PH|H2PD)Zrm(k|bkz)$")>;
3114
3115def SPRWriteResGroup311 : SchedWriteRes<[SPRPort00, SPRPort05]> {
3116  let ReleaseAtCycles = [2, 2];
3117  let Latency = 15;
3118  let NumMicroOps = 4;
3119}
3120def : InstRW<[SPRWriteResGroup311], (instregex "^VCVTP(D2PH|H2PD)Zrr(b?)$")>;
3121
3122def SPRWriteResGroup312 : SchedWriteRes<[SPRPort00, SPRPort05]> {
3123  let ReleaseAtCycles = [2, 2];
3124  let Latency = 18;
3125  let NumMicroOps = 4;
3126}
3127def : InstRW<[SPRWriteResGroup312], (instregex "^VCVTP(D2PH|H2PD)Zrr(bk|kz)$",
3128                                               "^VCVTP(D2PH|H2PD)Zrr(k|bkz)$")>;
3129
3130def SPRWriteResGroup313 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_11]> {
3131  let Latency = 11;
3132  let NumMicroOps = 2;
3133}
3134def : InstRW<[SPRWriteResGroup313], (instregex "^VCVT(T?)PD2(U?)QQZ128rm((b|k|bk|kz)?)$",
3135                                               "^VCVT(T?)PD2(U?)QQZ128rmbkz$",
3136                                               "^VPABS(B|W)Z(128|256)rmk(z?)$",
3137                                               "^VPLZCNT(D|Q)Z128rm((b|k|bk|kz)?)$",
3138                                               "^VPLZCNT(D|Q)Z128rmbkz$",
3139                                               "^VPS(L|R)LWZ(128|256)mik(z?)$",
3140                                               "^VPSRAWZ(128|256)mik(z?)$")>;
3141def : InstRW<[SPRWriteResGroup313, ReadAfterVecLd], (instregex "^VFIXUPIMMS(D|S)Zrmi((k|kz)?)$",
3142                                                               "^VSCALEFS(D|S)Zrm((k|kz)?)$")>;
3143def : InstRW<[SPRWriteResGroup313, ReadAfterVecXLd], (instregex "^VP(ADD|SUB)(U?)S(B|W)Z128rmk(z?)$",
3144                                                                "^VPAVG(B|W)Z128rmk(z?)$",
3145                                                                "^VPM(AX|IN)(SB|UW)Z128rmk(z?)$",
3146                                                                "^VPM(AX|IN)(SW|UB)Z128rmk(z?)$",
3147                                                                "^VPSH(L|R)DVWZ128mk(z?)$",
3148                                                                "^VPS(L|R)L(V?)WZ128rmk(z?)$",
3149                                                                "^VPSRA(V?)WZ128rmk(z?)$")>;
3150def : InstRW<[SPRWriteResGroup313, ReadAfterVecYLd], (instregex "^VP(ADD|SUB)(U?)S(B|W)Z256rmk(z?)$",
3151                                                                "^VPAVG(B|W)Z256rmk(z?)$",
3152                                                                "^VPM(AX|IN)(SB|UW)Z256rmk(z?)$",
3153                                                                "^VPM(AX|IN)(SW|UB)Z256rmk(z?)$",
3154                                                                "^VPSH(L|R)DVWZ256mk(z?)$",
3155                                                                "^VPS(L|R)L(V?)WZ256rmk(z?)$",
3156                                                                "^VPSRA(V?)WZ256rmk(z?)$")>;
3157def : InstRW<[SPRWriteResGroup313, ReadAfterVecXLd, ReadAfterVecXLd], (instregex "^VPMADD52(H|L)UQZ128m((b|k|bk|kz)?)$",
3158                                                                                 "^VPMADD52(H|L)UQZ128mbkz$")>;
3159
3160def SPRWriteResGroup314 : SchedWriteRes<[SPRPort00_01]> {
3161  let Latency = 4;
3162}
3163def : InstRW<[SPRWriteResGroup314], (instregex "^VCVT(T?)PD2(U?)QQZ(128|256)rr((k|kz)?)$",
3164                                               "^VCVT(U?)QQ2PDZ(128|256)rr((k|kz)?)$",
3165                                               "^VFIXUPIMMS(D|S)Zrri((k|kz)?)$",
3166                                               "^VPLZCNT(D|Q)Z(128|256)rr((k|kz)?)$",
3167                                               "^VPMADD52(H|L)UQZ(128|256)r((k|kz)?)$",
3168                                               "^VSCALEFS(D|S)Zrr((k|kz)?)$",
3169                                               "^VSCALEFS(D|S)Zrrb_Int((k|kz)?)$")>;
3170def : InstRW<[SPRWriteResGroup314, ReadAfterVecLd], (instregex "^VFIXUPIMMS(D|S)Zrrib((k|kz)?)$")>;
3171
3172def SPRWriteResGroup315 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_11, SPRPort05]> {
3173  let Latency = 14;
3174  let NumMicroOps = 3;
3175}
3176def : InstRW<[SPRWriteResGroup315], (instregex "^VCVT(T?)PH2(U?)DQZ128rm(b?)$",
3177                                               "^VCVTPS2PHXZ128rm(b?)$")>;
3178
3179def SPRWriteResGroup316 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_11, SPRPort05]> {
3180  let Latency = 17;
3181  let NumMicroOps = 3;
3182}
3183def : InstRW<[SPRWriteResGroup316], (instregex "^VCVT(T?)PH2(U?)DQZ128rm(bk|kz)$",
3184                                               "^VCVT(T?)PH2(U?)DQZ128rm(k|bkz)$")>;
3185
3186def SPRWriteResGroup317 : SchedWriteRes<[SPRPort00_01, SPRPort05]> {
3187  let Latency = 11;
3188  let NumMicroOps = 2;
3189}
3190def : InstRW<[SPRWriteResGroup317], (instregex "^VCVT(T?)PH2(U?)DQZ(128|256)rrk(z?)$",
3191                                               "^VCVTP(H2PS|S2PH)(X?)Z256rrk(z?)$")>;
3192
3193def SPRWriteResGroup318 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_11, SPRPort05]> {
3194  let Latency = 18;
3195  let NumMicroOps = 3;
3196}
3197def : InstRW<[SPRWriteResGroup318], (instregex "^VCVT(T?)PH2(U?)DQZ256rm(bk|kz)$",
3198                                               "^VCVT(T?)PH2(U?)DQZ256rm(k|bkz)$",
3199                                               "^VCVTP(H2PS|S2PH)XZ256rm(bk|kz)$",
3200                                               "^VCVTP(H2PS|S2PH)XZ256rm(k|bkz)$")>;
3201
3202def SPRWriteResGroup319 : SchedWriteRes<[SPRPort00, SPRPort02_03_11, SPRPort05]> {
3203  let Latency = 18;
3204  let NumMicroOps = 3;
3205}
3206def : InstRW<[SPRWriteResGroup319], (instregex "^VCVT(T?)PH2(U?)DQZrm(bk|kz)$",
3207                                               "^VCVT(T?)PH2(U?)DQZrm(k|bkz)$",
3208                                               "^VCVTP(H2PS|S2PH)XZrm(bk|kz)$",
3209                                               "^VCVTP(H2PS|S2PH)XZrm(k|bkz)$")>;
3210
3211def SPRWriteResGroup320 : SchedWriteRes<[SPRPort00, SPRPort05]> {
3212  let Latency = 8;
3213  let NumMicroOps = 2;
3214}
3215def : InstRW<[SPRWriteResGroup320], (instregex "^VCVT(T?)PH2(U?)DQZrr(b?)$",
3216                                               "^VCVTP(H2PS|S2PH)(X?)Zrr(b?)$",
3217                                               "^VPSHUFBITQMBZ(128|256)rrk$")>;
3218def : InstRW<[SPRWriteResGroup320], (instrs VPSHUFBITQMBZrrk)>;
3219
3220def SPRWriteResGroup321 : SchedWriteRes<[SPRPort00, SPRPort05]> {
3221  let Latency = 11;
3222  let NumMicroOps = 2;
3223}
3224def : InstRW<[SPRWriteResGroup321], (instregex "^VCVT(T?)PH2(U?)DQZrr(bk|kz)$",
3225                                               "^VCVT(T?)PH2(U?)DQZrr(k|bkz)$",
3226                                               "^VCVTP(H2PS|S2PH)XZrr(bk|kz)$",
3227                                               "^VCVTP(H2PS|S2PH)XZrr(k|bkz)$")>;
3228
3229def SPRWriteResGroup322 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_06, SPRPort02_03_11, SPRPort05]> {
3230  let ReleaseAtCycles = [2, 1, 1, 1, 2];
3231  let Latency = 23;
3232  let NumMicroOps = 7;
3233}
3234def : InstRW<[SPRWriteResGroup322], (instregex "^VCVTPH2PDZ128rm(b?)$")>;
3235
3236def SPRWriteResGroup323 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_06, SPRPort02_03_11, SPRPort05]> {
3237  let ReleaseAtCycles = [2, 1, 1, 1, 2];
3238  let Latency = 26;
3239  let NumMicroOps = 7;
3240}
3241def : InstRW<[SPRWriteResGroup323], (instregex "^VCVTPH2PDZ128rm(bk|kz)$",
3242                                               "^VCVTPH2PDZ128rm(k|bkz)$")>;
3243
3244def SPRWriteResGroup324 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_06, SPRPort05]> {
3245  let ReleaseAtCycles = [2, 1, 1, 2];
3246  let Latency = 16;
3247  let NumMicroOps = 6;
3248}
3249def : InstRW<[SPRWriteResGroup324], (instrs VCVTPH2PDZ128rr)>;
3250
3251def SPRWriteResGroup325 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_06, SPRPort05]> {
3252  let ReleaseAtCycles = [2, 1, 1, 2];
3253  let Latency = 19;
3254  let NumMicroOps = 6;
3255}
3256def : InstRW<[SPRWriteResGroup325], (instregex "^VCVTPH2PDZ128rrk(z?)$")>;
3257
3258def SPRWriteResGroup326 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_11, SPRPort05]> {
3259  let ReleaseAtCycles = [2, 1, 2];
3260  let Latency = 22;
3261  let NumMicroOps = 5;
3262}
3263def : InstRW<[SPRWriteResGroup326], (instregex "^VCVTPH2PDZ256rm(b?)$")>;
3264
3265def SPRWriteResGroup327 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_11, SPRPort05]> {
3266  let ReleaseAtCycles = [2, 1, 2];
3267  let Latency = 25;
3268  let NumMicroOps = 5;
3269}
3270def : InstRW<[SPRWriteResGroup327], (instregex "^VCVTPH2PDZ256rm(bk|kz)$",
3271                                               "^VCVTPH2PDZ256rm(k|bkz)$")>;
3272
3273def SPRWriteResGroup328 : SchedWriteRes<[SPRPort00_01, SPRPort05]> {
3274  let ReleaseAtCycles = [2, 2];
3275  let Latency = 15;
3276  let NumMicroOps = 4;
3277}
3278def : InstRW<[SPRWriteResGroup328], (instrs VCVTPH2PDZ256rr)>;
3279
3280def SPRWriteResGroup329 : SchedWriteRes<[SPRPort00_01, SPRPort05]> {
3281  let ReleaseAtCycles = [2, 2];
3282  let Latency = 18;
3283  let NumMicroOps = 4;
3284}
3285def : InstRW<[SPRWriteResGroup329], (instregex "^VCVTPH2PDZ256rrk(z?)$")>;
3286
3287def SPRWriteResGroup330 : SchedWriteRes<[SPRPort00_01, SPRPort05]> {
3288  let Latency = 9;
3289  let NumMicroOps = 2;
3290}
3291def : InstRW<[SPRWriteResGroup330], (instregex "^VCVTP(H2PS|S2PH)(X?)Z128rrk(z?)$")>;
3292
3293def SPRWriteResGroup331 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_11]> {
3294  let Latency = 14;
3295  let NumMicroOps = 2;
3296}
3297def : InstRW<[SPRWriteResGroup331], (instregex "^VCVTPH2PSZ(128|256)rmk(z?)$")>;
3298def : InstRW<[SPRWriteResGroup331, ReadAfterVecLd], (instregex "^VCVTSH2SSZrm_Intk(z?)$")>;
3299def : InstRW<[SPRWriteResGroup331, ReadAfterVecXLd], (instregex "^VPMADDUBSWZ128rmk(z?)$",
3300                                                                "^VPMULH((U|RS)?)WZ128rmk(z?)$",
3301                                                                "^VPMULLWZ128rmk(z?)$")>;
3302def : InstRW<[SPRWriteResGroup331, ReadAfterVecYLd], (instregex "^VPMADDUBSWZ256rmk(z?)$",
3303                                                                "^VPMULH((U|RS)?)WZ256rmk(z?)$",
3304                                                                "^VPMULLWZ256rmk(z?)$")>;
3305
3306def SPRWriteResGroup332 : SchedWriteRes<[SPRPort00, SPRPort02_03_11, SPRPort05]> {
3307  let Latency = 13;
3308  let NumMicroOps = 3;
3309}
3310def : InstRW<[SPRWriteResGroup332], (instregex "^VCVT(T?)PS2(U?)QQZrm((b|k|bk|kz)?)$",
3311                                               "^VCVT(T?)PS2(U?)QQZrmbkz$")>;
3312def : InstRW<[SPRWriteResGroup332], (instrs VCVTPH2PSZrm)>;
3313def : InstRW<[SPRWriteResGroup332, ReadAfterVecYLd], (instregex "^VPERMWZrmk(z?)$")>;
3314
3315def SPRWriteResGroup333 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_06, SPRPort02_03_11, SPRPort05]> {
3316  let ReleaseAtCycles = [1, 2, 1, 1, 1];
3317  let Latency = 17;
3318  let NumMicroOps = 6;
3319}
3320def : InstRW<[SPRWriteResGroup333], (instregex "^VCVT(T?)PH2(U?)QQZ128rm((b|k|bk|kz)?)$",
3321                                               "^VCVT(T?)PH2(U?)QQZ128rmbkz$")>;
3322
3323def SPRWriteResGroup334 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort05]> {
3324  let ReleaseAtCycles = [1, 2, 1];
3325  let Latency = 10;
3326  let NumMicroOps = 4;
3327}
3328def : InstRW<[SPRWriteResGroup334], (instregex "^VCVT(T?)PH2(U?)QQZ(128|256)rr((k|kz)?)$")>;
3329
3330def SPRWriteResGroup335 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_06, SPRPort02_03_11, SPRPort05]> {
3331  let ReleaseAtCycles = [1, 2, 1, 1, 1];
3332  let Latency = 18;
3333  let NumMicroOps = 6;
3334}
3335def : InstRW<[SPRWriteResGroup335], (instregex "^VCVT(T?)PH2(U?)QQZ256rm((b|k|bk|kz)?)$",
3336                                               "^VCVT(T?)PH2(U?)QQZ256rmbkz$")>;
3337
3338def SPRWriteResGroup336 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_11, SPRPort05]> {
3339  let Latency = 16;
3340  let NumMicroOps = 3;
3341}
3342def : InstRW<[SPRWriteResGroup336], (instregex "^VCVTPS2PHXZ128rm(bk|kz)$",
3343                                               "^VCVTPS2PHXZ128rm(k|bkz)$",
3344                                               "^VCVTPS2PHXZ256rm(b?)$")>;
3345
3346def SPRWriteResGroup337 : SchedWriteRes<[SPRPort00, SPRPort02_03_11, SPRPort05]> {
3347  let Latency = 16;
3348  let NumMicroOps = 3;
3349}
3350def : InstRW<[SPRWriteResGroup337], (instregex "^VCVTPS2PHXZrm(b?)$")>;
3351
3352def SPRWriteResGroup338 : SchedWriteRes<[SPRPort00_01, SPRPort04_09, SPRPort07_08]> {
3353  let Latency = 16;
3354  let NumMicroOps = 3;
3355}
3356def : InstRW<[SPRWriteResGroup338], (instregex "^VCVTPS2PHZ(128|256)mrk$")>;
3357
3358def SPRWriteResGroup339 : SchedWriteRes<[SPRPort00, SPRPort04_09, SPRPort07_08]> {
3359  let Latency = 16;
3360  let NumMicroOps = 3;
3361}
3362def : InstRW<[SPRWriteResGroup339], (instrs VCVTPS2PHZmrk)>;
3363
3364def SPRWriteResGroup340 : SchedWriteRes<[SPRPort00_01, SPRPort05]> {
3365  let Latency = 5;
3366  let NumMicroOps = 2;
3367}
3368def : InstRW<[SPRWriteResGroup340], (instregex "^VCVT(T?)PS2(U?)QQZ128rr((k|kz)?)$",
3369                                               "^VCVT(U?)QQ2PSZ128rr((k|kz)?)$")>;
3370
3371def SPRWriteResGroup341 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort01_05, SPRPort02_03_11, SPRPort05]> {
3372  let Latency = 15;
3373  let NumMicroOps = 5;
3374}
3375def : InstRW<[SPRWriteResGroup341], (instregex "^VCVT(U?)QQ2PHZ128rm(b?)$")>;
3376
3377def SPRWriteResGroup342 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort01_05, SPRPort02_03_11, SPRPort05]> {
3378  let Latency = 17;
3379  let NumMicroOps = 5;
3380}
3381def : InstRW<[SPRWriteResGroup342], (instregex "^VCVT(U?)QQ2PHZ128rm(bk|kz)$",
3382                                               "^VCVT(U?)QQ2PHZ128rm(k|bkz)$")>;
3383
3384def SPRWriteResGroup343 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort01_05, SPRPort05]> {
3385  let Latency = 8;
3386  let NumMicroOps = 4;
3387}
3388def : InstRW<[SPRWriteResGroup343], (instregex "^VCVT(U?)QQ2PHZ128rr$")>;
3389
3390def SPRWriteResGroup344 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort01_05, SPRPort05]> {
3391  let Latency = 10;
3392  let NumMicroOps = 4;
3393}
3394def : InstRW<[SPRWriteResGroup344], (instregex "^VCVT(U?)QQ2PHZ128rrk(z?)$",
3395                                               "^VCVT(U?)QQ2PHZ256rr$")>;
3396
3397def SPRWriteResGroup345 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort01_05, SPRPort02_03_11, SPRPort05]> {
3398  let Latency = 18;
3399  let NumMicroOps = 5;
3400}
3401def : InstRW<[SPRWriteResGroup345], (instregex "^VCVT(U?)QQ2PHZ256rm(b?)$")>;
3402
3403def SPRWriteResGroup346 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort01_05, SPRPort02_03_11, SPRPort05]> {
3404  let Latency = 20;
3405  let NumMicroOps = 5;
3406}
3407def : InstRW<[SPRWriteResGroup346], (instregex "^VCVT(U?)QQ2PHZ256rm(bk|kz)$",
3408                                               "^VCVT(U?)QQ2PHZ256rm(k|bkz)$")>;
3409
3410def SPRWriteResGroup347 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort01_05, SPRPort05]> {
3411  let Latency = 12;
3412  let NumMicroOps = 4;
3413}
3414def : InstRW<[SPRWriteResGroup347], (instregex "^VCVT(U?)QQ2PHZ256rrk(z?)$")>;
3415
3416def SPRWriteResGroup348 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort02_03_11, SPRPort05]> {
3417  let ReleaseAtCycles = [1, 1, 1, 2];
3418  let Latency = 18;
3419  let NumMicroOps = 5;
3420}
3421def : InstRW<[SPRWriteResGroup348], (instregex "^VCVT(U?)QQ2PHZrm(b?)$")>;
3422
3423def SPRWriteResGroup349 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort02_03_11, SPRPort05]> {
3424  let ReleaseAtCycles = [1, 1, 1, 2];
3425  let Latency = 20;
3426  let NumMicroOps = 5;
3427}
3428def : InstRW<[SPRWriteResGroup349], (instregex "^VCVT(U?)QQ2PHZrm(bk|kz)$",
3429                                               "^VCVT(U?)QQ2PHZrm(k|bkz)$")>;
3430
3431def SPRWriteResGroup350 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort05]> {
3432  let ReleaseAtCycles = [1, 1, 2];
3433  let Latency = 10;
3434  let NumMicroOps = 4;
3435}
3436def : InstRW<[SPRWriteResGroup350], (instregex "^VCVT(U?)QQ2PHZrr(b?)$")>;
3437
3438def SPRWriteResGroup351 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort05]> {
3439  let ReleaseAtCycles = [1, 1, 2];
3440  let Latency = 12;
3441  let NumMicroOps = 4;
3442}
3443def : InstRW<[SPRWriteResGroup351], (instregex "^VCVT(U?)QQ2PHZrr(bk|kz)$",
3444                                               "^VCVT(U?)QQ2PHZrr(k|bkz)$")>;
3445
3446def SPRWriteResGroup352 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_06, SPRPort02_03_11, SPRPort05]> {
3447  let ReleaseAtCycles = [2, 2, 1, 1, 1];
3448  let Latency = 18;
3449  let NumMicroOps = 7;
3450}
3451def : InstRW<[SPRWriteResGroup352, ReadAfterVecLd], (instregex "^VCVTSD2SHZrm((_Int)?)$")>;
3452
3453def SPRWriteResGroup353 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_06, SPRPort02_03_11, SPRPort05]> {
3454  let ReleaseAtCycles = [2, 2, 1, 1, 1];
3455  let Latency = 21;
3456  let NumMicroOps = 7;
3457}
3458def : InstRW<[SPRWriteResGroup353, ReadAfterVecLd], (instregex "^VCVTSD2SHZrm_Intk(z?)$")>;
3459
3460def SPRWriteResGroup354 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort05]> {
3461  let ReleaseAtCycles = [2, 1, 1];
3462  let Latency = 11;
3463  let NumMicroOps = 4;
3464}
3465def : InstRW<[SPRWriteResGroup354], (instregex "^VCVTSD2SHZrr(b?)_Int$")>;
3466def : InstRW<[SPRWriteResGroup354], (instrs VCVTSD2SHZrr)>;
3467
3468def SPRWriteResGroup355 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort05]> {
3469  let ReleaseAtCycles = [2, 1, 1];
3470  let Latency = 14;
3471  let NumMicroOps = 4;
3472}
3473def : InstRW<[SPRWriteResGroup355], (instregex "^VCVTSD2SHZrr(b?)_Intk(z?)$")>;
3474
3475def SPRWriteResGroup356 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_11, SPRPort05]> {
3476  let ReleaseAtCycles = [2, 1, 1];
3477  let Latency = 18;
3478  let NumMicroOps = 4;
3479}
3480def : InstRW<[SPRWriteResGroup356, ReadAfterVecLd], (instregex "^VCVTSH2SDZrm((_Int)?)$")>;
3481
3482def SPRWriteResGroup357 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_11, SPRPort05]> {
3483  let ReleaseAtCycles = [2, 1, 1];
3484  let Latency = 20;
3485  let NumMicroOps = 4;
3486}
3487def : InstRW<[SPRWriteResGroup357, ReadAfterVecLd], (instregex "^VCVTSH2SDZrm_Intk(z?)$")>;
3488
3489def SPRWriteResGroup358 : SchedWriteRes<[SPRPort00_01, SPRPort05]> {
3490  let ReleaseAtCycles = [2, 1];
3491  let Latency = 10;
3492  let NumMicroOps = 3;
3493}
3494def : InstRW<[SPRWriteResGroup358], (instregex "^VCVTSH2SDZrr(b?)_Int$")>;
3495def : InstRW<[SPRWriteResGroup358], (instrs VCVTSH2SDZrr)>;
3496
3497def SPRWriteResGroup359 : SchedWriteRes<[SPRPort00_01, SPRPort05]> {
3498  let ReleaseAtCycles = [2, 1];
3499  let Latency = 13;
3500  let NumMicroOps = 3;
3501}
3502def : InstRW<[SPRWriteResGroup359], (instregex "^VCVTSH2SDZrr(b?)_Intk(z?)$")>;
3503
3504def SPRWriteResGroup360 : SchedWriteRes<[SPRPort00, SPRPort00_01, SPRPort02_03_11]> {
3505  let Latency = 13;
3506  let NumMicroOps = 3;
3507}
3508def : InstRW<[SPRWriteResGroup360, ReadAfterVecLd], (instregex "^VCVT(T?)SH2(U?)SI((64)?)Zrm_Int$",
3509                                                               "^VCVTTSH2(U?)SI((64)?)Zrm$")>;
3510
3511def SPRWriteResGroup361 : SchedWriteRes<[SPRPort00, SPRPort00_01, SPRPort00_01_05]> {
3512  let Latency = 8;
3513  let NumMicroOps = 3;
3514}
3515def : InstRW<[SPRWriteResGroup361], (instregex "^VCVT(T?)SH2(U?)SI((64)?)Zrr(b?)_Int$",
3516                                               "^VCVTTSH2(U?)SI((64)?)Zrr$")>;
3517
3518def SPRWriteResGroup362 : SchedWriteRes<[SPRPort00_01]> {
3519  let Latency = 8;
3520}
3521def : InstRW<[SPRWriteResGroup362], (instregex "^VCVTSH2SSZrr(b?)_Intk(z?)$")>;
3522
3523def SPRWriteResGroup363 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort02_03_11]> {
3524  let Latency = 14;
3525  let NumMicroOps = 3;
3526}
3527def : InstRW<[SPRWriteResGroup363, ReadAfterVecLd], (instregex "^VCVT(U?)SI((64)?)2SHZrm((_Int)?)$",
3528                                                               "^VCVTSS2SHZrm((_Int)?)$")>;
3529
3530def SPRWriteResGroup364 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort02_03_11]> {
3531  let Latency = 16;
3532  let NumMicroOps = 3;
3533}
3534def : InstRW<[SPRWriteResGroup364, ReadAfterVecLd], (instregex "^VCVTSS2SHZrm_Intk(z?)$")>;
3535
3536def SPRWriteResGroup365 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05]> {
3537  let Latency = 6;
3538  let NumMicroOps = 2;
3539}
3540def : InstRW<[SPRWriteResGroup365], (instregex "^VCVTSS2SHZrr(b?)_Int$")>;
3541def : InstRW<[SPRWriteResGroup365], (instrs VCVTSS2SHZrr)>;
3542
3543def SPRWriteResGroup366 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05]> {
3544  let Latency = 9;
3545  let NumMicroOps = 2;
3546}
3547def : InstRW<[SPRWriteResGroup366], (instregex "^VCVTSS2SHZrr(b?)_Intk(z?)$")>;
3548
3549def SPRWriteResGroup367 : SchedWriteRes<[SPRPort05]> {
3550  let Latency = 5;
3551}
3552def : InstRW<[SPRWriteResGroup367], (instregex "^VDBPSADBWZ(128|256)rrik(z?)$",
3553                                               "^VDBPSADBWZrrik(z?)$",
3554                                               "^VPACK(S|U)S(DW|WB)Z(128|256)rrk(z?)$",
3555                                               "^VPACK(S|U)S(DW|WB)Zrrk(z?)$",
3556                                               "^VPBROADCAST(B|W|Dr|Qr|Wr)Z((256)?)rrk(z?)$",
3557                                               "^VPBROADCAST(B|D|Q|W)rZ(128|256)rr$",
3558                                               "^VPBROADCASTBrZ(128|256)rrk(z?)$",
3559                                               "^VPBROADCAST(B|D|Q|W)rZrr$",
3560                                               "^VPBROADCASTBrZrrk(z?)$",
3561                                               "^VPBROADCAST(D|Q|W)rZ128rrk(z?)$",
3562                                               "^VPERMBZ(128|256)rrk(z?)$",
3563                                               "^VPERMBZrrk(z?)$",
3564                                               "^VPMOV(S|Z)XBWZ((256)?)rrk(z?)$",
3565                                               "^VPMULTISHIFTQBZ(128|256)rrk(z?)$",
3566                                               "^VPMULTISHIFTQBZrrk(z?)$",
3567                                               "^VPOPCNT(B|W)Z(128|256)rrk(z?)$",
3568                                               "^VPOPCNT(B|W)Zrrk(z?)$")>;
3569
3570def SPRWriteResGroup368 : SchedWriteRes<[SPRPort00, SPRPort00_01_05, SPRPort02_03_11]> {
3571  let ReleaseAtCycles = [2, 1, 1];
3572  let Latency = 36;
3573  let NumMicroOps = 4;
3574}
3575def : InstRW<[SPRWriteResGroup368, ReadAfterVecXLd], (instregex "^VDIVPHZ128rm(b?)$")>;
3576
3577def SPRWriteResGroup369 : SchedWriteRes<[SPRPort00, SPRPort00_01_05, SPRPort02_03_11]> {
3578  let ReleaseAtCycles = [2, 1, 1];
3579  let Latency = 38;
3580  let NumMicroOps = 4;
3581}
3582def : InstRW<[SPRWriteResGroup369, ReadAfterVecXLd], (instregex "^VDIVPHZ128rm(bk|kz)$",
3583                                                                "^VDIVPHZ128rm(k|bkz)$")>;
3584
3585def SPRWriteResGroup370 : SchedWriteRes<[SPRPort00, SPRPort00_01_05]> {
3586  let ReleaseAtCycles = [2, 1];
3587  let Latency = 31;
3588  let NumMicroOps = 3;
3589}
3590def : InstRW<[SPRWriteResGroup370], (instregex "^VDIVPHZ(128|256)rr$")>;
3591
3592def SPRWriteResGroup371 : SchedWriteRes<[SPRPort00, SPRPort00_01_05]> {
3593  let ReleaseAtCycles = [2, 1];
3594  let Latency = 33;
3595  let NumMicroOps = 3;
3596}
3597def : InstRW<[SPRWriteResGroup371], (instregex "^VDIVPHZ(128|256)rrk$",
3598                                               "^VSQRTPHZ(128|256)r$")>;
3599def : InstRW<[SPRWriteResGroup371], (instrs VDIVPHZ128rrkz)>;
3600
3601def SPRWriteResGroup372 : SchedWriteRes<[SPRPort00, SPRPort00_01_05, SPRPort02_03_11]> {
3602  let ReleaseAtCycles = [2, 1, 1];
3603  let Latency = 37;
3604  let NumMicroOps = 4;
3605}
3606def : InstRW<[SPRWriteResGroup372, ReadAfterVecYLd], (instregex "^VDIVPHZ256rm(b?)$")>;
3607
3608def SPRWriteResGroup373 : SchedWriteRes<[SPRPort00, SPRPort00_01_05, SPRPort02_03_11]> {
3609  let ReleaseAtCycles = [2, 1, 1];
3610  let Latency = 39;
3611  let NumMicroOps = 4;
3612}
3613def : InstRW<[SPRWriteResGroup373, ReadAfterVecYLd], (instregex "^VDIVPHZ256rm(bk|kz)$",
3614                                                                "^VDIVPHZ256rm(k|bkz)$")>;
3615def : InstRW<[SPRWriteResGroup373, ReadAfterVecXLd], (instregex "^VSQRTPHZ128m(b?)$")>;
3616
3617def SPRWriteResGroup374 : SchedWriteRes<[SPRPort00, SPRPort00_01_05]> {
3618  let ReleaseAtCycles = [2, 1];
3619  let Latency = 11;
3620  let NumMicroOps = 3;
3621}
3622def : InstRW<[SPRWriteResGroup374], (instrs VDIVPHZ256rrkz)>;
3623
3624def SPRWriteResGroup375 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort00_06, SPRPort02_03_11, SPRPort05]> {
3625  let ReleaseAtCycles = [4, 2, 1, 1, 1];
3626  let Latency = 49;
3627  let NumMicroOps = 9;
3628}
3629def : InstRW<[SPRWriteResGroup375, ReadAfterVecYLd], (instregex "^VDIVPHZrm(b?)$")>;
3630
3631def SPRWriteResGroup376 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort00_06, SPRPort02_03_11, SPRPort05]> {
3632  let ReleaseAtCycles = [4, 2, 1, 1, 1];
3633  let Latency = 51;
3634  let NumMicroOps = 9;
3635}
3636def : InstRW<[SPRWriteResGroup376, ReadAfterVecYLd], (instregex "^VDIVPHZrm(bk|kz)$",
3637                                                                "^VDIVPHZrm(k|bkz)$")>;
3638
3639def SPRWriteResGroup377 : SchedWriteRes<[SPRPort00, SPRPort00_06, SPRPort05]> {
3640  let ReleaseAtCycles = [4, 1, 1];
3641  let Latency = 41;
3642  let NumMicroOps = 6;
3643}
3644def : InstRW<[SPRWriteResGroup377], (instregex "^VDIVPHZrr(b?)$")>;
3645
3646def SPRWriteResGroup378 : SchedWriteRes<[SPRPort00, SPRPort00_06, SPRPort05]> {
3647  let ReleaseAtCycles = [4, 1, 1];
3648  let Latency = 43;
3649  let NumMicroOps = 6;
3650}
3651def : InstRW<[SPRWriteResGroup378], (instregex "^VDIVPHZrr(bk|kz)$",
3652                                               "^VDIVPHZrr(k|bkz)$")>;
3653
3654def SPRWriteResGroup379 : SchedWriteRes<[SPRPort00, SPRPort00_05]> {
3655  let ReleaseAtCycles = [2, 1];
3656  let Latency = 17;
3657  let NumMicroOps = 3;
3658}
3659def : InstRW<[SPRWriteResGroup379], (instrs VDIVPSZrr)>;
3660
3661def SPRWriteResGroup380 : SchedWriteRes<[SPRPort00, SPRPort02_03_11]> {
3662  let Latency = 21;
3663  let NumMicroOps = 2;
3664}
3665def : InstRW<[SPRWriteResGroup380, ReadAfterVecLd], (instregex "^VDIVSHZrm_Int((k|kz)?)$")>;
3666def : InstRW<[SPRWriteResGroup380, ReadAfterVecLd], (instrs VDIVSHZrm)>;
3667
3668def SPRWriteResGroup381 : SchedWriteRes<[SPRPort00]> {
3669  let Latency = 14;
3670}
3671def : InstRW<[SPRWriteResGroup381], (instrs VDIVSHZrr_Int,
3672                                            VSQRTSHZr_Int)>;
3673
3674def SPRWriteResGroup382 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_11, SPRPort05]> {
3675  let ReleaseAtCycles = [2, 1, 2];
3676  let Latency = 15;
3677  let NumMicroOps = 5;
3678}
3679def : InstRW<[SPRWriteResGroup382, ReadAfterVecXLd], (instregex "^VDPBF16PSZ128m((b|k|bk|kz)?)$")>;
3680def : InstRW<[SPRWriteResGroup382, ReadAfterVecXLd], (instrs VDPBF16PSZ128mbkz)>;
3681
3682def SPRWriteResGroup383 : SchedWriteRes<[SPRPort00_01, SPRPort05]> {
3683  let ReleaseAtCycles = [2, 2];
3684  let Latency = 8;
3685  let NumMicroOps = 4;
3686}
3687def : InstRW<[SPRWriteResGroup383], (instregex "^VDPBF16PSZ(128|256)r((k|kz)?)$")>;
3688
3689def SPRWriteResGroup384 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_11, SPRPort05]> {
3690  let ReleaseAtCycles = [2, 1, 2];
3691  let Latency = 16;
3692  let NumMicroOps = 5;
3693}
3694def : InstRW<[SPRWriteResGroup384, ReadAfterVecYLd], (instregex "^VDPBF16PSZ256m((b|k|bk|kz)?)$")>;
3695def : InstRW<[SPRWriteResGroup384, ReadAfterVecYLd], (instrs VDPBF16PSZ256mbkz)>;
3696
3697def SPRWriteResGroup385 : SchedWriteRes<[SPRPort00, SPRPort01, SPRPort02_03_11]> {
3698  let ReleaseAtCycles = [6, 7, 18];
3699  let Latency = 81;
3700  let NumMicroOps = 31;
3701}
3702def : InstRW<[SPRWriteResGroup385], (instrs VERRm)>;
3703
3704def SPRWriteResGroup386 : SchedWriteRes<[SPRPort00, SPRPort01, SPRPort02_03_11]> {
3705  let ReleaseAtCycles = [6, 7, 17];
3706  let Latency = 74;
3707  let NumMicroOps = 30;
3708}
3709def : InstRW<[SPRWriteResGroup386], (instrs VERRr)>;
3710
3711def SPRWriteResGroup387 : SchedWriteRes<[SPRPort00, SPRPort01, SPRPort02_03_11]> {
3712  let ReleaseAtCycles = [5, 8, 21];
3713  let Latency = 81;
3714  let NumMicroOps = 34;
3715}
3716def : InstRW<[SPRWriteResGroup387], (instrs VERWm)>;
3717
3718def SPRWriteResGroup388 : SchedWriteRes<[SPRPort00, SPRPort01, SPRPort02_03_11]> {
3719  let ReleaseAtCycles = [5, 8, 20];
3720  let Latency = 74;
3721  let NumMicroOps = 33;
3722}
3723def : InstRW<[SPRWriteResGroup388], (instrs VERWr)>;
3724
3725def SPRWriteResGroup389 : SchedWriteRes<[SPRPort02_03_11, SPRPort05]> {
3726  let ReleaseAtCycles = [1, 2];
3727  let Latency = 10;
3728  let NumMicroOps = 3;
3729}
3730def : InstRW<[SPRWriteResGroup389, ReadAfterVecYLd], (instregex "^VEXPANDP(D|S)Z128rm((k|kz)?)$",
3731                                                                "^VPEXPAND(B|D|Q|W)Z128rm$",
3732                                                                "^VPEXPAND(D|Q)Z128rmk(z?)$")>;
3733
3734def SPRWriteResGroup390 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_11]> {
3735  let ReleaseAtCycles = [2, 1];
3736  let Latency = 16;
3737  let NumMicroOps = 3;
3738}
3739def : InstRW<[SPRWriteResGroup390], (instregex "^VF(C?)MADDCPHZ(128|256)m(b?)$",
3740                                               "^VROUNDP(D|S)Ym$")>;
3741def : InstRW<[SPRWriteResGroup390, ReadAfterVecXLd], (instregex "^VF(C?)MADDCSHZm$",
3742                                                                "^VF(C?)MULCPHZ128rm(b?)$",
3743                                                                "^VF(C?)MULCSHZrm$",
3744                                                                "^VRNDSCALEPHZ128rm(b?)i$",
3745                                                                "^VRNDSCALESHZm((_Int)?)$",
3746                                                                "^VSCALEFPHZ128rm(b?)$")>;
3747def : InstRW<[SPRWriteResGroup390, ReadAfterVecYLd], (instregex "^VF(C?)MULCPHZ256rm(b?)$",
3748                                                                "^VRNDSCALEP(D|H|S)Z256rm(b?)i$",
3749                                                                "^VRNDSCALEP(D|S)Z256rm(b?)ik(z?)$",
3750                                                                "^VSCALEFPHZ256rm(b?)$")>;
3751def : InstRW<[SPRWriteResGroup390, ReadAfterVecLd], (instrs VSCALEFSHZrm)>;
3752
3753def SPRWriteResGroup391 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_11]> {
3754  let ReleaseAtCycles = [2, 1];
3755  let Latency = 21;
3756  let NumMicroOps = 3;
3757}
3758def : InstRW<[SPRWriteResGroup391], (instregex "^VF(C?)MADDCPHZ(128|256)m(bk|kz)$",
3759                                               "^VF(C?)MADDCPHZ(128|256)m(k|bkz)$")>;
3760def : InstRW<[SPRWriteResGroup391, ReadAfterVecXLd], (instregex "^VF(C?)MADDCSHZmk(z?)$",
3761                                                                "^VF(C?)MULCPHZ128rm(bk|kz)$",
3762                                                                "^VF(C?)MULCPHZ128rm(k|bkz)$",
3763                                                                "^VF(C?)MULCSHZrmk(z?)$")>;
3764def : InstRW<[SPRWriteResGroup391, ReadAfterVecYLd], (instregex "^VF(C?)MULCPHZ256rm(bk|kz)$",
3765                                                                "^VF(C?)MULCPHZ256rm(k|bkz)$")>;
3766
3767def SPRWriteResGroup392 : SchedWriteRes<[SPRPort00_01]> {
3768  let ReleaseAtCycles = [2];
3769  let Latency = 9;
3770  let NumMicroOps = 2;
3771}
3772def : InstRW<[SPRWriteResGroup392], (instregex "^VF(C?)MADDCPHZ(128|256)r$",
3773                                               "^VF(C?)MADDCSHZr(b?)$",
3774                                               "^VF(C?)MULCPHZ(128|256)rr$",
3775                                               "^VF(C?)MULCSHZrr(b?)$",
3776                                               "^VRNDSCALEPHZ(128|256)rri$",
3777                                               "^VRNDSCALESHZr(b?)_Int$",
3778                                               "^VSCALEFPHZ(128|256)rr$")>;
3779def : InstRW<[SPRWriteResGroup392], (instrs VRNDSCALESHZr,
3780                                            VSCALEFSHZrr,
3781                                            VSCALEFSHZrrb_Int)>;
3782
3783def SPRWriteResGroup393 : SchedWriteRes<[SPRPort00_01]> {
3784  let ReleaseAtCycles = [2];
3785  let Latency = 15;
3786  let NumMicroOps = 2;
3787}
3788def : InstRW<[SPRWriteResGroup393], (instregex "^VF(C?)MADDCPHZ(128|256)rk(z?)$",
3789                                               "^VF(C?)MADDCSHZr(bk|kz)$",
3790                                               "^VF(C?)MADDCSHZr(k|bkz)$",
3791                                               "^VF(C?)MULCPHZ(128|256)rrk(z?)$",
3792                                               "^VF(C?)MULCSHZrr(bk|kz)$",
3793                                               "^VF(C?)MULCSHZrr(k|bkz)$")>;
3794
3795def SPRWriteResGroup394 : SchedWriteRes<[SPRPort00, SPRPort02_03_11]> {
3796  let ReleaseAtCycles = [2, 1];
3797  let Latency = 16;
3798  let NumMicroOps = 3;
3799}
3800def : InstRW<[SPRWriteResGroup394], (instregex "^VF(C?)MADDCPHZm(b?)$")>;
3801def : InstRW<[SPRWriteResGroup394, ReadAfterVecYLd], (instregex "^VF(C?)MULCPHZrm(b?)$",
3802                                                                "^VRNDSCALEP(D|H|S)Zrm(b?)i$",
3803                                                                "^VRNDSCALEP(D|S)Zrm(b?)ik(z?)$",
3804                                                                "^VSCALEFPHZrm(b?)$")>;
3805
3806def SPRWriteResGroup395 : SchedWriteRes<[SPRPort00, SPRPort02_03_11]> {
3807  let ReleaseAtCycles = [2, 1];
3808  let Latency = 21;
3809  let NumMicroOps = 3;
3810}
3811def : InstRW<[SPRWriteResGroup395], (instregex "^VF(C?)MADDCPHZm(bk|kz)$",
3812                                               "^VF(C?)MADDCPHZm(k|bkz)$")>;
3813def : InstRW<[SPRWriteResGroup395, ReadAfterVecYLd], (instregex "^VF(C?)MULCPHZrm(bk|kz)$",
3814                                                                "^VF(C?)MULCPHZrm(k|bkz)$")>;
3815
3816def SPRWriteResGroup396 : SchedWriteRes<[SPRPort00]> {
3817  let ReleaseAtCycles = [2];
3818  let Latency = 9;
3819  let NumMicroOps = 2;
3820}
3821def : InstRW<[SPRWriteResGroup396], (instregex "^VF(C?)MADDCPHZr(b?)$",
3822                                               "^VF(C?)MULCPHZrr(b?)$",
3823                                               "^VRNDSCALEPHZrri(b?)$",
3824                                               "^VSCALEFPHZrr(b?)$")>;
3825
3826def SPRWriteResGroup397 : SchedWriteRes<[SPRPort00]> {
3827  let ReleaseAtCycles = [2];
3828  let Latency = 15;
3829  let NumMicroOps = 2;
3830}
3831def : InstRW<[SPRWriteResGroup397], (instregex "^VF(C?)MADDCPHZr(bk|kz)$",
3832                                               "^VF(C?)MADDCPHZr(k|bkz)$",
3833                                               "^VF(C?)MULCPHZrr(bk|kz)$",
3834                                               "^VF(C?)MULCPHZrr(k|bkz)$")>;
3835
3836def SPRWriteResGroup398 : SchedWriteRes<[SPRPort00, SPRPort00_01_05, SPRPort01_05, SPRPort02_03_11]> {
3837  let ReleaseAtCycles = [1, 1, 2, 4];
3838  let Latency = 29;
3839  let NumMicroOps = 8;
3840}
3841def : InstRW<[SPRWriteResGroup398, WriteVecMaskedGatherWriteback], (instregex "^VGATHER(D|Q)PDYrm$",
3842                                                                              "^VPGATHER(D|Q)QYrm$")>;
3843def : InstRW<[SPRWriteResGroup398, WriteVecMaskedGatherWriteback], (instrs VGATHERQPSYrm,
3844                                                                           VPGATHERQDYrm)>;
3845
3846def SPRWriteResGroup399 : SchedWriteRes<[SPRPort00, SPRPort01_05, SPRPort02_03_11]> {
3847  let ReleaseAtCycles = [1, 1, 2];
3848  let Latency = 20;
3849  let NumMicroOps = 4;
3850}
3851def : InstRW<[SPRWriteResGroup399, WriteVecMaskedGatherWriteback], (instregex "^VGATHER(D|Q)PDZ128rm$",
3852                                                                              "^VPGATHER(D|Q)QZ128rm$")>;
3853def : InstRW<[SPRWriteResGroup399, WriteVecMaskedGatherWriteback], (instrs VGATHERQPSZ128rm,
3854                                                                           VPGATHERQDZ128rm)>;
3855
3856def SPRWriteResGroup400 : SchedWriteRes<[SPRPort00, SPRPort01_05, SPRPort02_03_11]> {
3857  let ReleaseAtCycles = [1, 2, 4];
3858  let Latency = 28;
3859  let NumMicroOps = 7;
3860}
3861def : InstRW<[SPRWriteResGroup400, WriteVecMaskedGatherWriteback], (instregex "^VGATHER(D|Q)PDZ256rm$",
3862                                                                              "^VPGATHER(D|Q)QZ256rm$")>;
3863def : InstRW<[SPRWriteResGroup400, WriteVecMaskedGatherWriteback], (instrs VGATHERQPSZ256rm,
3864                                                                           VPGATHERQDZ256rm)>;
3865
3866def SPRWriteResGroup401 : SchedWriteRes<[SPRPort00, SPRPort02_03_11, SPRPort05]> {
3867  let ReleaseAtCycles = [1, 8, 2];
3868  let Latency = 28;
3869  let NumMicroOps = 11;
3870}
3871def : InstRW<[SPRWriteResGroup401, WriteVecMaskedGatherWriteback], (instregex "^VGATHER(D|Q)PDZrm$",
3872                                                                              "^VPGATHER(D|Q)QZrm$")>;
3873def : InstRW<[SPRWriteResGroup401, WriteVecMaskedGatherWriteback], (instrs VGATHERQPSZrm,
3874                                                                           VPGATHERQDZrm)>;
3875
3876def SPRWriteResGroup402 : SchedWriteRes<[SPRPort00, SPRPort00_01_05, SPRPort01_05, SPRPort02_03_11]> {
3877  let ReleaseAtCycles = [1, 1, 1, 2];
3878  let Latency = 20;
3879  let NumMicroOps = 5;
3880}
3881def : InstRW<[SPRWriteResGroup402, WriteVecMaskedGatherWriteback], (instregex "^VGATHER(D|Q)PDrm$",
3882                                                                              "^VPGATHER(D|Q)Qrm$")>;
3883def : InstRW<[SPRWriteResGroup402, WriteVecMaskedGatherWriteback], (instrs VGATHERQPSrm,
3884                                                                           VPGATHERQDrm)>;
3885
3886def SPRWriteResGroup403 : SchedWriteRes<[SPRPort00, SPRPort00_01_05, SPRPort01_05, SPRPort02_03_11]> {
3887  let ReleaseAtCycles = [1, 1, 2, 8];
3888  let Latency = 30;
3889  let NumMicroOps = 12;
3890}
3891def : InstRW<[SPRWriteResGroup403, WriteVecMaskedGatherWriteback], (instrs VGATHERDPSYrm,
3892                                                                           VPGATHERDDYrm)>;
3893
3894def SPRWriteResGroup404 : SchedWriteRes<[SPRPort00, SPRPort01_05, SPRPort02_03_11]> {
3895  let ReleaseAtCycles = [1, 2, 4];
3896  let Latency = 27;
3897  let NumMicroOps = 7;
3898}
3899def : InstRW<[SPRWriteResGroup404, WriteVecMaskedGatherWriteback], (instrs VGATHERDPSZ128rm,
3900                                                                           VPGATHERDDZ128rm)>;
3901
3902def SPRWriteResGroup405 : SchedWriteRes<[SPRPort00, SPRPort01_05, SPRPort02_03_11]> {
3903  let ReleaseAtCycles = [1, 2, 8];
3904  let Latency = 29;
3905  let NumMicroOps = 11;
3906}
3907def : InstRW<[SPRWriteResGroup405, WriteVecMaskedGatherWriteback], (instrs VGATHERDPSZ256rm,
3908                                                                           VPGATHERDDZ256rm)>;
3909
3910def SPRWriteResGroup406 : SchedWriteRes<[SPRPort00, SPRPort02_03_11, SPRPort05]> {
3911  let ReleaseAtCycles = [1, 16, 2];
3912  let Latency = 30;
3913  let NumMicroOps = 19;
3914}
3915def : InstRW<[SPRWriteResGroup406, WriteVecMaskedGatherWriteback], (instrs VGATHERDPSZrm,
3916                                                                           VPGATHERDDZrm)>;
3917
3918def SPRWriteResGroup407 : SchedWriteRes<[SPRPort00, SPRPort00_01_05, SPRPort01_05, SPRPort02_03_11]> {
3919  let ReleaseAtCycles = [1, 1, 2, 4];
3920  let Latency = 28;
3921  let NumMicroOps = 8;
3922}
3923def : InstRW<[SPRWriteResGroup407, WriteVecMaskedGatherWriteback], (instrs VGATHERDPSrm,
3924                                                                           VPGATHERDDrm)>;
3925
3926def SPRWriteResGroup408 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_11]> {
3927  let Latency = 15;
3928  let NumMicroOps = 2;
3929}
3930def : InstRW<[SPRWriteResGroup408, ReadAfterVecXLd], (instregex "^VGF2P8AFFINE((INV)?)QBZ128rm(b?)ik(z?)$",
3931                                                                "^VGF2P8MULBZ128rmk(z?)$")>;
3932def : InstRW<[SPRWriteResGroup408, ReadAfterVecYLd], (instregex "^VGF2P8AFFINE((INV)?)QBZ256rm(b?)ik(z?)$",
3933                                                                "^VGF2P8MULBZ256rmk(z?)$")>;
3934
3935def SPRWriteResGroup409 : SchedWriteRes<[SPRPort00_01]> {
3936  let Latency = 9;
3937}
3938def : InstRW<[SPRWriteResGroup409], (instregex "^VGF2P8AFFINE((INV)?)QBZ(128|256)rrik$",
3939                                               "^VGF2P8MULBZ(128|256)rrk$")>;
3940
3941def SPRWriteResGroup410 : SchedWriteRes<[SPRPort00_01]> {
3942  let Latency = 10;
3943}
3944def : InstRW<[SPRWriteResGroup410], (instregex "^VGF2P8AFFINE((INV)?)QBZ(128|256)rrikz$",
3945                                               "^VGF2P8MULBZ(128|256)rrkz$")>;
3946
3947def SPRWriteResGroup411 : SchedWriteRes<[SPRPort00, SPRPort02_03_11]> {
3948  let Latency = 15;
3949  let NumMicroOps = 2;
3950}
3951def : InstRW<[SPRWriteResGroup411, ReadAfterVecYLd], (instregex "^VGF2P8AFFINE((INV)?)QBZrm(b?)ik(z?)$",
3952                                                                "^VGF2P8MULBZrmk(z?)$")>;
3953
3954def SPRWriteResGroup412 : SchedWriteRes<[SPRPort00]> {
3955  let Latency = 9;
3956}
3957def : InstRW<[SPRWriteResGroup412], (instregex "^VGF2P8AFFINE((INV)?)QBZrrik$")>;
3958def : InstRW<[SPRWriteResGroup412], (instrs VGF2P8MULBZrrk)>;
3959
3960def SPRWriteResGroup413 : SchedWriteRes<[SPRPort00]> {
3961  let Latency = 10;
3962}
3963def : InstRW<[SPRWriteResGroup413], (instregex "^VGF2P8AFFINE((INV)?)QBZrrikz$")>;
3964def : InstRW<[SPRWriteResGroup413], (instrs VGF2P8MULBZrrkz)>;
3965
3966def SPRWriteResGroup414 : SchedWriteRes<[SPRPort01_05, SPRPort05]> {
3967  let ReleaseAtCycles = [1, 2];
3968  let Latency = 5;
3969  let NumMicroOps = 3;
3970}
3971def : InstRW<[SPRWriteResGroup414], (instregex "^VH(ADD|SUB)P(D|S)rr$")>;
3972
3973def SPRWriteResGroup415 : SchedWriteRes<[SPRPort00, SPRPort00_06, SPRPort02_03_11]> {
3974  let Latency = 7;
3975  let NumMicroOps = 3;
3976}
3977def : InstRW<[SPRWriteResGroup415], (instrs VLDMXCSR)>;
3978
3979def SPRWriteResGroup416 : SchedWriteRes<[SPRPort01, SPRPort01_05, SPRPort02_03, SPRPort02_03_11, SPRPort04, SPRPort04_09, SPRPort05, SPRPort06]> {
3980  let ReleaseAtCycles = [1, 1, 1, 8, 1, 1, 2, 3];
3981  let Latency = 40;
3982  let NumMicroOps = 18;
3983}
3984def : InstRW<[SPRWriteResGroup416], (instrs VMCLEARm)>;
3985
3986def SPRWriteResGroup417 : SchedWriteRes<[SPRPort00_01_05, SPRPort02_03_11]> {
3987  let Latency = 11;
3988  let NumMicroOps = 2;
3989}
3990def : InstRW<[SPRWriteResGroup417], (instregex "^VMOVDQU(8|16)Z(128|256)rmk(z?)$",
3991                                               "^VMOVSHZrmk(z?)$")>;
3992def : InstRW<[SPRWriteResGroup417, ReadAfterVecXLd], (instregex "^VP(ADD|SUB)(B|W)Z128rmk(z?)$",
3993                                                                "^VPBLENDM(B|W)Z128rmk(z?)$")>;
3994def : InstRW<[SPRWriteResGroup417, ReadAfterVecYLd], (instregex "^VP(ADD|SUB)(B|W)Z256rmk(z?)$",
3995                                                                "^VPBLENDM(B|W)Z256rmk(z?)$")>;
3996
3997def SPRWriteResGroup418 : SchedWriteRes<[SPRPort00_01_05]> {
3998  let Latency = 3;
3999}
4000def : InstRW<[SPRWriteResGroup418], (instregex "^VMOVDQU(8|16)Z(128|256)rrk(z?)((_REV)?)$",
4001                                               "^VMOVSHZrrk(z?)((_REV)?)$",
4002                                               "^VP(ADD|SUB)(B|W)Z(128|256)rrk(z?)$",
4003                                               "^VPBLENDM(B|W)Z(128|256)rrk(z?)$",
4004                                               "^VPMOVM2(B|W)Z(128|256)rr$")>;
4005
4006def SPRWriteResGroup419 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort04_09, SPRPort07_08]> {
4007  let ReleaseAtCycles = [1, 2, 2];
4008  let Latency = 12;
4009  let NumMicroOps = 5;
4010}
4011def : InstRW<[SPRWriteResGroup419], (instrs VMOVDQU8Zmrk)>;
4012
4013def SPRWriteResGroup420 : SchedWriteRes<[SPRPort04_09, SPRPort07_08]> {
4014  let Latency = 477;
4015  let NumMicroOps = 2;
4016}
4017def : InstRW<[SPRWriteResGroup420], (instrs VMOVNTDQZ128mr)>;
4018
4019def SPRWriteResGroup421 : SchedWriteRes<[SPRPort04_09, SPRPort07_08]> {
4020  let Latency = 470;
4021  let NumMicroOps = 2;
4022}
4023def : InstRW<[SPRWriteResGroup421], (instrs VMOVNTDQZ256mr,
4024                                            VMOVNTPSmr)>;
4025
4026def SPRWriteResGroup422 : SchedWriteRes<[SPRPort04_09, SPRPort07_08]> {
4027  let Latency = 473;
4028  let NumMicroOps = 2;
4029}
4030def : InstRW<[SPRWriteResGroup422], (instregex "^VMOVNT(PD|DQZ)mr$")>;
4031
4032def SPRWriteResGroup423 : SchedWriteRes<[SPRPort04_09, SPRPort07_08]> {
4033  let Latency = 521;
4034  let NumMicroOps = 2;
4035}
4036def : InstRW<[SPRWriteResGroup423], (instrs VMOVNTDQmr)>;
4037
4038def SPRWriteResGroup424 : SchedWriteRes<[SPRPort04_09, SPRPort07_08]> {
4039  let Latency = 550;
4040  let NumMicroOps = 2;
4041}
4042def : InstRW<[SPRWriteResGroup424], (instrs VMOVNTPDZ128mr)>;
4043
4044def SPRWriteResGroup425 : SchedWriteRes<[SPRPort04_09, SPRPort07_08]> {
4045  let Latency = 474;
4046  let NumMicroOps = 2;
4047}
4048def : InstRW<[SPRWriteResGroup425], (instrs VMOVNTPDZ256mr)>;
4049
4050def SPRWriteResGroup426 : SchedWriteRes<[SPRPort04_09, SPRPort07_08]> {
4051  let Latency = 464;
4052  let NumMicroOps = 2;
4053}
4054def : InstRW<[SPRWriteResGroup426], (instrs VMOVNTPDZmr)>;
4055
4056def SPRWriteResGroup427 : SchedWriteRes<[SPRPort04_09, SPRPort07_08]> {
4057  let Latency = 494;
4058  let NumMicroOps = 2;
4059}
4060def : InstRW<[SPRWriteResGroup427], (instrs VMOVNTPSYmr)>;
4061
4062def SPRWriteResGroup428 : SchedWriteRes<[SPRPort04_09, SPRPort07_08]> {
4063  let Latency = 475;
4064  let NumMicroOps = 2;
4065}
4066def : InstRW<[SPRWriteResGroup428], (instrs VMOVNTPSZ128mr)>;
4067
4068def SPRWriteResGroup429 : SchedWriteRes<[SPRPort04_09, SPRPort07_08]> {
4069  let Latency = 476;
4070  let NumMicroOps = 2;
4071}
4072def : InstRW<[SPRWriteResGroup429], (instrs VMOVNTPSZ256mr)>;
4073
4074def SPRWriteResGroup430 : SchedWriteRes<[SPRPort04_09, SPRPort07_08]> {
4075  let Latency = 471;
4076  let NumMicroOps = 2;
4077}
4078def : InstRW<[SPRWriteResGroup430], (instrs VMOVNTPSZmr)>;
4079
4080def SPRWriteResGroup431 : SchedWriteRes<[SPRPort00_01_05, SPRPort02_03_11, SPRPort05]> {
4081  let ReleaseAtCycles = [3, 1, 8];
4082  let Latency = 10;
4083  let NumMicroOps = 12;
4084}
4085def : InstRW<[SPRWriteResGroup431, ReadAfterVecXLd], (instregex "^VP2INTERSECTDZ128rm(b?)$")>;
4086def : InstRW<[SPRWriteResGroup431, ReadAfterVecYLd], (instregex "^VP2INTERSECTQZ256rm(b?)$")>;
4087
4088def SPRWriteResGroup432 : SchedWriteRes<[SPRPort00_01_05, SPRPort05]> {
4089  let ReleaseAtCycles = [4, 8];
4090  let Latency = 10;
4091  let NumMicroOps = 12;
4092}
4093def : InstRW<[SPRWriteResGroup432], (instrs VP2INTERSECTDZ128rr,
4094                                            VP2INTERSECTQZ256rr)>;
4095
4096def SPRWriteResGroup433 : SchedWriteRes<[SPRPort00, SPRPort00_01, SPRPort00_01_05, SPRPort01_05, SPRPort02_03_11, SPRPort05]> {
4097  let ReleaseAtCycles = [1, 8, 7, 2, 1, 11];
4098  let Latency = 27;
4099  let NumMicroOps = 30;
4100}
4101def : InstRW<[SPRWriteResGroup433, ReadAfterVecYLd], (instregex "^VP2INTERSECTDZ256rm(b?)$")>;
4102
4103def SPRWriteResGroup434 : SchedWriteRes<[SPRPort00, SPRPort00_01, SPRPort00_01_05, SPRPort01_05, SPRPort05]> {
4104  let ReleaseAtCycles = [1, 8, 8, 2, 11];
4105  let Latency = 27;
4106  let NumMicroOps = 30;
4107}
4108def : InstRW<[SPRWriteResGroup434], (instrs VP2INTERSECTDZ256rr)>;
4109
4110def SPRWriteResGroup435 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort02_03_11, SPRPort05]> {
4111  let ReleaseAtCycles = [13, 9, 1, 23];
4112  let Latency = 40;
4113  let NumMicroOps = 46;
4114}
4115def : InstRW<[SPRWriteResGroup435, ReadAfterVecYLd], (instregex "^VP2INTERSECTDZrm(b?)$")>;
4116
4117def SPRWriteResGroup436 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort05]> {
4118  let ReleaseAtCycles = [13, 10, 23];
4119  let Latency = 40;
4120  let NumMicroOps = 46;
4121}
4122def : InstRW<[SPRWriteResGroup436], (instrs VP2INTERSECTDZrr)>;
4123
4124def SPRWriteResGroup437 : SchedWriteRes<[SPRPort02_03_11, SPRPort05]> {
4125  let ReleaseAtCycles = [1, 4];
4126  let Latency = 6;
4127  let NumMicroOps = 5;
4128}
4129def : InstRW<[SPRWriteResGroup437, ReadAfterVecXLd], (instregex "^VP2INTERSECTQZ128rm(b?)$")>;
4130
4131def SPRWriteResGroup438 : SchedWriteRes<[SPRPort05]> {
4132  let ReleaseAtCycles = [4];
4133  let Latency = 6;
4134  let NumMicroOps = 4;
4135}
4136def : InstRW<[SPRWriteResGroup438], (instrs VP2INTERSECTQZ128rr)>;
4137
4138def SPRWriteResGroup439 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort02_03_11, SPRPort05]> {
4139  let ReleaseAtCycles = [8, 7, 1, 14];
4140  let Latency = 29;
4141  let NumMicroOps = 30;
4142}
4143def : InstRW<[SPRWriteResGroup439, ReadAfterVecYLd], (instregex "^VP2INTERSECTQZrm(b?)$")>;
4144
4145def SPRWriteResGroup440 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort05]> {
4146  let ReleaseAtCycles = [8, 8, 14];
4147  let Latency = 30;
4148  let NumMicroOps = 30;
4149}
4150def : InstRW<[SPRWriteResGroup440], (instrs VP2INTERSECTQZrr)>;
4151
4152def SPRWriteResGroup441 : SchedWriteRes<[SPRPort00_01]> {
4153  let Latency = 3;
4154}
4155def : InstRW<[SPRWriteResGroup441], (instregex "^VP(A|SU)BS(B|W)Z(128|256)rrk(z?)$",
4156                                               "^VPADD(U?)S(B|W)Z(128|256)rrk(z?)$",
4157                                               "^VPAVG(B|W)Z(128|256)rrk(z?)$",
4158                                               "^VPM(AX|IN)(SB|UW)Z(128|256)rrk(z?)$",
4159                                               "^VPM(AX|IN)(SW|UB)Z(128|256)rrk(z?)$",
4160                                               "^VPSH(L|R)DVWZ(128|256)rk(z?)$",
4161                                               "^VPS(L|R)LVWZ(128|256)rrk(z?)$",
4162                                               "^VPS(L|R)LWZ(128|256)rik(z?)$",
4163                                               "^VPSRAVWZ(128|256)rrk(z?)$",
4164                                               "^VPSRAWZ(128|256)rik(z?)$",
4165                                               "^VPSUBUS(B|W)Z(128|256)rrk(z?)$")>;
4166
4167def SPRWriteResGroup442 : SchedWriteRes<[SPRPort01_05, SPRPort02_03_11]> {
4168  let Latency = 9;
4169  let NumMicroOps = 2;
4170}
4171def : InstRW<[SPRWriteResGroup442, ReadAfterVecYLd], (instregex "^VSHUFP(D|S)Yrmi$",
4172                                                                "^VSHUFP(D|S)Z256rm(bi|ik)$",
4173                                                                "^VSHUFP(D|S)Z256rmbik(z?)$",
4174                                                                "^VSHUFP(D|S)Z256rmi((kz)?)$")>;
4175def : InstRW<[SPRWriteResGroup442, ReadAfterVecYLd], (instrs VPBLENDWYrmi)>;
4176
4177def SPRWriteResGroup443 : SchedWriteRes<[SPRPort00, SPRPort05]> {
4178  let Latency = 6;
4179  let NumMicroOps = 2;
4180}
4181def : InstRW<[SPRWriteResGroup443], (instregex "^VPBROADCASTM(B2Q|W2D)Z(128|256)rr$",
4182                                               "^VPBROADCASTM(B2Q|W2D)Zrr$",
4183                                               "^VP(ERM|SRA)WZrrk(z?)$",
4184                                               "^VPSHUFBITQMBZ(128|256)rr$",
4185                                               "^VPS(L|R)LWZrrk(z?)$")>;
4186def : InstRW<[SPRWriteResGroup443], (instrs VPSHUFBITQMBZrr)>;
4187
4188def SPRWriteResGroup444 : SchedWriteRes<[SPRPort00, SPRPort00_06, SPRPort04_09, SPRPort05, SPRPort07_08]> {
4189  let ReleaseAtCycles = [1, 1, 1, 2, 1];
4190  let Latency = 12;
4191  let NumMicroOps = 6;
4192}
4193def : InstRW<[SPRWriteResGroup444], (instregex "^VPCOMPRESS(B|W)Z(128|256)mr$")>;
4194def : InstRW<[SPRWriteResGroup444], (instrs VPCOMPRESSWZmr)>;
4195
4196def SPRWriteResGroup445 : SchedWriteRes<[SPRPort00, SPRPort00_06, SPRPort04_09, SPRPort05, SPRPort07_08]> {
4197  let ReleaseAtCycles = [1, 1, 1, 2, 1];
4198  let Latency = 14;
4199  let NumMicroOps = 6;
4200}
4201def : InstRW<[SPRWriteResGroup445], (instregex "^VPCOMPRESS(B|W)Z(128|256)mrk$")>;
4202def : InstRW<[SPRWriteResGroup445], (instrs VPCOMPRESSWZmrk)>;
4203
4204def SPRWriteResGroup446 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort04_09, SPRPort05, SPRPort07_08]> {
4205  let ReleaseAtCycles = [1, 1, 2, 2, 2];
4206  let Latency = 12;
4207  let NumMicroOps = 8;
4208}
4209def : InstRW<[SPRWriteResGroup446], (instrs VPCOMPRESSBZmr)>;
4210
4211def SPRWriteResGroup447 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort04_09, SPRPort05, SPRPort07_08]> {
4212  let ReleaseAtCycles = [1, 1, 2, 2, 2];
4213  let Latency = 14;
4214  let NumMicroOps = 8;
4215}
4216def : InstRW<[SPRWriteResGroup447], (instrs VPCOMPRESSBZmrk)>;
4217
4218def SPRWriteResGroup448 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort02_03_11, SPRPort05]> {
4219  let ReleaseAtCycles = [5, 4, 1, 5];
4220  let Latency = 17;
4221  let NumMicroOps = 15;
4222}
4223def : InstRW<[SPRWriteResGroup448], (instregex "^VPCONFLICTDZ128rm((b|k|bk|kz)?)$")>;
4224def : InstRW<[SPRWriteResGroup448], (instrs VPCONFLICTDZ128rmbkz)>;
4225
4226def SPRWriteResGroup449 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort05]> {
4227  let ReleaseAtCycles = [5, 5, 5];
4228  let Latency = 12;
4229  let NumMicroOps = 15;
4230}
4231def : InstRW<[SPRWriteResGroup449], (instregex "^VPCONFLICTDZ128rr((k|kz)?)$")>;
4232
4233def SPRWriteResGroup450 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_06, SPRPort02_03_11, SPRPort05]> {
4234  let ReleaseAtCycles = [7, 5, 1, 1, 9];
4235  let Latency = 24;
4236  let NumMicroOps = 23;
4237}
4238def : InstRW<[SPRWriteResGroup450], (instregex "^VPCONFLICTDZ256rm((b|k|bk|kz)?)$")>;
4239def : InstRW<[SPRWriteResGroup450], (instrs VPCONFLICTDZ256rmbkz)>;
4240
4241def SPRWriteResGroup451 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort00_06, SPRPort05]> {
4242  let ReleaseAtCycles = [7, 6, 1, 9];
4243  let Latency = 17;
4244  let NumMicroOps = 23;
4245}
4246def : InstRW<[SPRWriteResGroup451], (instregex "^VPCONFLICTDZ256rr((k|kz)?)$")>;
4247
4248def SPRWriteResGroup452 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort02_03_11, SPRPort05]> {
4249  let ReleaseAtCycles = [11, 8, 1, 17];
4250  let Latency = 33;
4251  let NumMicroOps = 37;
4252}
4253def : InstRW<[SPRWriteResGroup452], (instregex "^VPCONFLICTDZrm((b|k|bk|kz)?)$")>;
4254def : InstRW<[SPRWriteResGroup452], (instrs VPCONFLICTDZrmbkz)>;
4255
4256def SPRWriteResGroup453 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort05]> {
4257  let ReleaseAtCycles = [11, 9, 17];
4258  let Latency = 26;
4259  let NumMicroOps = 37;
4260}
4261def : InstRW<[SPRWriteResGroup453], (instregex "^VPCONFLICTDZrr((kz)?)$")>;
4262
4263def SPRWriteResGroup454 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort05]> {
4264  let ReleaseAtCycles = [11, 9, 17];
4265  let Latency = 25;
4266  let NumMicroOps = 37;
4267}
4268def : InstRW<[SPRWriteResGroup454], (instrs VPCONFLICTDZrrk)>;
4269
4270def SPRWriteResGroup455 : SchedWriteRes<[SPRPort00_01_05, SPRPort02_03_11, SPRPort05]> {
4271  let ReleaseAtCycles = [1, 1, 2];
4272  let Latency = 11;
4273  let NumMicroOps = 4;
4274}
4275def : InstRW<[SPRWriteResGroup455], (instregex "^VPCONFLICTQZ128rm((b|k|bk|kz)?)$")>;
4276def : InstRW<[SPRWriteResGroup455], (instrs VPCONFLICTQZ128rmbkz)>;
4277def : InstRW<[SPRWriteResGroup455, ReadAfterVecYLd], (instregex "^VPERM(I|T)2BZ128rm$")>;
4278
4279def SPRWriteResGroup456 : SchedWriteRes<[SPRPort00_01_05, SPRPort05]> {
4280  let ReleaseAtCycles = [1, 2];
4281  let Latency = 4;
4282  let NumMicroOps = 3;
4283}
4284def : InstRW<[SPRWriteResGroup456], (instregex "^VPCONFLICTQZ128rr((k|kz)?)$")>;
4285
4286def SPRWriteResGroup457 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort02_03_11, SPRPort05]> {
4287  let ReleaseAtCycles = [5, 4, 1, 5];
4288  let Latency = 20;
4289  let NumMicroOps = 15;
4290}
4291def : InstRW<[SPRWriteResGroup457], (instregex "^VPCONFLICTQZ256rm((b|k|bk|kz)?)$")>;
4292def : InstRW<[SPRWriteResGroup457], (instrs VPCONFLICTQZ256rmbkz)>;
4293
4294def SPRWriteResGroup458 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort05]> {
4295  let ReleaseAtCycles = [5, 5, 5];
4296  let Latency = 13;
4297  let NumMicroOps = 15;
4298}
4299def : InstRW<[SPRWriteResGroup458], (instregex "^VPCONFLICTQZ256rr((k|kz)?)$")>;
4300
4301def SPRWriteResGroup459 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort02_03_11, SPRPort05]> {
4302  let ReleaseAtCycles = [7, 5, 1, 9];
4303  let Latency = 23;
4304  let NumMicroOps = 22;
4305}
4306def : InstRW<[SPRWriteResGroup459], (instregex "^VPCONFLICTQZrm((b|k|bk|kz)?)$")>;
4307def : InstRW<[SPRWriteResGroup459], (instrs VPCONFLICTQZrmbkz)>;
4308
4309def SPRWriteResGroup460 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort05]> {
4310  let ReleaseAtCycles = [7, 6, 9];
4311  let Latency = 17;
4312  let NumMicroOps = 22;
4313}
4314def : InstRW<[SPRWriteResGroup460], (instregex "^VPCONFLICTQZrr((kz)?)$")>;
4315
4316def SPRWriteResGroup461 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort05]> {
4317  let ReleaseAtCycles = [7, 6, 9];
4318  let Latency = 16;
4319  let NumMicroOps = 22;
4320}
4321def : InstRW<[SPRWriteResGroup461], (instrs VPCONFLICTQZrrk)>;
4322
4323def SPRWriteResGroup462 : SchedWriteRes<[SPRPort00_01_05, SPRPort02_03_11, SPRPort05]> {
4324  let ReleaseAtCycles = [1, 1, 2];
4325  let Latency = 13;
4326  let NumMicroOps = 4;
4327}
4328def : InstRW<[SPRWriteResGroup462, ReadAfterVecYLd], (instregex "^VPERM(I|T)2BZ128rmk(z?)$")>;
4329def : InstRW<[SPRWriteResGroup462, ReadAfterVecYLd], (instrs VPERMT2WZ128rm)>;
4330
4331def SPRWriteResGroup463 : SchedWriteRes<[SPRPort00_01_05, SPRPort05]> {
4332  let ReleaseAtCycles = [1, 2];
4333  let Latency = 5;
4334  let NumMicroOps = 3;
4335}
4336def : InstRW<[SPRWriteResGroup463], (instregex "^VPERM(I|T)2BZ(128|256)rr$")>;
4337
4338def SPRWriteResGroup464 : SchedWriteRes<[SPRPort00_01_05, SPRPort05]> {
4339  let ReleaseAtCycles = [1, 2];
4340  let Latency = 7;
4341  let NumMicroOps = 3;
4342}
4343def : InstRW<[SPRWriteResGroup464], (instregex "^VPERM(I|T)2BZ(128|256)rrk(z?)$",
4344                                               "^VPERM(I|T)2WZ(128|256)rr$")>;
4345
4346def SPRWriteResGroup465 : SchedWriteRes<[SPRPort00_01_05, SPRPort02_03_11, SPRPort05]> {
4347  let ReleaseAtCycles = [1, 1, 2];
4348  let Latency = 12;
4349  let NumMicroOps = 4;
4350}
4351def : InstRW<[SPRWriteResGroup465, ReadAfterVecYLd], (instregex "^VPERM(I|T)2BZ256rm$")>;
4352
4353def SPRWriteResGroup466 : SchedWriteRes<[SPRPort00_01_05, SPRPort02_03_11, SPRPort05]> {
4354  let ReleaseAtCycles = [1, 1, 2];
4355  let Latency = 14;
4356  let NumMicroOps = 4;
4357}
4358def : InstRW<[SPRWriteResGroup466, ReadAfterVecYLd], (instregex "^VPERM(I|T)2BZ256rmk(z?)$")>;
4359def : InstRW<[SPRWriteResGroup466, ReadAfterVecYLd], (instrs VPERMI2WZ128rm,
4360                                                             VPERMT2WZ256rm)>;
4361
4362def SPRWriteResGroup467 : SchedWriteRes<[SPRPort00_05, SPRPort02_03_11, SPRPort05]> {
4363  let ReleaseAtCycles = [1, 1, 2];
4364  let Latency = 12;
4365  let NumMicroOps = 4;
4366}
4367def : InstRW<[SPRWriteResGroup467, ReadAfterVecYLd], (instregex "^VPERM(I|T)2BZrm$")>;
4368
4369def SPRWriteResGroup468 : SchedWriteRes<[SPRPort00_05, SPRPort02_03_11, SPRPort05]> {
4370  let ReleaseAtCycles = [1, 1, 2];
4371  let Latency = 14;
4372  let NumMicroOps = 4;
4373}
4374def : InstRW<[SPRWriteResGroup468, ReadAfterVecYLd], (instregex "^VPERM(I|T)2BZrmk(z?)$")>;
4375def : InstRW<[SPRWriteResGroup468, ReadAfterVecYLd], (instrs VPERMT2WZrm)>;
4376
4377def SPRWriteResGroup469 : SchedWriteRes<[SPRPort00_05, SPRPort05]> {
4378  let ReleaseAtCycles = [1, 2];
4379  let Latency = 5;
4380  let NumMicroOps = 3;
4381}
4382def : InstRW<[SPRWriteResGroup469], (instregex "^VPERM(I|T)2BZrr$")>;
4383
4384def SPRWriteResGroup470 : SchedWriteRes<[SPRPort00_05, SPRPort05]> {
4385  let ReleaseAtCycles = [1, 2];
4386  let Latency = 7;
4387  let NumMicroOps = 3;
4388}
4389def : InstRW<[SPRWriteResGroup470], (instregex "^VPERM(I|T)2BZrrk(z?)$",
4390                                               "^VPERM(I|T)2WZrr$")>;
4391
4392def SPRWriteResGroup471 : SchedWriteRes<[SPRPort00_01_05, SPRPort02_03_11, SPRPort05]> {
4393  let ReleaseAtCycles = [1, 1, 2];
4394  let Latency = 16;
4395  let NumMicroOps = 4;
4396}
4397def : InstRW<[SPRWriteResGroup471, ReadAfterVecYLd], (instregex "^VPERMI2WZ128rmk(z?)$",
4398                                                                "^VPERMT2WZ256rmk(z?)$")>;
4399
4400def SPRWriteResGroup472 : SchedWriteRes<[SPRPort00_01_05, SPRPort05]> {
4401  let ReleaseAtCycles = [1, 2];
4402  let Latency = 9;
4403  let NumMicroOps = 3;
4404}
4405def : InstRW<[SPRWriteResGroup472], (instregex "^VPERM(I|T)2WZ(128|256)rrk(z?)$")>;
4406
4407def SPRWriteResGroup473 : SchedWriteRes<[SPRPort00_01_05, SPRPort02_03_11, SPRPort05]> {
4408  let ReleaseAtCycles = [1, 1, 2];
4409  let Latency = 15;
4410  let NumMicroOps = 4;
4411}
4412def : InstRW<[SPRWriteResGroup473, ReadAfterVecYLd], (instregex "^VPERMT2WZ128rmk(z?)$")>;
4413def : InstRW<[SPRWriteResGroup473, ReadAfterVecYLd], (instrs VPERMI2WZ256rm)>;
4414
4415def SPRWriteResGroup474 : SchedWriteRes<[SPRPort00_01_05, SPRPort02_03_11, SPRPort05]> {
4416  let ReleaseAtCycles = [1, 1, 2];
4417  let Latency = 17;
4418  let NumMicroOps = 4;
4419}
4420def : InstRW<[SPRWriteResGroup474, ReadAfterVecYLd], (instregex "^VPERMI2WZ256rmk(z?)$")>;
4421
4422def SPRWriteResGroup475 : SchedWriteRes<[SPRPort00_05, SPRPort02_03_11, SPRPort05]> {
4423  let ReleaseAtCycles = [1, 1, 2];
4424  let Latency = 15;
4425  let NumMicroOps = 4;
4426}
4427def : InstRW<[SPRWriteResGroup475, ReadAfterVecYLd], (instrs VPERMI2WZrm)>;
4428
4429def SPRWriteResGroup476 : SchedWriteRes<[SPRPort00_05, SPRPort02_03_11, SPRPort05]> {
4430  let ReleaseAtCycles = [1, 1, 2];
4431  let Latency = 17;
4432  let NumMicroOps = 4;
4433}
4434def : InstRW<[SPRWriteResGroup476, ReadAfterVecYLd], (instregex "^VPERMI2WZrmk(z?)$")>;
4435
4436def SPRWriteResGroup477 : SchedWriteRes<[SPRPort00_05, SPRPort05]> {
4437  let ReleaseAtCycles = [1, 2];
4438  let Latency = 9;
4439  let NumMicroOps = 3;
4440}
4441def : InstRW<[SPRWriteResGroup477], (instregex "^VPERM(I|T)2WZrrk(z?)$")>;
4442
4443def SPRWriteResGroup478 : SchedWriteRes<[SPRPort00_05, SPRPort02_03_11, SPRPort05]> {
4444  let ReleaseAtCycles = [1, 1, 2];
4445  let Latency = 16;
4446  let NumMicroOps = 4;
4447}
4448def : InstRW<[SPRWriteResGroup478, ReadAfterVecYLd], (instregex "^VPERMT2WZrmk(z?)$")>;
4449
4450def SPRWriteResGroup479 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_11, SPRPort05]> {
4451  let Latency = 10;
4452  let NumMicroOps = 3;
4453}
4454def : InstRW<[SPRWriteResGroup479, ReadAfterVecYLd], (instrs VPERMWZ128rm)>;
4455
4456def SPRWriteResGroup480 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_11, SPRPort05]> {
4457  let Latency = 13;
4458  let NumMicroOps = 3;
4459}
4460def : InstRW<[SPRWriteResGroup480, ReadAfterVecYLd], (instregex "^VPERMWZ(128|256)rmk(z?)$")>;
4461
4462def SPRWriteResGroup481 : SchedWriteRes<[SPRPort00_01, SPRPort05]> {
4463  let Latency = 4;
4464  let NumMicroOps = 2;
4465}
4466def : InstRW<[SPRWriteResGroup481], (instregex "^VPERMWZ(128|256)rr$")>;
4467
4468def SPRWriteResGroup482 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_11, SPRPort05]> {
4469  let Latency = 11;
4470  let NumMicroOps = 3;
4471}
4472def : InstRW<[SPRWriteResGroup482, ReadAfterVecYLd], (instrs VPERMWZ256rm)>;
4473
4474def SPRWriteResGroup483 : SchedWriteRes<[SPRPort00, SPRPort02_03_11, SPRPort05]> {
4475  let Latency = 11;
4476  let NumMicroOps = 3;
4477}
4478def : InstRW<[SPRWriteResGroup483, ReadAfterVecYLd], (instrs VPERMWZrm)>;
4479
4480def SPRWriteResGroup484 : SchedWriteRes<[SPRPort05]> {
4481  let ReleaseAtCycles = [2];
4482  let Latency = 8;
4483  let NumMicroOps = 2;
4484}
4485def : InstRW<[SPRWriteResGroup484], (instregex "^VPEXPAND(B|W)Z(128|256)rrk(z?)$",
4486                                               "^VPEXPAND(B|W)Zrrk(z?)$")>;
4487
4488def SPRWriteResGroup485 : SchedWriteRes<[SPRPort00_01, SPRPort01_05, SPRPort02_03_11]> {
4489  let ReleaseAtCycles = [1, 2, 1];
4490  let Latency = 10;
4491  let NumMicroOps = 4;
4492}
4493def : InstRW<[SPRWriteResGroup485, ReadAfterVecYLd], (instregex "^VPH(ADD|SUB)SWYrm$")>;
4494
4495def SPRWriteResGroup486 : SchedWriteRes<[SPRPort00_01]> {
4496  let Latency = 7;
4497}
4498def : InstRW<[SPRWriteResGroup486], (instregex "^VPMADDUBSWZ(128|256)rrk(z?)$",
4499                                               "^VPMULH((U|RS)?)WZ(128|256)rrk(z?)$",
4500                                               "^VPMULLWZ(128|256)rrk(z?)$")>;
4501
4502def SPRWriteResGroup487 : SchedWriteRes<[SPRPort00, SPRPort02_03_11]> {
4503  let Latency = 14;
4504  let NumMicroOps = 2;
4505}
4506def : InstRW<[SPRWriteResGroup487, ReadAfterVecYLd], (instregex "^VPMADDUBSWZrmk(z?)$",
4507                                                                "^VPMULH((U|RS)?)WZrmk(z?)$",
4508                                                                "^VPMULLWZrmk(z?)$")>;
4509
4510def SPRWriteResGroup488 : SchedWriteRes<[SPRPort00]> {
4511  let Latency = 7;
4512}
4513def : InstRW<[SPRWriteResGroup488], (instregex "^VPMADDUBSWZrrk(z?)$",
4514                                               "^VPMULH((U|RS)?)WZrrk(z?)$",
4515                                               "^VPMULLWZrrk(z?)$")>;
4516
4517def SPRWriteResGroup489 : SchedWriteRes<[SPRPort01_05, SPRPort04_09, SPRPort05, SPRPort07_08]> {
4518  let Latency = 12;
4519  let NumMicroOps = 4;
4520}
4521def : InstRW<[SPRWriteResGroup489], (instregex "^VPMOV((US)?)DBZ(128|256)mr$",
4522                                               "^VPMOV((S|US)?)(D|Q)WZ(128|256)mr$",
4523                                               "^VPMOV(Q|W|SD|SW)BZ256mr$",
4524                                               "^VPMOV(W|SD)BZ128mr$",
4525                                               "^VPMOV(U?)SQBZ256mr$",
4526                                               "^VPMOV(U?)SQDZ(128|256)mr$",
4527                                               "^VPMOV(U?)SWBZ128mr$")>;
4528def : InstRW<[SPRWriteResGroup489], (instrs VPMOVUSWBZ256mr)>;
4529
4530def SPRWriteResGroup490 : SchedWriteRes<[SPRPort01_05, SPRPort04_09, SPRPort05, SPRPort07_08]> {
4531  let Latency = 13;
4532  let NumMicroOps = 4;
4533}
4534def : InstRW<[SPRWriteResGroup490], (instregex "^VPMOV(D|Q|W|SQ|SW)BZ128mrk$",
4535                                               "^VPMOV((S|US)?)(D|Q)WZ128mrk$",
4536                                               "^VPMOV(U?)S(DB|QD)Z128mrk$",
4537                                               "^VPMOVUS(Q|W)BZ128mrk$")>;
4538
4539def SPRWriteResGroup491 : SchedWriteRes<[SPRPort01_05, SPRPort05]> {
4540  let Latency = 2;
4541  let NumMicroOps = 2;
4542}
4543def : InstRW<[SPRWriteResGroup491], (instregex "^VPMOV(D|Q|W|SQ|SW)BZ128rr$",
4544                                               "^VPMOV((S|US)?)(D|Q)WZ128rr$",
4545                                               "^VPMOV(U?)S(DB|QD)Z128rr$",
4546                                               "^VPMOV(U?)SQDZ128rrk(z?)$",
4547                                               "^VPMOVUS(Q|W)BZ128rr$")>;
4548
4549def SPRWriteResGroup492 : SchedWriteRes<[SPRPort01_05, SPRPort05]> {
4550  let Latency = 4;
4551  let NumMicroOps = 2;
4552}
4553def : InstRW<[SPRWriteResGroup492], (instregex "^VPMOV(D|Q|W|SQ|SW)BZ128rrk(z?)$",
4554                                               "^VPMOV(D|Q|W|SQ|SW)BZ256rr$",
4555                                               "^VPMOV((S|US)?)(D|Q)WZ128rrk(z?)$",
4556                                               "^VPMOV((S|US)?)(D|Q)WZ256rr$",
4557                                               "^VPMOV(U?)SDBZ128rrk(z?)$",
4558                                               "^VPMOV(U?)S(DB|QD)Z256rr$",
4559                                               "^VPMOV(U?)SQDZ256rrk(z?)$",
4560                                               "^VPMOVUS(Q|W)BZ128rrk(z?)$",
4561                                               "^VPMOVUS(Q|W)BZ256rr$")>;
4562
4563def SPRWriteResGroup493 : SchedWriteRes<[SPRPort01_05, SPRPort04_09, SPRPort05, SPRPort07_08]> {
4564  let Latency = 15;
4565  let NumMicroOps = 4;
4566}
4567def : InstRW<[SPRWriteResGroup493], (instregex "^VPMOV(D|Q|W|SQ|SW)BZ256mrk$",
4568                                               "^VPMOV((S|US)?)(D|Q)WZ256mrk$",
4569                                               "^VPMOV(U?)S(DB|QD)Z256mrk$",
4570                                               "^VPMOVUS(Q|W)BZ256mrk$")>;
4571
4572def SPRWriteResGroup494 : SchedWriteRes<[SPRPort01_05, SPRPort05]> {
4573  let Latency = 6;
4574  let NumMicroOps = 2;
4575}
4576def : InstRW<[SPRWriteResGroup494], (instregex "^VPMOV(D|Q|W|SQ|SW)BZ256rrk(z?)$",
4577                                               "^VPMOV((S|US)?)(D|Q)WZ256rrk(z?)$",
4578                                               "^VPMOV(U?)SDBZ256rrk(z?)$",
4579                                               "^VPMOVUS(Q|W)BZ256rrk(z?)$")>;
4580
4581def SPRWriteResGroup495 : SchedWriteRes<[SPRPort01_05, SPRPort04_09, SPRPort05, SPRPort07_08]> {
4582  let Latency = 20;
4583  let NumMicroOps = 4;
4584}
4585def : InstRW<[SPRWriteResGroup495], (instregex "^VPMOV((S|US)?)QBZ128mr$")>;
4586
4587def SPRWriteResGroup496 : SchedWriteRes<[SPRPort04_09, SPRPort05, SPRPort07_08]> {
4588  let Latency = 14;
4589  let NumMicroOps = 3;
4590}
4591def : InstRW<[SPRWriteResGroup496], (instregex "^VPMOVQDZ((256)?)mrk$")>;
4592
4593def SPRWriteResGroup497 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_11]> {
4594  let ReleaseAtCycles = [3, 1];
4595  let Latency = 23;
4596  let NumMicroOps = 4;
4597}
4598def : InstRW<[SPRWriteResGroup497, ReadAfterVecXLd], (instregex "^VPMULLQZ128rm((b|k|bk|kz)?)$")>;
4599def : InstRW<[SPRWriteResGroup497, ReadAfterVecXLd], (instrs VPMULLQZ128rmbkz)>;
4600def : InstRW<[SPRWriteResGroup497, ReadAfterVecYLd], (instregex "^VPMULLQZ256rm((b|k|bk|kz)?)$")>;
4601def : InstRW<[SPRWriteResGroup497, ReadAfterVecYLd], (instrs VPMULLQZ256rmbkz)>;
4602
4603def SPRWriteResGroup498 : SchedWriteRes<[SPRPort00_01]> {
4604  let ReleaseAtCycles = [3];
4605  let Latency = 15;
4606  let NumMicroOps = 3;
4607}
4608def : InstRW<[SPRWriteResGroup498], (instregex "^VPMULLQZ(128|256)rr((k|kz)?)$")>;
4609
4610def SPRWriteResGroup499 : SchedWriteRes<[SPRPort00, SPRPort02_03_11]> {
4611  let ReleaseAtCycles = [3, 1];
4612  let Latency = 23;
4613  let NumMicroOps = 4;
4614}
4615def : InstRW<[SPRWriteResGroup499, ReadAfterVecYLd], (instregex "^VPMULLQZrm((b|k|bk|kz)?)$")>;
4616def : InstRW<[SPRWriteResGroup499, ReadAfterVecYLd], (instrs VPMULLQZrmbkz)>;
4617
4618def SPRWriteResGroup500 : SchedWriteRes<[SPRPort00]> {
4619  let ReleaseAtCycles = [3];
4620  let Latency = 15;
4621  let NumMicroOps = 3;
4622}
4623def : InstRW<[SPRWriteResGroup500], (instregex "^VPMULLQZrr((k|kz)?)$")>;
4624
4625def SPRWriteResGroup501 : SchedWriteRes<[SPRPort00, SPRPort00_01, SPRPort00_01_05_06_10, SPRPort04_09, SPRPort07_08]> {
4626  let ReleaseAtCycles = [1, 1, 1, 4, 4];
4627  let Latency = 12;
4628  let NumMicroOps = 11;
4629}
4630def : InstRW<[SPRWriteResGroup501], (instregex "^VPSCATTER(D|Q)QZ256mr$",
4631                                               "^VSCATTER(D|Q)PDZ256mr$")>;
4632def : InstRW<[SPRWriteResGroup501], (instrs VPSCATTERDDZ128mr,
4633                                            VPSCATTERQDZ256mr,
4634                                            VSCATTERDPSZ128mr,
4635                                            VSCATTERQPSZ256mr)>;
4636
4637def SPRWriteResGroup502 : SchedWriteRes<[SPRPort00, SPRPort00_01, SPRPort00_01_05_06_10, SPRPort04_09, SPRPort07_08]> {
4638  let ReleaseAtCycles = [1, 1, 1, 8, 8];
4639  let Latency = 12;
4640  let NumMicroOps = 19;
4641}
4642def : InstRW<[SPRWriteResGroup502], (instrs VPSCATTERDDZ256mr,
4643                                            VSCATTERDPSZ256mr)>;
4644
4645def SPRWriteResGroup503 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort04_09, SPRPort07_08]> {
4646  let ReleaseAtCycles = [2, 1, 16, 16];
4647  let Latency = 19;
4648  let NumMicroOps = 35;
4649}
4650def : InstRW<[SPRWriteResGroup503], (instrs VPSCATTERDDZmr,
4651                                            VSCATTERDPSZmr)>;
4652
4653def SPRWriteResGroup504 : SchedWriteRes<[SPRPort00, SPRPort00_01, SPRPort00_01_05_06_10, SPRPort04_09, SPRPort07_08]> {
4654  let ReleaseAtCycles = [1, 1, 1, 2, 2];
4655  let Latency = 12;
4656  let NumMicroOps = 7;
4657}
4658def : InstRW<[SPRWriteResGroup504], (instregex "^VPSCATTER(D|Q)QZ128mr$",
4659                                               "^VSCATTER(D|Q)PDZ128mr$")>;
4660def : InstRW<[SPRWriteResGroup504], (instrs VPSCATTERQDZ128mr,
4661                                            VSCATTERQPSZ128mr)>;
4662
4663def SPRWriteResGroup505 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06_10, SPRPort04_09, SPRPort07_08]> {
4664  let ReleaseAtCycles = [2, 1, 8, 8];
4665  let Latency = 12;
4666  let NumMicroOps = 19;
4667}
4668def : InstRW<[SPRWriteResGroup505], (instregex "^VPSCATTER(D|Q)QZmr$",
4669                                               "^VSCATTER(D|Q)PDZmr$")>;
4670def : InstRW<[SPRWriteResGroup505], (instrs VPSCATTERQDZmr,
4671                                            VSCATTERQPSZmr)>;
4672
4673def SPRWriteResGroup506 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_11]> {
4674  let Latency = 8;
4675  let NumMicroOps = 2;
4676}
4677def : InstRW<[SPRWriteResGroup506, ReadAfterVecXLd], (instregex "^VPSH(L|R)D(D|Q)Z128rmbi$",
4678                                                                "^VPSH(L|R)D(D|Q|W)Z128rmi$",
4679                                                                "^VPSH(L|R)DV(D|Q|W)Z128m$",
4680                                                                "^VPSH(L|R)DV(D|Q)Z128m(b|k|kz)$",
4681                                                                "^VPSH(L|R)DV(D|Q)Z128mbk(z?)$")>;
4682
4683def SPRWriteResGroup507 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort02_03_11]> {
4684  let Latency = 9;
4685  let NumMicroOps = 3;
4686}
4687def : InstRW<[SPRWriteResGroup507, ReadAfterVecXLd], (instregex "^VPSH(L|R)D(D|Q)Z128rm(b?)ik(z?)$")>;
4688
4689def SPRWriteResGroup508 : SchedWriteRes<[SPRPort00_01]>;
4690def : InstRW<[SPRWriteResGroup508], (instregex "^VPSH(L|R)D(D|Q|W)Z(128|256)rri$",
4691                                               "^VPSH(L|R)DV(D|Q|W)Z(128|256)r$",
4692                                               "^VPSH(L|R)DV(D|Q)Z(128|256)rk(z?)$")>;
4693
4694def SPRWriteResGroup509 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05]> {
4695  let Latency = 2;
4696  let NumMicroOps = 2;
4697}
4698def : InstRW<[SPRWriteResGroup509], (instregex "^VPSH(L|R)D(D|Q)Z(128|256)rrik(z?)$")>;
4699
4700def SPRWriteResGroup510 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_11]> {
4701  let Latency = 9;
4702  let NumMicroOps = 2;
4703}
4704def : InstRW<[SPRWriteResGroup510, ReadAfterVecYLd], (instregex "^VPSH(L|R)D(D|Q)Z256rmbi$",
4705                                                                "^VPSH(L|R)D(D|Q|W)Z256rmi$",
4706                                                                "^VPSH(L|R)DV(D|Q|W)Z256m$",
4707                                                                "^VPSH(L|R)DV(D|Q)Z256m(b|k|kz)$",
4708                                                                "^VPSH(L|R)DV(D|Q)Z256mbk(z?)$")>;
4709
4710def SPRWriteResGroup511 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort02_03_11]> {
4711  let Latency = 10;
4712  let NumMicroOps = 3;
4713}
4714def : InstRW<[SPRWriteResGroup511, ReadAfterVecYLd], (instregex "^VPSH(L|R)D(D|Q)Z256rm(b?)ik(z?)$")>;
4715
4716def SPRWriteResGroup512 : SchedWriteRes<[SPRPort00, SPRPort02_03_11]> {
4717  let Latency = 9;
4718  let NumMicroOps = 2;
4719}
4720def : InstRW<[SPRWriteResGroup512, ReadAfterVecYLd], (instregex "^VPSH(L|R)D(D|Q)Zrmbi$",
4721                                                                "^VPSH(L|R)D(D|Q|W)Zrmi$",
4722                                                                "^VPSH(L|R)DV(D|Q|W)Zm$",
4723                                                                "^VPSH(L|R)DV(D|Q)Zm(b|k|kz)$",
4724                                                                "^VPSH(L|R)DV(D|Q)Zmbk(z?)$")>;
4725
4726def SPRWriteResGroup513 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort02_03_11]> {
4727  let Latency = 10;
4728  let NumMicroOps = 3;
4729}
4730def : InstRW<[SPRWriteResGroup513, ReadAfterVecYLd], (instregex "^VPSH(L|R)D(D|Q)Zrm(b?)ik(z?)$")>;
4731
4732def SPRWriteResGroup514 : SchedWriteRes<[SPRPort00, SPRPort00_05]> {
4733  let Latency = 2;
4734  let NumMicroOps = 2;
4735}
4736def : InstRW<[SPRWriteResGroup514], (instregex "^VPSH(L|R)D(D|Q)Zrrik(z?)$")>;
4737
4738def SPRWriteResGroup515 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort02_03_11]> {
4739  let Latency = 11;
4740  let NumMicroOps = 3;
4741}
4742def : InstRW<[SPRWriteResGroup515, ReadAfterVecXLd], (instregex "^VPSH(L|R)DWZ128rmik(z?)$")>;
4743
4744def SPRWriteResGroup516 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05]> {
4745  let Latency = 4;
4746  let NumMicroOps = 2;
4747}
4748def : InstRW<[SPRWriteResGroup516], (instregex "^VPSH(L|R)DWZ(128|256)rrik(z?)$")>;
4749
4750def SPRWriteResGroup517 : SchedWriteRes<[SPRPort00_01, SPRPort00_01_05, SPRPort02_03_11]> {
4751  let Latency = 12;
4752  let NumMicroOps = 3;
4753}
4754def : InstRW<[SPRWriteResGroup517, ReadAfterVecYLd], (instregex "^VPSH(L|R)DWZ256rmik(z?)$")>;
4755
4756def SPRWriteResGroup518 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort02_03_11]> {
4757  let Latency = 12;
4758  let NumMicroOps = 3;
4759}
4760def : InstRW<[SPRWriteResGroup518, ReadAfterVecYLd], (instregex "^VPSH(L|R)DWZrmik(z?)$")>;
4761
4762def SPRWriteResGroup519 : SchedWriteRes<[SPRPort00, SPRPort00_05]> {
4763  let Latency = 4;
4764  let NumMicroOps = 2;
4765}
4766def : InstRW<[SPRWriteResGroup519], (instregex "^VPSH(L|R)DWZrrik(z?)$")>;
4767
4768def SPRWriteResGroup520 : SchedWriteRes<[SPRPort00, SPRPort02_03_11, SPRPort05]> {
4769  let Latency = 6;
4770  let NumMicroOps = 3;
4771}
4772def : InstRW<[SPRWriteResGroup520, ReadAfterVecXLd], (instrs VPSHUFBITQMBZ128rm)>;
4773def : InstRW<[SPRWriteResGroup520, ReadAfterVecYLd], (instregex "^VPSHUFBITQMBZ((256)?)rm$")>;
4774
4775def SPRWriteResGroup521 : SchedWriteRes<[SPRPort00, SPRPort02_03_11, SPRPort05]> {
4776  let Latency = 8;
4777  let NumMicroOps = 3;
4778}
4779def : InstRW<[SPRWriteResGroup521, ReadAfterVecXLd], (instrs VPSHUFBITQMBZ128rmk)>;
4780def : InstRW<[SPRWriteResGroup521, ReadAfterVecYLd], (instregex "^VPSHUFBITQMBZ((256)?)rmk$")>;
4781
4782def SPRWriteResGroup522 : SchedWriteRes<[SPRPort00_01, SPRPort01_05]> {
4783  let Latency = 4;
4784  let NumMicroOps = 2;
4785}
4786def : InstRW<[SPRWriteResGroup522], (instregex "^VPS(L|R)LWZ128rrk(z?)$",
4787                                               "^VPSRAWZ128rrk(z?)$")>;
4788
4789def SPRWriteResGroup523 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort02_03_11]> {
4790  let ReleaseAtCycles = [2, 1, 1];
4791  let Latency = 16;
4792  let NumMicroOps = 4;
4793}
4794def : InstRW<[SPRWriteResGroup523, ReadAfterVecYLd], (instregex "^VR(CP|SQRT)PHZm(bk|kz)$",
4795                                                                "^VR(CP|SQRT)PHZm(k|bkz)$")>;
4796
4797def SPRWriteResGroup524 : SchedWriteRes<[SPRPort00, SPRPort00_05]> {
4798  let ReleaseAtCycles = [2, 1];
4799  let Latency = 9;
4800  let NumMicroOps = 3;
4801}
4802def : InstRW<[SPRWriteResGroup524], (instregex "^VRCPPHZrk(z?)$")>;
4803
4804def SPRWriteResGroup525 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_11]> {
4805  let ReleaseAtCycles = [3, 1];
4806  let Latency = 20;
4807  let NumMicroOps = 4;
4808}
4809def : InstRW<[SPRWriteResGroup525, ReadAfterVecXLd], (instregex "^VREDUCEPHZ128rm(b?)i$")>;
4810def : InstRW<[SPRWriteResGroup525, ReadAfterVecXLd], (instrs VREDUCESHZrmi)>;
4811def : InstRW<[SPRWriteResGroup525, ReadAfterVecYLd], (instregex "^VREDUCEPHZ256rm(b?)i$")>;
4812
4813def SPRWriteResGroup526 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_11]> {
4814  let ReleaseAtCycles = [3, 1];
4815  let Latency = 22;
4816  let NumMicroOps = 4;
4817}
4818def : InstRW<[SPRWriteResGroup526, ReadAfterVecXLd], (instregex "^VREDUCEPHZ128rm(b?)ik(z?)$",
4819                                                                "^VREDUCESHZrmik(z?)$")>;
4820def : InstRW<[SPRWriteResGroup526, ReadAfterVecYLd], (instregex "^VREDUCEPHZ256rm(b?)ik(z?)$")>;
4821
4822def SPRWriteResGroup527 : SchedWriteRes<[SPRPort00_01]> {
4823  let ReleaseAtCycles = [3];
4824  let Latency = 13;
4825  let NumMicroOps = 3;
4826}
4827def : InstRW<[SPRWriteResGroup527], (instregex "^VREDUCEPHZ(128|256)rri$",
4828                                               "^VREDUCESHZrri(b?)$")>;
4829
4830def SPRWriteResGroup528 : SchedWriteRes<[SPRPort00_01]> {
4831  let ReleaseAtCycles = [3];
4832  let Latency = 16;
4833  let NumMicroOps = 3;
4834}
4835def : InstRW<[SPRWriteResGroup528], (instregex "^VREDUCEPHZ(128|256)rrik(z?)$",
4836                                               "^VREDUCESHZrri(bk|kz)$",
4837                                               "^VREDUCESHZrri(k|bkz)$")>;
4838
4839def SPRWriteResGroup529 : SchedWriteRes<[SPRPort00, SPRPort02_03_11]> {
4840  let ReleaseAtCycles = [3, 1];
4841  let Latency = 20;
4842  let NumMicroOps = 4;
4843}
4844def : InstRW<[SPRWriteResGroup529, ReadAfterVecYLd], (instregex "^VREDUCEPHZrm(b?)i$")>;
4845
4846def SPRWriteResGroup530 : SchedWriteRes<[SPRPort00, SPRPort02_03_11]> {
4847  let ReleaseAtCycles = [3, 1];
4848  let Latency = 22;
4849  let NumMicroOps = 4;
4850}
4851def : InstRW<[SPRWriteResGroup530, ReadAfterVecYLd], (instregex "^VREDUCEPHZrm(b?)ik(z?)$")>;
4852
4853def SPRWriteResGroup531 : SchedWriteRes<[SPRPort00]> {
4854  let ReleaseAtCycles = [3];
4855  let Latency = 13;
4856  let NumMicroOps = 3;
4857}
4858def : InstRW<[SPRWriteResGroup531], (instregex "^VREDUCEPHZrri(b?)$")>;
4859
4860def SPRWriteResGroup532 : SchedWriteRes<[SPRPort00]> {
4861  let ReleaseAtCycles = [3];
4862  let Latency = 16;
4863  let NumMicroOps = 3;
4864}
4865def : InstRW<[SPRWriteResGroup532], (instregex "^VREDUCEPHZrri(bk|kz)$",
4866                                               "^VREDUCEPHZrri(k|bkz)$")>;
4867
4868def SPRWriteResGroup533 : SchedWriteRes<[SPRPort00]> {
4869  let ReleaseAtCycles = [2];
4870  let Latency = 8;
4871  let NumMicroOps = 2;
4872}
4873def : InstRW<[SPRWriteResGroup533], (instregex "^VRNDSCALEP(D|S)Zrri((b|k|bk|kz)?)$",
4874                                               "^VRNDSCALEP(D|S)Zrribkz$")>;
4875
4876def SPRWriteResGroup534 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_11]> {
4877  let ReleaseAtCycles = [2, 1];
4878  let Latency = 17;
4879  let NumMicroOps = 3;
4880}
4881def : InstRW<[SPRWriteResGroup534, ReadAfterVecXLd], (instregex "^VRNDSCALEPHZ128rm(b?)ik(z?)$",
4882                                                                "^VRNDSCALESHZm_Intk(z?)$",
4883                                                                "^VSCALEFPHZ128rm(bk|kz)$",
4884                                                                "^VSCALEFPHZ128rm(k|bkz)$")>;
4885def : InstRW<[SPRWriteResGroup534, ReadAfterVecYLd], (instregex "^VRNDSCALEPHZ256rm(b?)ik(z?)$",
4886                                                                "^VSCALEFPHZ256rm(bk|kz)$",
4887                                                                "^VSCALEFPHZ256rm(k|bkz)$")>;
4888def : InstRW<[SPRWriteResGroup534, ReadAfterVecLd], (instregex "^VSCALEFSHZrmk(z?)$")>;
4889
4890def SPRWriteResGroup535 : SchedWriteRes<[SPRPort00_01]> {
4891  let ReleaseAtCycles = [2];
4892  let Latency = 11;
4893  let NumMicroOps = 2;
4894}
4895def : InstRW<[SPRWriteResGroup535], (instregex "^VRNDSCALEPHZ(128|256)rrik(z?)$",
4896                                               "^VRNDSCALESHZr(b?)_Intk(z?)$",
4897                                               "^VSCALEFPHZ(128|256)rrk(z?)$",
4898                                               "^VSCALEFSHZrrb_Intk(z?)$",
4899                                               "^VSCALEFSHZrrk(z?)$")>;
4900
4901def SPRWriteResGroup536 : SchedWriteRes<[SPRPort00, SPRPort02_03_11]> {
4902  let ReleaseAtCycles = [2, 1];
4903  let Latency = 17;
4904  let NumMicroOps = 3;
4905}
4906def : InstRW<[SPRWriteResGroup536, ReadAfterVecYLd], (instregex "^VRNDSCALEPHZrm(b?)ik(z?)$",
4907                                                                "^VSCALEFPHZrm(bk|kz)$",
4908                                                                "^VSCALEFPHZrm(k|bkz)$")>;
4909
4910def SPRWriteResGroup537 : SchedWriteRes<[SPRPort00]> {
4911  let ReleaseAtCycles = [2];
4912  let Latency = 11;
4913  let NumMicroOps = 2;
4914}
4915def : InstRW<[SPRWriteResGroup537], (instregex "^VRNDSCALEPHZrri(bk|kz)$",
4916                                               "^VRNDSCALEPHZrri(k|bkz)$",
4917                                               "^VSCALEFPHZrr(bk|kz)$",
4918                                               "^VSCALEFPHZrr(k|bkz)$")>;
4919
4920def SPRWriteResGroup538 : SchedWriteRes<[SPRPort00, SPRPort00_05]> {
4921  let ReleaseAtCycles = [2, 1];
4922  let Latency = 6;
4923  let NumMicroOps = 3;
4924}
4925def : InstRW<[SPRWriteResGroup538], (instregex "^VRSQRT14P(D|S)Zr$")>;
4926def : InstRW<[SPRWriteResGroup538], (instrs VRSQRT14PSZrk,
4927                                            VRSQRTPHZr)>;
4928
4929def SPRWriteResGroup539 : SchedWriteRes<[SPRPort00, SPRPort02_03_11]> {
4930  let Latency = 25;
4931  let NumMicroOps = 2;
4932}
4933def : InstRW<[SPRWriteResGroup539], (instrs VSQRTPDYm)>;
4934def : InstRW<[SPRWriteResGroup539, ReadAfterVecYLd], (instregex "^VSQRTPDZ256m(b?)$")>;
4935
4936def SPRWriteResGroup540 : SchedWriteRes<[SPRPort00, SPRPort02_03_11]> {
4937  let Latency = 20;
4938  let NumMicroOps = 2;
4939}
4940def : InstRW<[SPRWriteResGroup540, ReadAfterVecXLd], (instregex "^VSQRTPDZ128m(bk|kz)$",
4941                                                                "^VSQRTPDZ128m(k|bkz)$")>;
4942def : InstRW<[SPRWriteResGroup540, ReadAfterVecLd], (instregex "^VSQRTSDZm_Intk(z?)$")>;
4943
4944def SPRWriteResGroup541 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort02_03_11]> {
4945  let ReleaseAtCycles = [2, 1, 1];
4946  let Latency = 38;
4947  let NumMicroOps = 4;
4948}
4949def : InstRW<[SPRWriteResGroup541, ReadAfterVecYLd], (instrs VSQRTPDZm)>;
4950
4951def SPRWriteResGroup542 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort02_03_11]> {
4952  let ReleaseAtCycles = [2, 1, 1];
4953  let Latency = 39;
4954  let NumMicroOps = 4;
4955}
4956def : InstRW<[SPRWriteResGroup542, ReadAfterVecYLd], (instrs VSQRTPDZmb)>;
4957
4958def SPRWriteResGroup543 : SchedWriteRes<[SPRPort00, SPRPort00_05]> {
4959  let ReleaseAtCycles = [2, 1];
4960  let Latency = 31;
4961  let NumMicroOps = 3;
4962}
4963def : InstRW<[SPRWriteResGroup543], (instrs VSQRTPDZr)>;
4964
4965def SPRWriteResGroup544 : SchedWriteRes<[SPRPort00, SPRPort00_01_05, SPRPort02_03_11]> {
4966  let ReleaseAtCycles = [2, 1, 1];
4967  let Latency = 41;
4968  let NumMicroOps = 4;
4969}
4970def : InstRW<[SPRWriteResGroup544, ReadAfterVecXLd], (instregex "^VSQRTPHZ128m(bk|kz)$",
4971                                                                "^VSQRTPHZ128m(k|bkz)$")>;
4972
4973def SPRWriteResGroup545 : SchedWriteRes<[SPRPort00, SPRPort00_01_05]> {
4974  let ReleaseAtCycles = [2, 1];
4975  let Latency = 35;
4976  let NumMicroOps = 3;
4977}
4978def : InstRW<[SPRWriteResGroup545], (instregex "^VSQRTPHZ(128|256)rk$")>;
4979def : InstRW<[SPRWriteResGroup545], (instrs VSQRTPHZ256rkz)>;
4980
4981def SPRWriteResGroup546 : SchedWriteRes<[SPRPort00, SPRPort00_01_05]> {
4982  let ReleaseAtCycles = [2, 1];
4983  let Latency = 12;
4984  let NumMicroOps = 3;
4985}
4986def : InstRW<[SPRWriteResGroup546], (instrs VSQRTPHZ128rkz)>;
4987
4988def SPRWriteResGroup547 : SchedWriteRes<[SPRPort00, SPRPort00_01_05, SPRPort02_03_11]> {
4989  let ReleaseAtCycles = [2, 1, 1];
4990  let Latency = 40;
4991  let NumMicroOps = 4;
4992}
4993def : InstRW<[SPRWriteResGroup547, ReadAfterVecYLd], (instregex "^VSQRTPHZ256m(b?)$")>;
4994
4995def SPRWriteResGroup548 : SchedWriteRes<[SPRPort00, SPRPort00_01_05, SPRPort02_03_11]> {
4996  let ReleaseAtCycles = [2, 1, 1];
4997  let Latency = 42;
4998  let NumMicroOps = 4;
4999}
5000def : InstRW<[SPRWriteResGroup548, ReadAfterVecYLd], (instregex "^VSQRTPHZ256m(bk|kz)$",
5001                                                                "^VSQRTPHZ256m(k|bkz)$")>;
5002
5003def SPRWriteResGroup549 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort00_06, SPRPort02_03_11, SPRPort05]> {
5004  let ReleaseAtCycles = [4, 2, 1, 1, 1];
5005  let Latency = 53;
5006  let NumMicroOps = 9;
5007}
5008def : InstRW<[SPRWriteResGroup549, ReadAfterVecYLd], (instregex "^VSQRTPHZm(b?)$")>;
5009
5010def SPRWriteResGroup550 : SchedWriteRes<[SPRPort00, SPRPort00_05, SPRPort00_06, SPRPort02_03_11, SPRPort05]> {
5011  let ReleaseAtCycles = [4, 2, 1, 1, 1];
5012  let Latency = 55;
5013  let NumMicroOps = 9;
5014}
5015def : InstRW<[SPRWriteResGroup550, ReadAfterVecYLd], (instregex "^VSQRTPHZm(bk|kz)$",
5016                                                                "^VSQRTPHZm(k|bkz)$")>;
5017
5018def SPRWriteResGroup551 : SchedWriteRes<[SPRPort00, SPRPort00_06, SPRPort05]> {
5019  let ReleaseAtCycles = [4, 1, 1];
5020  let Latency = 45;
5021  let NumMicroOps = 6;
5022}
5023def : InstRW<[SPRWriteResGroup551], (instregex "^VSQRTPHZr(b?)$")>;
5024
5025def SPRWriteResGroup552 : SchedWriteRes<[SPRPort00, SPRPort00_06, SPRPort05]> {
5026  let ReleaseAtCycles = [4, 1, 1];
5027  let Latency = 47;
5028  let NumMicroOps = 6;
5029}
5030def : InstRW<[SPRWriteResGroup552], (instregex "^VSQRTPHZr(bk|kz)$",
5031                                               "^VSQRTPHZr(k|bkz)$")>;
5032
5033def SPRWriteResGroup553 : SchedWriteRes<[SPRPort00, SPRPort00_05]> {
5034  let ReleaseAtCycles = [2, 1];
5035  let Latency = 19;
5036  let NumMicroOps = 3;
5037}
5038def : InstRW<[SPRWriteResGroup553], (instrs VSQRTPSZr)>;
5039
5040def SPRWriteResGroup554 : SchedWriteRes<[SPRPort00_01_05, SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort01_05_10]> {
5041  let ReleaseAtCycles = [1, 2, 3, 3, 1];
5042  let Latency = 12;
5043  let NumMicroOps = 10;
5044}
5045def : InstRW<[SPRWriteResGroup554], (instrs VZEROALL)>;
5046
5047def SPRWriteResGroup555 : SchedWriteRes<[SPRPort00_01_05_06]> {
5048  let ReleaseAtCycles = [2];
5049  let Latency = 2;
5050  let NumMicroOps = 2;
5051}
5052def : InstRW<[SPRWriteResGroup555], (instrs WAIT)>;
5053
5054def SPRWriteResGroup556 : SchedWriteRes<[SPRPort00, SPRPort00_01, SPRPort00_05, SPRPort00_06, SPRPort01, SPRPort01_05, SPRPort04_09, SPRPort05, SPRPort07_08]> {
5055  let ReleaseAtCycles = [8, 6, 19, 63, 21, 15, 1, 10, 1];
5056  let Latency = SapphireRapidsModel.MaxLatency;
5057  let NumMicroOps = 144;
5058}
5059def : InstRW<[SPRWriteResGroup556], (instrs WRMSR)>;
5060
5061def SPRWriteResGroup557 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06, SPRPort01, SPRPort05]> {
5062  let ReleaseAtCycles = [2, 1, 4, 1];
5063  let Latency = SapphireRapidsModel.MaxLatency;
5064  let NumMicroOps = 8;
5065}
5066def : InstRW<[SPRWriteResGroup557], (instrs WRPKRUr)>;
5067
5068def SPRWriteResGroup558 : SchedWriteRes<[SPRPort00_01_05_06_10]> {
5069  let ReleaseAtCycles = [2];
5070  let Latency = 12;
5071  let NumMicroOps = 2;
5072}
5073def : InstRW<[SPRWriteResGroup558, WriteRMW], (instregex "^XADD(16|32|64)rm$")>;
5074
5075def SPRWriteResGroup559 : SchedWriteRes<[SPRPort00_01_05_06_10]> {
5076  let ReleaseAtCycles = [2];
5077  let Latency = 13;
5078  let NumMicroOps = 2;
5079}
5080def : InstRW<[SPRWriteResGroup559, WriteRMW], (instrs XADD8rm)>;
5081
5082def SPRWriteResGroup560 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06]> {
5083  let ReleaseAtCycles = [4, 1];
5084  let Latency = 39;
5085  let NumMicroOps = 5;
5086}
5087def : InstRW<[SPRWriteResGroup560, WriteRMW], (instregex "^XCHG(16|32)rm$")>;
5088
5089def SPRWriteResGroup561 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06]> {
5090  let ReleaseAtCycles = [5, 1];
5091  let Latency = 39;
5092  let NumMicroOps = 6;
5093}
5094def : InstRW<[SPRWriteResGroup561, WriteRMW], (instrs XCHG64rm)>;
5095
5096def SPRWriteResGroup562 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06]> {
5097  let ReleaseAtCycles = [4, 1];
5098  let Latency = 40;
5099  let NumMicroOps = 5;
5100}
5101def : InstRW<[SPRWriteResGroup562, WriteRMW], (instrs XCHG8rm)>;
5102
5103def SPRWriteResGroup563 : SchedWriteRes<[SPRPort00, SPRPort00_01_05_06, SPRPort00_05, SPRPort01, SPRPort05, SPRPort06]> {
5104  let ReleaseAtCycles = [2, 4, 2, 1, 2, 4];
5105  let Latency = 17;
5106  let NumMicroOps = 15;
5107}
5108def : InstRW<[SPRWriteResGroup563], (instrs XCH_F)>;
5109
5110def SPRWriteResGroup564 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_05_06, SPRPort00_06, SPRPort01]> {
5111  let ReleaseAtCycles = [7, 3, 8, 5];
5112  let Latency = 4;
5113  let NumMicroOps = 23;
5114}
5115def : InstRW<[SPRWriteResGroup564], (instrs XGETBV)>;
5116
5117def SPRWriteResGroup565 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort02_03_11]> {
5118  let ReleaseAtCycles = [2, 1];
5119  let Latency = 7;
5120  let NumMicroOps = 3;
5121}
5122def : InstRW<[SPRWriteResGroup565], (instrs XLAT)>;
5123
5124def SPRWriteResGroup566 : SchedWriteRes<[SPRPort01, SPRPort02_03, SPRPort02_03_11, SPRPort06]> {
5125  let ReleaseAtCycles = [1, 21, 1, 8];
5126  let Latency = 37;
5127  let NumMicroOps = 31;
5128}
5129def : InstRW<[SPRWriteResGroup566], (instregex "^XRSTOR((S|64)?)$")>;
5130def : InstRW<[SPRWriteResGroup566], (instrs XRSTORS64)>;
5131
5132def SPRWriteResGroup567 : SchedWriteRes<[SPRPort00_01, SPRPort00_05, SPRPort00_06, SPRPort01, SPRPort01_05, SPRPort02_03_11, SPRPort04_09, SPRPort05, SPRPort07_08]> {
5133  let ReleaseAtCycles = [14, 25, 44, 21, 21, 4, 1, 9, 1];
5134  let Latency = 42;
5135  let NumMicroOps = 140;
5136}
5137def : InstRW<[SPRWriteResGroup567], (instrs XSAVE)>;
5138
5139def SPRWriteResGroup568 : SchedWriteRes<[SPRPort00_01, SPRPort00_05, SPRPort00_06, SPRPort01, SPRPort01_05, SPRPort02_03_11, SPRPort04_09, SPRPort05, SPRPort07_08]> {
5140  let ReleaseAtCycles = [14, 25, 44, 21, 21, 4, 1, 9, 1];
5141  let Latency = 41;
5142  let NumMicroOps = 140;
5143}
5144def : InstRW<[SPRWriteResGroup568], (instrs XSAVE64)>;
5145
5146def SPRWriteResGroup569 : SchedWriteRes<[SPRPort00, SPRPort00_01, SPRPort00_05, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort04_09, SPRPort05, SPRPort07_08]> {
5147  let ReleaseAtCycles = [1, 19, 36, 52, 23, 4, 2, 12, 2];
5148  let Latency = 42;
5149  let NumMicroOps = 151;
5150}
5151def : InstRW<[SPRWriteResGroup569], (instrs XSAVEC)>;
5152
5153def SPRWriteResGroup570 : SchedWriteRes<[SPRPort00, SPRPort00_01, SPRPort00_05, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort04_09, SPRPort05, SPRPort07_08]> {
5154  let ReleaseAtCycles = [1, 19, 36, 53, 23, 4, 2, 12, 2];
5155  let Latency = 42;
5156  let NumMicroOps = 152;
5157}
5158def : InstRW<[SPRWriteResGroup570], (instrs XSAVEC64)>;
5159
5160def SPRWriteResGroup571 : SchedWriteRes<[SPRPort00_01, SPRPort00_05, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort04_09, SPRPort05, SPRPort07_08]> {
5161  let ReleaseAtCycles = [25, 35, 52, 27, 4, 1, 10, 1];
5162  let Latency = 42;
5163  let NumMicroOps = 155;
5164}
5165def : InstRW<[SPRWriteResGroup571], (instrs XSAVEOPT)>;
5166
5167def SPRWriteResGroup572 : SchedWriteRes<[SPRPort00_01, SPRPort00_05, SPRPort00_06, SPRPort01, SPRPort02_03_11, SPRPort04_09, SPRPort05, SPRPort07_08]> {
5168  let ReleaseAtCycles = [25, 35, 53, 27, 4, 1, 10, 1];
5169  let Latency = 42;
5170  let NumMicroOps = 156;
5171}
5172def : InstRW<[SPRWriteResGroup572], (instrs XSAVEOPT64)>;
5173
5174def SPRWriteResGroup573 : SchedWriteRes<[SPRPort00_01, SPRPort00_05, SPRPort00_06, SPRPort01, SPRPort01_05, SPRPort02_03_11, SPRPort04_09, SPRPort05, SPRPort07_08]> {
5175  let ReleaseAtCycles = [23, 32, 53, 29, 30, 4, 2, 9, 2];
5176  let Latency = 42;
5177  let NumMicroOps = 184;
5178}
5179def : InstRW<[SPRWriteResGroup573], (instrs XSAVES)>;
5180
5181def SPRWriteResGroup574 : SchedWriteRes<[SPRPort00_01, SPRPort00_05, SPRPort00_06, SPRPort01, SPRPort01_05, SPRPort02_03_11, SPRPort04_09, SPRPort05, SPRPort07_08]> {
5182  let ReleaseAtCycles = [23, 33, 53, 29, 32, 4, 2, 8, 2];
5183  let Latency = 42;
5184  let NumMicroOps = 186;
5185}
5186def : InstRW<[SPRWriteResGroup574], (instrs XSAVES64)>;
5187
5188def SPRWriteResGroup575 : SchedWriteRes<[SPRPort00_01_05, SPRPort00_01_05_06_10, SPRPort00_05_06, SPRPort00_06, SPRPort01, SPRPort01_05_10, SPRPort05]> {
5189  let ReleaseAtCycles = [4, 23, 2, 14, 8, 1, 2];
5190  let Latency = 5;
5191  let NumMicroOps = 54;
5192}
5193def : InstRW<[SPRWriteResGroup575], (instrs XSETBV)>;
5194
5195def SPRWriteResGroup576 : SchedWriteRes<[SPRPort00_01_05_06_10, SPRPort00_06]> {
5196  let ReleaseAtCycles = [2, 1];
5197  let Latency = SapphireRapidsModel.MaxLatency;
5198  let NumMicroOps = 3;
5199}
5200def : InstRW<[SPRWriteResGroup576], (instrs XTEST)>;
5201
5202}
5203