xref: /freebsd/contrib/llvm-project/llvm/lib/Target/X86/X86SchedSandyBridge.td (revision ec0ea6efa1ad229d75c394c1a9b9cac33af2b1d3)
1//=- X86SchedSandyBridge.td - X86 Sandy Bridge Scheduling ----*- tablegen -*-=//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the machine model for Sandy Bridge to support instruction
10// scheduling and other instruction cost heuristics.
11//
12// Note that we define some instructions here that are not supported by SNB,
13// but we still have to define them because SNB is the default subtarget for
14// X86. These instructions are tagged with a comment `Unsupported = 1`.
15//
16//===----------------------------------------------------------------------===//
17
18def SandyBridgeModel : SchedMachineModel {
19  // All x86 instructions are modeled as a single micro-op, and SB can decode 4
20  // instructions per cycle.
21  // FIXME: Identify instructions that aren't a single fused micro-op.
22  let IssueWidth = 4;
23  let MicroOpBufferSize = 168; // Based on the reorder buffer.
24  let LoadLatency = 5;
25  let MispredictPenalty = 16;
26
27  // Based on the LSD (loop-stream detector) queue size.
28  let LoopMicroOpBufferSize = 28;
29
30  // This flag is set to allow the scheduler to assign
31  // a default model to unrecognized opcodes.
32  let CompleteModel = 0;
33}
34
35let SchedModel = SandyBridgeModel in {
36
37// Sandy Bridge can issue micro-ops to 6 different ports in one cycle.
38
39// Ports 0, 1, and 5 handle all computation.
40def SBPort0 : ProcResource<1>;
41def SBPort1 : ProcResource<1>;
42def SBPort5 : ProcResource<1>;
43
44// Ports 2 and 3 are identical. They handle loads and the address half of
45// stores.
46def SBPort23 : ProcResource<2>;
47
48// Port 4 gets the data half of stores. Store data can be available later than
49// the store address, but since we don't model the latency of stores, we can
50// ignore that.
51def SBPort4 : ProcResource<1>;
52
53// Many micro-ops are capable of issuing on multiple ports.
54def SBPort01  : ProcResGroup<[SBPort0, SBPort1]>;
55def SBPort05  : ProcResGroup<[SBPort0, SBPort5]>;
56def SBPort15  : ProcResGroup<[SBPort1, SBPort5]>;
57def SBPort015 : ProcResGroup<[SBPort0, SBPort1, SBPort5]>;
58
59// 54 Entry Unified Scheduler
60def SBPortAny : ProcResGroup<[SBPort0, SBPort1, SBPort23, SBPort4, SBPort5]> {
61  let BufferSize=54;
62}
63
64// Integer division issued on port 0.
65def SBDivider : ProcResource<1>;
66// FP division and sqrt on port 0.
67def SBFPDivider : ProcResource<1>;
68
69// Integer loads are 5 cycles, so ReadAfterLd registers needn't be available until 5
70// cycles after the memory operand.
71def : ReadAdvance<ReadAfterLd, 5>;
72
73// Vector loads are 5/6/7 cycles, so ReadAfterVec*Ld registers needn't be available
74// until 5/6/7 cycles after the memory operand.
75def : ReadAdvance<ReadAfterVecLd, 5>;
76def : ReadAdvance<ReadAfterVecXLd, 6>;
77def : ReadAdvance<ReadAfterVecYLd, 7>;
78
79def : ReadAdvance<ReadInt2Fpu, 0>;
80
81// Many SchedWrites are defined in pairs with and without a folded load.
82// Instructions with folded loads are usually micro-fused, so they only appear
83// as two micro-ops when queued in the reservation station.
84// This multiclass defines the resource usage for variants with and without
85// folded loads.
86multiclass SBWriteResPair<X86FoldableSchedWrite SchedRW,
87                          list<ProcResourceKind> ExePorts,
88                          int Lat, list<int> Res = [1], int UOps = 1,
89                          int LoadLat = 5> {
90  // Register variant is using a single cycle on ExePort.
91  def : WriteRes<SchedRW, ExePorts> {
92    let Latency = Lat;
93    let ResourceCycles = Res;
94    let NumMicroOps = UOps;
95  }
96
97  // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to
98  // the latency (default = 5).
99  def : WriteRes<SchedRW.Folded, !listconcat([SBPort23], ExePorts)> {
100    let Latency = !add(Lat, LoadLat);
101    let ResourceCycles = !listconcat([1], Res);
102    let NumMicroOps = !add(UOps, 1);
103  }
104}
105
106// A folded store needs a cycle on port 4 for the store data, and an extra port
107// 2/3 cycle to recompute the address.
108def : WriteRes<WriteRMW, [SBPort23,SBPort4]>;
109
110def : WriteRes<WriteStore,   [SBPort23, SBPort4]>;
111def : WriteRes<WriteStoreNT, [SBPort23, SBPort4]>;
112def : WriteRes<WriteLoad,    [SBPort23]> { let Latency = 5; }
113def : WriteRes<WriteMove,    [SBPort015]>;
114def : WriteRes<WriteZero,    []>;
115def : WriteRes<WriteVecMaskedGatherWriteback, []> { let Latency = 5; let NumMicroOps = 0; }
116
117// Arithmetic.
118defm : SBWriteResPair<WriteALU,    [SBPort015], 1>;
119defm : SBWriteResPair<WriteADC,    [SBPort05,SBPort015], 2, [1,1], 2>;
120
121defm : SBWriteResPair<WriteIMul8,     [SBPort1],   3>;
122defm : SBWriteResPair<WriteIMul16,    [SBPort1,SBPort05,SBPort015], 4, [1,1,2], 4>;
123defm : X86WriteRes<WriteIMul16Imm,    [SBPort1,SBPort015], 4, [1,1], 2>;
124defm : X86WriteRes<WriteIMul16ImmLd,  [SBPort1,SBPort015,SBPort23], 8, [1,1,1], 3>;
125defm : SBWriteResPair<WriteIMul16Reg, [SBPort1],   3>;
126defm : SBWriteResPair<WriteIMul32,    [SBPort1,SBPort05,SBPort015], 4, [1,1,1], 3>;
127defm : SBWriteResPair<WriteIMul32Imm, [SBPort1],   3>;
128defm : SBWriteResPair<WriteIMul32Reg, [SBPort1],   3>;
129defm : SBWriteResPair<WriteIMul64,    [SBPort1,SBPort0], 4, [1,1], 2>;
130defm : SBWriteResPair<WriteIMul64Imm, [SBPort1],   3>;
131defm : SBWriteResPair<WriteIMul64Reg, [SBPort1],   3>;
132def  : WriteRes<WriteIMulH, []> { let Latency = 3; }
133
134defm : X86WriteRes<WriteXCHG,      [SBPort015], 2, [3], 3>;
135defm : X86WriteRes<WriteBSWAP32,   [SBPort1], 1, [1], 1>;
136defm : X86WriteRes<WriteBSWAP64,   [SBPort1, SBPort05], 2, [1,1], 2>;
137defm : X86WriteRes<WriteCMPXCHG,   [SBPort05, SBPort015], 5, [1,3], 4>;
138defm : X86WriteRes<WriteCMPXCHGRMW,[SBPort015, SBPort5, SBPort23, SBPort4], 8, [1, 2, 2, 1], 6>;
139
140defm : SBWriteResPair<WriteDiv8,   [SBPort0, SBDivider], 25, [1, 10]>;
141defm : SBWriteResPair<WriteDiv16,  [SBPort0, SBDivider], 25, [1, 10]>;
142defm : SBWriteResPair<WriteDiv32,  [SBPort0, SBDivider], 25, [1, 10]>;
143defm : SBWriteResPair<WriteDiv64,  [SBPort0, SBDivider], 25, [1, 10]>;
144defm : SBWriteResPair<WriteIDiv8,  [SBPort0, SBDivider], 25, [1, 10]>;
145defm : SBWriteResPair<WriteIDiv16, [SBPort0, SBDivider], 25, [1, 10]>;
146defm : SBWriteResPair<WriteIDiv32, [SBPort0, SBDivider], 25, [1, 10]>;
147defm : SBWriteResPair<WriteIDiv64, [SBPort0, SBDivider], 25, [1, 10]>;
148
149// SHLD/SHRD.
150defm : X86WriteRes<WriteSHDrri, [SBPort05, SBPort015], 2, [1, 1], 2>;
151defm : X86WriteRes<WriteSHDrrcl,[SBPort05, SBPort015], 4, [3, 1], 4>;
152defm : X86WriteRes<WriteSHDmri, [SBPort4,SBPort23,SBPort05,SBPort015], 8, [1, 2, 1, 1], 5>;
153defm : X86WriteRes<WriteSHDmrcl,[SBPort4,SBPort23,SBPort05,SBPort015], 10, [1, 2, 3, 1], 7>;
154
155defm : SBWriteResPair<WriteShift,    [SBPort05],  1>;
156defm : SBWriteResPair<WriteShiftCL,  [SBPort05],  3, [3], 3>;
157defm : SBWriteResPair<WriteRotate,   [SBPort05],  2, [2], 2>;
158defm : SBWriteResPair<WriteRotateCL, [SBPort05],  3, [3], 3>;
159
160defm : SBWriteResPair<WriteJump,  [SBPort5],   1>;
161defm : SBWriteResPair<WriteCRC32, [SBPort1],   3, [1], 1, 5>;
162
163defm : SBWriteResPair<WriteCMOV,  [SBPort05,SBPort015], 2, [1,1], 2>; // Conditional move.
164defm : X86WriteRes<WriteFCMOV, [SBPort5,SBPort05], 3, [2,1], 3>; // x87 conditional move.
165def  : WriteRes<WriteSETCC, [SBPort05]>; // Setcc.
166def  : WriteRes<WriteSETCCStore, [SBPort05,SBPort4,SBPort23]> {
167  let Latency = 2;
168  let NumMicroOps = 3;
169}
170
171defm : X86WriteRes<WriteLAHFSAHF,        [SBPort05], 1, [1], 1>;
172defm : X86WriteRes<WriteBitTest,         [SBPort05], 1, [1], 1>;
173defm : X86WriteRes<WriteBitTestImmLd,    [SBPort05,SBPort23], 6, [1,1], 2>;
174//defm : X86WriteRes<WriteBitTestRegLd,    [SBPort05,SBPort23], 6, [1,1], 2>;
175defm : X86WriteRes<WriteBitTestSet,      [SBPort05], 1, [1], 1>;
176defm : X86WriteRes<WriteBitTestSetImmLd, [SBPort05,SBPort23], 6, [1,1], 3>;
177defm : X86WriteRes<WriteBitTestSetRegLd, [SBPort05,SBPort23,SBPort5,SBPort015], 8, [1,1,1,1], 5>;
178
179// This is for simple LEAs with one or two input operands.
180// The complex ones can only execute on port 1, and they require two cycles on
181// the port to read all inputs. We don't model that.
182def : WriteRes<WriteLEA, [SBPort01]>;
183
184// Bit counts.
185defm : SBWriteResPair<WriteBSF, [SBPort1], 3, [1], 1, 5>;
186defm : SBWriteResPair<WriteBSR, [SBPort1], 3, [1], 1, 5>;
187defm : SBWriteResPair<WriteLZCNT,          [SBPort1], 3, [1], 1, 5>;
188defm : SBWriteResPair<WriteTZCNT,          [SBPort1], 3, [1], 1, 5>;
189defm : SBWriteResPair<WritePOPCNT,         [SBPort1], 3, [1], 1, 6>;
190
191// BMI1 BEXTR/BLS, BMI2 BZHI
192// NOTE: These don't exist on Sandy Bridge. Ports are guesses.
193defm : SBWriteResPair<WriteBEXTR, [SBPort05,SBPort1], 2, [1,1], 2>;
194defm : SBWriteResPair<WriteBLS,   [SBPort015], 1>;
195defm : SBWriteResPair<WriteBZHI,  [SBPort1], 1>;
196
197// Scalar and vector floating point.
198defm : X86WriteRes<WriteFLD0,          [SBPort5], 1, [1], 1>;
199defm : X86WriteRes<WriteFLD1,          [SBPort0,SBPort5], 1, [1,1], 2>;
200defm : X86WriteRes<WriteFLDC,          [SBPort0,SBPort1], 1, [1,1], 2>;
201defm : X86WriteRes<WriteFLoad,         [SBPort23], 5, [1], 1>;
202defm : X86WriteRes<WriteFLoadX,        [SBPort23], 6, [1], 1>;
203defm : X86WriteRes<WriteFLoadY,        [SBPort23], 7, [1], 1>;
204defm : X86WriteRes<WriteFMaskedLoad,   [SBPort23,SBPort05], 8, [1,2], 3>;
205defm : X86WriteRes<WriteFMaskedLoadY,  [SBPort23,SBPort05], 9, [1,2], 3>;
206defm : X86WriteRes<WriteFStore,        [SBPort23,SBPort4], 1, [1,1], 1>;
207defm : X86WriteRes<WriteFStoreX,       [SBPort23,SBPort4], 1, [1,1], 1>;
208defm : X86WriteRes<WriteFStoreY,       [SBPort23,SBPort4], 1, [1,1], 1>;
209defm : X86WriteRes<WriteFStoreNT,      [SBPort23,SBPort4], 1, [1,1], 1>;
210defm : X86WriteRes<WriteFStoreNTX,     [SBPort23,SBPort4], 1, [1,1], 1>;
211defm : X86WriteRes<WriteFStoreNTY,     [SBPort23,SBPort4], 1, [1,1], 1>;
212
213defm : X86WriteRes<WriteFMaskedStore32,  [SBPort4,SBPort01,SBPort23], 5, [1,1,1], 3>;
214defm : X86WriteRes<WriteFMaskedStore32Y, [SBPort4,SBPort01,SBPort23], 5, [1,1,1], 3>;
215defm : X86WriteRes<WriteFMaskedStore64,  [SBPort4,SBPort01,SBPort23], 5, [1,1,1], 3>;
216defm : X86WriteRes<WriteFMaskedStore64Y, [SBPort4,SBPort01,SBPort23], 5, [1,1,1], 3>;
217
218defm : X86WriteRes<WriteFMove,         [SBPort5], 1, [1], 1>;
219defm : X86WriteRes<WriteFMoveX,        [SBPort5], 1, [1], 1>;
220defm : X86WriteRes<WriteFMoveY,        [SBPort5], 1, [1], 1>;
221defm : X86WriteRes<WriteEMMS,          [SBPort015], 31, [31], 31>;
222
223defm : SBWriteResPair<WriteFAdd,    [SBPort1],  3, [1], 1, 6>;
224defm : SBWriteResPair<WriteFAddX,   [SBPort1],  3, [1], 1, 6>;
225defm : SBWriteResPair<WriteFAddY,   [SBPort1],  3, [1], 1, 7>;
226defm : SBWriteResPair<WriteFAddZ,   [SBPort1],  3, [1], 1, 7>; // Unsupported = 1
227defm : SBWriteResPair<WriteFAdd64,  [SBPort1],  3, [1], 1, 6>;
228defm : SBWriteResPair<WriteFAdd64X, [SBPort1],  3, [1], 1, 6>;
229defm : SBWriteResPair<WriteFAdd64Y, [SBPort1],  3, [1], 1, 7>;
230defm : SBWriteResPair<WriteFAdd64Z, [SBPort1],  3, [1], 1, 7>; // Unsupported = 1
231
232defm : SBWriteResPair<WriteFCmp,    [SBPort1],  3, [1], 1, 6>;
233defm : SBWriteResPair<WriteFCmpX,   [SBPort1],  3, [1], 1, 6>;
234defm : SBWriteResPair<WriteFCmpY,   [SBPort1],  3, [1], 1, 7>;
235defm : SBWriteResPair<WriteFCmpZ,   [SBPort1],  3, [1], 1, 7>; // Unsupported = 1
236defm : SBWriteResPair<WriteFCmp64,  [SBPort1],  3, [1], 1, 6>;
237defm : SBWriteResPair<WriteFCmp64X, [SBPort1],  3, [1], 1, 6>;
238defm : SBWriteResPair<WriteFCmp64Y, [SBPort1],  3, [1], 1, 7>;
239defm : SBWriteResPair<WriteFCmp64Z, [SBPort1],  3, [1], 1, 7>; // Unsupported = 1
240
241defm : SBWriteResPair<WriteFCom,    [SBPort1],  3>;
242defm : SBWriteResPair<WriteFComX,   [SBPort1],  3>;
243
244defm : SBWriteResPair<WriteFMul,    [SBPort0],  5, [1], 1, 6>;
245defm : SBWriteResPair<WriteFMulX,   [SBPort0],  5, [1], 1, 6>;
246defm : SBWriteResPair<WriteFMulY,   [SBPort0],  5, [1], 1, 7>;
247defm : SBWriteResPair<WriteFMulZ,   [SBPort0],  5, [1], 1, 7>; // Unsupported = 1
248defm : SBWriteResPair<WriteFMul64,  [SBPort0],  5, [1], 1, 6>;
249defm : SBWriteResPair<WriteFMul64X, [SBPort0],  5, [1], 1, 6>;
250defm : SBWriteResPair<WriteFMul64Y, [SBPort0],  5, [1], 1, 7>;
251defm : SBWriteResPair<WriteFMul64Z, [SBPort0],  5, [1], 1, 7>; // Unsupported = 1
252
253defm : SBWriteResPair<WriteFDiv,    [SBPort0,SBFPDivider], 14, [1,14], 1, 6>;
254defm : SBWriteResPair<WriteFDivX,   [SBPort0,SBFPDivider], 14, [1,14], 1, 6>;
255defm : SBWriteResPair<WriteFDivY,   [SBPort0,SBPort05,SBFPDivider], 29, [2,1,28], 3, 7>;
256defm : SBWriteResPair<WriteFDivZ,   [SBPort0,SBPort05,SBFPDivider], 29, [2,1,28], 3, 7>; // Unsupported = 1
257defm : SBWriteResPair<WriteFDiv64,  [SBPort0,SBFPDivider], 22, [1,22], 1, 6>;
258defm : SBWriteResPair<WriteFDiv64X, [SBPort0,SBFPDivider], 22, [1,22], 1, 6>;
259defm : SBWriteResPair<WriteFDiv64Y, [SBPort0,SBPort05,SBFPDivider], 45, [2,1,44], 3, 7>;
260defm : SBWriteResPair<WriteFDiv64Z, [SBPort0,SBPort05,SBFPDivider], 45, [2,1,44], 3, 7>; // Unsupported = 1
261
262defm : SBWriteResPair<WriteFRcp,   [SBPort0],  5, [1], 1, 6>;
263defm : SBWriteResPair<WriteFRcpX,  [SBPort0],  5, [1], 1, 6>;
264defm : SBWriteResPair<WriteFRcpY,  [SBPort0,SBPort05],  7, [2,1], 3, 7>;
265defm : SBWriteResPair<WriteFRcpZ,  [SBPort0,SBPort05],  7, [2,1], 3, 7>; // Unsupported = 1
266
267defm : SBWriteResPair<WriteFRsqrt, [SBPort0],  5, [1], 1, 6>;
268defm : SBWriteResPair<WriteFRsqrtX,[SBPort0],  5, [1], 1, 6>;
269defm : SBWriteResPair<WriteFRsqrtY,[SBPort0,SBPort05],  7, [2,1], 3, 7>;
270defm : SBWriteResPair<WriteFRsqrtZ,[SBPort0,SBPort05],  7, [2,1], 3, 7>; // Unsupported = 1
271
272defm : SBWriteResPair<WriteFSqrt,    [SBPort0,SBFPDivider], 14, [1,14], 1, 6>;
273defm : SBWriteResPair<WriteFSqrtX,   [SBPort0,SBFPDivider], 14, [1,14], 1, 6>;
274defm : SBWriteResPair<WriteFSqrtY,   [SBPort0,SBPort05,SBFPDivider], 29, [2,1,28], 3, 7>;
275defm : SBWriteResPair<WriteFSqrtZ,   [SBPort0,SBPort05,SBFPDivider], 29, [2,1,28], 3, 7>; // Unsupported = 1
276defm : SBWriteResPair<WriteFSqrt64,  [SBPort0,SBFPDivider], 21, [1,21], 1, 6>;
277defm : SBWriteResPair<WriteFSqrt64X, [SBPort0,SBFPDivider], 21, [1,21], 1, 6>;
278defm : SBWriteResPair<WriteFSqrt64Y, [SBPort0,SBPort05,SBFPDivider], 45, [2,1,44], 3, 7>;
279defm : SBWriteResPair<WriteFSqrt64Z, [SBPort0,SBPort05,SBFPDivider], 45, [2,1,44], 3, 7>; // Unsupported = 1
280defm : SBWriteResPair<WriteFSqrt80,  [SBPort0,SBFPDivider], 24, [1,24], 1, 6>;
281
282defm : SBWriteResPair<WriteDPPD,   [SBPort0,SBPort1,SBPort5],  9, [1,1,1], 3, 6>;
283defm : SBWriteResPair<WriteDPPS,   [SBPort0,SBPort1,SBPort5], 12, [1,2,1], 4, 6>;
284defm : SBWriteResPair<WriteDPPSY,  [SBPort0,SBPort1,SBPort5], 12, [1,2,1], 4, 7>;
285defm : SBWriteResPair<WriteDPPSZ,  [SBPort0,SBPort1,SBPort5], 12, [1,2,1], 4, 7>; // Unsupported = 1
286defm : SBWriteResPair<WriteFSign,    [SBPort5], 1>;
287defm : SBWriteResPair<WriteFRnd,     [SBPort1], 3, [1], 1, 6>;
288defm : SBWriteResPair<WriteFRndY,    [SBPort1], 3, [1], 1, 7>;
289defm : SBWriteResPair<WriteFRndZ,    [SBPort1], 3, [1], 1, 7>; // Unsupported = 1
290defm : SBWriteResPair<WriteFLogic,   [SBPort5], 1, [1], 1, 6>;
291defm : SBWriteResPair<WriteFLogicY,  [SBPort5], 1, [1], 1, 7>;
292defm : SBWriteResPair<WriteFLogicZ,  [SBPort5], 1, [1], 1, 7>; // Unsupported = 1
293defm : SBWriteResPair<WriteFTest,    [SBPort0], 1, [1], 1, 6>;
294defm : SBWriteResPair<WriteFTestY,   [SBPort0], 1, [1], 1, 7>;
295defm : SBWriteResPair<WriteFTestZ,   [SBPort0], 1, [1], 1, 7>; // Unsupported = 1
296defm : SBWriteResPair<WriteFShuffle, [SBPort5], 1, [1], 1, 6>;
297defm : SBWriteResPair<WriteFShuffleY,[SBPort5], 1, [1], 1, 7>;
298defm : SBWriteResPair<WriteFShuffleZ,[SBPort5], 1, [1], 1, 7>; // Unsupported = 1
299defm : SBWriteResPair<WriteFVarShuffle, [SBPort5], 1, [1], 1, 6>;
300defm : SBWriteResPair<WriteFVarShuffleY,[SBPort5], 1, [1], 1, 7>;
301defm : SBWriteResPair<WriteFVarShuffleZ,[SBPort5], 1, [1], 1, 7>; // Unsupported = 1
302defm : SBWriteResPair<WriteFBlend,    [SBPort05], 1, [1], 1, 6>;
303defm : SBWriteResPair<WriteFBlendY,   [SBPort05], 1, [1], 1, 7>;
304defm : SBWriteResPair<WriteFBlendZ,   [SBPort05], 1, [1], 1, 7>; // Unsupported = 1
305defm : SBWriteResPair<WriteFVarBlend, [SBPort05], 2, [2], 2, 6>;
306defm : SBWriteResPair<WriteFVarBlendY,[SBPort05], 2, [2], 2, 7>;
307defm : SBWriteResPair<WriteFVarBlendZ,[SBPort05], 2, [2], 2, 7>; // Unsupported = 1
308
309// Conversion between integer and float.
310defm : SBWriteResPair<WriteCvtSS2I,   [SBPort0,SBPort1], 5, [1,1], 2>;
311defm : SBWriteResPair<WriteCvtPS2I,           [SBPort1], 3, [1], 1, 6>;
312defm : SBWriteResPair<WriteCvtPS2IY,          [SBPort1], 3, [1], 1, 7>;
313defm : SBWriteResPair<WriteCvtPS2IZ,          [SBPort1], 3, [1], 1, 7>; // Unsupported = 1
314defm : SBWriteResPair<WriteCvtSD2I,   [SBPort0,SBPort1], 5, [1,1], 2>;
315defm : SBWriteResPair<WriteCvtPD2I,   [SBPort1,SBPort5], 4, [1,1], 2, 6>;
316defm : X86WriteRes<WriteCvtPD2IY,     [SBPort1,SBPort5], 4, [1,1], 2>;
317defm : X86WriteRes<WriteCvtPD2IZ,     [SBPort1,SBPort5], 4, [1,1], 2>; // Unsupported = 1
318defm : X86WriteRes<WriteCvtPD2IYLd,   [SBPort1,SBPort5,SBPort23], 11, [1,1,1], 3>;
319defm : X86WriteRes<WriteCvtPD2IZLd,   [SBPort1,SBPort5,SBPort23], 11, [1,1,1], 3>; // Unsupported = 1
320
321defm : X86WriteRes<WriteCvtI2SS,      [SBPort1,SBPort5],  5, [1,2], 3>;
322defm : X86WriteRes<WriteCvtI2SSLd,    [SBPort1,SBPort5,SBPort23], 10, [1,1,1], 3>;
323defm : SBWriteResPair<WriteCvtI2PS,           [SBPort1],  3, [1], 1, 6>;
324defm : SBWriteResPair<WriteCvtI2PSY,          [SBPort1],  3, [1], 1, 7>;
325defm : SBWriteResPair<WriteCvtI2PSZ,          [SBPort1],  3, [1], 1, 7>; // Unsupported = 1
326defm : X86WriteRes<WriteCvtI2SD,      [SBPort1,SBPort5],  4, [1,1], 2>;
327defm : X86WriteRes<WriteCvtI2PD,      [SBPort1,SBPort5],  4, [1,1], 2>;
328defm : X86WriteRes<WriteCvtI2PDY,     [SBPort1,SBPort5],  4, [1,1], 2>;
329defm : X86WriteRes<WriteCvtI2PDZ,     [SBPort1,SBPort5],  4, [1,1], 2>; // Unsupported = 1
330defm : X86WriteRes<WriteCvtI2SDLd,   [SBPort1,SBPort23],  9, [1,1], 2>;
331defm : X86WriteRes<WriteCvtI2PDLd,   [SBPort1,SBPort5,SBPort23], 10, [1,1,1], 3>;
332defm : X86WriteRes<WriteCvtI2PDYLd,  [SBPort1,SBPort5,SBPort23], 10, [1,1,1], 3>;
333defm : X86WriteRes<WriteCvtI2PDZLd,  [SBPort1,SBPort5,SBPort23], 10, [1,1,1], 3>; // Unsupported = 1
334
335defm : SBWriteResPair<WriteCvtSS2SD,  [SBPort0], 1, [1], 1, 6>;
336defm : X86WriteRes<WriteCvtPS2PD,     [SBPort0,SBPort5], 2, [1,1], 2>;
337defm : X86WriteRes<WriteCvtPS2PDY,    [SBPort0,SBPort5], 2, [1,1], 2>;
338defm : X86WriteRes<WriteCvtPS2PDZ,    [SBPort0,SBPort5], 2, [1,1], 2>; // Unsupported = 1
339defm : X86WriteRes<WriteCvtPS2PDLd,  [SBPort0,SBPort23], 7, [1,1], 2>;
340defm : X86WriteRes<WriteCvtPS2PDYLd, [SBPort0,SBPort23], 7, [1,1], 2>;
341defm : X86WriteRes<WriteCvtPS2PDZLd, [SBPort0,SBPort23], 7, [1,1], 2>; // Unsupported = 1
342defm : SBWriteResPair<WriteCvtSD2SS,  [SBPort1,SBPort5], 4, [1,1], 2, 6>;
343defm : SBWriteResPair<WriteCvtPD2PS,  [SBPort1,SBPort5], 4, [1,1], 2, 6>;
344defm : SBWriteResPair<WriteCvtPD2PSY, [SBPort1,SBPort5], 4, [1,1], 2, 7>;
345defm : SBWriteResPair<WriteCvtPD2PSZ, [SBPort1,SBPort5], 4, [1,1], 2, 7>; // Unsupported = 1
346
347defm : SBWriteResPair<WriteCvtPH2PS,  [SBPort1], 3>;
348defm : SBWriteResPair<WriteCvtPH2PSY, [SBPort1], 3>;
349defm : SBWriteResPair<WriteCvtPH2PSZ, [SBPort1], 3>; // Unsupported = 1
350
351defm : X86WriteRes<WriteCvtPS2PH,    [SBPort1], 3, [1], 1>;
352defm : X86WriteRes<WriteCvtPS2PHY,   [SBPort1], 3, [1], 1>;
353defm : X86WriteRes<WriteCvtPS2PHZ,   [SBPort1], 3, [1], 1>; // Unsupported = 1
354defm : X86WriteRes<WriteCvtPS2PHSt,  [SBPort1, SBPort23, SBPort4], 4, [1,1,1], 1>;
355defm : X86WriteRes<WriteCvtPS2PHYSt, [SBPort1, SBPort23, SBPort4], 4, [1,1,1], 1>;
356defm : X86WriteRes<WriteCvtPS2PHZSt, [SBPort1, SBPort23, SBPort4], 4, [1,1,1], 1>; // Unsupported = 1
357
358// Vector integer operations.
359defm : X86WriteRes<WriteVecLoad,         [SBPort23], 5, [1], 1>;
360defm : X86WriteRes<WriteVecLoadX,        [SBPort23], 6, [1], 1>;
361defm : X86WriteRes<WriteVecLoadY,        [SBPort23], 7, [1], 1>;
362defm : X86WriteRes<WriteVecLoadNT,       [SBPort23], 6, [1], 1>;
363defm : X86WriteRes<WriteVecLoadNTY,      [SBPort23], 7, [1], 1>;
364defm : X86WriteRes<WriteVecMaskedLoad,   [SBPort23,SBPort05], 8, [1,2], 3>;
365defm : X86WriteRes<WriteVecMaskedLoadY,  [SBPort23,SBPort05], 9, [1,2], 3>;
366defm : X86WriteRes<WriteVecStore,        [SBPort23,SBPort4], 1, [1,1], 1>;
367defm : X86WriteRes<WriteVecStoreX,       [SBPort23,SBPort4], 1, [1,1], 1>;
368defm : X86WriteRes<WriteVecStoreY,       [SBPort23,SBPort4], 1, [1,1], 1>;
369defm : X86WriteRes<WriteVecStoreNT,      [SBPort23,SBPort4], 1, [1,1], 1>;
370defm : X86WriteRes<WriteVecStoreNTY,     [SBPort23,SBPort4], 1, [1,1], 1>;
371defm : X86WriteRes<WriteVecMaskedStore32,  [SBPort4,SBPort01,SBPort23], 5, [1,1,1], 3>;
372defm : X86WriteRes<WriteVecMaskedStore32Y, [SBPort4,SBPort01,SBPort23], 5, [1,1,1], 3>;
373defm : X86WriteRes<WriteVecMaskedStore64,  [SBPort4,SBPort01,SBPort23], 5, [1,1,1], 3>;
374defm : X86WriteRes<WriteVecMaskedStore64Y, [SBPort4,SBPort01,SBPort23], 5, [1,1,1], 3>;
375defm : X86WriteRes<WriteVecMove,         [SBPort05], 1, [1], 1>;
376defm : X86WriteRes<WriteVecMoveX,        [SBPort015], 1, [1], 1>;
377defm : X86WriteRes<WriteVecMoveY,        [SBPort05], 1, [1], 1>;
378defm : X86WriteRes<WriteVecMoveToGpr,    [SBPort0], 2, [1], 1>;
379defm : X86WriteRes<WriteVecMoveFromGpr,  [SBPort5], 1, [1], 1>;
380
381defm : SBWriteResPair<WriteVecLogic, [SBPort015], 1, [1], 1, 5>;
382defm : SBWriteResPair<WriteVecLogicX,[SBPort015], 1, [1], 1, 6>;
383defm : SBWriteResPair<WriteVecLogicY,[SBPort015], 1, [1], 1, 7>;
384defm : SBWriteResPair<WriteVecLogicZ,[SBPort015], 1, [1], 1, 7>; // Unsupported = 1
385defm : SBWriteResPair<WriteVecTest,  [SBPort0,SBPort5], 2, [1,1], 2, 6>;
386defm : SBWriteResPair<WriteVecTestY, [SBPort0,SBPort5], 2, [1,1], 2, 7>;
387defm : SBWriteResPair<WriteVecTestZ, [SBPort0,SBPort5], 2, [1,1], 2, 7>; // Unsupported = 1
388defm : SBWriteResPair<WriteVecALU,   [SBPort1],  3, [1], 1, 5>;
389defm : SBWriteResPair<WriteVecALUX,  [SBPort15], 1, [1], 1, 6>;
390defm : SBWriteResPair<WriteVecALUY,  [SBPort15], 1, [1], 1, 7>;
391defm : SBWriteResPair<WriteVecALUZ,  [SBPort15], 1, [1], 1, 7>; // Unsupported = 1
392defm : SBWriteResPair<WriteVecIMul,  [SBPort0], 5, [1], 1, 5>;
393defm : SBWriteResPair<WriteVecIMulX, [SBPort0], 5, [1], 1, 6>;
394defm : SBWriteResPair<WriteVecIMulY, [SBPort0], 5, [1], 1, 7>;
395defm : SBWriteResPair<WriteVecIMulZ, [SBPort0], 5, [1], 1, 7>; // Unsupported = 1
396defm : SBWriteResPair<WritePMULLD,   [SBPort0], 5, [1], 1, 6>;
397defm : SBWriteResPair<WritePMULLDY,  [SBPort0], 5, [1], 1, 7>; // TODO this is probably wrong for 256/512-bit for the "generic" model
398defm : SBWriteResPair<WritePMULLDZ,  [SBPort0], 5, [1], 1, 7>;  // Unsupported = 1
399defm : SBWriteResPair<WriteShuffle,  [SBPort5], 1, [1], 1, 5>;
400defm : SBWriteResPair<WriteShuffleX, [SBPort15], 1, [1], 1, 6>;
401defm : SBWriteResPair<WriteShuffleY, [SBPort5], 1, [1], 1, 7>;
402defm : SBWriteResPair<WriteShuffleZ, [SBPort5], 1, [1], 1, 7>; // Unsupported = 1
403defm : SBWriteResPair<WriteVarShuffle,  [SBPort15], 1, [1], 1, 5>;
404defm : SBWriteResPair<WriteVarShuffleX, [SBPort15], 1, [1], 1, 6>;
405defm : SBWriteResPair<WriteVarShuffleY, [SBPort15], 1, [1], 1, 7>;
406defm : SBWriteResPair<WriteVarShuffleZ, [SBPort15], 1, [1], 1, 7>; // Unsupported = 1
407defm : SBWriteResPair<WriteBlend,   [SBPort15], 1, [1], 1, 6>;
408defm : SBWriteResPair<WriteBlendY,  [SBPort15], 1, [1], 1, 7>;
409defm : SBWriteResPair<WriteBlendZ,  [SBPort15], 1, [1], 1, 7>; // Unsupported = 1
410defm : SBWriteResPair<WriteVarBlend, [SBPort15], 2, [2], 2, 6>;
411defm : SBWriteResPair<WriteVarBlendY,[SBPort15], 2, [2], 2, 7>;
412defm : SBWriteResPair<WriteVarBlendZ,[SBPort15], 2, [2], 2, 7>; // Unsupported = 1
413defm : SBWriteResPair<WriteMPSAD,  [SBPort0, SBPort15], 7, [1,2], 3, 6>;
414defm : SBWriteResPair<WriteMPSADY, [SBPort0, SBPort15], 7, [1,2], 3, 7>;
415defm : SBWriteResPair<WriteMPSADZ, [SBPort0, SBPort15], 7, [1,2], 3, 7>; // Unsupported = 1
416defm : SBWriteResPair<WritePSADBW,  [SBPort0], 5, [1], 1, 5>;
417defm : SBWriteResPair<WritePSADBWX, [SBPort0], 5, [1], 1, 6>;
418defm : SBWriteResPair<WritePSADBWY, [SBPort0], 5, [1], 1, 7>;
419defm : SBWriteResPair<WritePSADBWZ, [SBPort0], 5, [1], 1, 7>; // Unsupported = 1
420defm : SBWriteResPair<WritePHMINPOS,  [SBPort0], 5, [1], 1, 6>;
421
422// Vector integer shifts.
423defm : SBWriteResPair<WriteVecShift,     [SBPort5], 1, [1], 1, 5>;
424defm : SBWriteResPair<WriteVecShiftX,    [SBPort0,SBPort15], 2, [1,1], 2, 6>;
425defm : SBWriteResPair<WriteVecShiftY,    [SBPort0,SBPort15], 4, [1,1], 2, 7>;
426defm : SBWriteResPair<WriteVecShiftZ,    [SBPort0,SBPort15], 4, [1,1], 2, 7>; // Unsupported = 1
427defm : SBWriteResPair<WriteVecShiftImm,  [SBPort5], 1, [1], 1, 5>;
428defm : SBWriteResPair<WriteVecShiftImmX, [SBPort0], 1, [1], 1, 6>;
429defm : SBWriteResPair<WriteVecShiftImmY, [SBPort0], 1, [1], 1, 7>;
430defm : SBWriteResPair<WriteVecShiftImmZ, [SBPort0], 1, [1], 1, 7>; // Unsupported = 1
431defm : SBWriteResPair<WriteVarVecShift,  [SBPort0], 1, [1], 1, 6>;
432defm : SBWriteResPair<WriteVarVecShiftY, [SBPort0], 1, [1], 1, 7>;
433defm : SBWriteResPair<WriteVarVecShiftZ, [SBPort0], 1, [1], 1, 7>; // Unsupported = 1
434
435// Vector insert/extract operations.
436def : WriteRes<WriteVecInsert, [SBPort5,SBPort15]> {
437  let Latency = 2;
438  let NumMicroOps = 2;
439}
440def : WriteRes<WriteVecInsertLd, [SBPort23,SBPort15]> {
441  let Latency = 7;
442  let NumMicroOps = 2;
443}
444
445def : WriteRes<WriteVecExtract, [SBPort0,SBPort15]> {
446  let Latency = 3;
447  let NumMicroOps = 2;
448}
449def : WriteRes<WriteVecExtractSt, [SBPort4,SBPort23,SBPort15]> {
450  let Latency = 5;
451  let NumMicroOps = 3;
452}
453
454////////////////////////////////////////////////////////////////////////////////
455// Horizontal add/sub  instructions.
456////////////////////////////////////////////////////////////////////////////////
457
458defm : SBWriteResPair<WriteFHAdd,  [SBPort1,SBPort5], 5, [1,2], 3, 6>;
459defm : SBWriteResPair<WriteFHAddY, [SBPort1,SBPort5], 5, [1,2], 3, 7>;
460defm : SBWriteResPair<WriteFHAddZ, [SBPort1,SBPort5], 5, [1,2], 3, 7>; // Unsupported = 1
461defm : SBWriteResPair<WritePHAdd,  [SBPort15], 3, [3], 3, 5>;
462defm : SBWriteResPair<WritePHAddX, [SBPort15], 3, [3], 3, 6>;
463defm : SBWriteResPair<WritePHAddY, [SBPort15], 3, [3], 3, 7>;
464defm : SBWriteResPair<WritePHAddZ, [SBPort15], 3, [3], 3, 7>; // Unsupported = 1
465
466////////////////////////////////////////////////////////////////////////////////
467// String instructions.
468////////////////////////////////////////////////////////////////////////////////
469
470// Packed Compare Implicit Length Strings, Return Mask
471def : WriteRes<WritePCmpIStrM, [SBPort0]> {
472  let Latency = 11;
473  let NumMicroOps = 3;
474  let ResourceCycles = [3];
475}
476def : WriteRes<WritePCmpIStrMLd, [SBPort0, SBPort23]> {
477  let Latency = 17;
478  let NumMicroOps = 4;
479  let ResourceCycles = [3,1];
480}
481
482// Packed Compare Explicit Length Strings, Return Mask
483def : WriteRes<WritePCmpEStrM, [SBPort015]> {
484  let Latency = 11;
485  let ResourceCycles = [8];
486}
487def : WriteRes<WritePCmpEStrMLd, [SBPort015, SBPort23]> {
488  let Latency = 17;
489  let ResourceCycles = [7, 1];
490}
491
492// Packed Compare Implicit Length Strings, Return Index
493def : WriteRes<WritePCmpIStrI, [SBPort0]> {
494  let Latency = 11;
495  let NumMicroOps = 3;
496  let ResourceCycles = [3];
497}
498def : WriteRes<WritePCmpIStrILd, [SBPort0,SBPort23]> {
499  let Latency = 17;
500  let NumMicroOps = 4;
501  let ResourceCycles = [3,1];
502}
503
504// Packed Compare Explicit Length Strings, Return Index
505def : WriteRes<WritePCmpEStrI, [SBPort015]> {
506  let Latency = 4;
507  let ResourceCycles = [8];
508}
509def : WriteRes<WritePCmpEStrILd, [SBPort015, SBPort23]> {
510  let Latency = 10;
511  let ResourceCycles = [7, 1];
512}
513
514// MOVMSK Instructions.
515def : WriteRes<WriteFMOVMSK,    [SBPort0]> { let Latency = 2; }
516def : WriteRes<WriteVecMOVMSK,  [SBPort0]> { let Latency = 2; }
517def : WriteRes<WriteVecMOVMSKY, [SBPort0]> { let Latency = 2; }
518def : WriteRes<WriteMMXMOVMSK,  [SBPort0]> { let Latency = 1; }
519
520// AES Instructions.
521def : WriteRes<WriteAESDecEnc, [SBPort5,SBPort015]> {
522  let Latency = 7;
523  let NumMicroOps = 2;
524  let ResourceCycles = [1,1];
525}
526def : WriteRes<WriteAESDecEncLd, [SBPort5,SBPort23,SBPort015]> {
527  let Latency = 13;
528  let NumMicroOps = 3;
529  let ResourceCycles = [1,1,1];
530}
531
532def : WriteRes<WriteAESIMC, [SBPort5]> {
533  let Latency = 12;
534  let NumMicroOps = 2;
535  let ResourceCycles = [2];
536}
537def : WriteRes<WriteAESIMCLd, [SBPort5,SBPort23]> {
538  let Latency = 18;
539  let NumMicroOps = 3;
540  let ResourceCycles = [2,1];
541}
542
543def : WriteRes<WriteAESKeyGen, [SBPort015]> {
544  let Latency = 8;
545  let ResourceCycles = [11];
546}
547def : WriteRes<WriteAESKeyGenLd, [SBPort015, SBPort23]> {
548  let Latency = 14;
549  let ResourceCycles = [10, 1];
550}
551
552// Carry-less multiplication instructions.
553def : WriteRes<WriteCLMul, [SBPort015]> {
554  let Latency = 14;
555  let ResourceCycles = [18];
556}
557def : WriteRes<WriteCLMulLd, [SBPort015, SBPort23]> {
558  let Latency = 20;
559  let ResourceCycles = [17, 1];
560}
561
562// Load/store MXCSR.
563// FIXME: This is probably wrong. Only STMXCSR should require Port4.
564def : WriteRes<WriteLDMXCSR, [SBPort0,SBPort4,SBPort5,SBPort23]> { let Latency = 5; let NumMicroOps = 4; let ResourceCycles = [1,1,1,1]; }
565def : WriteRes<WriteSTMXCSR, [SBPort0,SBPort4,SBPort5,SBPort23]> { let Latency = 5; let NumMicroOps = 4; let ResourceCycles = [1,1,1,1]; }
566
567def : WriteRes<WriteSystem,     [SBPort015]> { let Latency = 100; }
568def : WriteRes<WriteMicrocoded, [SBPort015]> { let Latency = 100; }
569def : WriteRes<WriteFence, [SBPort23, SBPort4]>;
570def : WriteRes<WriteNop, []>;
571
572// AVX2/FMA is not supported on that architecture, but we should define the basic
573// scheduling resources anyway.
574defm : SBWriteResPair<WriteFShuffle256, [SBPort5], 1, [1], 1, 7>;
575defm : SBWriteResPair<WriteFVarShuffle256, [SBPort5], 1, [1], 1, 7>;
576defm : SBWriteResPair<WriteShuffle256, [SBPort5], 1, [1], 1, 7>;
577defm : SBWriteResPair<WriteVPMOV256, [SBPort5], 1, [1], 1, 7>;
578defm : SBWriteResPair<WriteVarShuffle256, [SBPort5], 1, [1], 1, 7>;
579defm : SBWriteResPair<WriteFMA,  [SBPort01],  5>;
580defm : SBWriteResPair<WriteFMAX, [SBPort01],  5>;
581defm : SBWriteResPair<WriteFMAY, [SBPort01],  5>;
582defm : SBWriteResPair<WriteFMAZ, [SBPort01],  5>;  // Unsupported = 1
583
584// Remaining SNB instrs.
585
586def SBWriteResGroup1 : SchedWriteRes<[SBPort1]> {
587  let Latency = 1;
588  let NumMicroOps = 1;
589  let ResourceCycles = [1];
590}
591def: InstRW<[SBWriteResGroup1], (instrs COMP_FST0r,
592                                        COM_FST0r,
593                                        UCOM_FPr,
594                                        UCOM_Fr)>;
595
596def SBWriteResGroup2 : SchedWriteRes<[SBPort5]> {
597  let Latency = 1;
598  let NumMicroOps = 1;
599  let ResourceCycles = [1];
600}
601def: InstRW<[SBWriteResGroup2], (instrs FDECSTP, FINCSTP, FFREE, FFREEP, FNOP,
602                                        LD_Frr, ST_Frr, ST_FPrr)>;
603def: InstRW<[SBWriteResGroup2], (instrs LOOP, LOOPE, LOOPNE)>; // FIXME: This seems wrong compared to other Intel CPUs.
604def: InstRW<[SBWriteResGroup2], (instrs RETQ)>;
605
606def SBWriteResGroup4 : SchedWriteRes<[SBPort05]> {
607  let Latency = 1;
608  let NumMicroOps = 1;
609  let ResourceCycles = [1];
610}
611def: InstRW<[SBWriteResGroup4], (instrs CDQ, CQO)>;
612
613def SBWriteResGroup5 : SchedWriteRes<[SBPort15]> {
614  let Latency = 1;
615  let NumMicroOps = 1;
616  let ResourceCycles = [1];
617}
618def: InstRW<[SBWriteResGroup5], (instrs MMX_PABSBrr,
619                                        MMX_PABSDrr,
620                                        MMX_PABSWrr,
621                                        MMX_PADDQirr,
622                                        MMX_PALIGNRrri,
623                                        MMX_PSIGNBrr,
624                                        MMX_PSIGNDrr,
625                                        MMX_PSIGNWrr)>;
626
627def SBWriteResGroup11 : SchedWriteRes<[SBPort015]> {
628  let Latency = 2;
629  let NumMicroOps = 2;
630  let ResourceCycles = [2];
631}
632def: InstRW<[SBWriteResGroup11], (instrs SCASB,
633                                         SCASL,
634                                         SCASQ,
635                                         SCASW)>;
636
637def SBWriteResGroup12 : SchedWriteRes<[SBPort0,SBPort1]> {
638  let Latency = 2;
639  let NumMicroOps = 2;
640  let ResourceCycles = [1,1];
641}
642def: InstRW<[SBWriteResGroup12], (instregex "(V?)(U?)COMI(SD|SS)rr")>;
643
644def SBWriteResGroup15 : SchedWriteRes<[SBPort0,SBPort015]> {
645  let Latency = 2;
646  let NumMicroOps = 2;
647  let ResourceCycles = [1,1];
648}
649def: InstRW<[SBWriteResGroup15], (instrs CWD,
650                                         FNSTSW16r)>;
651
652def SBWriteResGroup18 : SchedWriteRes<[SBPort5,SBPort015]> {
653  let Latency = 2;
654  let NumMicroOps = 2;
655  let ResourceCycles = [1,1];
656}
657def: InstRW<[SBWriteResGroup18], (instrs JCXZ, JECXZ, JRCXZ,
658                                         MMX_MOVDQ2Qrr)>;
659
660def SBWriteResGroup21 : SchedWriteRes<[SBPort1]> {
661  let Latency = 3;
662  let NumMicroOps = 1;
663  let ResourceCycles = [1];
664}
665def: InstRW<[SBWriteResGroup21], (instrs PUSHFS64)>;
666
667def SBWriteResGroup22 : SchedWriteRes<[SBPort0,SBPort5]> {
668  let Latency = 3;
669  let NumMicroOps = 2;
670  let ResourceCycles = [1,1];
671}
672def: InstRW<[SBWriteResGroup22], (instregex "(V?)EXTRACTPSrr")>;
673
674def SBWriteResGroup23 : SchedWriteRes<[SBPort05]> {
675  let Latency = 2;
676  let NumMicroOps = 3;
677  let ResourceCycles = [3];
678}
679def: InstRW<[SBWriteResGroup23], (instregex "RCL(8|16|32|64)r1",
680                                            "RCR(8|16|32|64)r1")>;
681
682def SBWriteResGroup25_1 : SchedWriteRes<[SBPort23,SBPort015]> {
683  let Latency = 7;
684  let NumMicroOps = 3;
685  let ResourceCycles = [1,2];
686}
687def: InstRW<[SBWriteResGroup25_1], (instrs LEAVE, LEAVE64)>;
688
689def SBWriteResGroup26_2 : SchedWriteRes<[SBPort0,SBPort1,SBPort5]> {
690  let Latency = 3;
691  let NumMicroOps = 3;
692  let ResourceCycles = [1,1,1];
693}
694def: InstRW<[SBWriteResGroup26_2], (instrs COM_FIPr, COM_FIr, UCOM_FIPr, UCOM_FIr)>;
695
696def SBWriteResGroup29 : SchedWriteRes<[SBPort1,SBPort015]> {
697  let Latency = 4;
698  let NumMicroOps = 2;
699  let ResourceCycles = [1,1];
700}
701def: InstRW<[SBWriteResGroup29], (instrs MOV64sr)>;
702
703def SBWriteResGroup29_2 : SchedWriteRes<[SBPort5,SBPort015]> {
704  let Latency = 4;
705  let NumMicroOps = 4;
706  let ResourceCycles = [1,3];
707}
708def: InstRW<[SBWriteResGroup29_2], (instrs PAUSE)>;
709
710def SBWriteResGroup31 : SchedWriteRes<[SBPort23]> {
711  let Latency = 5;
712  let NumMicroOps = 1;
713  let ResourceCycles = [1];
714}
715def: InstRW<[SBWriteResGroup31], (instregex "MOVSX(16|32|64)rm(8|16|32)",
716                                            "MOVZX(16|32|64)rm(8|16)")>;
717
718def SBWriteResGroup76 : SchedWriteRes<[SBPort05]> {
719  let Latency = 5;
720  let NumMicroOps = 8;
721  let ResourceCycles = [8];
722}
723def: InstRW<[SBWriteResGroup76], (instregex "RCL(8|16|32|64)r(i|CL)",
724                                            "RCR(8|16|32|64)r(i|CL)")>;
725
726def SBWriteResGroup33 : SchedWriteRes<[SBPort4,SBPort23]> {
727  let Latency = 5;
728  let NumMicroOps = 2;
729  let ResourceCycles = [1,1];
730}
731def: InstRW<[SBWriteResGroup33], (instregex "PUSH(16r|32r|64r|64i8)")>;
732
733def SBWriteResGroup35 : SchedWriteRes<[SBPort1,SBPort5]> {
734  let Latency = 5;
735  let NumMicroOps = 3;
736  let ResourceCycles = [1,2];
737}
738def: InstRW<[SBWriteResGroup35], (instrs CLI)>;
739
740def SBWriteResGroup35_2 : SchedWriteRes<[SBPort1,SBPort4,SBPort23]> {
741  let Latency = 5;
742  let NumMicroOps = 3;
743  let ResourceCycles = [1,1,1];
744}
745def: InstRW<[SBWriteResGroup35_2], (instrs PUSHGS64)>;
746def: InstRW<[SBWriteResGroup35_2], (instregex "ISTT_FP(16|32|64)m")>;
747
748def SBWriteResGroup36 : SchedWriteRes<[SBPort4,SBPort5,SBPort23]> {
749  let Latency = 5;
750  let NumMicroOps = 3;
751  let ResourceCycles = [1,1,1];
752}
753def: InstRW<[SBWriteResGroup36], (instrs CALL64pcrel32)>;
754def: InstRW<[SBWriteResGroup36], (instregex "CALL(16|32|64)r",
755                                            "(V?)EXTRACTPSmr")>;
756
757def SBWriteResGroup40 : SchedWriteRes<[SBPort4,SBPort23,SBPort015]> {
758  let Latency = 5;
759  let NumMicroOps = 3;
760  let ResourceCycles = [1,1,1];
761}
762def: InstRW<[SBWriteResGroup40], (instrs STOSB, STOSL, STOSQ, STOSW)>;
763
764def SBWriteResGroup41 : SchedWriteRes<[SBPort5,SBPort015]> {
765  let Latency = 5;
766  let NumMicroOps = 4;
767  let ResourceCycles = [1,3];
768}
769def: InstRW<[SBWriteResGroup41], (instrs FNINIT)>;
770
771def SBWriteResGroup45 : SchedWriteRes<[SBPort0,SBPort4,SBPort23,SBPort15]> {
772  let Latency = 5;
773  let NumMicroOps = 4;
774  let ResourceCycles = [1,1,1,1];
775}
776def: InstRW<[SBWriteResGroup45], (instregex "(V?)PEXTR(D|Q)mr",
777                                            "PUSHF(16|64)")>;
778
779def SBWriteResGroup46 : SchedWriteRes<[SBPort4,SBPort5,SBPort01,SBPort23]> {
780  let Latency = 5;
781  let NumMicroOps = 4;
782  let ResourceCycles = [1,1,1,1];
783}
784def: InstRW<[SBWriteResGroup46], (instregex "CLFLUSH")>;
785
786def SBWriteResGroup47 : SchedWriteRes<[SBPort4,SBPort5,SBPort01,SBPort23]> {
787  let Latency = 5;
788  let NumMicroOps = 5;
789  let ResourceCycles = [1,2,1,1];
790}
791def: InstRW<[SBWriteResGroup47], (instregex "FXRSTOR")>;
792
793def SBWriteResGroup48 : SchedWriteRes<[SBPort23]> {
794  let Latency = 6;
795  let NumMicroOps = 1;
796  let ResourceCycles = [1];
797}
798def: InstRW<[SBWriteResGroup48], (instrs MMX_MOVD64from64rm,
799                                         VBROADCASTSSrm)>;
800def: InstRW<[SBWriteResGroup48], (instregex "POP(16|32|64)r",
801                                            "(V?)MOV64toPQIrm",
802                                            "(V?)MOVDDUPrm",
803                                            "(V?)MOVDI2PDIrm",
804                                            "(V?)MOVQI2PQIrm",
805                                            "(V?)MOVSDrm",
806                                            "(V?)MOVSHDUPrm",
807                                            "(V?)MOVSLDUPrm",
808                                            "(V?)MOVSSrm")>;
809
810def SBWriteResGroup49 : SchedWriteRes<[SBPort5,SBPort23]> {
811  let Latency = 6;
812  let NumMicroOps = 2;
813  let ResourceCycles = [1,1];
814}
815def: InstRW<[SBWriteResGroup49], (instrs MOV16sm)>;
816
817def SBWriteResGroup51 : SchedWriteRes<[SBPort23,SBPort15]> {
818  let Latency = 6;
819  let NumMicroOps = 2;
820  let ResourceCycles = [1,1];
821}
822def: InstRW<[SBWriteResGroup51], (instrs MMX_PABSBrm,
823                                         MMX_PABSDrm,
824                                         MMX_PABSWrm,
825                                         MMX_PALIGNRrmi,
826                                         MMX_PSIGNBrm,
827                                         MMX_PSIGNDrm,
828                                         MMX_PSIGNWrm)>;
829
830def SBWriteResGroup52 : SchedWriteRes<[SBPort23,SBPort015]> {
831  let Latency = 6;
832  let NumMicroOps = 2;
833  let ResourceCycles = [1,1];
834}
835def: InstRW<[SBWriteResGroup52], (instrs LODSL, LODSQ)>;
836
837def SBWriteResGroup53 : SchedWriteRes<[SBPort4,SBPort23]> {
838  let Latency = 6;
839  let NumMicroOps = 3;
840  let ResourceCycles = [1,2];
841}
842def: InstRW<[SBWriteResGroup53], (instregex "ST_F(32|64)m",
843                                            "ST_FP(32|64|80)m")>;
844
845def SBWriteResGroup54 : SchedWriteRes<[SBPort23]> {
846  let Latency = 7;
847  let NumMicroOps = 1;
848  let ResourceCycles = [1];
849}
850def: InstRW<[SBWriteResGroup54], (instrs VBROADCASTSDYrm,
851                                         VBROADCASTSSYrm,
852                                         VMOVDDUPYrm,
853                                         VMOVSHDUPYrm,
854                                         VMOVSLDUPYrm)>;
855
856def SBWriteResGroup58 : SchedWriteRes<[SBPort23,SBPort05]> {
857  let Latency = 7;
858  let NumMicroOps = 2;
859  let ResourceCycles = [1,1];
860}
861def: InstRW<[SBWriteResGroup58], (instrs VINSERTF128rm)>;
862
863def SBWriteResGroup59 : SchedWriteRes<[SBPort23,SBPort15]> {
864  let Latency = 7;
865  let NumMicroOps = 2;
866  let ResourceCycles = [1,1];
867}
868def: InstRW<[SBWriteResGroup59], (instrs MMX_PADDQirm)>;
869
870def SBWriteResGroup62 : SchedWriteRes<[SBPort5,SBPort23]> {
871  let Latency = 7;
872  let NumMicroOps = 3;
873  let ResourceCycles = [2,1];
874}
875def: InstRW<[SBWriteResGroup62], (instrs VERRm, VERWm)>;
876
877def SBWriteResGroup63 : SchedWriteRes<[SBPort23,SBPort015]> {
878  let Latency = 7;
879  let NumMicroOps = 3;
880  let ResourceCycles = [1,2];
881}
882def: InstRW<[SBWriteResGroup63], (instrs LODSB, LODSW)>;
883
884def SBWriteResGroup64 : SchedWriteRes<[SBPort5,SBPort01,SBPort23]> {
885  let Latency = 7;
886  let NumMicroOps = 3;
887  let ResourceCycles = [1,1,1];
888}
889def: InstRW<[SBWriteResGroup64], (instrs FARJMP64m)>;
890
891def SBWriteResGroup66 : SchedWriteRes<[SBPort0,SBPort4,SBPort23]> {
892  let Latency = 7;
893  let NumMicroOps = 4;
894  let ResourceCycles = [1,1,2];
895}
896def: InstRW<[SBWriteResGroup66], (instrs FNSTSWm)>;
897
898def SBWriteResGroup67 : SchedWriteRes<[SBPort1,SBPort5,SBPort015]> {
899  let Latency = 7;
900  let NumMicroOps = 4;
901  let ResourceCycles = [1,2,1];
902}
903def: InstRW<[SBWriteResGroup67], (instregex "SLDT(16|32|64)r",
904                                            "STR(16|32|64)r")>;
905
906def SBWriteResGroup68 : SchedWriteRes<[SBPort4,SBPort5,SBPort23]> {
907  let Latency = 7;
908  let NumMicroOps = 4;
909  let ResourceCycles = [1,1,2];
910}
911def: InstRW<[SBWriteResGroup68], (instrs FNSTCW16m)>;
912def: InstRW<[SBWriteResGroup68], (instregex "CALL(16|32|64)m")>;
913
914def SBWriteResGroup69 : SchedWriteRes<[SBPort4,SBPort23,SBPort05]> {
915  let Latency = 7;
916  let NumMicroOps = 4;
917  let ResourceCycles = [1,2,1];
918}
919def: InstRW<[SBWriteResGroup69], (instregex "SAR(8|16|32|64)m(1|i)",
920                                            "SHL(8|16|32|64)m(1|i)",
921                                            "SHR(8|16|32|64)m(1|i)")>;
922
923def SBWriteResGroup77 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> {
924  let Latency = 8;
925  let NumMicroOps = 3;
926  let ResourceCycles = [1,1,1];
927}
928def: InstRW<[SBWriteResGroup77], (instregex "(V?)(U?)COMI(SD|SS)rm")>;
929
930def SBWriteResGroup81 : SchedWriteRes<[SBPort4, SBPort23, SBPort015]> {
931  let Latency = 6;
932  let NumMicroOps = 3;
933  let ResourceCycles = [1, 2, 1];
934}
935def: InstRW<[SBWriteResGroup81], (instregex "CMPXCHG(8|16)B")>;
936
937def SBWriteResGroup83 : SchedWriteRes<[SBPort23,SBPort015]> {
938  let Latency = 8;
939  let NumMicroOps = 5;
940  let ResourceCycles = [2,3];
941}
942def: InstRW<[SBWriteResGroup83], (instrs CMPSB,
943                                         CMPSL,
944                                         CMPSQ,
945                                         CMPSW)>;
946
947def SBWriteResGroup84 : SchedWriteRes<[SBPort4,SBPort5,SBPort23]> {
948  let Latency = 8;
949  let NumMicroOps = 5;
950  let ResourceCycles = [1,2,2];
951}
952def: InstRW<[SBWriteResGroup84], (instrs FLDCW16m)>;
953
954def SBWriteResGroup85 : SchedWriteRes<[SBPort4,SBPort23,SBPort05]> {
955  let Latency = 8;
956  let NumMicroOps = 5;
957  let ResourceCycles = [1,2,2];
958}
959def: InstRW<[SBWriteResGroup85], (instregex "ROL(8|16|32|64)m(1|i)",
960                                            "ROR(8|16|32|64)m(1|i)")>;
961
962def SBWriteResGroup86 : SchedWriteRes<[SBPort4,SBPort23,SBPort015]> {
963  let Latency = 8;
964  let NumMicroOps = 5;
965  let ResourceCycles = [1,2,2];
966}
967def: InstRW<[SBWriteResGroup86], (instrs MOVSB, MOVSL, MOVSQ, MOVSW)>;
968def: InstRW<[SBWriteResGroup86], (instregex "XADD(8|16|32|64)rm")>;
969
970def SBWriteResGroup87 : SchedWriteRes<[SBPort4,SBPort5,SBPort01,SBPort23]> {
971  let Latency = 8;
972  let NumMicroOps = 5;
973  let ResourceCycles = [1,1,1,2];
974}
975def: InstRW<[SBWriteResGroup87], (instrs FARCALL64m)>;
976
977def SBWriteResGroup93 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> {
978  let Latency = 9;
979  let NumMicroOps = 3;
980  let ResourceCycles = [1,1,1];
981}
982def: InstRW<[SBWriteResGroup93], (instregex "CVT(T?)(SD|SS)2SI(64)?rm")>;
983
984def SBWriteResGroup95 : SchedWriteRes<[SBPort5,SBPort01,SBPort23]> {
985  let Latency = 9;
986  let NumMicroOps = 3;
987  let ResourceCycles = [1,1,1];
988}
989def: InstRW<[SBWriteResGroup95], (instregex "LD_F(32|64|80)m")>;
990
991def SBWriteResGroup97 : SchedWriteRes<[SBPort1,SBPort4,SBPort23]> {
992  let Latency = 9;
993  let NumMicroOps = 4;
994  let ResourceCycles = [1,1,2];
995}
996def: InstRW<[SBWriteResGroup97], (instregex "IST_F(16|32)m",
997                                            "IST_FP(16|32|64)m")>;
998
999def SBWriteResGroup97_2 : SchedWriteRes<[SBPort4,SBPort23,SBPort05]> {
1000  let Latency = 9;
1001  let NumMicroOps = 6;
1002  let ResourceCycles = [1,2,3];
1003}
1004def: InstRW<[SBWriteResGroup97_2], (instregex "ROL(8|16|32|64)mCL",
1005                                              "ROR(8|16|32|64)mCL",
1006                                              "SAR(8|16|32|64)mCL",
1007                                              "SHL(8|16|32|64)mCL",
1008                                              "SHR(8|16|32|64)mCL")>;
1009
1010def SBWriteResGroup98 : SchedWriteRes<[SBPort4,SBPort23,SBPort015]> {
1011  let Latency = 9;
1012  let NumMicroOps = 6;
1013  let ResourceCycles = [1,2,3];
1014}
1015def: SchedAlias<WriteADCRMW, SBWriteResGroup98>;
1016
1017def SBWriteResGroup99 : SchedWriteRes<[SBPort4,SBPort23,SBPort05,SBPort015]> {
1018  let Latency = 9;
1019  let NumMicroOps = 6;
1020  let ResourceCycles = [1,2,2,1];
1021}
1022def: InstRW<[SBWriteResGroup99, ReadAfterLd], (instrs ADC8mr, ADC16mr, ADC32mr, ADC64mr,
1023                                                      SBB8mr, SBB16mr, SBB32mr, SBB64mr)>;
1024
1025def SBWriteResGroup100 : SchedWriteRes<[SBPort4,SBPort5,SBPort23,SBPort05,SBPort015]> {
1026  let Latency = 9;
1027  let NumMicroOps = 6;
1028  let ResourceCycles = [1,1,2,1,1];
1029}
1030def : SchedAlias<WriteBitTestRegLd, SBWriteResGroup100>; // TODO - this is incorrect - no RMW
1031
1032def SBWriteResGroup101 : SchedWriteRes<[SBPort1,SBPort23]> {
1033  let Latency = 10;
1034  let NumMicroOps = 2;
1035  let ResourceCycles = [1,1];
1036}
1037def: InstRW<[SBWriteResGroup101], (instregex "(ADD|SUB|SUBR)_F(32|64)m",
1038                                             "ILD_F(16|32|64)m")>;
1039
1040def SBWriteResGroup104 : SchedWriteRes<[SBPort0,SBPort23]> {
1041  let Latency = 11;
1042  let NumMicroOps = 2;
1043  let ResourceCycles = [1,1];
1044}
1045def: InstRW<[SBWriteResGroup104], (instregex "(V?)PCMPGTQrm")>;
1046
1047def SBWriteResGroup106 : SchedWriteRes<[SBPort1,SBPort23]> {
1048  let Latency = 11;
1049  let NumMicroOps = 3;
1050  let ResourceCycles = [2,1];
1051}
1052def: InstRW<[SBWriteResGroup106], (instregex "FICOM(P?)(16|32)m")>;
1053
1054def SBWriteResGroup108 : SchedWriteRes<[SBPort05,SBPort23]> {
1055  let Latency = 11;
1056  let NumMicroOps = 11;
1057  let ResourceCycles = [7,4];
1058}
1059def: InstRW<[SBWriteResGroup108], (instregex "RCL(8|16|32|64)m",
1060                                             "RCR(8|16|32|64)m")>;
1061
1062def SBWriteResGroup111 : SchedWriteRes<[SBPort0,SBPort23]> {
1063  let Latency = 12;
1064  let NumMicroOps = 2;
1065  let ResourceCycles = [1,1];
1066}
1067def: InstRW<[SBWriteResGroup111], (instregex "MUL_F(32|64)m")>;
1068
1069def SBWriteResGroup114 : SchedWriteRes<[SBPort1,SBPort23]> {
1070  let Latency = 13;
1071  let NumMicroOps = 3;
1072  let ResourceCycles = [2,1];
1073}
1074def: InstRW<[SBWriteResGroup114], (instregex "(ADD|SUB|SUBR)_FI(16|32)m")>;
1075
1076def SBWriteResGroup119 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> {
1077  let Latency = 15;
1078  let NumMicroOps = 3;
1079  let ResourceCycles = [1,1,1];
1080}
1081def: InstRW<[SBWriteResGroup119], (instregex "MUL_FI(16|32)m")>;
1082
1083def SBWriteResGroup130 : SchedWriteRes<[SBPort0,SBPort23]> {
1084  let Latency = 31;
1085  let NumMicroOps = 2;
1086  let ResourceCycles = [1,1];
1087}
1088def: InstRW<[SBWriteResGroup130], (instregex "DIV(R?)_F(32|64)m")>;
1089
1090def SBWriteResGroup131 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> {
1091  let Latency = 34;
1092  let NumMicroOps = 3;
1093  let ResourceCycles = [1,1,1];
1094}
1095def: InstRW<[SBWriteResGroup131], (instregex "DIV(R?)_FI(16|32)m")>;
1096
1097def SBWriteResGroupVzeroall : SchedWriteRes<[SBPort5]> {
1098  let Latency = 9;
1099  let NumMicroOps = 20;
1100  let ResourceCycles = [2];
1101}
1102def: InstRW<[SBWriteResGroupVzeroall], (instrs VZEROALL)>;
1103
1104def SBWriteResGroupVzeroupper : SchedWriteRes<[]> {
1105  let Latency = 1;
1106  let NumMicroOps = 4;
1107  let ResourceCycles = [];
1108}
1109def: InstRW<[SBWriteResGroupVzeroupper], (instrs VZEROUPPER)>;
1110
1111def: InstRW<[WriteZero], (instrs CLC)>;
1112
1113// Instruction variants handled by the renamer. These might not need execution
1114// ports in certain conditions.
1115// See Agner's Fog "The microarchitecture of Intel, AMD and VIA CPUs",
1116// section "Sandy Bridge and Ivy Bridge Pipeline" > "Register allocation and
1117// renaming".
1118// These can be investigated with llvm-exegesis, e.g.
1119// echo 'pxor %mm0, %mm0' | /tmp/llvm-exegesis -mode=uops -snippets-file=-
1120// echo 'vxorpd %xmm0, %xmm0, %xmm1' | /tmp/llvm-exegesis -mode=uops -snippets-file=-
1121
1122def SBWriteZeroLatency : SchedWriteRes<[]> {
1123  let Latency = 0;
1124}
1125
1126def SBWriteZeroIdiom : SchedWriteVariant<[
1127    SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SBWriteZeroLatency]>,
1128    SchedVar<NoSchedPred,                          [WriteALU]>
1129]>;
1130def : InstRW<[SBWriteZeroIdiom], (instrs SUB32rr, SUB64rr,
1131                                         XOR32rr, XOR64rr)>;
1132
1133def SBWriteFZeroIdiom : SchedWriteVariant<[
1134    SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SBWriteZeroLatency]>,
1135    SchedVar<NoSchedPred,                          [WriteFLogic]>
1136]>;
1137def : InstRW<[SBWriteFZeroIdiom], (instrs XORPSrr, VXORPSrr, XORPDrr,
1138                                          VXORPDrr)>;
1139
1140def SBWriteFZeroIdiomY : SchedWriteVariant<[
1141    SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SBWriteZeroLatency]>,
1142    SchedVar<NoSchedPred,                          [WriteFLogicY]>
1143]>;
1144def : InstRW<[SBWriteFZeroIdiomY], (instrs VXORPSYrr, VXORPDYrr)>;
1145
1146def SBWriteVZeroIdiomLogicX : SchedWriteVariant<[
1147    SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SBWriteZeroLatency]>,
1148    SchedVar<NoSchedPred,                          [WriteVecLogicX]>
1149]>;
1150def : InstRW<[SBWriteVZeroIdiomLogicX], (instrs PXORrr, VPXORrr)>;
1151
1152def SBWriteVZeroIdiomALUX : SchedWriteVariant<[
1153    SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SBWriteZeroLatency]>,
1154    SchedVar<NoSchedPred,                          [WriteVecALUX]>
1155]>;
1156def : InstRW<[SBWriteVZeroIdiomALUX], (instrs PSUBBrr, VPSUBBrr,
1157                                              PSUBDrr, VPSUBDrr,
1158                                              PSUBQrr, VPSUBQrr,
1159                                              PSUBWrr, VPSUBWrr,
1160                                              PCMPGTBrr, VPCMPGTBrr,
1161                                              PCMPGTDrr, VPCMPGTDrr,
1162                                              PCMPGTWrr, VPCMPGTWrr)>;
1163
1164def SBWritePCMPGTQ : SchedWriteRes<[SBPort0]> {
1165  let Latency = 5;
1166  let NumMicroOps = 1;
1167  let ResourceCycles = [1];
1168}
1169
1170def SBWriteVZeroIdiomPCMPGTQ : SchedWriteVariant<[
1171    SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SBWriteZeroLatency]>,
1172    SchedVar<NoSchedPred,                          [SBWritePCMPGTQ]>
1173]>;
1174def : InstRW<[SBWriteVZeroIdiomPCMPGTQ], (instrs PCMPGTQrr, VPCMPGTQrr)>;
1175
1176// CMOVs that use both Z and C flag require an extra uop.
1177def SBWriteCMOVA_CMOVBErr : SchedWriteRes<[SBPort05,SBPort015]> {
1178  let Latency = 3;
1179  let ResourceCycles = [2,1];
1180  let NumMicroOps = 3;
1181}
1182
1183def SBWriteCMOVA_CMOVBErm : SchedWriteRes<[SBPort23,SBPort05,SBPort015]> {
1184  let Latency = 8;
1185  let ResourceCycles = [1,2,1];
1186  let NumMicroOps = 4;
1187}
1188
1189def SBCMOVA_CMOVBErr :  SchedWriteVariant<[
1190  SchedVar<MCSchedPredicate<IsCMOVArr_Or_CMOVBErr>, [SBWriteCMOVA_CMOVBErr]>,
1191  SchedVar<NoSchedPred,                             [WriteCMOV]>
1192]>;
1193
1194def SBCMOVA_CMOVBErm :  SchedWriteVariant<[
1195  SchedVar<MCSchedPredicate<IsCMOVArm_Or_CMOVBErm>, [SBWriteCMOVA_CMOVBErm]>,
1196  SchedVar<NoSchedPred,                             [WriteCMOV.Folded]>
1197]>;
1198
1199def : InstRW<[SBCMOVA_CMOVBErr], (instrs CMOV16rr, CMOV32rr, CMOV64rr)>;
1200def : InstRW<[SBCMOVA_CMOVBErm], (instrs CMOV16rm, CMOV32rm, CMOV64rm)>;
1201
1202// SETCCs that use both Z and C flag require an extra uop.
1203def SBWriteSETA_SETBEr : SchedWriteRes<[SBPort05]> {
1204  let Latency = 2;
1205  let ResourceCycles = [2];
1206  let NumMicroOps = 2;
1207}
1208
1209def SBWriteSETA_SETBEm : SchedWriteRes<[SBPort4,SBPort23,SBPort05]> {
1210  let Latency = 3;
1211  let ResourceCycles = [1,1,2];
1212  let NumMicroOps = 4;
1213}
1214
1215def SBSETA_SETBErr :  SchedWriteVariant<[
1216  SchedVar<MCSchedPredicate<IsSETAr_Or_SETBEr>, [SBWriteSETA_SETBEr]>,
1217  SchedVar<NoSchedPred,                         [WriteSETCC]>
1218]>;
1219
1220def SBSETA_SETBErm :  SchedWriteVariant<[
1221  SchedVar<MCSchedPredicate<IsSETAm_Or_SETBEm>, [SBWriteSETA_SETBEm]>,
1222  SchedVar<NoSchedPred,                         [WriteSETCCStore]>
1223]>;
1224
1225def : InstRW<[SBSETA_SETBErr], (instrs SETCCr)>;
1226def : InstRW<[SBSETA_SETBErm], (instrs SETCCm)>;
1227
1228} // SchedModel
1229