1//=- X86SchedSandyBridge.td - X86 Sandy Bridge Scheduling ----*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the machine model for Sandy Bridge to support instruction 10// scheduling and other instruction cost heuristics. 11// 12// Note that we define some instructions here that are not supported by SNB, 13// but we still have to define them because SNB is the default subtarget for 14// X86. These instructions are tagged with a comment `Unsupported = 1`. 15// 16//===----------------------------------------------------------------------===// 17 18def SandyBridgeModel : SchedMachineModel { 19 // All x86 instructions are modeled as a single micro-op, and SB can decode 4 20 // instructions per cycle. 21 // FIXME: Identify instructions that aren't a single fused micro-op. 22 let IssueWidth = 4; 23 let MicroOpBufferSize = 168; // Based on the reorder buffer. 24 let LoadLatency = 5; 25 let MispredictPenalty = 16; 26 27 // Based on the LSD (loop-stream detector) queue size. 28 let LoopMicroOpBufferSize = 28; 29 30 // This flag is set to allow the scheduler to assign 31 // a default model to unrecognized opcodes. 32 let CompleteModel = 0; 33} 34 35let SchedModel = SandyBridgeModel in { 36 37// Sandy Bridge can issue micro-ops to 6 different ports in one cycle. 38 39// Ports 0, 1, and 5 handle all computation. 40def SBPort0 : ProcResource<1>; 41def SBPort1 : ProcResource<1>; 42def SBPort5 : ProcResource<1>; 43 44// Ports 2 and 3 are identical. They handle loads and the address half of 45// stores. 46def SBPort23 : ProcResource<2>; 47 48// Port 4 gets the data half of stores. Store data can be available later than 49// the store address, but since we don't model the latency of stores, we can 50// ignore that. 51def SBPort4 : ProcResource<1>; 52 53// Many micro-ops are capable of issuing on multiple ports. 54def SBPort01 : ProcResGroup<[SBPort0, SBPort1]>; 55def SBPort05 : ProcResGroup<[SBPort0, SBPort5]>; 56def SBPort15 : ProcResGroup<[SBPort1, SBPort5]>; 57def SBPort015 : ProcResGroup<[SBPort0, SBPort1, SBPort5]>; 58 59// 54 Entry Unified Scheduler 60def SBPortAny : ProcResGroup<[SBPort0, SBPort1, SBPort23, SBPort4, SBPort5]> { 61 let BufferSize=54; 62} 63 64// Integer division issued on port 0. 65def SBDivider : ProcResource<1>; 66// FP division and sqrt on port 0. 67def SBFPDivider : ProcResource<1>; 68 69// Integer loads are 5 cycles, so ReadAfterLd registers needn't be available until 5 70// cycles after the memory operand. 71def : ReadAdvance<ReadAfterLd, 5>; 72 73// Vector loads are 5/6/7 cycles, so ReadAfterVec*Ld registers needn't be available 74// until 5/6/7 cycles after the memory operand. 75def : ReadAdvance<ReadAfterVecLd, 5>; 76def : ReadAdvance<ReadAfterVecXLd, 6>; 77def : ReadAdvance<ReadAfterVecYLd, 7>; 78 79def : ReadAdvance<ReadInt2Fpu, 0>; 80 81// Many SchedWrites are defined in pairs with and without a folded load. 82// Instructions with folded loads are usually micro-fused, so they only appear 83// as two micro-ops when queued in the reservation station. 84// This multiclass defines the resource usage for variants with and without 85// folded loads. 86multiclass SBWriteResPair<X86FoldableSchedWrite SchedRW, 87 list<ProcResourceKind> ExePorts, 88 int Lat, list<int> Res = [1], int UOps = 1, 89 int LoadLat = 5> { 90 // Register variant is using a single cycle on ExePort. 91 def : WriteRes<SchedRW, ExePorts> { 92 let Latency = Lat; 93 let ResourceCycles = Res; 94 let NumMicroOps = UOps; 95 } 96 97 // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to 98 // the latency (default = 5). 99 def : WriteRes<SchedRW.Folded, !listconcat([SBPort23], ExePorts)> { 100 let Latency = !add(Lat, LoadLat); 101 let ResourceCycles = !listconcat([1], Res); 102 let NumMicroOps = !add(UOps, 1); 103 } 104} 105 106// A folded store needs a cycle on port 4 for the store data, and an extra port 107// 2/3 cycle to recompute the address. 108def : WriteRes<WriteRMW, [SBPort23,SBPort4]>; 109 110def : WriteRes<WriteStore, [SBPort23, SBPort4]>; 111def : WriteRes<WriteStoreNT, [SBPort23, SBPort4]>; 112def : WriteRes<WriteLoad, [SBPort23]> { let Latency = 5; } 113def : WriteRes<WriteMove, [SBPort015]>; 114def : WriteRes<WriteZero, []>; 115 116// Arithmetic. 117defm : SBWriteResPair<WriteALU, [SBPort015], 1>; 118defm : SBWriteResPair<WriteADC, [SBPort05,SBPort015], 2, [1,1], 2>; 119 120defm : SBWriteResPair<WriteIMul8, [SBPort1], 3>; 121defm : SBWriteResPair<WriteIMul16, [SBPort1,SBPort05,SBPort015], 4, [1,1,2], 4>; 122defm : X86WriteRes<WriteIMul16Imm, [SBPort1,SBPort015], 4, [1,1], 2>; 123defm : X86WriteRes<WriteIMul16ImmLd, [SBPort1,SBPort015,SBPort23], 8, [1,1,1], 3>; 124defm : SBWriteResPair<WriteIMul16Reg, [SBPort1], 3>; 125defm : SBWriteResPair<WriteIMul32, [SBPort1,SBPort05,SBPort015], 4, [1,1,1], 3>; 126defm : SBWriteResPair<WriteIMul32Imm, [SBPort1], 3>; 127defm : SBWriteResPair<WriteIMul32Reg, [SBPort1], 3>; 128defm : SBWriteResPair<WriteIMul64, [SBPort1,SBPort0], 4, [1,1], 2>; 129defm : SBWriteResPair<WriteIMul64Imm, [SBPort1], 3>; 130defm : SBWriteResPair<WriteIMul64Reg, [SBPort1], 3>; 131def : WriteRes<WriteIMulH, []> { let Latency = 3; } 132 133defm : X86WriteRes<WriteXCHG, [SBPort015], 2, [3], 3>; 134defm : X86WriteRes<WriteBSWAP32, [SBPort1], 1, [1], 1>; 135defm : X86WriteRes<WriteBSWAP64, [SBPort1, SBPort05], 2, [1,1], 2>; 136defm : X86WriteRes<WriteCMPXCHG, [SBPort05, SBPort015], 5, [1,3], 4>; 137defm : X86WriteRes<WriteCMPXCHGRMW,[SBPort015, SBPort5, SBPort23, SBPort4], 8, [1, 2, 2, 1], 6>; 138 139defm : SBWriteResPair<WriteDiv8, [SBPort0, SBDivider], 25, [1, 10]>; 140defm : SBWriteResPair<WriteDiv16, [SBPort0, SBDivider], 25, [1, 10]>; 141defm : SBWriteResPair<WriteDiv32, [SBPort0, SBDivider], 25, [1, 10]>; 142defm : SBWriteResPair<WriteDiv64, [SBPort0, SBDivider], 25, [1, 10]>; 143defm : SBWriteResPair<WriteIDiv8, [SBPort0, SBDivider], 25, [1, 10]>; 144defm : SBWriteResPair<WriteIDiv16, [SBPort0, SBDivider], 25, [1, 10]>; 145defm : SBWriteResPair<WriteIDiv32, [SBPort0, SBDivider], 25, [1, 10]>; 146defm : SBWriteResPair<WriteIDiv64, [SBPort0, SBDivider], 25, [1, 10]>; 147 148// SHLD/SHRD. 149defm : X86WriteRes<WriteSHDrri, [SBPort05, SBPort015], 2, [1, 1], 2>; 150defm : X86WriteRes<WriteSHDrrcl,[SBPort05, SBPort015], 4, [3, 1], 4>; 151defm : X86WriteRes<WriteSHDmri, [SBPort4,SBPort23,SBPort05,SBPort015], 8, [1, 2, 1, 1], 5>; 152defm : X86WriteRes<WriteSHDmrcl,[SBPort4,SBPort23,SBPort05,SBPort015], 10, [1, 2, 3, 1], 7>; 153 154defm : SBWriteResPair<WriteShift, [SBPort05], 1>; 155defm : SBWriteResPair<WriteShiftCL, [SBPort05], 3, [3], 3>; 156defm : SBWriteResPair<WriteRotate, [SBPort05], 2, [2], 2>; 157defm : SBWriteResPair<WriteRotateCL, [SBPort05], 3, [3], 3>; 158 159defm : SBWriteResPair<WriteJump, [SBPort5], 1>; 160defm : SBWriteResPair<WriteCRC32, [SBPort1], 3, [1], 1, 5>; 161 162defm : SBWriteResPair<WriteCMOV, [SBPort05,SBPort015], 2, [1,1], 2>; // Conditional move. 163defm : X86WriteRes<WriteFCMOV, [SBPort5,SBPort05], 3, [2,1], 3>; // x87 conditional move. 164def : WriteRes<WriteSETCC, [SBPort05]>; // Setcc. 165def : WriteRes<WriteSETCCStore, [SBPort05,SBPort4,SBPort23]> { 166 let Latency = 2; 167 let NumMicroOps = 3; 168} 169 170defm : X86WriteRes<WriteLAHFSAHF, [SBPort05], 1, [1], 1>; 171defm : X86WriteRes<WriteBitTest, [SBPort05], 1, [1], 1>; 172defm : X86WriteRes<WriteBitTestImmLd, [SBPort05,SBPort23], 6, [1,1], 2>; 173//defm : X86WriteRes<WriteBitTestRegLd, [SBPort05,SBPort23], 6, [1,1], 2>; 174defm : X86WriteRes<WriteBitTestSet, [SBPort05], 1, [1], 1>; 175defm : X86WriteRes<WriteBitTestSetImmLd, [SBPort05,SBPort23], 6, [1,1], 3>; 176defm : X86WriteRes<WriteBitTestSetRegLd, [SBPort05,SBPort23,SBPort5,SBPort015], 8, [1,1,1,1], 5>; 177 178// This is for simple LEAs with one or two input operands. 179// The complex ones can only execute on port 1, and they require two cycles on 180// the port to read all inputs. We don't model that. 181def : WriteRes<WriteLEA, [SBPort01]>; 182 183// Bit counts. 184defm : SBWriteResPair<WriteBSF, [SBPort1], 3, [1], 1, 5>; 185defm : SBWriteResPair<WriteBSR, [SBPort1], 3, [1], 1, 5>; 186defm : SBWriteResPair<WriteLZCNT, [SBPort1], 3, [1], 1, 5>; 187defm : SBWriteResPair<WriteTZCNT, [SBPort1], 3, [1], 1, 5>; 188defm : SBWriteResPair<WritePOPCNT, [SBPort1], 3, [1], 1, 6>; 189 190// BMI1 BEXTR/BLS, BMI2 BZHI 191// NOTE: These don't exist on Sandy Bridge. Ports are guesses. 192defm : SBWriteResPair<WriteBEXTR, [SBPort05,SBPort1], 2, [1,1], 2>; 193defm : SBWriteResPair<WriteBLS, [SBPort015], 1>; 194defm : SBWriteResPair<WriteBZHI, [SBPort1], 1>; 195 196// Scalar and vector floating point. 197defm : X86WriteRes<WriteFLD0, [SBPort5], 1, [1], 1>; 198defm : X86WriteRes<WriteFLD1, [SBPort0,SBPort5], 1, [1,1], 2>; 199defm : X86WriteRes<WriteFLDC, [SBPort0,SBPort1], 1, [1,1], 2>; 200defm : X86WriteRes<WriteFLoad, [SBPort23], 5, [1], 1>; 201defm : X86WriteRes<WriteFLoadX, [SBPort23], 6, [1], 1>; 202defm : X86WriteRes<WriteFLoadY, [SBPort23], 7, [1], 1>; 203defm : X86WriteRes<WriteFMaskedLoad, [SBPort23,SBPort05], 8, [1,2], 3>; 204defm : X86WriteRes<WriteFMaskedLoadY, [SBPort23,SBPort05], 9, [1,2], 3>; 205defm : X86WriteRes<WriteFStore, [SBPort23,SBPort4], 1, [1,1], 1>; 206defm : X86WriteRes<WriteFStoreX, [SBPort23,SBPort4], 1, [1,1], 1>; 207defm : X86WriteRes<WriteFStoreY, [SBPort23,SBPort4], 1, [1,1], 1>; 208defm : X86WriteRes<WriteFStoreNT, [SBPort23,SBPort4], 1, [1,1], 1>; 209defm : X86WriteRes<WriteFStoreNTX, [SBPort23,SBPort4], 1, [1,1], 1>; 210defm : X86WriteRes<WriteFStoreNTY, [SBPort23,SBPort4], 1, [1,1], 1>; 211 212defm : X86WriteRes<WriteFMaskedStore32, [SBPort4,SBPort01,SBPort23], 5, [1,1,1], 3>; 213defm : X86WriteRes<WriteFMaskedStore32Y, [SBPort4,SBPort01,SBPort23], 5, [1,1,1], 3>; 214defm : X86WriteRes<WriteFMaskedStore64, [SBPort4,SBPort01,SBPort23], 5, [1,1,1], 3>; 215defm : X86WriteRes<WriteFMaskedStore64Y, [SBPort4,SBPort01,SBPort23], 5, [1,1,1], 3>; 216 217defm : X86WriteRes<WriteFMove, [SBPort5], 1, [1], 1>; 218defm : X86WriteRes<WriteFMoveX, [SBPort5], 1, [1], 1>; 219defm : X86WriteRes<WriteFMoveY, [SBPort5], 1, [1], 1>; 220defm : X86WriteRes<WriteEMMS, [SBPort015], 31, [31], 31>; 221 222defm : SBWriteResPair<WriteFAdd, [SBPort1], 3, [1], 1, 6>; 223defm : SBWriteResPair<WriteFAddX, [SBPort1], 3, [1], 1, 6>; 224defm : SBWriteResPair<WriteFAddY, [SBPort1], 3, [1], 1, 7>; 225defm : SBWriteResPair<WriteFAddZ, [SBPort1], 3, [1], 1, 7>; // Unsupported = 1 226defm : SBWriteResPair<WriteFAdd64, [SBPort1], 3, [1], 1, 6>; 227defm : SBWriteResPair<WriteFAdd64X, [SBPort1], 3, [1], 1, 6>; 228defm : SBWriteResPair<WriteFAdd64Y, [SBPort1], 3, [1], 1, 7>; 229defm : SBWriteResPair<WriteFAdd64Z, [SBPort1], 3, [1], 1, 7>; // Unsupported = 1 230 231defm : SBWriteResPair<WriteFCmp, [SBPort1], 3, [1], 1, 6>; 232defm : SBWriteResPair<WriteFCmpX, [SBPort1], 3, [1], 1, 6>; 233defm : SBWriteResPair<WriteFCmpY, [SBPort1], 3, [1], 1, 7>; 234defm : SBWriteResPair<WriteFCmpZ, [SBPort1], 3, [1], 1, 7>; // Unsupported = 1 235defm : SBWriteResPair<WriteFCmp64, [SBPort1], 3, [1], 1, 6>; 236defm : SBWriteResPair<WriteFCmp64X, [SBPort1], 3, [1], 1, 6>; 237defm : SBWriteResPair<WriteFCmp64Y, [SBPort1], 3, [1], 1, 7>; 238defm : SBWriteResPair<WriteFCmp64Z, [SBPort1], 3, [1], 1, 7>; // Unsupported = 1 239 240defm : SBWriteResPair<WriteFCom, [SBPort1], 3>; 241 242defm : SBWriteResPair<WriteFMul, [SBPort0], 5, [1], 1, 6>; 243defm : SBWriteResPair<WriteFMulX, [SBPort0], 5, [1], 1, 6>; 244defm : SBWriteResPair<WriteFMulY, [SBPort0], 5, [1], 1, 7>; 245defm : SBWriteResPair<WriteFMulZ, [SBPort0], 5, [1], 1, 7>; // Unsupported = 1 246defm : SBWriteResPair<WriteFMul64, [SBPort0], 5, [1], 1, 6>; 247defm : SBWriteResPair<WriteFMul64X, [SBPort0], 5, [1], 1, 6>; 248defm : SBWriteResPair<WriteFMul64Y, [SBPort0], 5, [1], 1, 7>; 249defm : SBWriteResPair<WriteFMul64Z, [SBPort0], 5, [1], 1, 7>; // Unsupported = 1 250 251defm : SBWriteResPair<WriteFDiv, [SBPort0,SBFPDivider], 14, [1,14], 1, 6>; 252defm : SBWriteResPair<WriteFDivX, [SBPort0,SBFPDivider], 14, [1,14], 1, 6>; 253defm : SBWriteResPair<WriteFDivY, [SBPort0,SBPort05,SBFPDivider], 29, [2,1,28], 3, 7>; 254defm : SBWriteResPair<WriteFDivZ, [SBPort0,SBPort05,SBFPDivider], 29, [2,1,28], 3, 7>; // Unsupported = 1 255defm : SBWriteResPair<WriteFDiv64, [SBPort0,SBFPDivider], 22, [1,22], 1, 6>; 256defm : SBWriteResPair<WriteFDiv64X, [SBPort0,SBFPDivider], 22, [1,22], 1, 6>; 257defm : SBWriteResPair<WriteFDiv64Y, [SBPort0,SBPort05,SBFPDivider], 45, [2,1,44], 3, 7>; 258defm : SBWriteResPair<WriteFDiv64Z, [SBPort0,SBPort05,SBFPDivider], 45, [2,1,44], 3, 7>; // Unsupported = 1 259 260defm : SBWriteResPair<WriteFRcp, [SBPort0], 5, [1], 1, 6>; 261defm : SBWriteResPair<WriteFRcpX, [SBPort0], 5, [1], 1, 6>; 262defm : SBWriteResPair<WriteFRcpY, [SBPort0,SBPort05], 7, [2,1], 3, 7>; 263defm : SBWriteResPair<WriteFRcpZ, [SBPort0,SBPort05], 7, [2,1], 3, 7>; // Unsupported = 1 264 265defm : SBWriteResPair<WriteFRsqrt, [SBPort0], 5, [1], 1, 6>; 266defm : SBWriteResPair<WriteFRsqrtX,[SBPort0], 5, [1], 1, 6>; 267defm : SBWriteResPair<WriteFRsqrtY,[SBPort0,SBPort05], 7, [2,1], 3, 7>; 268defm : SBWriteResPair<WriteFRsqrtZ,[SBPort0,SBPort05], 7, [2,1], 3, 7>; // Unsupported = 1 269 270defm : SBWriteResPair<WriteFSqrt, [SBPort0,SBFPDivider], 14, [1,14], 1, 6>; 271defm : SBWriteResPair<WriteFSqrtX, [SBPort0,SBFPDivider], 14, [1,14], 1, 6>; 272defm : SBWriteResPair<WriteFSqrtY, [SBPort0,SBPort05,SBFPDivider], 29, [2,1,28], 3, 7>; 273defm : SBWriteResPair<WriteFSqrtZ, [SBPort0,SBPort05,SBFPDivider], 29, [2,1,28], 3, 7>; // Unsupported = 1 274defm : SBWriteResPair<WriteFSqrt64, [SBPort0,SBFPDivider], 21, [1,21], 1, 6>; 275defm : SBWriteResPair<WriteFSqrt64X, [SBPort0,SBFPDivider], 21, [1,21], 1, 6>; 276defm : SBWriteResPair<WriteFSqrt64Y, [SBPort0,SBPort05,SBFPDivider], 45, [2,1,44], 3, 7>; 277defm : SBWriteResPair<WriteFSqrt64Z, [SBPort0,SBPort05,SBFPDivider], 45, [2,1,44], 3, 7>; // Unsupported = 1 278defm : SBWriteResPair<WriteFSqrt80, [SBPort0,SBFPDivider], 24, [1,24], 1, 6>; 279 280defm : SBWriteResPair<WriteDPPD, [SBPort0,SBPort1,SBPort5], 9, [1,1,1], 3, 6>; 281defm : SBWriteResPair<WriteDPPS, [SBPort0,SBPort1,SBPort5], 12, [1,2,1], 4, 6>; 282defm : SBWriteResPair<WriteDPPSY, [SBPort0,SBPort1,SBPort5], 12, [1,2,1], 4, 7>; 283defm : SBWriteResPair<WriteDPPSZ, [SBPort0,SBPort1,SBPort5], 12, [1,2,1], 4, 7>; // Unsupported = 1 284defm : SBWriteResPair<WriteFSign, [SBPort5], 1>; 285defm : SBWriteResPair<WriteFRnd, [SBPort1], 3, [1], 1, 6>; 286defm : SBWriteResPair<WriteFRndY, [SBPort1], 3, [1], 1, 7>; 287defm : SBWriteResPair<WriteFRndZ, [SBPort1], 3, [1], 1, 7>; // Unsupported = 1 288defm : SBWriteResPair<WriteFLogic, [SBPort5], 1, [1], 1, 6>; 289defm : SBWriteResPair<WriteFLogicY, [SBPort5], 1, [1], 1, 7>; 290defm : SBWriteResPair<WriteFLogicZ, [SBPort5], 1, [1], 1, 7>; // Unsupported = 1 291defm : SBWriteResPair<WriteFTest, [SBPort0], 1, [1], 1, 6>; 292defm : SBWriteResPair<WriteFTestY, [SBPort0], 1, [1], 1, 7>; 293defm : SBWriteResPair<WriteFTestZ, [SBPort0], 1, [1], 1, 7>; // Unsupported = 1 294defm : SBWriteResPair<WriteFShuffle, [SBPort5], 1, [1], 1, 6>; 295defm : SBWriteResPair<WriteFShuffleY,[SBPort5], 1, [1], 1, 7>; 296defm : SBWriteResPair<WriteFShuffleZ,[SBPort5], 1, [1], 1, 7>; // Unsupported = 1 297defm : SBWriteResPair<WriteFVarShuffle, [SBPort5], 1, [1], 1, 6>; 298defm : SBWriteResPair<WriteFVarShuffleY,[SBPort5], 1, [1], 1, 7>; 299defm : SBWriteResPair<WriteFVarShuffleZ,[SBPort5], 1, [1], 1, 7>; // Unsupported = 1 300defm : SBWriteResPair<WriteFBlend, [SBPort05], 1, [1], 1, 6>; 301defm : SBWriteResPair<WriteFBlendY, [SBPort05], 1, [1], 1, 7>; 302defm : SBWriteResPair<WriteFBlendZ, [SBPort05], 1, [1], 1, 7>; // Unsupported = 1 303defm : SBWriteResPair<WriteFVarBlend, [SBPort05], 2, [2], 2, 6>; 304defm : SBWriteResPair<WriteFVarBlendY,[SBPort05], 2, [2], 2, 7>; 305defm : SBWriteResPair<WriteFVarBlendZ,[SBPort05], 2, [2], 2, 7>; // Unsupported = 1 306 307// Conversion between integer and float. 308defm : SBWriteResPair<WriteCvtSS2I, [SBPort0,SBPort1], 5, [1,1], 2>; 309defm : SBWriteResPair<WriteCvtPS2I, [SBPort1], 3, [1], 1, 6>; 310defm : SBWriteResPair<WriteCvtPS2IY, [SBPort1], 3, [1], 1, 7>; 311defm : SBWriteResPair<WriteCvtPS2IZ, [SBPort1], 3, [1], 1, 7>; // Unsupported = 1 312defm : SBWriteResPair<WriteCvtSD2I, [SBPort0,SBPort1], 5, [1,1], 2>; 313defm : SBWriteResPair<WriteCvtPD2I, [SBPort1,SBPort5], 4, [1,1], 2, 6>; 314defm : X86WriteRes<WriteCvtPD2IY, [SBPort1,SBPort5], 4, [1,1], 2>; 315defm : X86WriteRes<WriteCvtPD2IZ, [SBPort1,SBPort5], 4, [1,1], 2>; // Unsupported = 1 316defm : X86WriteRes<WriteCvtPD2IYLd, [SBPort1,SBPort5,SBPort23], 11, [1,1,1], 3>; 317defm : X86WriteRes<WriteCvtPD2IZLd, [SBPort1,SBPort5,SBPort23], 11, [1,1,1], 3>; // Unsupported = 1 318 319defm : X86WriteRes<WriteCvtI2SS, [SBPort1,SBPort5], 5, [1,2], 3>; 320defm : X86WriteRes<WriteCvtI2SSLd, [SBPort1,SBPort5,SBPort23], 10, [1,1,1], 3>; 321defm : SBWriteResPair<WriteCvtI2PS, [SBPort1], 3, [1], 1, 6>; 322defm : SBWriteResPair<WriteCvtI2PSY, [SBPort1], 3, [1], 1, 7>; 323defm : SBWriteResPair<WriteCvtI2PSZ, [SBPort1], 3, [1], 1, 7>; // Unsupported = 1 324defm : X86WriteRes<WriteCvtI2SD, [SBPort1,SBPort5], 4, [1,1], 2>; 325defm : X86WriteRes<WriteCvtI2PD, [SBPort1,SBPort5], 4, [1,1], 2>; 326defm : X86WriteRes<WriteCvtI2PDY, [SBPort1,SBPort5], 4, [1,1], 2>; 327defm : X86WriteRes<WriteCvtI2PDZ, [SBPort1,SBPort5], 4, [1,1], 2>; // Unsupported = 1 328defm : X86WriteRes<WriteCvtI2SDLd, [SBPort1,SBPort23], 9, [1,1], 2>; 329defm : X86WriteRes<WriteCvtI2PDLd, [SBPort1,SBPort5,SBPort23], 10, [1,1,1], 3>; 330defm : X86WriteRes<WriteCvtI2PDYLd, [SBPort1,SBPort5,SBPort23], 10, [1,1,1], 3>; 331defm : X86WriteRes<WriteCvtI2PDZLd, [SBPort1,SBPort5,SBPort23], 10, [1,1,1], 3>; // Unsupported = 1 332 333defm : SBWriteResPair<WriteCvtSS2SD, [SBPort0], 1, [1], 1, 6>; 334defm : X86WriteRes<WriteCvtPS2PD, [SBPort0,SBPort5], 2, [1,1], 2>; 335defm : X86WriteRes<WriteCvtPS2PDY, [SBPort0,SBPort5], 2, [1,1], 2>; 336defm : X86WriteRes<WriteCvtPS2PDZ, [SBPort0,SBPort5], 2, [1,1], 2>; // Unsupported = 1 337defm : X86WriteRes<WriteCvtPS2PDLd, [SBPort0,SBPort23], 7, [1,1], 2>; 338defm : X86WriteRes<WriteCvtPS2PDYLd, [SBPort0,SBPort23], 7, [1,1], 2>; 339defm : X86WriteRes<WriteCvtPS2PDZLd, [SBPort0,SBPort23], 7, [1,1], 2>; // Unsupported = 1 340defm : SBWriteResPair<WriteCvtSD2SS, [SBPort1,SBPort5], 4, [1,1], 2, 6>; 341defm : SBWriteResPair<WriteCvtPD2PS, [SBPort1,SBPort5], 4, [1,1], 2, 6>; 342defm : SBWriteResPair<WriteCvtPD2PSY, [SBPort1,SBPort5], 4, [1,1], 2, 7>; 343defm : SBWriteResPair<WriteCvtPD2PSZ, [SBPort1,SBPort5], 4, [1,1], 2, 7>; // Unsupported = 1 344 345defm : SBWriteResPair<WriteCvtPH2PS, [SBPort1], 3>; 346defm : SBWriteResPair<WriteCvtPH2PSY, [SBPort1], 3>; 347defm : SBWriteResPair<WriteCvtPH2PSZ, [SBPort1], 3>; // Unsupported = 1 348 349defm : X86WriteRes<WriteCvtPS2PH, [SBPort1], 3, [1], 1>; 350defm : X86WriteRes<WriteCvtPS2PHY, [SBPort1], 3, [1], 1>; 351defm : X86WriteRes<WriteCvtPS2PHZ, [SBPort1], 3, [1], 1>; // Unsupported = 1 352defm : X86WriteRes<WriteCvtPS2PHSt, [SBPort1, SBPort23, SBPort4], 4, [1,1,1], 1>; 353defm : X86WriteRes<WriteCvtPS2PHYSt, [SBPort1, SBPort23, SBPort4], 4, [1,1,1], 1>; 354defm : X86WriteRes<WriteCvtPS2PHZSt, [SBPort1, SBPort23, SBPort4], 4, [1,1,1], 1>; // Unsupported = 1 355 356// Vector integer operations. 357defm : X86WriteRes<WriteVecLoad, [SBPort23], 5, [1], 1>; 358defm : X86WriteRes<WriteVecLoadX, [SBPort23], 6, [1], 1>; 359defm : X86WriteRes<WriteVecLoadY, [SBPort23], 7, [1], 1>; 360defm : X86WriteRes<WriteVecLoadNT, [SBPort23], 6, [1], 1>; 361defm : X86WriteRes<WriteVecLoadNTY, [SBPort23], 7, [1], 1>; 362defm : X86WriteRes<WriteVecMaskedLoad, [SBPort23,SBPort05], 8, [1,2], 3>; 363defm : X86WriteRes<WriteVecMaskedLoadY, [SBPort23,SBPort05], 9, [1,2], 3>; 364defm : X86WriteRes<WriteVecStore, [SBPort23,SBPort4], 1, [1,1], 1>; 365defm : X86WriteRes<WriteVecStoreX, [SBPort23,SBPort4], 1, [1,1], 1>; 366defm : X86WriteRes<WriteVecStoreY, [SBPort23,SBPort4], 1, [1,1], 1>; 367defm : X86WriteRes<WriteVecStoreNT, [SBPort23,SBPort4], 1, [1,1], 1>; 368defm : X86WriteRes<WriteVecStoreNTY, [SBPort23,SBPort4], 1, [1,1], 1>; 369defm : X86WriteRes<WriteVecMaskedStore, [SBPort4,SBPort01,SBPort23], 5, [1,1,1], 3>; 370defm : X86WriteRes<WriteVecMaskedStoreY, [SBPort4,SBPort01,SBPort23], 5, [1,1,1], 3>; 371defm : X86WriteRes<WriteVecMove, [SBPort05], 1, [1], 1>; 372defm : X86WriteRes<WriteVecMoveX, [SBPort015], 1, [1], 1>; 373defm : X86WriteRes<WriteVecMoveY, [SBPort05], 1, [1], 1>; 374defm : X86WriteRes<WriteVecMoveToGpr, [SBPort0], 2, [1], 1>; 375defm : X86WriteRes<WriteVecMoveFromGpr, [SBPort5], 1, [1], 1>; 376 377defm : SBWriteResPair<WriteVecLogic, [SBPort015], 1, [1], 1, 5>; 378defm : SBWriteResPair<WriteVecLogicX,[SBPort015], 1, [1], 1, 6>; 379defm : SBWriteResPair<WriteVecLogicY,[SBPort015], 1, [1], 1, 7>; 380defm : SBWriteResPair<WriteVecLogicZ,[SBPort015], 1, [1], 1, 7>; // Unsupported = 1 381defm : SBWriteResPair<WriteVecTest, [SBPort0,SBPort5], 2, [1,1], 2, 6>; 382defm : SBWriteResPair<WriteVecTestY, [SBPort0,SBPort5], 2, [1,1], 2, 7>; 383defm : SBWriteResPair<WriteVecTestZ, [SBPort0,SBPort5], 2, [1,1], 2, 7>; // Unsupported = 1 384defm : SBWriteResPair<WriteVecALU, [SBPort1], 3, [1], 1, 5>; 385defm : SBWriteResPair<WriteVecALUX, [SBPort15], 1, [1], 1, 6>; 386defm : SBWriteResPair<WriteVecALUY, [SBPort15], 1, [1], 1, 7>; 387defm : SBWriteResPair<WriteVecALUZ, [SBPort15], 1, [1], 1, 7>; // Unsupported = 1 388defm : SBWriteResPair<WriteVecIMul, [SBPort0], 5, [1], 1, 5>; 389defm : SBWriteResPair<WriteVecIMulX, [SBPort0], 5, [1], 1, 6>; 390defm : SBWriteResPair<WriteVecIMulY, [SBPort0], 5, [1], 1, 7>; 391defm : SBWriteResPair<WriteVecIMulZ, [SBPort0], 5, [1], 1, 7>; // Unsupported = 1 392defm : SBWriteResPair<WritePMULLD, [SBPort0], 5, [1], 1, 6>; 393defm : SBWriteResPair<WritePMULLDY, [SBPort0], 5, [1], 1, 7>; // TODO this is probably wrong for 256/512-bit for the "generic" model 394defm : SBWriteResPair<WritePMULLDZ, [SBPort0], 5, [1], 1, 7>; // Unsupported = 1 395defm : SBWriteResPair<WriteShuffle, [SBPort5], 1, [1], 1, 5>; 396defm : SBWriteResPair<WriteShuffleX, [SBPort15], 1, [1], 1, 6>; 397defm : SBWriteResPair<WriteShuffleY, [SBPort5], 1, [1], 1, 7>; 398defm : SBWriteResPair<WriteShuffleZ, [SBPort5], 1, [1], 1, 7>; // Unsupported = 1 399defm : SBWriteResPair<WriteVarShuffle, [SBPort15], 1, [1], 1, 5>; 400defm : SBWriteResPair<WriteVarShuffleX, [SBPort15], 1, [1], 1, 6>; 401defm : SBWriteResPair<WriteVarShuffleY, [SBPort15], 1, [1], 1, 7>; 402defm : SBWriteResPair<WriteVarShuffleZ, [SBPort15], 1, [1], 1, 7>; // Unsupported = 1 403defm : SBWriteResPair<WriteBlend, [SBPort15], 1, [1], 1, 6>; 404defm : SBWriteResPair<WriteBlendY, [SBPort15], 1, [1], 1, 7>; 405defm : SBWriteResPair<WriteBlendZ, [SBPort15], 1, [1], 1, 7>; // Unsupported = 1 406defm : SBWriteResPair<WriteVarBlend, [SBPort15], 2, [2], 2, 6>; 407defm : SBWriteResPair<WriteVarBlendY,[SBPort15], 2, [2], 2, 7>; 408defm : SBWriteResPair<WriteVarBlendZ,[SBPort15], 2, [2], 2, 7>; // Unsupported = 1 409defm : SBWriteResPair<WriteMPSAD, [SBPort0, SBPort15], 7, [1,2], 3, 6>; 410defm : SBWriteResPair<WriteMPSADY, [SBPort0, SBPort15], 7, [1,2], 3, 7>; 411defm : SBWriteResPair<WriteMPSADZ, [SBPort0, SBPort15], 7, [1,2], 3, 7>; // Unsupported = 1 412defm : SBWriteResPair<WritePSADBW, [SBPort0], 5, [1], 1, 5>; 413defm : SBWriteResPair<WritePSADBWX, [SBPort0], 5, [1], 1, 6>; 414defm : SBWriteResPair<WritePSADBWY, [SBPort0], 5, [1], 1, 7>; 415defm : SBWriteResPair<WritePSADBWZ, [SBPort0], 5, [1], 1, 7>; // Unsupported = 1 416defm : SBWriteResPair<WritePHMINPOS, [SBPort0], 5, [1], 1, 6>; 417 418// Vector integer shifts. 419defm : SBWriteResPair<WriteVecShift, [SBPort5], 1, [1], 1, 5>; 420defm : SBWriteResPair<WriteVecShiftX, [SBPort0,SBPort15], 2, [1,1], 2, 6>; 421defm : SBWriteResPair<WriteVecShiftY, [SBPort0,SBPort15], 4, [1,1], 2, 7>; 422defm : SBWriteResPair<WriteVecShiftZ, [SBPort0,SBPort15], 4, [1,1], 2, 7>; // Unsupported = 1 423defm : SBWriteResPair<WriteVecShiftImm, [SBPort5], 1, [1], 1, 5>; 424defm : SBWriteResPair<WriteVecShiftImmX, [SBPort0], 1, [1], 1, 6>; 425defm : SBWriteResPair<WriteVecShiftImmY, [SBPort0], 1, [1], 1, 7>; 426defm : SBWriteResPair<WriteVecShiftImmZ, [SBPort0], 1, [1], 1, 7>; // Unsupported = 1 427defm : SBWriteResPair<WriteVarVecShift, [SBPort0], 1, [1], 1, 6>; 428defm : SBWriteResPair<WriteVarVecShiftY, [SBPort0], 1, [1], 1, 7>; 429defm : SBWriteResPair<WriteVarVecShiftZ, [SBPort0], 1, [1], 1, 7>; // Unsupported = 1 430 431// Vector insert/extract operations. 432def : WriteRes<WriteVecInsert, [SBPort5,SBPort15]> { 433 let Latency = 2; 434 let NumMicroOps = 2; 435} 436def : WriteRes<WriteVecInsertLd, [SBPort23,SBPort15]> { 437 let Latency = 7; 438 let NumMicroOps = 2; 439} 440 441def : WriteRes<WriteVecExtract, [SBPort0,SBPort15]> { 442 let Latency = 3; 443 let NumMicroOps = 2; 444} 445def : WriteRes<WriteVecExtractSt, [SBPort4,SBPort23,SBPort15]> { 446 let Latency = 5; 447 let NumMicroOps = 3; 448} 449 450//////////////////////////////////////////////////////////////////////////////// 451// Horizontal add/sub instructions. 452//////////////////////////////////////////////////////////////////////////////// 453 454defm : SBWriteResPair<WriteFHAdd, [SBPort1,SBPort5], 5, [1,2], 3, 6>; 455defm : SBWriteResPair<WriteFHAddY, [SBPort1,SBPort5], 5, [1,2], 3, 7>; 456defm : SBWriteResPair<WriteFHAddZ, [SBPort1,SBPort5], 5, [1,2], 3, 7>; // Unsupported = 1 457defm : SBWriteResPair<WritePHAdd, [SBPort15], 3, [3], 3, 5>; 458defm : SBWriteResPair<WritePHAddX, [SBPort15], 3, [3], 3, 6>; 459defm : SBWriteResPair<WritePHAddY, [SBPort15], 3, [3], 3, 7>; 460defm : SBWriteResPair<WritePHAddZ, [SBPort15], 3, [3], 3, 7>; // Unsupported = 1 461 462//////////////////////////////////////////////////////////////////////////////// 463// String instructions. 464//////////////////////////////////////////////////////////////////////////////// 465 466// Packed Compare Implicit Length Strings, Return Mask 467def : WriteRes<WritePCmpIStrM, [SBPort0]> { 468 let Latency = 11; 469 let NumMicroOps = 3; 470 let ResourceCycles = [3]; 471} 472def : WriteRes<WritePCmpIStrMLd, [SBPort0, SBPort23]> { 473 let Latency = 17; 474 let NumMicroOps = 4; 475 let ResourceCycles = [3,1]; 476} 477 478// Packed Compare Explicit Length Strings, Return Mask 479def : WriteRes<WritePCmpEStrM, [SBPort015]> { 480 let Latency = 11; 481 let ResourceCycles = [8]; 482} 483def : WriteRes<WritePCmpEStrMLd, [SBPort015, SBPort23]> { 484 let Latency = 11; 485 let ResourceCycles = [7, 1]; 486} 487 488// Packed Compare Implicit Length Strings, Return Index 489def : WriteRes<WritePCmpIStrI, [SBPort0]> { 490 let Latency = 11; 491 let NumMicroOps = 3; 492 let ResourceCycles = [3]; 493} 494def : WriteRes<WritePCmpIStrILd, [SBPort0,SBPort23]> { 495 let Latency = 17; 496 let NumMicroOps = 4; 497 let ResourceCycles = [3,1]; 498} 499 500// Packed Compare Explicit Length Strings, Return Index 501def : WriteRes<WritePCmpEStrI, [SBPort015]> { 502 let Latency = 4; 503 let ResourceCycles = [8]; 504} 505def : WriteRes<WritePCmpEStrILd, [SBPort015, SBPort23]> { 506 let Latency = 4; 507 let ResourceCycles = [7, 1]; 508} 509 510// MOVMSK Instructions. 511def : WriteRes<WriteFMOVMSK, [SBPort0]> { let Latency = 2; } 512def : WriteRes<WriteVecMOVMSK, [SBPort0]> { let Latency = 2; } 513def : WriteRes<WriteVecMOVMSKY, [SBPort0]> { let Latency = 2; } 514def : WriteRes<WriteMMXMOVMSK, [SBPort0]> { let Latency = 1; } 515 516// AES Instructions. 517def : WriteRes<WriteAESDecEnc, [SBPort5,SBPort015]> { 518 let Latency = 7; 519 let NumMicroOps = 2; 520 let ResourceCycles = [1,1]; 521} 522def : WriteRes<WriteAESDecEncLd, [SBPort5,SBPort23,SBPort015]> { 523 let Latency = 13; 524 let NumMicroOps = 3; 525 let ResourceCycles = [1,1,1]; 526} 527 528def : WriteRes<WriteAESIMC, [SBPort5]> { 529 let Latency = 12; 530 let NumMicroOps = 2; 531 let ResourceCycles = [2]; 532} 533def : WriteRes<WriteAESIMCLd, [SBPort5,SBPort23]> { 534 let Latency = 18; 535 let NumMicroOps = 3; 536 let ResourceCycles = [2,1]; 537} 538 539def : WriteRes<WriteAESKeyGen, [SBPort015]> { 540 let Latency = 8; 541 let ResourceCycles = [11]; 542} 543def : WriteRes<WriteAESKeyGenLd, [SBPort015, SBPort23]> { 544 let Latency = 8; 545 let ResourceCycles = [10, 1]; 546} 547 548// Carry-less multiplication instructions. 549def : WriteRes<WriteCLMul, [SBPort015]> { 550 let Latency = 14; 551 let ResourceCycles = [18]; 552} 553def : WriteRes<WriteCLMulLd, [SBPort015, SBPort23]> { 554 let Latency = 14; 555 let ResourceCycles = [17, 1]; 556} 557 558// Load/store MXCSR. 559// FIXME: This is probably wrong. Only STMXCSR should require Port4. 560def : WriteRes<WriteLDMXCSR, [SBPort0,SBPort4,SBPort5,SBPort23]> { let Latency = 5; let NumMicroOps = 4; let ResourceCycles = [1,1,1,1]; } 561def : WriteRes<WriteSTMXCSR, [SBPort0,SBPort4,SBPort5,SBPort23]> { let Latency = 5; let NumMicroOps = 4; let ResourceCycles = [1,1,1,1]; } 562 563def : WriteRes<WriteSystem, [SBPort015]> { let Latency = 100; } 564def : WriteRes<WriteMicrocoded, [SBPort015]> { let Latency = 100; } 565def : WriteRes<WriteFence, [SBPort23, SBPort4]>; 566def : WriteRes<WriteNop, []>; 567 568// AVX2/FMA is not supported on that architecture, but we should define the basic 569// scheduling resources anyway. 570defm : SBWriteResPair<WriteFShuffle256, [SBPort5], 1, [1], 1, 7>; 571defm : SBWriteResPair<WriteFVarShuffle256, [SBPort5], 1, [1], 1, 7>; 572defm : SBWriteResPair<WriteShuffle256, [SBPort5], 1, [1], 1, 7>; 573defm : SBWriteResPair<WriteVarShuffle256, [SBPort5], 1, [1], 1, 7>; 574defm : SBWriteResPair<WriteFMA, [SBPort01], 5>; 575defm : SBWriteResPair<WriteFMAX, [SBPort01], 5>; 576defm : SBWriteResPair<WriteFMAY, [SBPort01], 5>; 577defm : SBWriteResPair<WriteFMAZ, [SBPort01], 5>; // Unsupported = 1 578 579// Remaining SNB instrs. 580 581def SBWriteResGroup1 : SchedWriteRes<[SBPort1]> { 582 let Latency = 1; 583 let NumMicroOps = 1; 584 let ResourceCycles = [1]; 585} 586def: InstRW<[SBWriteResGroup1], (instrs COMP_FST0r, 587 COM_FST0r, 588 UCOM_FPr, 589 UCOM_Fr)>; 590 591def SBWriteResGroup2 : SchedWriteRes<[SBPort5]> { 592 let Latency = 1; 593 let NumMicroOps = 1; 594 let ResourceCycles = [1]; 595} 596def: InstRW<[SBWriteResGroup2], (instrs FDECSTP, FINCSTP, FFREE, FFREEP, FNOP, 597 LD_Frr, ST_Frr, ST_FPrr)>; 598def: InstRW<[SBWriteResGroup2], (instrs LOOP, LOOPE, LOOPNE)>; // FIXME: This seems wrong compared to other Intel CPUs. 599def: InstRW<[SBWriteResGroup2], (instrs RETQ)>; 600 601def SBWriteResGroup4 : SchedWriteRes<[SBPort05]> { 602 let Latency = 1; 603 let NumMicroOps = 1; 604 let ResourceCycles = [1]; 605} 606def: InstRW<[SBWriteResGroup4], (instrs CDQ, CQO)>; 607 608def SBWriteResGroup5 : SchedWriteRes<[SBPort15]> { 609 let Latency = 1; 610 let NumMicroOps = 1; 611 let ResourceCycles = [1]; 612} 613def: InstRW<[SBWriteResGroup5], (instrs MMX_PABSBrr, 614 MMX_PABSDrr, 615 MMX_PABSWrr, 616 MMX_PADDQirr, 617 MMX_PALIGNRrri, 618 MMX_PSIGNBrr, 619 MMX_PSIGNDrr, 620 MMX_PSIGNWrr)>; 621 622def SBWriteResGroup11 : SchedWriteRes<[SBPort015]> { 623 let Latency = 2; 624 let NumMicroOps = 2; 625 let ResourceCycles = [2]; 626} 627def: InstRW<[SBWriteResGroup11], (instrs SCASB, 628 SCASL, 629 SCASQ, 630 SCASW)>; 631 632def SBWriteResGroup12 : SchedWriteRes<[SBPort0,SBPort1]> { 633 let Latency = 2; 634 let NumMicroOps = 2; 635 let ResourceCycles = [1,1]; 636} 637def: InstRW<[SBWriteResGroup12], (instregex "(V?)(U?)COMI(SD|SS)rr")>; 638 639def SBWriteResGroup15 : SchedWriteRes<[SBPort0,SBPort015]> { 640 let Latency = 2; 641 let NumMicroOps = 2; 642 let ResourceCycles = [1,1]; 643} 644def: InstRW<[SBWriteResGroup15], (instrs CWD, 645 FNSTSW16r)>; 646 647def SBWriteResGroup18 : SchedWriteRes<[SBPort5,SBPort015]> { 648 let Latency = 2; 649 let NumMicroOps = 2; 650 let ResourceCycles = [1,1]; 651} 652def: InstRW<[SBWriteResGroup18], (instrs JCXZ, JECXZ, JRCXZ, 653 MMX_MOVDQ2Qrr)>; 654 655def SBWriteResGroup21 : SchedWriteRes<[SBPort1]> { 656 let Latency = 3; 657 let NumMicroOps = 1; 658 let ResourceCycles = [1]; 659} 660def: InstRW<[SBWriteResGroup21], (instrs PUSHFS64)>; 661 662def SBWriteResGroup22 : SchedWriteRes<[SBPort0,SBPort5]> { 663 let Latency = 3; 664 let NumMicroOps = 2; 665 let ResourceCycles = [1,1]; 666} 667def: InstRW<[SBWriteResGroup22], (instregex "(V?)EXTRACTPSrr")>; 668 669def SBWriteResGroup23 : SchedWriteRes<[SBPort05]> { 670 let Latency = 2; 671 let NumMicroOps = 3; 672 let ResourceCycles = [3]; 673} 674def: InstRW<[SBWriteResGroup23], (instregex "RCL(8|16|32|64)r1", 675 "RCR(8|16|32|64)r1")>; 676 677def SBWriteResGroup25_1 : SchedWriteRes<[SBPort23,SBPort015]> { 678 let Latency = 7; 679 let NumMicroOps = 3; 680 let ResourceCycles = [1,2]; 681} 682def: InstRW<[SBWriteResGroup25_1], (instrs LEAVE, LEAVE64)>; 683 684def SBWriteResGroup26_2 : SchedWriteRes<[SBPort0,SBPort1,SBPort5]> { 685 let Latency = 3; 686 let NumMicroOps = 3; 687 let ResourceCycles = [1,1,1]; 688} 689def: InstRW<[SBWriteResGroup26_2], (instrs COM_FIPr, COM_FIr, UCOM_FIPr, UCOM_FIr)>; 690 691def SBWriteResGroup29 : SchedWriteRes<[SBPort1,SBPort015]> { 692 let Latency = 4; 693 let NumMicroOps = 2; 694 let ResourceCycles = [1,1]; 695} 696def: InstRW<[SBWriteResGroup29], (instrs MOV64sr)>; 697 698def SBWriteResGroup29_2 : SchedWriteRes<[SBPort5,SBPort015]> { 699 let Latency = 4; 700 let NumMicroOps = 4; 701 let ResourceCycles = [1,3]; 702} 703def: InstRW<[SBWriteResGroup29_2], (instrs PAUSE)>; 704 705def SBWriteResGroup31 : SchedWriteRes<[SBPort23]> { 706 let Latency = 5; 707 let NumMicroOps = 1; 708 let ResourceCycles = [1]; 709} 710def: InstRW<[SBWriteResGroup31], (instregex "MOVSX(16|32|64)rm(8|16|32)", 711 "MOVZX(16|32|64)rm(8|16)")>; 712 713def SBWriteResGroup76 : SchedWriteRes<[SBPort05]> { 714 let Latency = 5; 715 let NumMicroOps = 8; 716 let ResourceCycles = [8]; 717} 718def: InstRW<[SBWriteResGroup76], (instregex "RCL(8|16|32|64)r(i|CL)", 719 "RCR(8|16|32|64)r(i|CL)")>; 720 721def SBWriteResGroup33 : SchedWriteRes<[SBPort4,SBPort23]> { 722 let Latency = 5; 723 let NumMicroOps = 2; 724 let ResourceCycles = [1,1]; 725} 726def: InstRW<[SBWriteResGroup33], (instregex "PUSH(16r|32r|64r|64i8)")>; 727 728def SBWriteResGroup35 : SchedWriteRes<[SBPort1,SBPort5]> { 729 let Latency = 5; 730 let NumMicroOps = 3; 731 let ResourceCycles = [1,2]; 732} 733def: InstRW<[SBWriteResGroup35], (instrs CLI)>; 734 735def SBWriteResGroup35_2 : SchedWriteRes<[SBPort1,SBPort4,SBPort23]> { 736 let Latency = 5; 737 let NumMicroOps = 3; 738 let ResourceCycles = [1,1,1]; 739} 740def: InstRW<[SBWriteResGroup35_2], (instrs PUSHGS64)>; 741def: InstRW<[SBWriteResGroup35_2], (instregex "ISTT_FP(16|32|64)m")>; 742 743def SBWriteResGroup36 : SchedWriteRes<[SBPort4,SBPort5,SBPort23]> { 744 let Latency = 5; 745 let NumMicroOps = 3; 746 let ResourceCycles = [1,1,1]; 747} 748def: InstRW<[SBWriteResGroup36], (instrs CALL64pcrel32)>; 749def: InstRW<[SBWriteResGroup36], (instregex "CALL(16|32|64)r", 750 "(V?)EXTRACTPSmr")>; 751 752def SBWriteResGroup40 : SchedWriteRes<[SBPort4,SBPort23,SBPort015]> { 753 let Latency = 5; 754 let NumMicroOps = 3; 755 let ResourceCycles = [1,1,1]; 756} 757def: InstRW<[SBWriteResGroup40], (instrs STOSB, STOSL, STOSQ, STOSW)>; 758 759def SBWriteResGroup41 : SchedWriteRes<[SBPort5,SBPort015]> { 760 let Latency = 5; 761 let NumMicroOps = 4; 762 let ResourceCycles = [1,3]; 763} 764def: InstRW<[SBWriteResGroup41], (instrs FNINIT)>; 765 766def SBWriteResGroup45 : SchedWriteRes<[SBPort0,SBPort4,SBPort23,SBPort15]> { 767 let Latency = 5; 768 let NumMicroOps = 4; 769 let ResourceCycles = [1,1,1,1]; 770} 771def: InstRW<[SBWriteResGroup45], (instregex "(V?)PEXTR(D|Q)mr", 772 "PUSHF(16|64)")>; 773 774def SBWriteResGroup46 : SchedWriteRes<[SBPort4,SBPort5,SBPort01,SBPort23]> { 775 let Latency = 5; 776 let NumMicroOps = 4; 777 let ResourceCycles = [1,1,1,1]; 778} 779def: InstRW<[SBWriteResGroup46], (instregex "CLFLUSH")>; 780 781def SBWriteResGroup47 : SchedWriteRes<[SBPort4,SBPort5,SBPort01,SBPort23]> { 782 let Latency = 5; 783 let NumMicroOps = 5; 784 let ResourceCycles = [1,2,1,1]; 785} 786def: InstRW<[SBWriteResGroup47], (instregex "FXRSTOR")>; 787 788def SBWriteResGroup48 : SchedWriteRes<[SBPort23]> { 789 let Latency = 6; 790 let NumMicroOps = 1; 791 let ResourceCycles = [1]; 792} 793def: InstRW<[SBWriteResGroup48], (instrs MMX_MOVD64from64rm, 794 VBROADCASTSSrm)>; 795def: InstRW<[SBWriteResGroup48], (instregex "POP(16|32|64)r", 796 "(V?)MOV64toPQIrm", 797 "(V?)MOVDDUPrm", 798 "(V?)MOVDI2PDIrm", 799 "(V?)MOVQI2PQIrm", 800 "(V?)MOVSDrm", 801 "(V?)MOVSHDUPrm", 802 "(V?)MOVSLDUPrm", 803 "(V?)MOVSSrm")>; 804 805def SBWriteResGroup49 : SchedWriteRes<[SBPort5,SBPort23]> { 806 let Latency = 6; 807 let NumMicroOps = 2; 808 let ResourceCycles = [1,1]; 809} 810def: InstRW<[SBWriteResGroup49], (instrs MOV16sm)>; 811 812def SBWriteResGroup51 : SchedWriteRes<[SBPort23,SBPort15]> { 813 let Latency = 6; 814 let NumMicroOps = 2; 815 let ResourceCycles = [1,1]; 816} 817def: InstRW<[SBWriteResGroup51], (instrs MMX_PABSBrm, 818 MMX_PABSDrm, 819 MMX_PABSWrm, 820 MMX_PALIGNRrmi, 821 MMX_PSIGNBrm, 822 MMX_PSIGNDrm, 823 MMX_PSIGNWrm)>; 824 825def SBWriteResGroup52 : SchedWriteRes<[SBPort23,SBPort015]> { 826 let Latency = 6; 827 let NumMicroOps = 2; 828 let ResourceCycles = [1,1]; 829} 830def: InstRW<[SBWriteResGroup52], (instrs LODSL, LODSQ)>; 831 832def SBWriteResGroup53 : SchedWriteRes<[SBPort4,SBPort23]> { 833 let Latency = 6; 834 let NumMicroOps = 3; 835 let ResourceCycles = [1,2]; 836} 837def: InstRW<[SBWriteResGroup53], (instregex "ST_F(32|64)m", 838 "ST_FP(32|64|80)m")>; 839 840def SBWriteResGroup54 : SchedWriteRes<[SBPort23]> { 841 let Latency = 7; 842 let NumMicroOps = 1; 843 let ResourceCycles = [1]; 844} 845def: InstRW<[SBWriteResGroup54], (instrs VBROADCASTSDYrm, 846 VBROADCASTSSYrm, 847 VMOVDDUPYrm, 848 VMOVSHDUPYrm, 849 VMOVSLDUPYrm)>; 850 851def SBWriteResGroup58 : SchedWriteRes<[SBPort23,SBPort05]> { 852 let Latency = 7; 853 let NumMicroOps = 2; 854 let ResourceCycles = [1,1]; 855} 856def: InstRW<[SBWriteResGroup58], (instrs VINSERTF128rm)>; 857 858def SBWriteResGroup59 : SchedWriteRes<[SBPort23,SBPort15]> { 859 let Latency = 7; 860 let NumMicroOps = 2; 861 let ResourceCycles = [1,1]; 862} 863def: InstRW<[SBWriteResGroup59], (instrs MMX_PADDQirm)>; 864 865def SBWriteResGroup62 : SchedWriteRes<[SBPort5,SBPort23]> { 866 let Latency = 7; 867 let NumMicroOps = 3; 868 let ResourceCycles = [2,1]; 869} 870def: InstRW<[SBWriteResGroup62], (instrs VERRm, VERWm)>; 871 872def SBWriteResGroup63 : SchedWriteRes<[SBPort23,SBPort015]> { 873 let Latency = 7; 874 let NumMicroOps = 3; 875 let ResourceCycles = [1,2]; 876} 877def: InstRW<[SBWriteResGroup63], (instrs LODSB, LODSW)>; 878 879def SBWriteResGroup64 : SchedWriteRes<[SBPort5,SBPort01,SBPort23]> { 880 let Latency = 7; 881 let NumMicroOps = 3; 882 let ResourceCycles = [1,1,1]; 883} 884def: InstRW<[SBWriteResGroup64], (instrs FARJMP64)>; 885 886def SBWriteResGroup66 : SchedWriteRes<[SBPort0,SBPort4,SBPort23]> { 887 let Latency = 7; 888 let NumMicroOps = 4; 889 let ResourceCycles = [1,1,2]; 890} 891def: InstRW<[SBWriteResGroup66], (instrs FNSTSWm)>; 892 893def SBWriteResGroup67 : SchedWriteRes<[SBPort1,SBPort5,SBPort015]> { 894 let Latency = 7; 895 let NumMicroOps = 4; 896 let ResourceCycles = [1,2,1]; 897} 898def: InstRW<[SBWriteResGroup67], (instregex "SLDT(16|32|64)r", 899 "STR(16|32|64)r")>; 900 901def SBWriteResGroup68 : SchedWriteRes<[SBPort4,SBPort5,SBPort23]> { 902 let Latency = 7; 903 let NumMicroOps = 4; 904 let ResourceCycles = [1,1,2]; 905} 906def: InstRW<[SBWriteResGroup68], (instrs FNSTCW16m)>; 907def: InstRW<[SBWriteResGroup68], (instregex "CALL(16|32|64)m")>; 908 909def SBWriteResGroup69 : SchedWriteRes<[SBPort4,SBPort23,SBPort05]> { 910 let Latency = 7; 911 let NumMicroOps = 4; 912 let ResourceCycles = [1,2,1]; 913} 914def: InstRW<[SBWriteResGroup69], (instregex "SAR(8|16|32|64)m(1|i)", 915 "SHL(8|16|32|64)m(1|i)", 916 "SHR(8|16|32|64)m(1|i)")>; 917 918def SBWriteResGroup77 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> { 919 let Latency = 8; 920 let NumMicroOps = 3; 921 let ResourceCycles = [1,1,1]; 922} 923def: InstRW<[SBWriteResGroup77], (instregex "(V?)(U?)COMI(SD|SS)rm")>; 924 925def SBWriteResGroup81 : SchedWriteRes<[SBPort4, SBPort23, SBPort015]> { 926 let Latency = 6; 927 let NumMicroOps = 3; 928 let ResourceCycles = [1, 2, 1]; 929} 930def: InstRW<[SBWriteResGroup81], (instregex "CMPXCHG(8|16)B")>; 931 932def SBWriteResGroup83 : SchedWriteRes<[SBPort23,SBPort015]> { 933 let Latency = 8; 934 let NumMicroOps = 5; 935 let ResourceCycles = [2,3]; 936} 937def: InstRW<[SBWriteResGroup83], (instrs CMPSB, 938 CMPSL, 939 CMPSQ, 940 CMPSW)>; 941 942def SBWriteResGroup84 : SchedWriteRes<[SBPort4,SBPort5,SBPort23]> { 943 let Latency = 8; 944 let NumMicroOps = 5; 945 let ResourceCycles = [1,2,2]; 946} 947def: InstRW<[SBWriteResGroup84], (instrs FLDCW16m)>; 948 949def SBWriteResGroup85 : SchedWriteRes<[SBPort4,SBPort23,SBPort05]> { 950 let Latency = 8; 951 let NumMicroOps = 5; 952 let ResourceCycles = [1,2,2]; 953} 954def: InstRW<[SBWriteResGroup85], (instregex "ROL(8|16|32|64)m(1|i)", 955 "ROR(8|16|32|64)m(1|i)")>; 956 957def SBWriteResGroup86 : SchedWriteRes<[SBPort4,SBPort23,SBPort015]> { 958 let Latency = 8; 959 let NumMicroOps = 5; 960 let ResourceCycles = [1,2,2]; 961} 962def: InstRW<[SBWriteResGroup86], (instrs MOVSB, MOVSL, MOVSQ, MOVSW)>; 963def: InstRW<[SBWriteResGroup86], (instregex "XADD(8|16|32|64)rm")>; 964 965def SBWriteResGroup87 : SchedWriteRes<[SBPort4,SBPort5,SBPort01,SBPort23]> { 966 let Latency = 8; 967 let NumMicroOps = 5; 968 let ResourceCycles = [1,1,1,2]; 969} 970def: InstRW<[SBWriteResGroup87], (instrs FARCALL64)>; 971 972def SBWriteResGroup93 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> { 973 let Latency = 9; 974 let NumMicroOps = 3; 975 let ResourceCycles = [1,1,1]; 976} 977def: InstRW<[SBWriteResGroup93], (instregex "CVT(T?)(SD|SS)2SI(64)?rm")>; 978 979def SBWriteResGroup95 : SchedWriteRes<[SBPort5,SBPort01,SBPort23]> { 980 let Latency = 9; 981 let NumMicroOps = 3; 982 let ResourceCycles = [1,1,1]; 983} 984def: InstRW<[SBWriteResGroup95], (instregex "LD_F(32|64|80)m")>; 985 986def SBWriteResGroup97 : SchedWriteRes<[SBPort1,SBPort4,SBPort23]> { 987 let Latency = 9; 988 let NumMicroOps = 4; 989 let ResourceCycles = [1,1,2]; 990} 991def: InstRW<[SBWriteResGroup97], (instregex "IST_F(16|32)m", 992 "IST_FP(16|32|64)m")>; 993 994def SBWriteResGroup97_2 : SchedWriteRes<[SBPort4,SBPort23,SBPort05]> { 995 let Latency = 9; 996 let NumMicroOps = 6; 997 let ResourceCycles = [1,2,3]; 998} 999def: InstRW<[SBWriteResGroup97_2], (instregex "ROL(8|16|32|64)mCL", 1000 "ROR(8|16|32|64)mCL", 1001 "SAR(8|16|32|64)mCL", 1002 "SHL(8|16|32|64)mCL", 1003 "SHR(8|16|32|64)mCL")>; 1004 1005def SBWriteResGroup98 : SchedWriteRes<[SBPort4,SBPort23,SBPort015]> { 1006 let Latency = 9; 1007 let NumMicroOps = 6; 1008 let ResourceCycles = [1,2,3]; 1009} 1010def: SchedAlias<WriteADCRMW, SBWriteResGroup98>; 1011 1012def SBWriteResGroup99 : SchedWriteRes<[SBPort4,SBPort23,SBPort05,SBPort015]> { 1013 let Latency = 9; 1014 let NumMicroOps = 6; 1015 let ResourceCycles = [1,2,2,1]; 1016} 1017def: InstRW<[SBWriteResGroup99, ReadAfterLd], (instrs ADC8mr, ADC16mr, ADC32mr, ADC64mr, 1018 SBB8mr, SBB16mr, SBB32mr, SBB64mr)>; 1019 1020def SBWriteResGroup100 : SchedWriteRes<[SBPort4,SBPort5,SBPort23,SBPort05,SBPort015]> { 1021 let Latency = 9; 1022 let NumMicroOps = 6; 1023 let ResourceCycles = [1,1,2,1,1]; 1024} 1025def : SchedAlias<WriteBitTestRegLd, SBWriteResGroup100>; // TODO - this is incorrect - no RMW 1026 1027def SBWriteResGroup101 : SchedWriteRes<[SBPort1,SBPort23]> { 1028 let Latency = 10; 1029 let NumMicroOps = 2; 1030 let ResourceCycles = [1,1]; 1031} 1032def: InstRW<[SBWriteResGroup101], (instregex "(ADD|SUB|SUBR)_F(32|64)m", 1033 "ILD_F(16|32|64)m")>; 1034 1035def SBWriteResGroup104 : SchedWriteRes<[SBPort0,SBPort23]> { 1036 let Latency = 11; 1037 let NumMicroOps = 2; 1038 let ResourceCycles = [1,1]; 1039} 1040def: InstRW<[SBWriteResGroup104], (instregex "(V?)PCMPGTQrm")>; 1041 1042def SBWriteResGroup106 : SchedWriteRes<[SBPort1,SBPort23]> { 1043 let Latency = 11; 1044 let NumMicroOps = 3; 1045 let ResourceCycles = [2,1]; 1046} 1047def: InstRW<[SBWriteResGroup106], (instregex "FICOM(P?)(16|32)m")>; 1048 1049def SBWriteResGroup108 : SchedWriteRes<[SBPort05,SBPort23]> { 1050 let Latency = 11; 1051 let NumMicroOps = 11; 1052 let ResourceCycles = [7,4]; 1053} 1054def: InstRW<[SBWriteResGroup108], (instregex "RCL(8|16|32|64)m", 1055 "RCR(8|16|32|64)m")>; 1056 1057def SBWriteResGroup111 : SchedWriteRes<[SBPort0,SBPort23]> { 1058 let Latency = 12; 1059 let NumMicroOps = 2; 1060 let ResourceCycles = [1,1]; 1061} 1062def: InstRW<[SBWriteResGroup111], (instregex "MUL_F(32|64)m")>; 1063 1064def SBWriteResGroup114 : SchedWriteRes<[SBPort1,SBPort23]> { 1065 let Latency = 13; 1066 let NumMicroOps = 3; 1067 let ResourceCycles = [2,1]; 1068} 1069def: InstRW<[SBWriteResGroup114], (instregex "(ADD|SUB|SUBR)_FI(16|32)m")>; 1070 1071def SBWriteResGroup119 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> { 1072 let Latency = 15; 1073 let NumMicroOps = 3; 1074 let ResourceCycles = [1,1,1]; 1075} 1076def: InstRW<[SBWriteResGroup119], (instregex "MUL_FI(16|32)m")>; 1077 1078def SBWriteResGroup130 : SchedWriteRes<[SBPort0,SBPort23]> { 1079 let Latency = 31; 1080 let NumMicroOps = 2; 1081 let ResourceCycles = [1,1]; 1082} 1083def: InstRW<[SBWriteResGroup130], (instregex "DIV(R?)_F(32|64)m")>; 1084 1085def SBWriteResGroup131 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> { 1086 let Latency = 34; 1087 let NumMicroOps = 3; 1088 let ResourceCycles = [1,1,1]; 1089} 1090def: InstRW<[SBWriteResGroup131], (instregex "DIV(R?)_FI(16|32)m")>; 1091 1092def SBWriteResGroupVzeroall : SchedWriteRes<[SBPort5]> { 1093 let Latency = 9; 1094 let NumMicroOps = 20; 1095 let ResourceCycles = [2]; 1096} 1097def: InstRW<[SBWriteResGroupVzeroall], (instrs VZEROALL)>; 1098 1099def SBWriteResGroupVzeroupper : SchedWriteRes<[]> { 1100 let Latency = 1; 1101 let NumMicroOps = 4; 1102 let ResourceCycles = []; 1103} 1104def: InstRW<[SBWriteResGroupVzeroupper], (instrs VZEROUPPER)>; 1105 1106def: InstRW<[WriteZero], (instrs CLC)>; 1107 1108// Intruction variants handled by the renamer. These might not need execution 1109// ports in certain conditions. 1110// See Agner's Fog "The microarchitecture of Intel, AMD and VIA CPUs", 1111// section "Sandy Bridge and Ivy Bridge Pipeline" > "Register allocation and 1112// renaming". 1113// These can be investigated with llvm-exegesis, e.g. 1114// echo 'pxor %mm0, %mm0' | /tmp/llvm-exegesis -mode=uops -snippets-file=- 1115// echo 'vxorpd %xmm0, %xmm0, %xmm1' | /tmp/llvm-exegesis -mode=uops -snippets-file=- 1116 1117def SBWriteZeroLatency : SchedWriteRes<[]> { 1118 let Latency = 0; 1119} 1120 1121def SBWriteZeroIdiom : SchedWriteVariant<[ 1122 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SBWriteZeroLatency]>, 1123 SchedVar<NoSchedPred, [WriteALU]> 1124]>; 1125def : InstRW<[SBWriteZeroIdiom], (instrs SUB32rr, SUB64rr, 1126 XOR32rr, XOR64rr)>; 1127 1128def SBWriteFZeroIdiom : SchedWriteVariant<[ 1129 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SBWriteZeroLatency]>, 1130 SchedVar<NoSchedPred, [WriteFLogic]> 1131]>; 1132def : InstRW<[SBWriteFZeroIdiom], (instrs XORPSrr, VXORPSrr, XORPDrr, 1133 VXORPDrr)>; 1134 1135def SBWriteFZeroIdiomY : SchedWriteVariant<[ 1136 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SBWriteZeroLatency]>, 1137 SchedVar<NoSchedPred, [WriteFLogicY]> 1138]>; 1139def : InstRW<[SBWriteFZeroIdiomY], (instrs VXORPSYrr, VXORPDYrr)>; 1140 1141def SBWriteVZeroIdiomLogicX : SchedWriteVariant<[ 1142 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SBWriteZeroLatency]>, 1143 SchedVar<NoSchedPred, [WriteVecLogicX]> 1144]>; 1145def : InstRW<[SBWriteVZeroIdiomLogicX], (instrs PXORrr, VPXORrr)>; 1146 1147def SBWriteVZeroIdiomALUX : SchedWriteVariant<[ 1148 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SBWriteZeroLatency]>, 1149 SchedVar<NoSchedPred, [WriteVecALUX]> 1150]>; 1151def : InstRW<[SBWriteVZeroIdiomALUX], (instrs PSUBBrr, VPSUBBrr, 1152 PSUBDrr, VPSUBDrr, 1153 PSUBQrr, VPSUBQrr, 1154 PSUBWrr, VPSUBWrr, 1155 PCMPGTBrr, VPCMPGTBrr, 1156 PCMPGTDrr, VPCMPGTDrr, 1157 PCMPGTWrr, VPCMPGTWrr)>; 1158 1159def SBWritePCMPGTQ : SchedWriteRes<[SBPort0]> { 1160 let Latency = 5; 1161 let NumMicroOps = 1; 1162 let ResourceCycles = [1]; 1163} 1164 1165def SBWriteVZeroIdiomPCMPGTQ : SchedWriteVariant<[ 1166 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SBWriteZeroLatency]>, 1167 SchedVar<NoSchedPred, [SBWritePCMPGTQ]> 1168]>; 1169def : InstRW<[SBWriteVZeroIdiomPCMPGTQ], (instrs PCMPGTQrr, VPCMPGTQrr)>; 1170 1171// CMOVs that use both Z and C flag require an extra uop. 1172def SBWriteCMOVA_CMOVBErr : SchedWriteRes<[SBPort05,SBPort015]> { 1173 let Latency = 3; 1174 let ResourceCycles = [2,1]; 1175 let NumMicroOps = 3; 1176} 1177 1178def SBWriteCMOVA_CMOVBErm : SchedWriteRes<[SBPort23,SBPort05,SBPort015]> { 1179 let Latency = 8; 1180 let ResourceCycles = [1,2,1]; 1181 let NumMicroOps = 4; 1182} 1183 1184def SBCMOVA_CMOVBErr : SchedWriteVariant<[ 1185 SchedVar<MCSchedPredicate<IsCMOVArr_Or_CMOVBErr>, [SBWriteCMOVA_CMOVBErr]>, 1186 SchedVar<NoSchedPred, [WriteCMOV]> 1187]>; 1188 1189def SBCMOVA_CMOVBErm : SchedWriteVariant<[ 1190 SchedVar<MCSchedPredicate<IsCMOVArm_Or_CMOVBErm>, [SBWriteCMOVA_CMOVBErm]>, 1191 SchedVar<NoSchedPred, [WriteCMOV.Folded]> 1192]>; 1193 1194def : InstRW<[SBCMOVA_CMOVBErr], (instrs CMOV16rr, CMOV32rr, CMOV64rr)>; 1195def : InstRW<[SBCMOVA_CMOVBErm], (instrs CMOV16rm, CMOV32rm, CMOV64rm)>; 1196 1197// SETCCs that use both Z and C flag require an extra uop. 1198def SBWriteSETA_SETBEr : SchedWriteRes<[SBPort05]> { 1199 let Latency = 2; 1200 let ResourceCycles = [2]; 1201 let NumMicroOps = 2; 1202} 1203 1204def SBWriteSETA_SETBEm : SchedWriteRes<[SBPort4,SBPort23,SBPort05]> { 1205 let Latency = 3; 1206 let ResourceCycles = [1,1,2]; 1207 let NumMicroOps = 4; 1208} 1209 1210def SBSETA_SETBErr : SchedWriteVariant<[ 1211 SchedVar<MCSchedPredicate<IsSETAr_Or_SETBEr>, [SBWriteSETA_SETBEr]>, 1212 SchedVar<NoSchedPred, [WriteSETCC]> 1213]>; 1214 1215def SBSETA_SETBErm : SchedWriteVariant<[ 1216 SchedVar<MCSchedPredicate<IsSETAm_Or_SETBEm>, [SBWriteSETA_SETBEm]>, 1217 SchedVar<NoSchedPred, [WriteSETCCStore]> 1218]>; 1219 1220def : InstRW<[SBSETA_SETBErr], (instrs SETCCr)>; 1221def : InstRW<[SBSETA_SETBErm], (instrs SETCCm)>; 1222 1223} // SchedModel 1224