1//=- X86SchedSandyBridge.td - X86 Sandy Bridge Scheduling ----*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the machine model for Sandy Bridge to support instruction 10// scheduling and other instruction cost heuristics. 11// 12// Note that we define some instructions here that are not supported by SNB, 13// but we still have to define them because SNB is the default subtarget for 14// X86. These instructions are tagged with a comment `Unsupported = 1`. 15// 16//===----------------------------------------------------------------------===// 17 18def SandyBridgeModel : SchedMachineModel { 19 // All x86 instructions are modeled as a single micro-op, and SB can decode 4 20 // instructions per cycle. 21 // FIXME: Identify instructions that aren't a single fused micro-op. 22 let IssueWidth = 4; 23 let MicroOpBufferSize = 168; // Based on the reorder buffer. 24 let LoadLatency = 5; 25 let MispredictPenalty = 16; 26 27 // Based on the LSD (loop-stream detector) queue size. 28 let LoopMicroOpBufferSize = 28; 29 30 // This flag is set to allow the scheduler to assign 31 // a default model to unrecognized opcodes. 32 let CompleteModel = 0; 33} 34 35let SchedModel = SandyBridgeModel in { 36 37// Sandy Bridge can issue micro-ops to 6 different ports in one cycle. 38 39// Ports 0, 1, and 5 handle all computation. 40def SBPort0 : ProcResource<1>; 41def SBPort1 : ProcResource<1>; 42def SBPort5 : ProcResource<1>; 43 44// Ports 2 and 3 are identical. They handle loads and the address half of 45// stores. 46def SBPort23 : ProcResource<2>; 47 48// Port 4 gets the data half of stores. Store data can be available later than 49// the store address, but since we don't model the latency of stores, we can 50// ignore that. 51def SBPort4 : ProcResource<1>; 52 53// Many micro-ops are capable of issuing on multiple ports. 54def SBPort01 : ProcResGroup<[SBPort0, SBPort1]>; 55def SBPort05 : ProcResGroup<[SBPort0, SBPort5]>; 56def SBPort15 : ProcResGroup<[SBPort1, SBPort5]>; 57def SBPort015 : ProcResGroup<[SBPort0, SBPort1, SBPort5]>; 58 59// 54 Entry Unified Scheduler 60def SBPortAny : ProcResGroup<[SBPort0, SBPort1, SBPort23, SBPort4, SBPort5]> { 61 let BufferSize=54; 62} 63 64// Integer division issued on port 0. 65def SBDivider : ProcResource<1>; 66// FP division and sqrt on port 0. 67def SBFPDivider : ProcResource<1>; 68 69// Integer loads are 5 cycles, so ReadAfterLd registers needn't be available until 5 70// cycles after the memory operand. 71def : ReadAdvance<ReadAfterLd, 5>; 72 73// Vector loads are 5/6/7 cycles, so ReadAfterVec*Ld registers needn't be available 74// until 5/6/7 cycles after the memory operand. 75def : ReadAdvance<ReadAfterVecLd, 5>; 76def : ReadAdvance<ReadAfterVecXLd, 6>; 77def : ReadAdvance<ReadAfterVecYLd, 7>; 78 79def : ReadAdvance<ReadInt2Fpu, 0>; 80 81// Many SchedWrites are defined in pairs with and without a folded load. 82// Instructions with folded loads are usually micro-fused, so they only appear 83// as two micro-ops when queued in the reservation station. 84// This multiclass defines the resource usage for variants with and without 85// folded loads. 86multiclass SBWriteResPair<X86FoldableSchedWrite SchedRW, 87 list<ProcResourceKind> ExePorts, 88 int Lat, list<int> Res = [1], int UOps = 1, 89 int LoadLat = 5> { 90 // Register variant is using a single cycle on ExePort. 91 def : WriteRes<SchedRW, ExePorts> { 92 let Latency = Lat; 93 let ResourceCycles = Res; 94 let NumMicroOps = UOps; 95 } 96 97 // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to 98 // the latency (default = 5). 99 def : WriteRes<SchedRW.Folded, !listconcat([SBPort23], ExePorts)> { 100 let Latency = !add(Lat, LoadLat); 101 let ResourceCycles = !listconcat([1], Res); 102 let NumMicroOps = !add(UOps, 1); 103 } 104} 105 106// A folded store needs a cycle on port 4 for the store data, and an extra port 107// 2/3 cycle to recompute the address. 108def : WriteRes<WriteRMW, [SBPort23,SBPort4]>; 109 110def : WriteRes<WriteStore, [SBPort23, SBPort4]>; 111def : WriteRes<WriteStoreNT, [SBPort23, SBPort4]>; 112def : WriteRes<WriteLoad, [SBPort23]> { let Latency = 5; } 113def : WriteRes<WriteMove, [SBPort015]>; 114def : WriteRes<WriteZero, []>; 115def : WriteRes<WriteVecMaskedGatherWriteback, []> { let Latency = 5; let NumMicroOps = 0; } 116 117// Arithmetic. 118defm : SBWriteResPair<WriteALU, [SBPort015], 1>; 119defm : SBWriteResPair<WriteADC, [SBPort05,SBPort015], 2, [1,1], 2>; 120 121defm : SBWriteResPair<WriteIMul8, [SBPort1], 3>; 122defm : SBWriteResPair<WriteIMul16, [SBPort1,SBPort05,SBPort015], 4, [1,1,2], 4>; 123defm : X86WriteRes<WriteIMul16Imm, [SBPort1,SBPort015], 4, [1,1], 2>; 124defm : X86WriteRes<WriteIMul16ImmLd, [SBPort1,SBPort015,SBPort23], 8, [1,1,1], 3>; 125defm : SBWriteResPair<WriteIMul16Reg, [SBPort1], 3>; 126defm : SBWriteResPair<WriteIMul32, [SBPort1,SBPort05,SBPort015], 4, [1,1,1], 3>; 127defm : SBWriteResPair<WriteMULX32, [SBPort1,SBPort05,SBPort015], 3, [1,1,1], 3>; 128defm : SBWriteResPair<WriteIMul32Imm, [SBPort1], 3>; 129defm : SBWriteResPair<WriteIMul32Reg, [SBPort1], 3>; 130defm : SBWriteResPair<WriteIMul64, [SBPort1,SBPort0], 4, [1,1], 2>; 131defm : SBWriteResPair<WriteMULX64, [SBPort1,SBPort0], 3, [1,1], 2>; 132defm : SBWriteResPair<WriteIMul64Imm, [SBPort1], 3>; 133defm : SBWriteResPair<WriteIMul64Reg, [SBPort1], 3>; 134def SBWriteIMulH : WriteRes<WriteIMulH, []> { let Latency = 4; } 135def : WriteRes<WriteIMulHLd, []> { 136 let Latency = !add(SBWriteIMulH.Latency, SandyBridgeModel.LoadLatency); 137} 138 139defm : X86WriteRes<WriteXCHG, [SBPort015], 2, [3], 3>; 140defm : X86WriteRes<WriteBSWAP32, [SBPort1], 1, [1], 1>; 141defm : X86WriteRes<WriteBSWAP64, [SBPort1, SBPort05], 2, [1,1], 2>; 142defm : X86WriteRes<WriteCMPXCHG, [SBPort05, SBPort015], 5, [1,3], 4>; 143defm : X86WriteRes<WriteCMPXCHGRMW,[SBPort015, SBPort5, SBPort23, SBPort4], 8, [1, 2, 2, 1], 6>; 144 145defm : SBWriteResPair<WriteDiv8, [SBPort0, SBDivider], 25, [1, 10]>; 146defm : SBWriteResPair<WriteDiv16, [SBPort0, SBDivider], 25, [1, 10]>; 147defm : SBWriteResPair<WriteDiv32, [SBPort0, SBDivider], 25, [1, 10]>; 148defm : SBWriteResPair<WriteDiv64, [SBPort0, SBDivider], 25, [1, 10]>; 149defm : SBWriteResPair<WriteIDiv8, [SBPort0, SBDivider], 25, [1, 10]>; 150defm : SBWriteResPair<WriteIDiv16, [SBPort0, SBDivider], 25, [1, 10]>; 151defm : SBWriteResPair<WriteIDiv32, [SBPort0, SBDivider], 25, [1, 10]>; 152defm : SBWriteResPair<WriteIDiv64, [SBPort0, SBDivider], 25, [1, 10]>; 153 154// SHLD/SHRD. 155defm : X86WriteRes<WriteSHDrri, [SBPort05, SBPort015], 2, [1, 1], 2>; 156defm : X86WriteRes<WriteSHDrrcl,[SBPort05, SBPort015], 4, [3, 1], 4>; 157defm : X86WriteRes<WriteSHDmri, [SBPort4,SBPort23,SBPort05,SBPort015], 8, [1, 2, 1, 1], 5>; 158defm : X86WriteRes<WriteSHDmrcl,[SBPort4,SBPort23,SBPort05,SBPort015], 10, [1, 2, 3, 1], 7>; 159 160defm : SBWriteResPair<WriteShift, [SBPort05], 1>; 161defm : SBWriteResPair<WriteShiftCL, [SBPort05], 3, [3], 3>; 162defm : SBWriteResPair<WriteRotate, [SBPort05], 2, [2], 2>; 163defm : SBWriteResPair<WriteRotateCL, [SBPort05], 3, [3], 3>; 164 165defm : SBWriteResPair<WriteJump, [SBPort5], 1>; 166defm : SBWriteResPair<WriteCRC32, [SBPort1], 3, [1], 1, 5>; 167 168defm : SBWriteResPair<WriteCMOV, [SBPort05,SBPort015], 2, [1,1], 2>; // Conditional move. 169defm : X86WriteRes<WriteFCMOV, [SBPort5,SBPort05], 3, [2,1], 3>; // x87 conditional move. 170def : WriteRes<WriteSETCC, [SBPort05]>; // Setcc. 171def : WriteRes<WriteSETCCStore, [SBPort05,SBPort4,SBPort23]> { 172 let Latency = 2; 173 let NumMicroOps = 3; 174} 175 176defm : X86WriteRes<WriteLAHFSAHF, [SBPort05], 1, [1], 1>; 177defm : X86WriteRes<WriteBitTest, [SBPort05], 1, [1], 1>; 178defm : X86WriteRes<WriteBitTestImmLd, [SBPort05,SBPort23], 6, [1,1], 2>; 179//defm : X86WriteRes<WriteBitTestRegLd, [SBPort05,SBPort23], 6, [1,1], 2>; 180defm : X86WriteRes<WriteBitTestSet, [SBPort05], 1, [1], 1>; 181defm : X86WriteRes<WriteBitTestSetImmLd, [SBPort05,SBPort23], 6, [1,1], 3>; 182defm : X86WriteRes<WriteBitTestSetRegLd, [SBPort05,SBPort23,SBPort5,SBPort015], 8, [1,1,1,1], 5>; 183 184// This is for simple LEAs with one or two input operands. 185// The complex ones can only execute on port 1, and they require two cycles on 186// the port to read all inputs. We don't model that. 187def : WriteRes<WriteLEA, [SBPort01]>; 188 189// Bit counts. 190defm : SBWriteResPair<WriteBSF, [SBPort1], 3, [1], 1, 5>; 191defm : SBWriteResPair<WriteBSR, [SBPort1], 3, [1], 1, 5>; 192defm : SBWriteResPair<WriteLZCNT, [SBPort1], 3, [1], 1, 5>; 193defm : SBWriteResPair<WriteTZCNT, [SBPort1], 3, [1], 1, 5>; 194defm : SBWriteResPair<WritePOPCNT, [SBPort1], 3, [1], 1, 6>; 195 196// BMI1 BEXTR/BLS, BMI2 BZHI 197// NOTE: These don't exist on Sandy Bridge. Ports are guesses. 198defm : SBWriteResPair<WriteBEXTR, [SBPort05,SBPort1], 2, [1,1], 2>; 199defm : SBWriteResPair<WriteBLS, [SBPort015], 1>; 200defm : SBWriteResPair<WriteBZHI, [SBPort1], 1>; 201 202// Scalar and vector floating point. 203defm : X86WriteRes<WriteFLD0, [SBPort5], 1, [1], 1>; 204defm : X86WriteRes<WriteFLD1, [SBPort0,SBPort5], 1, [1,1], 2>; 205defm : X86WriteRes<WriteFLDC, [SBPort0,SBPort1], 1, [1,1], 2>; 206defm : X86WriteRes<WriteFLoad, [SBPort23], 5, [1], 1>; 207defm : X86WriteRes<WriteFLoadX, [SBPort23], 6, [1], 1>; 208defm : X86WriteRes<WriteFLoadY, [SBPort23], 7, [1], 1>; 209defm : X86WriteRes<WriteFMaskedLoad, [SBPort23,SBPort05], 8, [1,2], 3>; 210defm : X86WriteRes<WriteFMaskedLoadY, [SBPort23,SBPort05], 9, [1,2], 3>; 211defm : X86WriteRes<WriteFStore, [SBPort23,SBPort4], 1, [1,1], 1>; 212defm : X86WriteRes<WriteFStoreX, [SBPort23,SBPort4], 1, [1,1], 1>; 213defm : X86WriteRes<WriteFStoreY, [SBPort23,SBPort4], 1, [1,1], 1>; 214defm : X86WriteRes<WriteFStoreNT, [SBPort23,SBPort4], 1, [1,1], 1>; 215defm : X86WriteRes<WriteFStoreNTX, [SBPort23,SBPort4], 1, [1,1], 1>; 216defm : X86WriteRes<WriteFStoreNTY, [SBPort23,SBPort4], 1, [1,1], 1>; 217 218defm : X86WriteRes<WriteFMaskedStore32, [SBPort4,SBPort01,SBPort23], 5, [1,1,1], 3>; 219defm : X86WriteRes<WriteFMaskedStore32Y, [SBPort4,SBPort01,SBPort23], 5, [1,1,1], 3>; 220defm : X86WriteRes<WriteFMaskedStore64, [SBPort4,SBPort01,SBPort23], 5, [1,1,1], 3>; 221defm : X86WriteRes<WriteFMaskedStore64Y, [SBPort4,SBPort01,SBPort23], 5, [1,1,1], 3>; 222 223defm : X86WriteRes<WriteFMove, [SBPort5], 1, [1], 1>; 224defm : X86WriteRes<WriteFMoveX, [SBPort5], 1, [1], 1>; 225defm : X86WriteRes<WriteFMoveY, [SBPort5], 1, [1], 1>; 226defm : X86WriteRes<WriteFMoveZ, [SBPort5], 1, [1], 1>; 227defm : X86WriteRes<WriteEMMS, [SBPort015], 31, [31], 31>; 228 229defm : SBWriteResPair<WriteFAdd, [SBPort1], 3, [1], 1, 6>; 230defm : SBWriteResPair<WriteFAddX, [SBPort1], 3, [1], 1, 6>; 231defm : SBWriteResPair<WriteFAddY, [SBPort1], 3, [1], 1, 7>; 232defm : SBWriteResPair<WriteFAddZ, [SBPort1], 3, [1], 1, 7>; // Unsupported = 1 233defm : SBWriteResPair<WriteFAdd64, [SBPort1], 3, [1], 1, 6>; 234defm : SBWriteResPair<WriteFAdd64X, [SBPort1], 3, [1], 1, 6>; 235defm : SBWriteResPair<WriteFAdd64Y, [SBPort1], 3, [1], 1, 7>; 236defm : SBWriteResPair<WriteFAdd64Z, [SBPort1], 3, [1], 1, 7>; // Unsupported = 1 237 238defm : SBWriteResPair<WriteFCmp, [SBPort1], 3, [1], 1, 6>; 239defm : SBWriteResPair<WriteFCmpX, [SBPort1], 3, [1], 1, 6>; 240defm : SBWriteResPair<WriteFCmpY, [SBPort1], 3, [1], 1, 7>; 241defm : SBWriteResPair<WriteFCmpZ, [SBPort1], 3, [1], 1, 7>; // Unsupported = 1 242defm : SBWriteResPair<WriteFCmp64, [SBPort1], 3, [1], 1, 6>; 243defm : SBWriteResPair<WriteFCmp64X, [SBPort1], 3, [1], 1, 6>; 244defm : SBWriteResPair<WriteFCmp64Y, [SBPort1], 3, [1], 1, 7>; 245defm : SBWriteResPair<WriteFCmp64Z, [SBPort1], 3, [1], 1, 7>; // Unsupported = 1 246 247defm : SBWriteResPair<WriteFCom, [SBPort1], 3>; 248defm : SBWriteResPair<WriteFComX, [SBPort1], 3>; 249 250defm : SBWriteResPair<WriteFMul, [SBPort0], 5, [1], 1, 6>; 251defm : SBWriteResPair<WriteFMulX, [SBPort0], 5, [1], 1, 6>; 252defm : SBWriteResPair<WriteFMulY, [SBPort0], 5, [1], 1, 7>; 253defm : SBWriteResPair<WriteFMulZ, [SBPort0], 5, [1], 1, 7>; // Unsupported = 1 254defm : SBWriteResPair<WriteFMul64, [SBPort0], 5, [1], 1, 6>; 255defm : SBWriteResPair<WriteFMul64X, [SBPort0], 5, [1], 1, 6>; 256defm : SBWriteResPair<WriteFMul64Y, [SBPort0], 5, [1], 1, 7>; 257defm : SBWriteResPair<WriteFMul64Z, [SBPort0], 5, [1], 1, 7>; // Unsupported = 1 258 259defm : SBWriteResPair<WriteFDiv, [SBPort0,SBFPDivider], 14, [1,14], 1, 6>; 260defm : SBWriteResPair<WriteFDivX, [SBPort0,SBFPDivider], 14, [1,14], 1, 6>; 261defm : SBWriteResPair<WriteFDivY, [SBPort0,SBPort05,SBFPDivider], 29, [2,1,28], 3, 7>; 262defm : SBWriteResPair<WriteFDivZ, [SBPort0,SBPort05,SBFPDivider], 29, [2,1,28], 3, 7>; // Unsupported = 1 263defm : SBWriteResPair<WriteFDiv64, [SBPort0,SBFPDivider], 22, [1,22], 1, 6>; 264defm : SBWriteResPair<WriteFDiv64X, [SBPort0,SBFPDivider], 22, [1,22], 1, 6>; 265defm : SBWriteResPair<WriteFDiv64Y, [SBPort0,SBPort05,SBFPDivider], 45, [2,1,44], 3, 7>; 266defm : SBWriteResPair<WriteFDiv64Z, [SBPort0,SBPort05,SBFPDivider], 45, [2,1,44], 3, 7>; // Unsupported = 1 267 268defm : SBWriteResPair<WriteFRcp, [SBPort0], 5, [1], 1, 6>; 269defm : SBWriteResPair<WriteFRcpX, [SBPort0], 5, [1], 1, 6>; 270defm : SBWriteResPair<WriteFRcpY, [SBPort0,SBPort05], 7, [2,1], 3, 7>; 271defm : SBWriteResPair<WriteFRcpZ, [SBPort0,SBPort05], 7, [2,1], 3, 7>; // Unsupported = 1 272 273defm : SBWriteResPair<WriteFRsqrt, [SBPort0], 5, [1], 1, 6>; 274defm : SBWriteResPair<WriteFRsqrtX,[SBPort0], 5, [1], 1, 6>; 275defm : SBWriteResPair<WriteFRsqrtY,[SBPort0,SBPort05], 7, [2,1], 3, 7>; 276defm : SBWriteResPair<WriteFRsqrtZ,[SBPort0,SBPort05], 7, [2,1], 3, 7>; // Unsupported = 1 277 278defm : SBWriteResPair<WriteFSqrt, [SBPort0,SBFPDivider], 14, [1,14], 1, 6>; 279defm : SBWriteResPair<WriteFSqrtX, [SBPort0,SBFPDivider], 14, [1,14], 1, 6>; 280defm : SBWriteResPair<WriteFSqrtY, [SBPort0,SBPort05,SBFPDivider], 29, [2,1,28], 3, 7>; 281defm : SBWriteResPair<WriteFSqrtZ, [SBPort0,SBPort05,SBFPDivider], 29, [2,1,28], 3, 7>; // Unsupported = 1 282defm : SBWriteResPair<WriteFSqrt64, [SBPort0,SBFPDivider], 21, [1,21], 1, 6>; 283defm : SBWriteResPair<WriteFSqrt64X, [SBPort0,SBFPDivider], 21, [1,21], 1, 6>; 284defm : SBWriteResPair<WriteFSqrt64Y, [SBPort0,SBPort05,SBFPDivider], 45, [2,1,44], 3, 7>; 285defm : SBWriteResPair<WriteFSqrt64Z, [SBPort0,SBPort05,SBFPDivider], 45, [2,1,44], 3, 7>; // Unsupported = 1 286defm : SBWriteResPair<WriteFSqrt80, [SBPort0,SBFPDivider], 24, [1,24], 1, 6>; 287 288defm : SBWriteResPair<WriteDPPD, [SBPort0,SBPort1,SBPort5], 9, [1,1,1], 3, 6>; 289defm : SBWriteResPair<WriteDPPS, [SBPort0,SBPort1,SBPort5], 12, [1,2,1], 4, 6>; 290defm : SBWriteResPair<WriteDPPSY, [SBPort0,SBPort1,SBPort5], 12, [1,2,1], 4, 7>; 291defm : SBWriteResPair<WriteDPPSZ, [SBPort0,SBPort1,SBPort5], 12, [1,2,1], 4, 7>; // Unsupported = 1 292defm : SBWriteResPair<WriteFSign, [SBPort5], 1>; 293defm : SBWriteResPair<WriteFRnd, [SBPort1], 3, [1], 1, 6>; 294defm : SBWriteResPair<WriteFRndY, [SBPort1], 3, [1], 1, 7>; 295defm : SBWriteResPair<WriteFRndZ, [SBPort1], 3, [1], 1, 7>; // Unsupported = 1 296defm : SBWriteResPair<WriteFLogic, [SBPort5], 1, [1], 1, 6>; 297defm : SBWriteResPair<WriteFLogicY, [SBPort5], 1, [1], 1, 7>; 298defm : SBWriteResPair<WriteFLogicZ, [SBPort5], 1, [1], 1, 7>; // Unsupported = 1 299defm : SBWriteResPair<WriteFTest, [SBPort0], 1, [1], 1, 6>; 300defm : SBWriteResPair<WriteFTestY, [SBPort0], 1, [1], 1, 7>; 301defm : SBWriteResPair<WriteFTestZ, [SBPort0], 1, [1], 1, 7>; // Unsupported = 1 302defm : SBWriteResPair<WriteFShuffle, [SBPort5], 1, [1], 1, 6>; 303defm : SBWriteResPair<WriteFShuffleY,[SBPort5], 1, [1], 1, 7>; 304defm : SBWriteResPair<WriteFShuffleZ,[SBPort5], 1, [1], 1, 7>; // Unsupported = 1 305defm : SBWriteResPair<WriteFVarShuffle, [SBPort5], 1, [1], 1, 6>; 306defm : SBWriteResPair<WriteFVarShuffleY,[SBPort5], 1, [1], 1, 7>; 307defm : SBWriteResPair<WriteFVarShuffleZ,[SBPort5], 1, [1], 1, 7>; // Unsupported = 1 308defm : SBWriteResPair<WriteFBlend, [SBPort05], 1, [1], 1, 6>; 309defm : SBWriteResPair<WriteFBlendY, [SBPort05], 1, [1], 1, 7>; 310defm : SBWriteResPair<WriteFBlendZ, [SBPort05], 1, [1], 1, 7>; // Unsupported = 1 311defm : SBWriteResPair<WriteFVarBlend, [SBPort05], 2, [2], 2, 6>; 312defm : SBWriteResPair<WriteFVarBlendY,[SBPort05], 2, [2], 2, 7>; 313defm : SBWriteResPair<WriteFVarBlendZ,[SBPort05], 2, [2], 2, 7>; // Unsupported = 1 314 315// Conversion between integer and float. 316defm : SBWriteResPair<WriteCvtSS2I, [SBPort0,SBPort1], 5, [1,1], 2>; 317defm : SBWriteResPair<WriteCvtPS2I, [SBPort1], 3, [1], 1, 6>; 318defm : SBWriteResPair<WriteCvtPS2IY, [SBPort1], 3, [1], 1, 7>; 319defm : SBWriteResPair<WriteCvtPS2IZ, [SBPort1], 3, [1], 1, 7>; // Unsupported = 1 320defm : SBWriteResPair<WriteCvtSD2I, [SBPort0,SBPort1], 5, [1,1], 2>; 321defm : SBWriteResPair<WriteCvtPD2I, [SBPort1,SBPort5], 4, [1,1], 2, 6>; 322defm : X86WriteRes<WriteCvtPD2IY, [SBPort1,SBPort5], 4, [1,1], 2>; 323defm : X86WriteRes<WriteCvtPD2IZ, [SBPort1,SBPort5], 4, [1,1], 2>; // Unsupported = 1 324defm : X86WriteRes<WriteCvtPD2IYLd, [SBPort1,SBPort5,SBPort23], 11, [1,1,1], 3>; 325defm : X86WriteRes<WriteCvtPD2IZLd, [SBPort1,SBPort5,SBPort23], 11, [1,1,1], 3>; // Unsupported = 1 326 327defm : X86WriteRes<WriteCvtI2SS, [SBPort1,SBPort5], 5, [1,2], 3>; 328defm : X86WriteRes<WriteCvtI2SSLd, [SBPort1,SBPort5,SBPort23], 10, [1,1,1], 3>; 329defm : SBWriteResPair<WriteCvtI2PS, [SBPort1], 3, [1], 1, 6>; 330defm : SBWriteResPair<WriteCvtI2PSY, [SBPort1], 3, [1], 1, 7>; 331defm : SBWriteResPair<WriteCvtI2PSZ, [SBPort1], 3, [1], 1, 7>; // Unsupported = 1 332defm : X86WriteRes<WriteCvtI2SD, [SBPort1,SBPort5], 4, [1,1], 2>; 333defm : X86WriteRes<WriteCvtI2PD, [SBPort1,SBPort5], 4, [1,1], 2>; 334defm : X86WriteRes<WriteCvtI2PDY, [SBPort1,SBPort5], 4, [1,1], 2>; 335defm : X86WriteRes<WriteCvtI2PDZ, [SBPort1,SBPort5], 4, [1,1], 2>; // Unsupported = 1 336defm : X86WriteRes<WriteCvtI2SDLd, [SBPort1,SBPort23], 9, [1,1], 2>; 337defm : X86WriteRes<WriteCvtI2PDLd, [SBPort1,SBPort5,SBPort23], 10, [1,1,1], 3>; 338defm : X86WriteRes<WriteCvtI2PDYLd, [SBPort1,SBPort5,SBPort23], 10, [1,1,1], 3>; 339defm : X86WriteRes<WriteCvtI2PDZLd, [SBPort1,SBPort5,SBPort23], 10, [1,1,1], 3>; // Unsupported = 1 340 341defm : SBWriteResPair<WriteCvtSS2SD, [SBPort0], 1, [1], 1, 6>; 342defm : X86WriteRes<WriteCvtPS2PD, [SBPort0,SBPort5], 2, [1,1], 2>; 343defm : X86WriteRes<WriteCvtPS2PDY, [SBPort0,SBPort5], 2, [1,1], 2>; 344defm : X86WriteRes<WriteCvtPS2PDZ, [SBPort0,SBPort5], 2, [1,1], 2>; // Unsupported = 1 345defm : X86WriteRes<WriteCvtPS2PDLd, [SBPort0,SBPort23], 7, [1,1], 2>; 346defm : X86WriteRes<WriteCvtPS2PDYLd, [SBPort0,SBPort23], 7, [1,1], 2>; 347defm : X86WriteRes<WriteCvtPS2PDZLd, [SBPort0,SBPort23], 7, [1,1], 2>; // Unsupported = 1 348defm : SBWriteResPair<WriteCvtSD2SS, [SBPort1,SBPort5], 4, [1,1], 2, 6>; 349defm : SBWriteResPair<WriteCvtPD2PS, [SBPort1,SBPort5], 4, [1,1], 2, 6>; 350defm : SBWriteResPair<WriteCvtPD2PSY, [SBPort1,SBPort5], 4, [1,1], 2, 7>; 351defm : SBWriteResPair<WriteCvtPD2PSZ, [SBPort1,SBPort5], 4, [1,1], 2, 7>; // Unsupported = 1 352 353defm : SBWriteResPair<WriteCvtPH2PS, [SBPort1], 3>; 354defm : SBWriteResPair<WriteCvtPH2PSY, [SBPort1], 3>; 355defm : SBWriteResPair<WriteCvtPH2PSZ, [SBPort1], 3>; // Unsupported = 1 356 357defm : X86WriteRes<WriteCvtPS2PH, [SBPort1], 3, [1], 1>; 358defm : X86WriteRes<WriteCvtPS2PHY, [SBPort1], 3, [1], 1>; 359defm : X86WriteRes<WriteCvtPS2PHZ, [SBPort1], 3, [1], 1>; // Unsupported = 1 360defm : X86WriteRes<WriteCvtPS2PHSt, [SBPort1, SBPort23, SBPort4], 4, [1,1,1], 1>; 361defm : X86WriteRes<WriteCvtPS2PHYSt, [SBPort1, SBPort23, SBPort4], 4, [1,1,1], 1>; 362defm : X86WriteRes<WriteCvtPS2PHZSt, [SBPort1, SBPort23, SBPort4], 4, [1,1,1], 1>; // Unsupported = 1 363 364// Vector integer operations. 365defm : X86WriteRes<WriteVecLoad, [SBPort23], 5, [1], 1>; 366defm : X86WriteRes<WriteVecLoadX, [SBPort23], 6, [1], 1>; 367defm : X86WriteRes<WriteVecLoadY, [SBPort23], 7, [1], 1>; 368defm : X86WriteRes<WriteVecLoadNT, [SBPort23], 6, [1], 1>; 369defm : X86WriteRes<WriteVecLoadNTY, [SBPort23], 7, [1], 1>; 370defm : X86WriteRes<WriteVecMaskedLoad, [SBPort23,SBPort05], 8, [1,2], 3>; 371defm : X86WriteRes<WriteVecMaskedLoadY, [SBPort23,SBPort05], 9, [1,2], 3>; 372defm : X86WriteRes<WriteVecStore, [SBPort23,SBPort4], 1, [1,1], 1>; 373defm : X86WriteRes<WriteVecStoreX, [SBPort23,SBPort4], 1, [1,1], 1>; 374defm : X86WriteRes<WriteVecStoreY, [SBPort23,SBPort4], 1, [1,1], 1>; 375defm : X86WriteRes<WriteVecStoreNT, [SBPort23,SBPort4], 1, [1,1], 1>; 376defm : X86WriteRes<WriteVecStoreNTY, [SBPort23,SBPort4], 1, [1,1], 1>; 377defm : X86WriteRes<WriteVecMaskedStore32, [SBPort4,SBPort01,SBPort23], 5, [1,1,1], 3>; 378defm : X86WriteRes<WriteVecMaskedStore32Y, [SBPort4,SBPort01,SBPort23], 5, [1,1,1], 3>; 379defm : X86WriteRes<WriteVecMaskedStore64, [SBPort4,SBPort01,SBPort23], 5, [1,1,1], 3>; 380defm : X86WriteRes<WriteVecMaskedStore64Y, [SBPort4,SBPort01,SBPort23], 5, [1,1,1], 3>; 381defm : X86WriteRes<WriteVecMove, [SBPort05], 1, [1], 1>; 382defm : X86WriteRes<WriteVecMoveX, [SBPort015], 1, [1], 1>; 383defm : X86WriteRes<WriteVecMoveY, [SBPort05], 1, [1], 1>; 384defm : X86WriteRes<WriteVecMoveZ, [SBPort05], 1, [1], 1>; 385defm : X86WriteRes<WriteVecMoveToGpr, [SBPort0], 2, [1], 1>; 386defm : X86WriteRes<WriteVecMoveFromGpr, [SBPort5], 1, [1], 1>; 387 388defm : SBWriteResPair<WriteVecLogic, [SBPort015], 1, [1], 1, 5>; 389defm : SBWriteResPair<WriteVecLogicX,[SBPort015], 1, [1], 1, 6>; 390defm : SBWriteResPair<WriteVecLogicY,[SBPort015], 1, [1], 1, 7>; 391defm : SBWriteResPair<WriteVecLogicZ,[SBPort015], 1, [1], 1, 7>; // Unsupported = 1 392defm : SBWriteResPair<WriteVecTest, [SBPort0,SBPort5], 2, [1,1], 2, 6>; 393defm : SBWriteResPair<WriteVecTestY, [SBPort0,SBPort5], 2, [1,1], 2, 7>; 394defm : SBWriteResPair<WriteVecTestZ, [SBPort0,SBPort5], 2, [1,1], 2, 7>; // Unsupported = 1 395defm : SBWriteResPair<WriteVecALU, [SBPort1], 3, [1], 1, 5>; 396defm : SBWriteResPair<WriteVecALUX, [SBPort15], 1, [1], 1, 6>; 397defm : SBWriteResPair<WriteVecALUY, [SBPort15], 1, [1], 1, 7>; 398defm : SBWriteResPair<WriteVecALUZ, [SBPort15], 1, [1], 1, 7>; // Unsupported = 1 399defm : SBWriteResPair<WriteVecIMul, [SBPort0], 5, [1], 1, 5>; 400defm : SBWriteResPair<WriteVecIMulX, [SBPort0], 5, [1], 1, 6>; 401defm : SBWriteResPair<WriteVecIMulY, [SBPort0], 5, [1], 1, 7>; 402defm : SBWriteResPair<WriteVecIMulZ, [SBPort0], 5, [1], 1, 7>; // Unsupported = 1 403defm : SBWriteResPair<WritePMULLD, [SBPort0], 5, [1], 1, 6>; 404defm : SBWriteResPair<WritePMULLDY, [SBPort0], 5, [1], 1, 7>; // TODO this is probably wrong for 256/512-bit for the "generic" model 405defm : SBWriteResPair<WritePMULLDZ, [SBPort0], 5, [1], 1, 7>; // Unsupported = 1 406defm : SBWriteResPair<WriteShuffle, [SBPort5], 1, [1], 1, 5>; 407defm : SBWriteResPair<WriteShuffleX, [SBPort15], 1, [1], 1, 6>; 408defm : SBWriteResPair<WriteShuffleY, [SBPort5], 1, [1], 1, 7>; 409defm : SBWriteResPair<WriteShuffleZ, [SBPort5], 1, [1], 1, 7>; // Unsupported = 1 410defm : SBWriteResPair<WriteVarShuffle, [SBPort15], 1, [1], 1, 5>; 411defm : SBWriteResPair<WriteVarShuffleX, [SBPort15], 1, [1], 1, 6>; 412defm : SBWriteResPair<WriteVarShuffleY, [SBPort15], 1, [1], 1, 7>; 413defm : SBWriteResPair<WriteVarShuffleZ, [SBPort15], 1, [1], 1, 7>; // Unsupported = 1 414defm : SBWriteResPair<WriteBlend, [SBPort15], 1, [1], 1, 6>; 415defm : SBWriteResPair<WriteBlendY, [SBPort15], 1, [1], 1, 7>; 416defm : SBWriteResPair<WriteBlendZ, [SBPort15], 1, [1], 1, 7>; // Unsupported = 1 417defm : SBWriteResPair<WriteVarBlend, [SBPort15], 2, [2], 2, 6>; 418defm : SBWriteResPair<WriteVarBlendY,[SBPort15], 2, [2], 2, 7>; 419defm : SBWriteResPair<WriteVarBlendZ,[SBPort15], 2, [2], 2, 7>; // Unsupported = 1 420defm : SBWriteResPair<WriteMPSAD, [SBPort0, SBPort15], 7, [1,2], 3, 6>; 421defm : SBWriteResPair<WriteMPSADY, [SBPort0, SBPort15], 7, [1,2], 3, 7>; 422defm : SBWriteResPair<WriteMPSADZ, [SBPort0, SBPort15], 7, [1,2], 3, 7>; // Unsupported = 1 423defm : SBWriteResPair<WritePSADBW, [SBPort0], 5, [1], 1, 5>; 424defm : SBWriteResPair<WritePSADBWX, [SBPort0], 5, [1], 1, 6>; 425defm : SBWriteResPair<WritePSADBWY, [SBPort0], 5, [1], 1, 7>; 426defm : SBWriteResPair<WritePSADBWZ, [SBPort0], 5, [1], 1, 7>; // Unsupported = 1 427defm : SBWriteResPair<WritePHMINPOS, [SBPort0], 5, [1], 1, 6>; 428 429// Vector integer shifts. 430defm : SBWriteResPair<WriteVecShift, [SBPort5], 1, [1], 1, 5>; 431defm : SBWriteResPair<WriteVecShiftX, [SBPort0,SBPort15], 2, [1,1], 2, 6>; 432defm : SBWriteResPair<WriteVecShiftY, [SBPort0,SBPort15], 4, [1,1], 2, 7>; 433defm : SBWriteResPair<WriteVecShiftZ, [SBPort0,SBPort15], 4, [1,1], 2, 7>; // Unsupported = 1 434defm : SBWriteResPair<WriteVecShiftImm, [SBPort5], 1, [1], 1, 5>; 435defm : SBWriteResPair<WriteVecShiftImmX, [SBPort0], 1, [1], 1, 6>; 436defm : SBWriteResPair<WriteVecShiftImmY, [SBPort0], 1, [1], 1, 7>; 437defm : SBWriteResPair<WriteVecShiftImmZ, [SBPort0], 1, [1], 1, 7>; // Unsupported = 1 438defm : SBWriteResPair<WriteVarVecShift, [SBPort0], 1, [1], 1, 6>; 439defm : SBWriteResPair<WriteVarVecShiftY, [SBPort0], 1, [1], 1, 7>; 440defm : SBWriteResPair<WriteVarVecShiftZ, [SBPort0], 1, [1], 1, 7>; // Unsupported = 1 441 442// Vector insert/extract operations. 443def : WriteRes<WriteVecInsert, [SBPort5,SBPort15]> { 444 let Latency = 2; 445 let NumMicroOps = 2; 446} 447def : WriteRes<WriteVecInsertLd, [SBPort23,SBPort15]> { 448 let Latency = 7; 449 let NumMicroOps = 2; 450} 451 452def : WriteRes<WriteVecExtract, [SBPort0,SBPort15]> { 453 let Latency = 3; 454 let NumMicroOps = 2; 455} 456def : WriteRes<WriteVecExtractSt, [SBPort4,SBPort23,SBPort15]> { 457 let Latency = 5; 458 let NumMicroOps = 3; 459} 460 461//////////////////////////////////////////////////////////////////////////////// 462// Horizontal add/sub instructions. 463//////////////////////////////////////////////////////////////////////////////// 464 465defm : SBWriteResPair<WriteFHAdd, [SBPort1,SBPort5], 5, [1,2], 3, 6>; 466defm : SBWriteResPair<WriteFHAddY, [SBPort1,SBPort5], 5, [1,2], 3, 7>; 467defm : SBWriteResPair<WriteFHAddZ, [SBPort1,SBPort5], 5, [1,2], 3, 7>; // Unsupported = 1 468defm : SBWriteResPair<WritePHAdd, [SBPort15], 3, [3], 3, 5>; 469defm : SBWriteResPair<WritePHAddX, [SBPort15], 3, [3], 3, 6>; 470defm : SBWriteResPair<WritePHAddY, [SBPort15], 3, [3], 3, 7>; 471defm : SBWriteResPair<WritePHAddZ, [SBPort15], 3, [3], 3, 7>; // Unsupported = 1 472 473//////////////////////////////////////////////////////////////////////////////// 474// String instructions. 475//////////////////////////////////////////////////////////////////////////////// 476 477// Packed Compare Implicit Length Strings, Return Mask 478def : WriteRes<WritePCmpIStrM, [SBPort0]> { 479 let Latency = 11; 480 let NumMicroOps = 3; 481 let ResourceCycles = [3]; 482} 483def : WriteRes<WritePCmpIStrMLd, [SBPort0, SBPort23]> { 484 let Latency = 17; 485 let NumMicroOps = 4; 486 let ResourceCycles = [3,1]; 487} 488 489// Packed Compare Explicit Length Strings, Return Mask 490def : WriteRes<WritePCmpEStrM, [SBPort015]> { 491 let Latency = 11; 492 let ResourceCycles = [8]; 493} 494def : WriteRes<WritePCmpEStrMLd, [SBPort015, SBPort23]> { 495 let Latency = 17; 496 let ResourceCycles = [7, 1]; 497} 498 499// Packed Compare Implicit Length Strings, Return Index 500def : WriteRes<WritePCmpIStrI, [SBPort0]> { 501 let Latency = 11; 502 let NumMicroOps = 3; 503 let ResourceCycles = [3]; 504} 505def : WriteRes<WritePCmpIStrILd, [SBPort0,SBPort23]> { 506 let Latency = 17; 507 let NumMicroOps = 4; 508 let ResourceCycles = [3,1]; 509} 510 511// Packed Compare Explicit Length Strings, Return Index 512def : WriteRes<WritePCmpEStrI, [SBPort015]> { 513 let Latency = 4; 514 let ResourceCycles = [8]; 515} 516def : WriteRes<WritePCmpEStrILd, [SBPort015, SBPort23]> { 517 let Latency = 10; 518 let ResourceCycles = [7, 1]; 519} 520 521// MOVMSK Instructions. 522def : WriteRes<WriteFMOVMSK, [SBPort0]> { let Latency = 2; } 523def : WriteRes<WriteVecMOVMSK, [SBPort0]> { let Latency = 2; } 524def : WriteRes<WriteVecMOVMSKY, [SBPort0]> { let Latency = 2; } 525def : WriteRes<WriteMMXMOVMSK, [SBPort0]> { let Latency = 1; } 526 527// AES Instructions. 528def : WriteRes<WriteAESDecEnc, [SBPort5,SBPort015]> { 529 let Latency = 7; 530 let NumMicroOps = 2; 531 let ResourceCycles = [1,1]; 532} 533def : WriteRes<WriteAESDecEncLd, [SBPort5,SBPort23,SBPort015]> { 534 let Latency = 13; 535 let NumMicroOps = 3; 536 let ResourceCycles = [1,1,1]; 537} 538 539def : WriteRes<WriteAESIMC, [SBPort5]> { 540 let Latency = 12; 541 let NumMicroOps = 2; 542 let ResourceCycles = [2]; 543} 544def : WriteRes<WriteAESIMCLd, [SBPort5,SBPort23]> { 545 let Latency = 18; 546 let NumMicroOps = 3; 547 let ResourceCycles = [2,1]; 548} 549 550def : WriteRes<WriteAESKeyGen, [SBPort015]> { 551 let Latency = 8; 552 let ResourceCycles = [11]; 553} 554def : WriteRes<WriteAESKeyGenLd, [SBPort015, SBPort23]> { 555 let Latency = 14; 556 let ResourceCycles = [10, 1]; 557} 558 559// Carry-less multiplication instructions. 560def : WriteRes<WriteCLMul, [SBPort015]> { 561 let Latency = 14; 562 let ResourceCycles = [18]; 563} 564def : WriteRes<WriteCLMulLd, [SBPort015, SBPort23]> { 565 let Latency = 20; 566 let ResourceCycles = [17, 1]; 567} 568 569// Load/store MXCSR. 570// FIXME: This is probably wrong. Only STMXCSR should require Port4. 571def : WriteRes<WriteLDMXCSR, [SBPort0,SBPort4,SBPort5,SBPort23]> { let Latency = 5; let NumMicroOps = 4; let ResourceCycles = [1,1,1,1]; } 572def : WriteRes<WriteSTMXCSR, [SBPort0,SBPort4,SBPort5,SBPort23]> { let Latency = 5; let NumMicroOps = 4; let ResourceCycles = [1,1,1,1]; } 573 574def : WriteRes<WriteSystem, [SBPort015]> { let Latency = 100; } 575def : WriteRes<WriteMicrocoded, [SBPort015]> { let Latency = 100; } 576def : WriteRes<WriteFence, [SBPort23, SBPort4]>; 577def : WriteRes<WriteNop, []>; 578 579// AVX2/FMA is not supported on that architecture, but we should define the basic 580// scheduling resources anyway. 581defm : SBWriteResPair<WriteFShuffle256, [SBPort5], 1, [1], 1, 7>; 582defm : SBWriteResPair<WriteFVarShuffle256, [SBPort5], 1, [1], 1, 7>; 583defm : SBWriteResPair<WriteShuffle256, [SBPort5], 1, [1], 1, 7>; 584defm : SBWriteResPair<WriteVPMOV256, [SBPort5], 1, [1], 1, 7>; 585defm : SBWriteResPair<WriteVarShuffle256, [SBPort5], 1, [1], 1, 7>; 586defm : SBWriteResPair<WriteFMA, [SBPort01], 5>; 587defm : SBWriteResPair<WriteFMAX, [SBPort01], 5>; 588defm : SBWriteResPair<WriteFMAY, [SBPort01], 5>; 589defm : SBWriteResPair<WriteFMAZ, [SBPort01], 5>; // Unsupported = 1 590 591// Remaining SNB instrs. 592 593def SBWriteResGroup1 : SchedWriteRes<[SBPort1]> { 594 let Latency = 1; 595 let NumMicroOps = 1; 596 let ResourceCycles = [1]; 597} 598def: InstRW<[SBWriteResGroup1], (instrs COMP_FST0r, 599 COM_FST0r, 600 UCOM_FPr, 601 UCOM_Fr)>; 602 603def SBWriteResGroup2 : SchedWriteRes<[SBPort5]> { 604 let Latency = 1; 605 let NumMicroOps = 1; 606 let ResourceCycles = [1]; 607} 608def: InstRW<[SBWriteResGroup2], (instrs FDECSTP, FINCSTP, FFREE, FFREEP, FNOP, 609 LD_Frr, ST_Frr, ST_FPrr)>; 610def: InstRW<[SBWriteResGroup2], (instrs LOOP, LOOPE, LOOPNE)>; // FIXME: This seems wrong compared to other Intel CPUs. 611def: InstRW<[SBWriteResGroup2], (instrs RET64)>; 612 613def SBWriteResGroup4 : SchedWriteRes<[SBPort05]> { 614 let Latency = 1; 615 let NumMicroOps = 1; 616 let ResourceCycles = [1]; 617} 618def: InstRW<[SBWriteResGroup4], (instrs CDQ, CQO)>; 619 620def SBWriteResGroup5 : SchedWriteRes<[SBPort15]> { 621 let Latency = 1; 622 let NumMicroOps = 1; 623 let ResourceCycles = [1]; 624} 625def: InstRW<[SBWriteResGroup5], (instrs MMX_PABSBrr, 626 MMX_PABSDrr, 627 MMX_PABSWrr, 628 MMX_PADDQrr, 629 MMX_PALIGNRrri, 630 MMX_PSIGNBrr, 631 MMX_PSIGNDrr, 632 MMX_PSIGNWrr)>; 633 634def SBWriteResGroup11 : SchedWriteRes<[SBPort015]> { 635 let Latency = 2; 636 let NumMicroOps = 2; 637 let ResourceCycles = [2]; 638} 639def: InstRW<[SBWriteResGroup11], (instrs SCASB, 640 SCASL, 641 SCASQ, 642 SCASW)>; 643 644def SBWriteResGroup12 : SchedWriteRes<[SBPort0,SBPort1]> { 645 let Latency = 2; 646 let NumMicroOps = 2; 647 let ResourceCycles = [1,1]; 648} 649def: InstRW<[SBWriteResGroup12], (instregex "(V?)(U?)COMI(SD|SS)rr")>; 650 651def SBWriteResGroup15 : SchedWriteRes<[SBPort0,SBPort015]> { 652 let Latency = 2; 653 let NumMicroOps = 2; 654 let ResourceCycles = [1,1]; 655} 656def: InstRW<[SBWriteResGroup15], (instrs CWD, 657 FNSTSW16r)>; 658 659def SBWriteResGroup18 : SchedWriteRes<[SBPort5,SBPort015]> { 660 let Latency = 2; 661 let NumMicroOps = 2; 662 let ResourceCycles = [1,1]; 663} 664def: InstRW<[SBWriteResGroup18], (instrs JCXZ, JECXZ, JRCXZ, 665 MMX_MOVDQ2Qrr)>; 666 667def SBWriteResGroup21 : SchedWriteRes<[SBPort1]> { 668 let Latency = 3; 669 let NumMicroOps = 1; 670 let ResourceCycles = [1]; 671} 672def: InstRW<[SBWriteResGroup21], (instrs PUSHFS64)>; 673 674def SBWriteResGroup22 : SchedWriteRes<[SBPort0,SBPort5]> { 675 let Latency = 3; 676 let NumMicroOps = 2; 677 let ResourceCycles = [1,1]; 678} 679def: InstRW<[SBWriteResGroup22], (instregex "(V?)EXTRACTPSrr")>; 680 681def SBWriteResGroup23 : SchedWriteRes<[SBPort05]> { 682 let Latency = 2; 683 let NumMicroOps = 3; 684 let ResourceCycles = [3]; 685} 686def: InstRW<[SBWriteResGroup23], (instregex "RCL(8|16|32|64)r1", 687 "RCR(8|16|32|64)r1")>; 688 689def SBWriteResGroup25_1 : SchedWriteRes<[SBPort23,SBPort015]> { 690 let Latency = 7; 691 let NumMicroOps = 3; 692 let ResourceCycles = [1,2]; 693} 694def: InstRW<[SBWriteResGroup25_1], (instrs LEAVE, LEAVE64)>; 695 696def SBWriteResGroup26_2 : SchedWriteRes<[SBPort0,SBPort1,SBPort5]> { 697 let Latency = 3; 698 let NumMicroOps = 3; 699 let ResourceCycles = [1,1,1]; 700} 701def: InstRW<[SBWriteResGroup26_2], (instrs COM_FIPr, COM_FIr, UCOM_FIPr, UCOM_FIr)>; 702 703def SBWriteResGroup29 : SchedWriteRes<[SBPort1,SBPort015]> { 704 let Latency = 4; 705 let NumMicroOps = 2; 706 let ResourceCycles = [1,1]; 707} 708def: InstRW<[SBWriteResGroup29], (instrs MOV64sr)>; 709 710def SBWriteResGroup29_2 : SchedWriteRes<[SBPort5,SBPort015]> { 711 let Latency = 4; 712 let NumMicroOps = 4; 713 let ResourceCycles = [1,3]; 714} 715def: InstRW<[SBWriteResGroup29_2], (instrs PAUSE)>; 716 717def SBWriteResGroup31 : SchedWriteRes<[SBPort23]> { 718 let Latency = 5; 719 let NumMicroOps = 1; 720 let ResourceCycles = [1]; 721} 722def: InstRW<[SBWriteResGroup31], (instregex "MOVSX(16|32|64)rm(8|16|32)", 723 "MOVZX(16|32|64)rm(8|16)")>; 724 725def SBWriteResGroup76 : SchedWriteRes<[SBPort05]> { 726 let Latency = 5; 727 let NumMicroOps = 8; 728 let ResourceCycles = [8]; 729} 730def: InstRW<[SBWriteResGroup76], (instregex "RCL(8|16|32|64)r(i|CL)", 731 "RCR(8|16|32|64)r(i|CL)")>; 732 733def SBWriteResGroup33 : SchedWriteRes<[SBPort4,SBPort23]> { 734 let Latency = 5; 735 let NumMicroOps = 2; 736 let ResourceCycles = [1,1]; 737} 738def: InstRW<[SBWriteResGroup33], (instregex "PUSH(16r|32r|64r|64i8)")>; 739 740def SBWriteResGroup35 : SchedWriteRes<[SBPort1,SBPort5]> { 741 let Latency = 5; 742 let NumMicroOps = 3; 743 let ResourceCycles = [1,2]; 744} 745def: InstRW<[SBWriteResGroup35], (instrs CLI)>; 746 747def SBWriteResGroup35_2 : SchedWriteRes<[SBPort1,SBPort4,SBPort23]> { 748 let Latency = 5; 749 let NumMicroOps = 3; 750 let ResourceCycles = [1,1,1]; 751} 752def: InstRW<[SBWriteResGroup35_2], (instrs PUSHGS64)>; 753def: InstRW<[SBWriteResGroup35_2], (instregex "ISTT_FP(16|32|64)m")>; 754 755def SBWriteResGroup36 : SchedWriteRes<[SBPort4,SBPort5,SBPort23]> { 756 let Latency = 5; 757 let NumMicroOps = 3; 758 let ResourceCycles = [1,1,1]; 759} 760def: InstRW<[SBWriteResGroup36], (instrs CALL64pcrel32)>; 761def: InstRW<[SBWriteResGroup36], (instregex "CALL(16|32|64)r", 762 "(V?)EXTRACTPSmr")>; 763 764def SBWriteResGroup40 : SchedWriteRes<[SBPort4,SBPort23,SBPort015]> { 765 let Latency = 5; 766 let NumMicroOps = 3; 767 let ResourceCycles = [1,1,1]; 768} 769def: InstRW<[SBWriteResGroup40], (instrs STOSB, STOSL, STOSQ, STOSW)>; 770 771def SBWriteResGroup41 : SchedWriteRes<[SBPort5,SBPort015]> { 772 let Latency = 5; 773 let NumMicroOps = 4; 774 let ResourceCycles = [1,3]; 775} 776def: InstRW<[SBWriteResGroup41], (instrs FNINIT)>; 777 778def SBWriteResGroup45 : SchedWriteRes<[SBPort0,SBPort4,SBPort23,SBPort15]> { 779 let Latency = 5; 780 let NumMicroOps = 4; 781 let ResourceCycles = [1,1,1,1]; 782} 783def: InstRW<[SBWriteResGroup45], (instregex "(V?)PEXTR(D|Q)mr", 784 "PUSHF(16|64)")>; 785 786def SBWriteResGroup46 : SchedWriteRes<[SBPort4,SBPort5,SBPort01,SBPort23]> { 787 let Latency = 5; 788 let NumMicroOps = 4; 789 let ResourceCycles = [1,1,1,1]; 790} 791def: InstRW<[SBWriteResGroup46], (instregex "CLFLUSH")>; 792 793def SBWriteResGroup47 : SchedWriteRes<[SBPort4,SBPort5,SBPort01,SBPort23]> { 794 let Latency = 5; 795 let NumMicroOps = 5; 796 let ResourceCycles = [1,2,1,1]; 797} 798def: InstRW<[SBWriteResGroup47], (instregex "FXRSTOR")>; 799 800def SBWriteResGroup48 : SchedWriteRes<[SBPort23]> { 801 let Latency = 6; 802 let NumMicroOps = 1; 803 let ResourceCycles = [1]; 804} 805def: InstRW<[SBWriteResGroup48], (instrs MMX_MOVD64from64rm, 806 VBROADCASTSSrm)>; 807def: InstRW<[SBWriteResGroup48], (instregex "POP(16|32|64)r", 808 "(V?)MOV64toPQIrm", 809 "(V?)MOVDDUPrm", 810 "(V?)MOVDI2PDIrm", 811 "(V?)MOVQI2PQIrm", 812 "(V?)MOVSDrm", 813 "(V?)MOVSHDUPrm", 814 "(V?)MOVSLDUPrm", 815 "(V?)MOVSSrm")>; 816 817def SBWriteResGroup49 : SchedWriteRes<[SBPort5,SBPort23]> { 818 let Latency = 6; 819 let NumMicroOps = 2; 820 let ResourceCycles = [1,1]; 821} 822def: InstRW<[SBWriteResGroup49], (instrs MOV16sm)>; 823 824def SBWriteResGroup51 : SchedWriteRes<[SBPort23,SBPort15]> { 825 let Latency = 6; 826 let NumMicroOps = 2; 827 let ResourceCycles = [1,1]; 828} 829def: InstRW<[SBWriteResGroup51], (instrs MMX_PABSBrm, 830 MMX_PABSDrm, 831 MMX_PABSWrm, 832 MMX_PALIGNRrmi, 833 MMX_PSIGNBrm, 834 MMX_PSIGNDrm, 835 MMX_PSIGNWrm)>; 836 837def SBWriteResGroup52 : SchedWriteRes<[SBPort23,SBPort015]> { 838 let Latency = 6; 839 let NumMicroOps = 2; 840 let ResourceCycles = [1,1]; 841} 842def: InstRW<[SBWriteResGroup52], (instrs LODSL, LODSQ)>; 843 844def SBWriteResGroup53 : SchedWriteRes<[SBPort4,SBPort23]> { 845 let Latency = 6; 846 let NumMicroOps = 3; 847 let ResourceCycles = [1,2]; 848} 849def: InstRW<[SBWriteResGroup53], (instregex "ST_F(32|64)m", 850 "ST_FP(32|64|80)m")>; 851 852def SBWriteResGroup54 : SchedWriteRes<[SBPort23]> { 853 let Latency = 7; 854 let NumMicroOps = 1; 855 let ResourceCycles = [1]; 856} 857def: InstRW<[SBWriteResGroup54], (instrs VBROADCASTSDYrm, 858 VBROADCASTSSYrm, 859 VMOVDDUPYrm, 860 VMOVSHDUPYrm, 861 VMOVSLDUPYrm)>; 862 863def SBWriteResGroup58 : SchedWriteRes<[SBPort23,SBPort05]> { 864 let Latency = 7; 865 let NumMicroOps = 2; 866 let ResourceCycles = [1,1]; 867} 868def: InstRW<[SBWriteResGroup58], (instrs VINSERTF128rm)>; 869 870def SBWriteResGroup59 : SchedWriteRes<[SBPort23,SBPort15]> { 871 let Latency = 7; 872 let NumMicroOps = 2; 873 let ResourceCycles = [1,1]; 874} 875def: InstRW<[SBWriteResGroup59], (instrs MMX_PADDQrm)>; 876 877def SBWriteResGroup62 : SchedWriteRes<[SBPort5,SBPort23]> { 878 let Latency = 7; 879 let NumMicroOps = 3; 880 let ResourceCycles = [2,1]; 881} 882def: InstRW<[SBWriteResGroup62], (instrs VERRm, VERWm)>; 883 884def SBWriteResGroup63 : SchedWriteRes<[SBPort23,SBPort015]> { 885 let Latency = 7; 886 let NumMicroOps = 3; 887 let ResourceCycles = [1,2]; 888} 889def: InstRW<[SBWriteResGroup63], (instrs LODSB, LODSW)>; 890 891def SBWriteResGroup64 : SchedWriteRes<[SBPort5,SBPort01,SBPort23]> { 892 let Latency = 7; 893 let NumMicroOps = 3; 894 let ResourceCycles = [1,1,1]; 895} 896def: InstRW<[SBWriteResGroup64], (instrs FARJMP64m)>; 897 898def SBWriteResGroup66 : SchedWriteRes<[SBPort0,SBPort4,SBPort23]> { 899 let Latency = 7; 900 let NumMicroOps = 4; 901 let ResourceCycles = [1,1,2]; 902} 903def: InstRW<[SBWriteResGroup66], (instrs FNSTSWm)>; 904 905def SBWriteResGroup67 : SchedWriteRes<[SBPort1,SBPort5,SBPort015]> { 906 let Latency = 7; 907 let NumMicroOps = 4; 908 let ResourceCycles = [1,2,1]; 909} 910def: InstRW<[SBWriteResGroup67], (instregex "SLDT(16|32|64)r", 911 "STR(16|32|64)r")>; 912 913def SBWriteResGroup68 : SchedWriteRes<[SBPort4,SBPort5,SBPort23]> { 914 let Latency = 7; 915 let NumMicroOps = 4; 916 let ResourceCycles = [1,1,2]; 917} 918def: InstRW<[SBWriteResGroup68], (instrs FNSTCW16m)>; 919def: InstRW<[SBWriteResGroup68], (instregex "CALL(16|32|64)m")>; 920 921def SBWriteResGroup69 : SchedWriteRes<[SBPort4,SBPort23,SBPort05]> { 922 let Latency = 7; 923 let NumMicroOps = 4; 924 let ResourceCycles = [1,2,1]; 925} 926def: InstRW<[SBWriteResGroup69], (instregex "SAR(8|16|32|64)m(1|i)", 927 "SHL(8|16|32|64)m(1|i)", 928 "SHR(8|16|32|64)m(1|i)")>; 929 930def SBWriteResGroup77 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> { 931 let Latency = 8; 932 let NumMicroOps = 3; 933 let ResourceCycles = [1,1,1]; 934} 935def: InstRW<[SBWriteResGroup77], (instregex "(V?)(U?)COMI(SD|SS)rm")>; 936 937def SBWriteResGroup81 : SchedWriteRes<[SBPort4, SBPort23, SBPort015]> { 938 let Latency = 6; 939 let NumMicroOps = 3; 940 let ResourceCycles = [1, 2, 1]; 941} 942def: InstRW<[SBWriteResGroup81], (instregex "CMPXCHG(8|16)B")>; 943 944def SBWriteResGroup83 : SchedWriteRes<[SBPort23,SBPort015]> { 945 let Latency = 8; 946 let NumMicroOps = 5; 947 let ResourceCycles = [2,3]; 948} 949def: InstRW<[SBWriteResGroup83], (instrs CMPSB, 950 CMPSL, 951 CMPSQ, 952 CMPSW)>; 953 954def SBWriteResGroup84 : SchedWriteRes<[SBPort4,SBPort5,SBPort23]> { 955 let Latency = 8; 956 let NumMicroOps = 5; 957 let ResourceCycles = [1,2,2]; 958} 959def: InstRW<[SBWriteResGroup84], (instrs FLDCW16m)>; 960 961def SBWriteResGroup85 : SchedWriteRes<[SBPort4,SBPort23,SBPort05]> { 962 let Latency = 8; 963 let NumMicroOps = 5; 964 let ResourceCycles = [1,2,2]; 965} 966def: InstRW<[SBWriteResGroup85], (instregex "ROL(8|16|32|64)m(1|i)", 967 "ROR(8|16|32|64)m(1|i)")>; 968 969def SBWriteResGroup86 : SchedWriteRes<[SBPort4,SBPort23,SBPort015]> { 970 let Latency = 8; 971 let NumMicroOps = 5; 972 let ResourceCycles = [1,2,2]; 973} 974def: InstRW<[SBWriteResGroup86], (instrs MOVSB, MOVSL, MOVSQ, MOVSW)>; 975def: InstRW<[SBWriteResGroup86], (instregex "XADD(8|16|32|64)rm")>; 976 977def SBWriteResGroup87 : SchedWriteRes<[SBPort4,SBPort5,SBPort01,SBPort23]> { 978 let Latency = 8; 979 let NumMicroOps = 5; 980 let ResourceCycles = [1,1,1,2]; 981} 982def: InstRW<[SBWriteResGroup87], (instrs FARCALL64m)>; 983 984def SBWriteResGroup93 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> { 985 let Latency = 9; 986 let NumMicroOps = 3; 987 let ResourceCycles = [1,1,1]; 988} 989def: InstRW<[SBWriteResGroup93], (instregex "CVT(T?)(SD|SS)2SI(64)?rm")>; 990 991def SBWriteResGroup95 : SchedWriteRes<[SBPort5,SBPort01,SBPort23]> { 992 let Latency = 9; 993 let NumMicroOps = 3; 994 let ResourceCycles = [1,1,1]; 995} 996def: InstRW<[SBWriteResGroup95], (instregex "LD_F(32|64|80)m")>; 997 998def SBWriteResGroup97 : SchedWriteRes<[SBPort1,SBPort4,SBPort23]> { 999 let Latency = 9; 1000 let NumMicroOps = 4; 1001 let ResourceCycles = [1,1,2]; 1002} 1003def: InstRW<[SBWriteResGroup97], (instregex "IST_F(16|32)m", 1004 "IST_FP(16|32|64)m")>; 1005 1006def SBWriteResGroup97_2 : SchedWriteRes<[SBPort4,SBPort23,SBPort05]> { 1007 let Latency = 9; 1008 let NumMicroOps = 6; 1009 let ResourceCycles = [1,2,3]; 1010} 1011def: InstRW<[SBWriteResGroup97_2], (instregex "ROL(8|16|32|64)mCL", 1012 "ROR(8|16|32|64)mCL", 1013 "SAR(8|16|32|64)mCL", 1014 "SHL(8|16|32|64)mCL", 1015 "SHR(8|16|32|64)mCL")>; 1016 1017def SBWriteResGroup98 : SchedWriteRes<[SBPort4,SBPort23,SBPort015]> { 1018 let Latency = 9; 1019 let NumMicroOps = 6; 1020 let ResourceCycles = [1,2,3]; 1021} 1022def: SchedAlias<WriteADCRMW, SBWriteResGroup98>; 1023 1024def SBWriteResGroup99 : SchedWriteRes<[SBPort4,SBPort23,SBPort05,SBPort015]> { 1025 let Latency = 9; 1026 let NumMicroOps = 6; 1027 let ResourceCycles = [1,2,2,1]; 1028} 1029def: InstRW<[SBWriteResGroup99, ReadAfterLd], (instrs ADC8mr, ADC16mr, ADC32mr, ADC64mr, 1030 SBB8mr, SBB16mr, SBB32mr, SBB64mr)>; 1031 1032def SBWriteResGroup100 : SchedWriteRes<[SBPort4,SBPort5,SBPort23,SBPort05,SBPort015]> { 1033 let Latency = 9; 1034 let NumMicroOps = 6; 1035 let ResourceCycles = [1,1,2,1,1]; 1036} 1037def : SchedAlias<WriteBitTestRegLd, SBWriteResGroup100>; // TODO - this is incorrect - no RMW 1038 1039def SBWriteResGroup101 : SchedWriteRes<[SBPort1,SBPort23]> { 1040 let Latency = 10; 1041 let NumMicroOps = 2; 1042 let ResourceCycles = [1,1]; 1043} 1044def: InstRW<[SBWriteResGroup101], (instregex "(ADD|SUB|SUBR)_F(32|64)m", 1045 "ILD_F(16|32|64)m")>; 1046 1047def SBWriteResGroup104 : SchedWriteRes<[SBPort0,SBPort23]> { 1048 let Latency = 11; 1049 let NumMicroOps = 2; 1050 let ResourceCycles = [1,1]; 1051} 1052def: InstRW<[SBWriteResGroup104], (instregex "(V?)PCMPGTQrm")>; 1053 1054def SBWriteResGroup106 : SchedWriteRes<[SBPort1,SBPort23]> { 1055 let Latency = 11; 1056 let NumMicroOps = 3; 1057 let ResourceCycles = [2,1]; 1058} 1059def: InstRW<[SBWriteResGroup106], (instregex "FICOM(P?)(16|32)m")>; 1060 1061def SBWriteResGroup108 : SchedWriteRes<[SBPort05,SBPort23]> { 1062 let Latency = 11; 1063 let NumMicroOps = 11; 1064 let ResourceCycles = [7,4]; 1065} 1066def: InstRW<[SBWriteResGroup108], (instregex "RCL(8|16|32|64)m", 1067 "RCR(8|16|32|64)m")>; 1068 1069def SBWriteResGroup111 : SchedWriteRes<[SBPort0,SBPort23]> { 1070 let Latency = 12; 1071 let NumMicroOps = 2; 1072 let ResourceCycles = [1,1]; 1073} 1074def: InstRW<[SBWriteResGroup111], (instregex "MUL_F(32|64)m")>; 1075 1076def SBWriteResGroup114 : SchedWriteRes<[SBPort1,SBPort23]> { 1077 let Latency = 13; 1078 let NumMicroOps = 3; 1079 let ResourceCycles = [2,1]; 1080} 1081def: InstRW<[SBWriteResGroup114], (instregex "(ADD|SUB|SUBR)_FI(16|32)m")>; 1082 1083def SBWriteResGroup119 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> { 1084 let Latency = 15; 1085 let NumMicroOps = 3; 1086 let ResourceCycles = [1,1,1]; 1087} 1088def: InstRW<[SBWriteResGroup119], (instregex "MUL_FI(16|32)m")>; 1089 1090def SBWriteResGroup130 : SchedWriteRes<[SBPort0,SBPort23]> { 1091 let Latency = 31; 1092 let NumMicroOps = 2; 1093 let ResourceCycles = [1,1]; 1094} 1095def: InstRW<[SBWriteResGroup130], (instregex "DIV(R?)_F(32|64)m")>; 1096 1097def SBWriteResGroup131 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> { 1098 let Latency = 34; 1099 let NumMicroOps = 3; 1100 let ResourceCycles = [1,1,1]; 1101} 1102def: InstRW<[SBWriteResGroup131], (instregex "DIV(R?)_FI(16|32)m")>; 1103 1104def SBWriteResGroupVzeroall : SchedWriteRes<[SBPort5]> { 1105 let Latency = 9; 1106 let NumMicroOps = 20; 1107 let ResourceCycles = [2]; 1108} 1109def: InstRW<[SBWriteResGroupVzeroall], (instrs VZEROALL)>; 1110 1111def SBWriteResGroupVzeroupper : SchedWriteRes<[]> { 1112 let Latency = 1; 1113 let NumMicroOps = 4; 1114 let ResourceCycles = []; 1115} 1116def: InstRW<[SBWriteResGroupVzeroupper], (instrs VZEROUPPER)>; 1117 1118def: InstRW<[WriteZero], (instrs CLC)>; 1119 1120// Instruction variants handled by the renamer. These might not need execution 1121// ports in certain conditions. 1122// See Agner's Fog "The microarchitecture of Intel, AMD and VIA CPUs", 1123// section "Sandy Bridge and Ivy Bridge Pipeline" > "Register allocation and 1124// renaming". 1125// These can be investigated with llvm-exegesis, e.g. 1126// echo 'pxor %mm0, %mm0' | /tmp/llvm-exegesis -mode=uops -snippets-file=- 1127// echo 'vxorpd %xmm0, %xmm0, %xmm1' | /tmp/llvm-exegesis -mode=uops -snippets-file=- 1128 1129def SBWriteZeroLatency : SchedWriteRes<[]> { 1130 let Latency = 0; 1131} 1132 1133def SBWriteZeroIdiom : SchedWriteVariant<[ 1134 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SBWriteZeroLatency]>, 1135 SchedVar<NoSchedPred, [WriteALU]> 1136]>; 1137def : InstRW<[SBWriteZeroIdiom], (instrs SUB32rr, SUB64rr, 1138 XOR32rr, XOR64rr)>; 1139 1140def SBWriteFZeroIdiom : SchedWriteVariant<[ 1141 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SBWriteZeroLatency]>, 1142 SchedVar<NoSchedPred, [WriteFLogic]> 1143]>; 1144def : InstRW<[SBWriteFZeroIdiom], (instrs XORPSrr, VXORPSrr, XORPDrr, 1145 VXORPDrr)>; 1146 1147def SBWriteFZeroIdiomY : SchedWriteVariant<[ 1148 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SBWriteZeroLatency]>, 1149 SchedVar<NoSchedPred, [WriteFLogicY]> 1150]>; 1151def : InstRW<[SBWriteFZeroIdiomY], (instrs VXORPSYrr, VXORPDYrr)>; 1152 1153def SBWriteVZeroIdiomLogicX : SchedWriteVariant<[ 1154 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SBWriteZeroLatency]>, 1155 SchedVar<NoSchedPred, [WriteVecLogicX]> 1156]>; 1157def : InstRW<[SBWriteVZeroIdiomLogicX], (instrs PXORrr, VPXORrr)>; 1158 1159def SBWriteVZeroIdiomALUX : SchedWriteVariant<[ 1160 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SBWriteZeroLatency]>, 1161 SchedVar<NoSchedPred, [WriteVecALUX]> 1162]>; 1163def : InstRW<[SBWriteVZeroIdiomALUX], (instrs PSUBBrr, VPSUBBrr, 1164 PSUBDrr, VPSUBDrr, 1165 PSUBQrr, VPSUBQrr, 1166 PSUBWrr, VPSUBWrr, 1167 PCMPGTBrr, VPCMPGTBrr, 1168 PCMPGTDrr, VPCMPGTDrr, 1169 PCMPGTWrr, VPCMPGTWrr)>; 1170 1171def SBWritePCMPGTQ : SchedWriteRes<[SBPort0]> { 1172 let Latency = 5; 1173 let NumMicroOps = 1; 1174 let ResourceCycles = [1]; 1175} 1176 1177def SBWriteVZeroIdiomPCMPGTQ : SchedWriteVariant<[ 1178 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SBWriteZeroLatency]>, 1179 SchedVar<NoSchedPred, [SBWritePCMPGTQ]> 1180]>; 1181def : InstRW<[SBWriteVZeroIdiomPCMPGTQ], (instrs PCMPGTQrr, VPCMPGTQrr)>; 1182 1183// CMOVs that use both Z and C flag require an extra uop. 1184def SBWriteCMOVA_CMOVBErr : SchedWriteRes<[SBPort05,SBPort015]> { 1185 let Latency = 3; 1186 let ResourceCycles = [2,1]; 1187 let NumMicroOps = 3; 1188} 1189 1190def SBWriteCMOVA_CMOVBErm : SchedWriteRes<[SBPort23,SBPort05,SBPort015]> { 1191 let Latency = 8; 1192 let ResourceCycles = [1,2,1]; 1193 let NumMicroOps = 4; 1194} 1195 1196def SBCMOVA_CMOVBErr : SchedWriteVariant<[ 1197 SchedVar<MCSchedPredicate<IsCMOVArr_Or_CMOVBErr>, [SBWriteCMOVA_CMOVBErr]>, 1198 SchedVar<NoSchedPred, [WriteCMOV]> 1199]>; 1200 1201def SBCMOVA_CMOVBErm : SchedWriteVariant<[ 1202 SchedVar<MCSchedPredicate<IsCMOVArm_Or_CMOVBErm>, [SBWriteCMOVA_CMOVBErm]>, 1203 SchedVar<NoSchedPred, [WriteCMOV.Folded]> 1204]>; 1205 1206def : InstRW<[SBCMOVA_CMOVBErr], (instrs CMOV16rr, CMOV32rr, CMOV64rr)>; 1207def : InstRW<[SBCMOVA_CMOVBErm], (instrs CMOV16rm, CMOV32rm, CMOV64rm)>; 1208 1209// SETCCs that use both Z and C flag require an extra uop. 1210def SBWriteSETA_SETBEr : SchedWriteRes<[SBPort05]> { 1211 let Latency = 2; 1212 let ResourceCycles = [2]; 1213 let NumMicroOps = 2; 1214} 1215 1216def SBWriteSETA_SETBEm : SchedWriteRes<[SBPort4,SBPort23,SBPort05]> { 1217 let Latency = 3; 1218 let ResourceCycles = [1,1,2]; 1219 let NumMicroOps = 4; 1220} 1221 1222def SBSETA_SETBErr : SchedWriteVariant<[ 1223 SchedVar<MCSchedPredicate<IsSETAr_Or_SETBEr>, [SBWriteSETA_SETBEr]>, 1224 SchedVar<NoSchedPred, [WriteSETCC]> 1225]>; 1226 1227def SBSETA_SETBErm : SchedWriteVariant<[ 1228 SchedVar<MCSchedPredicate<IsSETAm_Or_SETBEm>, [SBWriteSETA_SETBEm]>, 1229 SchedVar<NoSchedPred, [WriteSETCCStore]> 1230]>; 1231 1232def : InstRW<[SBSETA_SETBErr], (instrs SETCCr)>; 1233def : InstRW<[SBSETA_SETBErm], (instrs SETCCm)>; 1234 1235/////////////////////////////////////////////////////////////////////////////// 1236// Dependency breaking instructions. 1237/////////////////////////////////////////////////////////////////////////////// 1238 1239def : IsZeroIdiomFunction<[ 1240 // GPR Zero-idioms. 1241 DepBreakingClass<[ SUB32rr, SUB64rr, XOR32rr, XOR64rr ], ZeroIdiomPredicate>, 1242 1243 // SSE Zero-idioms. 1244 DepBreakingClass<[ 1245 // fp variants. 1246 XORPSrr, XORPDrr, 1247 1248 // int variants. 1249 PXORrr, 1250 PSUBBrr, PSUBWrr, PSUBDrr, PSUBQrr, 1251 PCMPGTBrr, PCMPGTDrr, PCMPGTQrr, PCMPGTWrr 1252 ], ZeroIdiomPredicate>, 1253 1254 // AVX Zero-idioms. 1255 DepBreakingClass<[ 1256 // xmm fp variants. 1257 VXORPSrr, VXORPDrr, 1258 1259 // xmm int variants. 1260 VPXORrr, 1261 VPSUBBrr, VPSUBWrr, VPSUBDrr, VPSUBQrr, 1262 VPCMPGTBrr, VPCMPGTWrr, VPCMPGTDrr, VPCMPGTQrr, 1263 ], ZeroIdiomPredicate>, 1264]>; 1265 1266} // SchedModel 1267