1//=- X86SchedSandyBridge.td - X86 Sandy Bridge Scheduling ----*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the machine model for Sandy Bridge to support instruction 10// scheduling and other instruction cost heuristics. 11// 12// Note that we define some instructions here that are not supported by SNB, 13// but we still have to define them because SNB is the default subtarget for 14// X86. These instructions are tagged with a comment `Unsupported = 1`. 15// 16//===----------------------------------------------------------------------===// 17 18def SandyBridgeModel : SchedMachineModel { 19 // All x86 instructions are modeled as a single micro-op, and SB can decode 4 20 // instructions per cycle. 21 // FIXME: Identify instructions that aren't a single fused micro-op. 22 let IssueWidth = 4; 23 let MicroOpBufferSize = 168; // Based on the reorder buffer. 24 let LoadLatency = 5; 25 let MispredictPenalty = 16; 26 27 // Based on the LSD (loop-stream detector) queue size. 28 let LoopMicroOpBufferSize = 28; 29 30 // This flag is set to allow the scheduler to assign 31 // a default model to unrecognized opcodes. 32 let CompleteModel = 0; 33} 34 35let SchedModel = SandyBridgeModel in { 36 37// Sandy Bridge can issue micro-ops to 6 different ports in one cycle. 38 39// Ports 0, 1, and 5 handle all computation. 40def SBPort0 : ProcResource<1>; 41def SBPort1 : ProcResource<1>; 42def SBPort5 : ProcResource<1>; 43 44// Ports 2 and 3 are identical. They handle loads and the address half of 45// stores. 46def SBPort23 : ProcResource<2>; 47 48// Port 4 gets the data half of stores. Store data can be available later than 49// the store address, but since we don't model the latency of stores, we can 50// ignore that. 51def SBPort4 : ProcResource<1>; 52 53// Many micro-ops are capable of issuing on multiple ports. 54def SBPort01 : ProcResGroup<[SBPort0, SBPort1]>; 55def SBPort05 : ProcResGroup<[SBPort0, SBPort5]>; 56def SBPort15 : ProcResGroup<[SBPort1, SBPort5]>; 57def SBPort015 : ProcResGroup<[SBPort0, SBPort1, SBPort5]>; 58 59// 54 Entry Unified Scheduler 60def SBPortAny : ProcResGroup<[SBPort0, SBPort1, SBPort23, SBPort4, SBPort5]> { 61 let BufferSize=54; 62} 63 64// Integer division issued on port 0. 65def SBDivider : ProcResource<1>; 66// FP division and sqrt on port 0. 67def SBFPDivider : ProcResource<1>; 68 69// Integer loads are 5 cycles, so ReadAfterLd registers needn't be available until 5 70// cycles after the memory operand. 71def : ReadAdvance<ReadAfterLd, 5>; 72 73// Vector loads are 5/6/7 cycles, so ReadAfterVec*Ld registers needn't be available 74// until 5/6/7 cycles after the memory operand. 75def : ReadAdvance<ReadAfterVecLd, 5>; 76def : ReadAdvance<ReadAfterVecXLd, 6>; 77def : ReadAdvance<ReadAfterVecYLd, 7>; 78 79def : ReadAdvance<ReadInt2Fpu, 0>; 80 81// Many SchedWrites are defined in pairs with and without a folded load. 82// Instructions with folded loads are usually micro-fused, so they only appear 83// as two micro-ops when queued in the reservation station. 84// This multiclass defines the resource usage for variants with and without 85// folded loads. 86multiclass SBWriteResPair<X86FoldableSchedWrite SchedRW, 87 list<ProcResourceKind> ExePorts, 88 int Lat, list<int> Res = [1], int UOps = 1, 89 int LoadLat = 5> { 90 // Register variant is using a single cycle on ExePort. 91 def : WriteRes<SchedRW, ExePorts> { 92 let Latency = Lat; 93 let ResourceCycles = Res; 94 let NumMicroOps = UOps; 95 } 96 97 // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to 98 // the latency (default = 5). 99 def : WriteRes<SchedRW.Folded, !listconcat([SBPort23], ExePorts)> { 100 let Latency = !add(Lat, LoadLat); 101 let ResourceCycles = !listconcat([1], Res); 102 let NumMicroOps = !add(UOps, 1); 103 } 104} 105 106// A folded store needs a cycle on port 4 for the store data, and an extra port 107// 2/3 cycle to recompute the address. 108def : WriteRes<WriteRMW, [SBPort23,SBPort4]>; 109 110def : WriteRes<WriteStore, [SBPort23, SBPort4]>; 111def : WriteRes<WriteStoreNT, [SBPort23, SBPort4]>; 112def : WriteRes<WriteLoad, [SBPort23]> { let Latency = 5; } 113def : WriteRes<WriteMove, [SBPort015]>; 114def : WriteRes<WriteZero, []>; 115 116// Arithmetic. 117defm : SBWriteResPair<WriteALU, [SBPort015], 1>; 118defm : SBWriteResPair<WriteADC, [SBPort05,SBPort015], 2, [1,1], 2>; 119 120defm : SBWriteResPair<WriteIMul8, [SBPort1], 3>; 121defm : SBWriteResPair<WriteIMul16, [SBPort1,SBPort05,SBPort015], 4, [1,1,2], 4>; 122defm : X86WriteRes<WriteIMul16Imm, [SBPort1,SBPort015], 4, [1,1], 2>; 123defm : X86WriteRes<WriteIMul16ImmLd, [SBPort1,SBPort015,SBPort23], 8, [1,1,1], 3>; 124defm : SBWriteResPair<WriteIMul16Reg, [SBPort1], 3>; 125defm : SBWriteResPair<WriteIMul32, [SBPort1,SBPort05,SBPort015], 4, [1,1,1], 3>; 126defm : SBWriteResPair<WriteIMul32Imm, [SBPort1], 3>; 127defm : SBWriteResPair<WriteIMul32Reg, [SBPort1], 3>; 128defm : SBWriteResPair<WriteIMul64, [SBPort1,SBPort0], 4, [1,1], 2>; 129defm : SBWriteResPair<WriteIMul64Imm, [SBPort1], 3>; 130defm : SBWriteResPair<WriteIMul64Reg, [SBPort1], 3>; 131def : WriteRes<WriteIMulH, []> { let Latency = 3; } 132 133defm : X86WriteRes<WriteXCHG, [SBPort015], 2, [3], 3>; 134defm : X86WriteRes<WriteBSWAP32, [SBPort1], 1, [1], 1>; 135defm : X86WriteRes<WriteBSWAP64, [SBPort1, SBPort05], 2, [1,1], 2>; 136defm : X86WriteRes<WriteCMPXCHG, [SBPort05, SBPort015], 5, [1,3], 4>; 137defm : X86WriteRes<WriteCMPXCHGRMW,[SBPort015, SBPort5, SBPort23, SBPort4], 8, [1, 2, 2, 1], 6>; 138 139defm : SBWriteResPair<WriteDiv8, [SBPort0, SBDivider], 25, [1, 10]>; 140defm : SBWriteResPair<WriteDiv16, [SBPort0, SBDivider], 25, [1, 10]>; 141defm : SBWriteResPair<WriteDiv32, [SBPort0, SBDivider], 25, [1, 10]>; 142defm : SBWriteResPair<WriteDiv64, [SBPort0, SBDivider], 25, [1, 10]>; 143defm : SBWriteResPair<WriteIDiv8, [SBPort0, SBDivider], 25, [1, 10]>; 144defm : SBWriteResPair<WriteIDiv16, [SBPort0, SBDivider], 25, [1, 10]>; 145defm : SBWriteResPair<WriteIDiv32, [SBPort0, SBDivider], 25, [1, 10]>; 146defm : SBWriteResPair<WriteIDiv64, [SBPort0, SBDivider], 25, [1, 10]>; 147 148// SHLD/SHRD. 149defm : X86WriteRes<WriteSHDrri, [SBPort05, SBPort015], 2, [1, 1], 2>; 150defm : X86WriteRes<WriteSHDrrcl,[SBPort05, SBPort015], 4, [3, 1], 4>; 151defm : X86WriteRes<WriteSHDmri, [SBPort4,SBPort23,SBPort05,SBPort015], 8, [1, 2, 1, 1], 5>; 152defm : X86WriteRes<WriteSHDmrcl,[SBPort4,SBPort23,SBPort05,SBPort015], 10, [1, 2, 3, 1], 7>; 153 154defm : SBWriteResPair<WriteShift, [SBPort05], 1>; 155defm : SBWriteResPair<WriteShiftCL, [SBPort05], 3, [3], 3>; 156defm : SBWriteResPair<WriteRotate, [SBPort05], 2, [2], 2>; 157defm : SBWriteResPair<WriteRotateCL, [SBPort05], 3, [3], 3>; 158 159defm : SBWriteResPair<WriteJump, [SBPort5], 1>; 160defm : SBWriteResPair<WriteCRC32, [SBPort1], 3, [1], 1, 5>; 161 162defm : SBWriteResPair<WriteCMOV, [SBPort05,SBPort015], 2, [1,1], 2>; // Conditional move. 163defm : X86WriteRes<WriteFCMOV, [SBPort5,SBPort05], 3, [2,1], 3>; // x87 conditional move. 164def : WriteRes<WriteSETCC, [SBPort05]>; // Setcc. 165def : WriteRes<WriteSETCCStore, [SBPort05,SBPort4,SBPort23]> { 166 let Latency = 2; 167 let NumMicroOps = 3; 168} 169 170defm : X86WriteRes<WriteLAHFSAHF, [SBPort05], 1, [1], 1>; 171defm : X86WriteRes<WriteBitTest, [SBPort05], 1, [1], 1>; 172defm : X86WriteRes<WriteBitTestImmLd, [SBPort05,SBPort23], 6, [1,1], 2>; 173//defm : X86WriteRes<WriteBitTestRegLd, [SBPort05,SBPort23], 6, [1,1], 2>; 174defm : X86WriteRes<WriteBitTestSet, [SBPort05], 1, [1], 1>; 175defm : X86WriteRes<WriteBitTestSetImmLd, [SBPort05,SBPort23], 6, [1,1], 3>; 176defm : X86WriteRes<WriteBitTestSetRegLd, [SBPort05,SBPort23,SBPort5,SBPort015], 8, [1,1,1,1], 5>; 177 178// This is for simple LEAs with one or two input operands. 179// The complex ones can only execute on port 1, and they require two cycles on 180// the port to read all inputs. We don't model that. 181def : WriteRes<WriteLEA, [SBPort01]>; 182 183// Bit counts. 184defm : SBWriteResPair<WriteBSF, [SBPort1], 3, [1], 1, 5>; 185defm : SBWriteResPair<WriteBSR, [SBPort1], 3, [1], 1, 5>; 186defm : SBWriteResPair<WriteLZCNT, [SBPort1], 3, [1], 1, 5>; 187defm : SBWriteResPair<WriteTZCNT, [SBPort1], 3, [1], 1, 5>; 188defm : SBWriteResPair<WritePOPCNT, [SBPort1], 3, [1], 1, 6>; 189 190// BMI1 BEXTR/BLS, BMI2 BZHI 191// NOTE: These don't exist on Sandy Bridge. Ports are guesses. 192defm : SBWriteResPair<WriteBEXTR, [SBPort05,SBPort1], 2, [1,1], 2>; 193defm : SBWriteResPair<WriteBLS, [SBPort015], 1>; 194defm : SBWriteResPair<WriteBZHI, [SBPort1], 1>; 195 196// Scalar and vector floating point. 197defm : X86WriteRes<WriteFLD0, [SBPort5], 1, [1], 1>; 198defm : X86WriteRes<WriteFLD1, [SBPort0,SBPort5], 1, [1,1], 2>; 199defm : X86WriteRes<WriteFLDC, [SBPort0,SBPort1], 1, [1,1], 2>; 200defm : X86WriteRes<WriteFLoad, [SBPort23], 5, [1], 1>; 201defm : X86WriteRes<WriteFLoadX, [SBPort23], 6, [1], 1>; 202defm : X86WriteRes<WriteFLoadY, [SBPort23], 7, [1], 1>; 203defm : X86WriteRes<WriteFMaskedLoad, [SBPort23,SBPort05], 8, [1,2], 3>; 204defm : X86WriteRes<WriteFMaskedLoadY, [SBPort23,SBPort05], 9, [1,2], 3>; 205defm : X86WriteRes<WriteFStore, [SBPort23,SBPort4], 1, [1,1], 1>; 206defm : X86WriteRes<WriteFStoreX, [SBPort23,SBPort4], 1, [1,1], 1>; 207defm : X86WriteRes<WriteFStoreY, [SBPort23,SBPort4], 1, [1,1], 1>; 208defm : X86WriteRes<WriteFStoreNT, [SBPort23,SBPort4], 1, [1,1], 1>; 209defm : X86WriteRes<WriteFStoreNTX, [SBPort23,SBPort4], 1, [1,1], 1>; 210defm : X86WriteRes<WriteFStoreNTY, [SBPort23,SBPort4], 1, [1,1], 1>; 211defm : X86WriteRes<WriteFMaskedStore, [SBPort4,SBPort01,SBPort23], 5, [1,1,1], 3>; 212defm : X86WriteRes<WriteFMaskedStoreY, [SBPort4,SBPort01,SBPort23], 5, [1,1,1], 3>; 213defm : X86WriteRes<WriteFMove, [SBPort5], 1, [1], 1>; 214defm : X86WriteRes<WriteFMoveX, [SBPort5], 1, [1], 1>; 215defm : X86WriteRes<WriteFMoveY, [SBPort5], 1, [1], 1>; 216defm : X86WriteRes<WriteEMMS, [SBPort015], 31, [31], 31>; 217 218defm : SBWriteResPair<WriteFAdd, [SBPort1], 3, [1], 1, 6>; 219defm : SBWriteResPair<WriteFAddX, [SBPort1], 3, [1], 1, 6>; 220defm : SBWriteResPair<WriteFAddY, [SBPort1], 3, [1], 1, 7>; 221defm : SBWriteResPair<WriteFAddZ, [SBPort1], 3, [1], 1, 7>; // Unsupported = 1 222defm : SBWriteResPair<WriteFAdd64, [SBPort1], 3, [1], 1, 6>; 223defm : SBWriteResPair<WriteFAdd64X, [SBPort1], 3, [1], 1, 6>; 224defm : SBWriteResPair<WriteFAdd64Y, [SBPort1], 3, [1], 1, 7>; 225defm : SBWriteResPair<WriteFAdd64Z, [SBPort1], 3, [1], 1, 7>; // Unsupported = 1 226 227defm : SBWriteResPair<WriteFCmp, [SBPort1], 3, [1], 1, 6>; 228defm : SBWriteResPair<WriteFCmpX, [SBPort1], 3, [1], 1, 6>; 229defm : SBWriteResPair<WriteFCmpY, [SBPort1], 3, [1], 1, 7>; 230defm : SBWriteResPair<WriteFCmpZ, [SBPort1], 3, [1], 1, 7>; // Unsupported = 1 231defm : SBWriteResPair<WriteFCmp64, [SBPort1], 3, [1], 1, 6>; 232defm : SBWriteResPair<WriteFCmp64X, [SBPort1], 3, [1], 1, 6>; 233defm : SBWriteResPair<WriteFCmp64Y, [SBPort1], 3, [1], 1, 7>; 234defm : SBWriteResPair<WriteFCmp64Z, [SBPort1], 3, [1], 1, 7>; // Unsupported = 1 235 236defm : SBWriteResPair<WriteFCom, [SBPort1], 3>; 237 238defm : SBWriteResPair<WriteFMul, [SBPort0], 5, [1], 1, 6>; 239defm : SBWriteResPair<WriteFMulX, [SBPort0], 5, [1], 1, 6>; 240defm : SBWriteResPair<WriteFMulY, [SBPort0], 5, [1], 1, 7>; 241defm : SBWriteResPair<WriteFMulZ, [SBPort0], 5, [1], 1, 7>; // Unsupported = 1 242defm : SBWriteResPair<WriteFMul64, [SBPort0], 5, [1], 1, 6>; 243defm : SBWriteResPair<WriteFMul64X, [SBPort0], 5, [1], 1, 6>; 244defm : SBWriteResPair<WriteFMul64Y, [SBPort0], 5, [1], 1, 7>; 245defm : SBWriteResPair<WriteFMul64Z, [SBPort0], 5, [1], 1, 7>; // Unsupported = 1 246 247defm : SBWriteResPair<WriteFDiv, [SBPort0,SBFPDivider], 14, [1,14], 1, 6>; 248defm : SBWriteResPair<WriteFDivX, [SBPort0,SBFPDivider], 14, [1,14], 1, 6>; 249defm : SBWriteResPair<WriteFDivY, [SBPort0,SBPort05,SBFPDivider], 29, [2,1,28], 3, 7>; 250defm : SBWriteResPair<WriteFDivZ, [SBPort0,SBPort05,SBFPDivider], 29, [2,1,28], 3, 7>; // Unsupported = 1 251defm : SBWriteResPair<WriteFDiv64, [SBPort0,SBFPDivider], 22, [1,22], 1, 6>; 252defm : SBWriteResPair<WriteFDiv64X, [SBPort0,SBFPDivider], 22, [1,22], 1, 6>; 253defm : SBWriteResPair<WriteFDiv64Y, [SBPort0,SBPort05,SBFPDivider], 45, [2,1,44], 3, 7>; 254defm : SBWriteResPair<WriteFDiv64Z, [SBPort0,SBPort05,SBFPDivider], 45, [2,1,44], 3, 7>; // Unsupported = 1 255 256defm : SBWriteResPair<WriteFRcp, [SBPort0], 5, [1], 1, 6>; 257defm : SBWriteResPair<WriteFRcpX, [SBPort0], 5, [1], 1, 6>; 258defm : SBWriteResPair<WriteFRcpY, [SBPort0,SBPort05], 7, [2,1], 3, 7>; 259defm : SBWriteResPair<WriteFRcpZ, [SBPort0,SBPort05], 7, [2,1], 3, 7>; // Unsupported = 1 260 261defm : SBWriteResPair<WriteFRsqrt, [SBPort0], 5, [1], 1, 6>; 262defm : SBWriteResPair<WriteFRsqrtX,[SBPort0], 5, [1], 1, 6>; 263defm : SBWriteResPair<WriteFRsqrtY,[SBPort0,SBPort05], 7, [2,1], 3, 7>; 264defm : SBWriteResPair<WriteFRsqrtZ,[SBPort0,SBPort05], 7, [2,1], 3, 7>; // Unsupported = 1 265 266defm : SBWriteResPair<WriteFSqrt, [SBPort0,SBFPDivider], 14, [1,14], 1, 6>; 267defm : SBWriteResPair<WriteFSqrtX, [SBPort0,SBFPDivider], 14, [1,14], 1, 6>; 268defm : SBWriteResPair<WriteFSqrtY, [SBPort0,SBPort05,SBFPDivider], 29, [2,1,28], 3, 7>; 269defm : SBWriteResPair<WriteFSqrtZ, [SBPort0,SBPort05,SBFPDivider], 29, [2,1,28], 3, 7>; // Unsupported = 1 270defm : SBWriteResPair<WriteFSqrt64, [SBPort0,SBFPDivider], 21, [1,21], 1, 6>; 271defm : SBWriteResPair<WriteFSqrt64X, [SBPort0,SBFPDivider], 21, [1,21], 1, 6>; 272defm : SBWriteResPair<WriteFSqrt64Y, [SBPort0,SBPort05,SBFPDivider], 45, [2,1,44], 3, 7>; 273defm : SBWriteResPair<WriteFSqrt64Z, [SBPort0,SBPort05,SBFPDivider], 45, [2,1,44], 3, 7>; // Unsupported = 1 274defm : SBWriteResPair<WriteFSqrt80, [SBPort0,SBFPDivider], 24, [1,24], 1, 6>; 275 276defm : SBWriteResPair<WriteDPPD, [SBPort0,SBPort1,SBPort5], 9, [1,1,1], 3, 6>; 277defm : SBWriteResPair<WriteDPPS, [SBPort0,SBPort1,SBPort5], 12, [1,2,1], 4, 6>; 278defm : SBWriteResPair<WriteDPPSY, [SBPort0,SBPort1,SBPort5], 12, [1,2,1], 4, 7>; 279defm : SBWriteResPair<WriteDPPSZ, [SBPort0,SBPort1,SBPort5], 12, [1,2,1], 4, 7>; // Unsupported = 1 280defm : SBWriteResPair<WriteFSign, [SBPort5], 1>; 281defm : SBWriteResPair<WriteFRnd, [SBPort1], 3, [1], 1, 6>; 282defm : SBWriteResPair<WriteFRndY, [SBPort1], 3, [1], 1, 7>; 283defm : SBWriteResPair<WriteFRndZ, [SBPort1], 3, [1], 1, 7>; // Unsupported = 1 284defm : SBWriteResPair<WriteFLogic, [SBPort5], 1, [1], 1, 6>; 285defm : SBWriteResPair<WriteFLogicY, [SBPort5], 1, [1], 1, 7>; 286defm : SBWriteResPair<WriteFLogicZ, [SBPort5], 1, [1], 1, 7>; // Unsupported = 1 287defm : SBWriteResPair<WriteFTest, [SBPort0], 1, [1], 1, 6>; 288defm : SBWriteResPair<WriteFTestY, [SBPort0], 1, [1], 1, 7>; 289defm : SBWriteResPair<WriteFTestZ, [SBPort0], 1, [1], 1, 7>; // Unsupported = 1 290defm : SBWriteResPair<WriteFShuffle, [SBPort5], 1, [1], 1, 6>; 291defm : SBWriteResPair<WriteFShuffleY,[SBPort5], 1, [1], 1, 7>; 292defm : SBWriteResPair<WriteFShuffleZ,[SBPort5], 1, [1], 1, 7>; // Unsupported = 1 293defm : SBWriteResPair<WriteFVarShuffle, [SBPort5], 1, [1], 1, 6>; 294defm : SBWriteResPair<WriteFVarShuffleY,[SBPort5], 1, [1], 1, 7>; 295defm : SBWriteResPair<WriteFVarShuffleZ,[SBPort5], 1, [1], 1, 7>; // Unsupported = 1 296defm : SBWriteResPair<WriteFBlend, [SBPort05], 1, [1], 1, 6>; 297defm : SBWriteResPair<WriteFBlendY, [SBPort05], 1, [1], 1, 7>; 298defm : SBWriteResPair<WriteFBlendZ, [SBPort05], 1, [1], 1, 7>; // Unsupported = 1 299defm : SBWriteResPair<WriteFVarBlend, [SBPort05], 2, [2], 2, 6>; 300defm : SBWriteResPair<WriteFVarBlendY,[SBPort05], 2, [2], 2, 7>; 301defm : SBWriteResPair<WriteFVarBlendZ,[SBPort05], 2, [2], 2, 7>; // Unsupported = 1 302 303// Conversion between integer and float. 304defm : SBWriteResPair<WriteCvtSS2I, [SBPort0,SBPort1], 5, [1,1], 2>; 305defm : SBWriteResPair<WriteCvtPS2I, [SBPort1], 3, [1], 1, 6>; 306defm : SBWriteResPair<WriteCvtPS2IY, [SBPort1], 3, [1], 1, 7>; 307defm : SBWriteResPair<WriteCvtPS2IZ, [SBPort1], 3, [1], 1, 7>; // Unsupported = 1 308defm : SBWriteResPair<WriteCvtSD2I, [SBPort0,SBPort1], 5, [1,1], 2>; 309defm : SBWriteResPair<WriteCvtPD2I, [SBPort1,SBPort5], 4, [1,1], 2, 6>; 310defm : X86WriteRes<WriteCvtPD2IY, [SBPort1,SBPort5], 4, [1,1], 2>; 311defm : X86WriteRes<WriteCvtPD2IZ, [SBPort1,SBPort5], 4, [1,1], 2>; // Unsupported = 1 312defm : X86WriteRes<WriteCvtPD2IYLd, [SBPort1,SBPort5,SBPort23], 11, [1,1,1], 3>; 313defm : X86WriteRes<WriteCvtPD2IZLd, [SBPort1,SBPort5,SBPort23], 11, [1,1,1], 3>; // Unsupported = 1 314 315defm : X86WriteRes<WriteCvtI2SS, [SBPort1,SBPort5], 5, [1,2], 3>; 316defm : X86WriteRes<WriteCvtI2SSLd, [SBPort1,SBPort5,SBPort23], 10, [1,1,1], 3>; 317defm : SBWriteResPair<WriteCvtI2PS, [SBPort1], 3, [1], 1, 6>; 318defm : SBWriteResPair<WriteCvtI2PSY, [SBPort1], 3, [1], 1, 7>; 319defm : SBWriteResPair<WriteCvtI2PSZ, [SBPort1], 3, [1], 1, 7>; // Unsupported = 1 320defm : X86WriteRes<WriteCvtI2SD, [SBPort1,SBPort5], 4, [1,1], 2>; 321defm : X86WriteRes<WriteCvtI2PD, [SBPort1,SBPort5], 4, [1,1], 2>; 322defm : X86WriteRes<WriteCvtI2PDY, [SBPort1,SBPort5], 4, [1,1], 2>; 323defm : X86WriteRes<WriteCvtI2PDZ, [SBPort1,SBPort5], 4, [1,1], 2>; // Unsupported = 1 324defm : X86WriteRes<WriteCvtI2SDLd, [SBPort1,SBPort23], 9, [1,1], 2>; 325defm : X86WriteRes<WriteCvtI2PDLd, [SBPort1,SBPort5,SBPort23], 10, [1,1,1], 3>; 326defm : X86WriteRes<WriteCvtI2PDYLd, [SBPort1,SBPort5,SBPort23], 10, [1,1,1], 3>; 327defm : X86WriteRes<WriteCvtI2PDZLd, [SBPort1,SBPort5,SBPort23], 10, [1,1,1], 3>; // Unsupported = 1 328 329defm : SBWriteResPair<WriteCvtSS2SD, [SBPort0], 1, [1], 1, 6>; 330defm : X86WriteRes<WriteCvtPS2PD, [SBPort0,SBPort5], 2, [1,1], 2>; 331defm : X86WriteRes<WriteCvtPS2PDY, [SBPort0,SBPort5], 2, [1,1], 2>; 332defm : X86WriteRes<WriteCvtPS2PDZ, [SBPort0,SBPort5], 2, [1,1], 2>; // Unsupported = 1 333defm : X86WriteRes<WriteCvtPS2PDLd, [SBPort0,SBPort23], 7, [1,1], 2>; 334defm : X86WriteRes<WriteCvtPS2PDYLd, [SBPort0,SBPort23], 7, [1,1], 2>; 335defm : X86WriteRes<WriteCvtPS2PDZLd, [SBPort0,SBPort23], 7, [1,1], 2>; // Unsupported = 1 336defm : SBWriteResPair<WriteCvtSD2SS, [SBPort1,SBPort5], 4, [1,1], 2, 6>; 337defm : SBWriteResPair<WriteCvtPD2PS, [SBPort1,SBPort5], 4, [1,1], 2, 6>; 338defm : SBWriteResPair<WriteCvtPD2PSY, [SBPort1,SBPort5], 4, [1,1], 2, 7>; 339defm : SBWriteResPair<WriteCvtPD2PSZ, [SBPort1,SBPort5], 4, [1,1], 2, 7>; // Unsupported = 1 340 341defm : SBWriteResPair<WriteCvtPH2PS, [SBPort1], 3>; 342defm : SBWriteResPair<WriteCvtPH2PSY, [SBPort1], 3>; 343defm : SBWriteResPair<WriteCvtPH2PSZ, [SBPort1], 3>; // Unsupported = 1 344 345defm : X86WriteRes<WriteCvtPS2PH, [SBPort1], 3, [1], 1>; 346defm : X86WriteRes<WriteCvtPS2PHY, [SBPort1], 3, [1], 1>; 347defm : X86WriteRes<WriteCvtPS2PHZ, [SBPort1], 3, [1], 1>; // Unsupported = 1 348defm : X86WriteRes<WriteCvtPS2PHSt, [SBPort1, SBPort23, SBPort4], 4, [1,1,1], 1>; 349defm : X86WriteRes<WriteCvtPS2PHYSt, [SBPort1, SBPort23, SBPort4], 4, [1,1,1], 1>; 350defm : X86WriteRes<WriteCvtPS2PHZSt, [SBPort1, SBPort23, SBPort4], 4, [1,1,1], 1>; // Unsupported = 1 351 352// Vector integer operations. 353defm : X86WriteRes<WriteVecLoad, [SBPort23], 5, [1], 1>; 354defm : X86WriteRes<WriteVecLoadX, [SBPort23], 6, [1], 1>; 355defm : X86WriteRes<WriteVecLoadY, [SBPort23], 7, [1], 1>; 356defm : X86WriteRes<WriteVecLoadNT, [SBPort23], 6, [1], 1>; 357defm : X86WriteRes<WriteVecLoadNTY, [SBPort23], 7, [1], 1>; 358defm : X86WriteRes<WriteVecMaskedLoad, [SBPort23,SBPort05], 8, [1,2], 3>; 359defm : X86WriteRes<WriteVecMaskedLoadY, [SBPort23,SBPort05], 9, [1,2], 3>; 360defm : X86WriteRes<WriteVecStore, [SBPort23,SBPort4], 1, [1,1], 1>; 361defm : X86WriteRes<WriteVecStoreX, [SBPort23,SBPort4], 1, [1,1], 1>; 362defm : X86WriteRes<WriteVecStoreY, [SBPort23,SBPort4], 1, [1,1], 1>; 363defm : X86WriteRes<WriteVecStoreNT, [SBPort23,SBPort4], 1, [1,1], 1>; 364defm : X86WriteRes<WriteVecStoreNTY, [SBPort23,SBPort4], 1, [1,1], 1>; 365defm : X86WriteRes<WriteVecMaskedStore, [SBPort4,SBPort01,SBPort23], 5, [1,1,1], 3>; 366defm : X86WriteRes<WriteVecMaskedStoreY, [SBPort4,SBPort01,SBPort23], 5, [1,1,1], 3>; 367defm : X86WriteRes<WriteVecMove, [SBPort05], 1, [1], 1>; 368defm : X86WriteRes<WriteVecMoveX, [SBPort015], 1, [1], 1>; 369defm : X86WriteRes<WriteVecMoveY, [SBPort05], 1, [1], 1>; 370defm : X86WriteRes<WriteVecMoveToGpr, [SBPort0], 2, [1], 1>; 371defm : X86WriteRes<WriteVecMoveFromGpr, [SBPort5], 1, [1], 1>; 372 373defm : SBWriteResPair<WriteVecLogic, [SBPort015], 1, [1], 1, 5>; 374defm : SBWriteResPair<WriteVecLogicX,[SBPort015], 1, [1], 1, 6>; 375defm : SBWriteResPair<WriteVecLogicY,[SBPort015], 1, [1], 1, 7>; 376defm : SBWriteResPair<WriteVecLogicZ,[SBPort015], 1, [1], 1, 7>; // Unsupported = 1 377defm : SBWriteResPair<WriteVecTest, [SBPort0,SBPort5], 2, [1,1], 2, 6>; 378defm : SBWriteResPair<WriteVecTestY, [SBPort0,SBPort5], 2, [1,1], 2, 7>; 379defm : SBWriteResPair<WriteVecTestZ, [SBPort0,SBPort5], 2, [1,1], 2, 7>; // Unsupported = 1 380defm : SBWriteResPair<WriteVecALU, [SBPort1], 3, [1], 1, 5>; 381defm : SBWriteResPair<WriteVecALUX, [SBPort15], 1, [1], 1, 6>; 382defm : SBWriteResPair<WriteVecALUY, [SBPort15], 1, [1], 1, 7>; 383defm : SBWriteResPair<WriteVecALUZ, [SBPort15], 1, [1], 1, 7>; // Unsupported = 1 384defm : SBWriteResPair<WriteVecIMul, [SBPort0], 5, [1], 1, 5>; 385defm : SBWriteResPair<WriteVecIMulX, [SBPort0], 5, [1], 1, 6>; 386defm : SBWriteResPair<WriteVecIMulY, [SBPort0], 5, [1], 1, 7>; 387defm : SBWriteResPair<WriteVecIMulZ, [SBPort0], 5, [1], 1, 7>; // Unsupported = 1 388defm : SBWriteResPair<WritePMULLD, [SBPort0], 5, [1], 1, 6>; 389defm : SBWriteResPair<WritePMULLDY, [SBPort0], 5, [1], 1, 7>; // TODO this is probably wrong for 256/512-bit for the "generic" model 390defm : SBWriteResPair<WritePMULLDZ, [SBPort0], 5, [1], 1, 7>; // Unsupported = 1 391defm : SBWriteResPair<WriteShuffle, [SBPort5], 1, [1], 1, 5>; 392defm : SBWriteResPair<WriteShuffleX, [SBPort15], 1, [1], 1, 6>; 393defm : SBWriteResPair<WriteShuffleY, [SBPort5], 1, [1], 1, 7>; 394defm : SBWriteResPair<WriteShuffleZ, [SBPort5], 1, [1], 1, 7>; // Unsupported = 1 395defm : SBWriteResPair<WriteVarShuffle, [SBPort15], 1, [1], 1, 5>; 396defm : SBWriteResPair<WriteVarShuffleX, [SBPort15], 1, [1], 1, 6>; 397defm : SBWriteResPair<WriteVarShuffleY, [SBPort15], 1, [1], 1, 7>; 398defm : SBWriteResPair<WriteVarShuffleZ, [SBPort15], 1, [1], 1, 7>; // Unsupported = 1 399defm : SBWriteResPair<WriteBlend, [SBPort15], 1, [1], 1, 6>; 400defm : SBWriteResPair<WriteBlendY, [SBPort15], 1, [1], 1, 7>; 401defm : SBWriteResPair<WriteBlendZ, [SBPort15], 1, [1], 1, 7>; // Unsupported = 1 402defm : SBWriteResPair<WriteVarBlend, [SBPort15], 2, [2], 2, 6>; 403defm : SBWriteResPair<WriteVarBlendY,[SBPort15], 2, [2], 2, 7>; 404defm : SBWriteResPair<WriteVarBlendZ,[SBPort15], 2, [2], 2, 7>; // Unsupported = 1 405defm : SBWriteResPair<WriteMPSAD, [SBPort0, SBPort15], 7, [1,2], 3, 6>; 406defm : SBWriteResPair<WriteMPSADY, [SBPort0, SBPort15], 7, [1,2], 3, 7>; 407defm : SBWriteResPair<WriteMPSADZ, [SBPort0, SBPort15], 7, [1,2], 3, 7>; // Unsupported = 1 408defm : SBWriteResPair<WritePSADBW, [SBPort0], 5, [1], 1, 5>; 409defm : SBWriteResPair<WritePSADBWX, [SBPort0], 5, [1], 1, 6>; 410defm : SBWriteResPair<WritePSADBWY, [SBPort0], 5, [1], 1, 7>; 411defm : SBWriteResPair<WritePSADBWZ, [SBPort0], 5, [1], 1, 7>; // Unsupported = 1 412defm : SBWriteResPair<WritePHMINPOS, [SBPort0], 5, [1], 1, 6>; 413 414// Vector integer shifts. 415defm : SBWriteResPair<WriteVecShift, [SBPort5], 1, [1], 1, 5>; 416defm : SBWriteResPair<WriteVecShiftX, [SBPort0,SBPort15], 2, [1,1], 2, 6>; 417defm : SBWriteResPair<WriteVecShiftY, [SBPort0,SBPort15], 4, [1,1], 2, 7>; 418defm : SBWriteResPair<WriteVecShiftZ, [SBPort0,SBPort15], 4, [1,1], 2, 7>; // Unsupported = 1 419defm : SBWriteResPair<WriteVecShiftImm, [SBPort5], 1, [1], 1, 5>; 420defm : SBWriteResPair<WriteVecShiftImmX, [SBPort0], 1, [1], 1, 6>; 421defm : SBWriteResPair<WriteVecShiftImmY, [SBPort0], 1, [1], 1, 7>; 422defm : SBWriteResPair<WriteVecShiftImmZ, [SBPort0], 1, [1], 1, 7>; // Unsupported = 1 423defm : SBWriteResPair<WriteVarVecShift, [SBPort0], 1, [1], 1, 6>; 424defm : SBWriteResPair<WriteVarVecShiftY, [SBPort0], 1, [1], 1, 7>; 425defm : SBWriteResPair<WriteVarVecShiftZ, [SBPort0], 1, [1], 1, 7>; // Unsupported = 1 426 427// Vector insert/extract operations. 428def : WriteRes<WriteVecInsert, [SBPort5,SBPort15]> { 429 let Latency = 2; 430 let NumMicroOps = 2; 431} 432def : WriteRes<WriteVecInsertLd, [SBPort23,SBPort15]> { 433 let Latency = 7; 434 let NumMicroOps = 2; 435} 436 437def : WriteRes<WriteVecExtract, [SBPort0,SBPort15]> { 438 let Latency = 3; 439 let NumMicroOps = 2; 440} 441def : WriteRes<WriteVecExtractSt, [SBPort4,SBPort23,SBPort15]> { 442 let Latency = 5; 443 let NumMicroOps = 3; 444} 445 446//////////////////////////////////////////////////////////////////////////////// 447// Horizontal add/sub instructions. 448//////////////////////////////////////////////////////////////////////////////// 449 450defm : SBWriteResPair<WriteFHAdd, [SBPort1,SBPort5], 5, [1,2], 3, 6>; 451defm : SBWriteResPair<WriteFHAddY, [SBPort1,SBPort5], 5, [1,2], 3, 7>; 452defm : SBWriteResPair<WriteFHAddZ, [SBPort1,SBPort5], 5, [1,2], 3, 7>; // Unsupported = 1 453defm : SBWriteResPair<WritePHAdd, [SBPort15], 3, [3], 3, 5>; 454defm : SBWriteResPair<WritePHAddX, [SBPort15], 3, [3], 3, 6>; 455defm : SBWriteResPair<WritePHAddY, [SBPort15], 3, [3], 3, 7>; 456defm : SBWriteResPair<WritePHAddZ, [SBPort15], 3, [3], 3, 7>; // Unsupported = 1 457 458//////////////////////////////////////////////////////////////////////////////// 459// String instructions. 460//////////////////////////////////////////////////////////////////////////////// 461 462// Packed Compare Implicit Length Strings, Return Mask 463def : WriteRes<WritePCmpIStrM, [SBPort0]> { 464 let Latency = 11; 465 let NumMicroOps = 3; 466 let ResourceCycles = [3]; 467} 468def : WriteRes<WritePCmpIStrMLd, [SBPort0, SBPort23]> { 469 let Latency = 17; 470 let NumMicroOps = 4; 471 let ResourceCycles = [3,1]; 472} 473 474// Packed Compare Explicit Length Strings, Return Mask 475def : WriteRes<WritePCmpEStrM, [SBPort015]> { 476 let Latency = 11; 477 let ResourceCycles = [8]; 478} 479def : WriteRes<WritePCmpEStrMLd, [SBPort015, SBPort23]> { 480 let Latency = 11; 481 let ResourceCycles = [7, 1]; 482} 483 484// Packed Compare Implicit Length Strings, Return Index 485def : WriteRes<WritePCmpIStrI, [SBPort0]> { 486 let Latency = 11; 487 let NumMicroOps = 3; 488 let ResourceCycles = [3]; 489} 490def : WriteRes<WritePCmpIStrILd, [SBPort0,SBPort23]> { 491 let Latency = 17; 492 let NumMicroOps = 4; 493 let ResourceCycles = [3,1]; 494} 495 496// Packed Compare Explicit Length Strings, Return Index 497def : WriteRes<WritePCmpEStrI, [SBPort015]> { 498 let Latency = 4; 499 let ResourceCycles = [8]; 500} 501def : WriteRes<WritePCmpEStrILd, [SBPort015, SBPort23]> { 502 let Latency = 4; 503 let ResourceCycles = [7, 1]; 504} 505 506// MOVMSK Instructions. 507def : WriteRes<WriteFMOVMSK, [SBPort0]> { let Latency = 2; } 508def : WriteRes<WriteVecMOVMSK, [SBPort0]> { let Latency = 2; } 509def : WriteRes<WriteVecMOVMSKY, [SBPort0]> { let Latency = 2; } 510def : WriteRes<WriteMMXMOVMSK, [SBPort0]> { let Latency = 1; } 511 512// AES Instructions. 513def : WriteRes<WriteAESDecEnc, [SBPort5,SBPort015]> { 514 let Latency = 7; 515 let NumMicroOps = 2; 516 let ResourceCycles = [1,1]; 517} 518def : WriteRes<WriteAESDecEncLd, [SBPort5,SBPort23,SBPort015]> { 519 let Latency = 13; 520 let NumMicroOps = 3; 521 let ResourceCycles = [1,1,1]; 522} 523 524def : WriteRes<WriteAESIMC, [SBPort5]> { 525 let Latency = 12; 526 let NumMicroOps = 2; 527 let ResourceCycles = [2]; 528} 529def : WriteRes<WriteAESIMCLd, [SBPort5,SBPort23]> { 530 let Latency = 18; 531 let NumMicroOps = 3; 532 let ResourceCycles = [2,1]; 533} 534 535def : WriteRes<WriteAESKeyGen, [SBPort015]> { 536 let Latency = 8; 537 let ResourceCycles = [11]; 538} 539def : WriteRes<WriteAESKeyGenLd, [SBPort015, SBPort23]> { 540 let Latency = 8; 541 let ResourceCycles = [10, 1]; 542} 543 544// Carry-less multiplication instructions. 545def : WriteRes<WriteCLMul, [SBPort015]> { 546 let Latency = 14; 547 let ResourceCycles = [18]; 548} 549def : WriteRes<WriteCLMulLd, [SBPort015, SBPort23]> { 550 let Latency = 14; 551 let ResourceCycles = [17, 1]; 552} 553 554// Load/store MXCSR. 555// FIXME: This is probably wrong. Only STMXCSR should require Port4. 556def : WriteRes<WriteLDMXCSR, [SBPort0,SBPort4,SBPort5,SBPort23]> { let Latency = 5; let NumMicroOps = 4; let ResourceCycles = [1,1,1,1]; } 557def : WriteRes<WriteSTMXCSR, [SBPort0,SBPort4,SBPort5,SBPort23]> { let Latency = 5; let NumMicroOps = 4; let ResourceCycles = [1,1,1,1]; } 558 559def : WriteRes<WriteSystem, [SBPort015]> { let Latency = 100; } 560def : WriteRes<WriteMicrocoded, [SBPort015]> { let Latency = 100; } 561def : WriteRes<WriteFence, [SBPort23, SBPort4]>; 562def : WriteRes<WriteNop, []>; 563 564// AVX2/FMA is not supported on that architecture, but we should define the basic 565// scheduling resources anyway. 566defm : SBWriteResPair<WriteFShuffle256, [SBPort5], 1, [1], 1, 7>; 567defm : SBWriteResPair<WriteFVarShuffle256, [SBPort5], 1, [1], 1, 7>; 568defm : SBWriteResPair<WriteShuffle256, [SBPort5], 1, [1], 1, 7>; 569defm : SBWriteResPair<WriteVarShuffle256, [SBPort5], 1, [1], 1, 7>; 570defm : SBWriteResPair<WriteFMA, [SBPort01], 5>; 571defm : SBWriteResPair<WriteFMAX, [SBPort01], 5>; 572defm : SBWriteResPair<WriteFMAY, [SBPort01], 5>; 573defm : SBWriteResPair<WriteFMAZ, [SBPort01], 5>; // Unsupported = 1 574 575// Remaining SNB instrs. 576 577def SBWriteResGroup1 : SchedWriteRes<[SBPort1]> { 578 let Latency = 1; 579 let NumMicroOps = 1; 580 let ResourceCycles = [1]; 581} 582def: InstRW<[SBWriteResGroup1], (instrs COMP_FST0r, 583 COM_FST0r, 584 UCOM_FPr, 585 UCOM_Fr)>; 586 587def SBWriteResGroup2 : SchedWriteRes<[SBPort5]> { 588 let Latency = 1; 589 let NumMicroOps = 1; 590 let ResourceCycles = [1]; 591} 592def: InstRW<[SBWriteResGroup2], (instrs FDECSTP, FINCSTP, FFREE, FFREEP, FNOP, 593 LD_Frr, ST_Frr, ST_FPrr)>; 594def: InstRW<[SBWriteResGroup2], (instrs LOOP, LOOPE, LOOPNE)>; // FIXME: This seems wrong compared to other Intel CPUs. 595def: InstRW<[SBWriteResGroup2], (instrs RETQ)>; 596 597def SBWriteResGroup4 : SchedWriteRes<[SBPort05]> { 598 let Latency = 1; 599 let NumMicroOps = 1; 600 let ResourceCycles = [1]; 601} 602def: InstRW<[SBWriteResGroup4], (instrs CDQ, CQO)>; 603 604def SBWriteResGroup5 : SchedWriteRes<[SBPort15]> { 605 let Latency = 1; 606 let NumMicroOps = 1; 607 let ResourceCycles = [1]; 608} 609def: InstRW<[SBWriteResGroup5], (instrs MMX_PABSBrr, 610 MMX_PABSDrr, 611 MMX_PABSWrr, 612 MMX_PADDQirr, 613 MMX_PALIGNRrri, 614 MMX_PSIGNBrr, 615 MMX_PSIGNDrr, 616 MMX_PSIGNWrr)>; 617 618def SBWriteResGroup11 : SchedWriteRes<[SBPort015]> { 619 let Latency = 2; 620 let NumMicroOps = 2; 621 let ResourceCycles = [2]; 622} 623def: InstRW<[SBWriteResGroup11], (instrs SCASB, 624 SCASL, 625 SCASQ, 626 SCASW)>; 627 628def SBWriteResGroup12 : SchedWriteRes<[SBPort0,SBPort1]> { 629 let Latency = 2; 630 let NumMicroOps = 2; 631 let ResourceCycles = [1,1]; 632} 633def: InstRW<[SBWriteResGroup12], (instregex "(V?)(U?)COMI(SD|SS)rr")>; 634 635def SBWriteResGroup15 : SchedWriteRes<[SBPort0,SBPort015]> { 636 let Latency = 2; 637 let NumMicroOps = 2; 638 let ResourceCycles = [1,1]; 639} 640def: InstRW<[SBWriteResGroup15], (instrs CWD, 641 FNSTSW16r)>; 642 643def SBWriteResGroup18 : SchedWriteRes<[SBPort5,SBPort015]> { 644 let Latency = 2; 645 let NumMicroOps = 2; 646 let ResourceCycles = [1,1]; 647} 648def: InstRW<[SBWriteResGroup18], (instrs JCXZ, JECXZ, JRCXZ, 649 MMX_MOVDQ2Qrr)>; 650 651def SBWriteResGroup21 : SchedWriteRes<[SBPort1]> { 652 let Latency = 3; 653 let NumMicroOps = 1; 654 let ResourceCycles = [1]; 655} 656def: InstRW<[SBWriteResGroup21], (instrs PUSHFS64)>; 657 658def SBWriteResGroup22 : SchedWriteRes<[SBPort0,SBPort5]> { 659 let Latency = 3; 660 let NumMicroOps = 2; 661 let ResourceCycles = [1,1]; 662} 663def: InstRW<[SBWriteResGroup22], (instregex "(V?)EXTRACTPSrr")>; 664 665def SBWriteResGroup23 : SchedWriteRes<[SBPort05]> { 666 let Latency = 2; 667 let NumMicroOps = 3; 668 let ResourceCycles = [3]; 669} 670def: InstRW<[SBWriteResGroup23], (instregex "RCL(8|16|32|64)r1", 671 "RCR(8|16|32|64)r1")>; 672 673def SBWriteResGroup25_1 : SchedWriteRes<[SBPort23,SBPort015]> { 674 let Latency = 7; 675 let NumMicroOps = 3; 676 let ResourceCycles = [1,2]; 677} 678def: InstRW<[SBWriteResGroup25_1], (instrs LEAVE, LEAVE64)>; 679 680def SBWriteResGroup26_2 : SchedWriteRes<[SBPort0,SBPort1,SBPort5]> { 681 let Latency = 3; 682 let NumMicroOps = 3; 683 let ResourceCycles = [1,1,1]; 684} 685def: InstRW<[SBWriteResGroup26_2], (instrs COM_FIPr, COM_FIr, UCOM_FIPr, UCOM_FIr)>; 686 687def SBWriteResGroup29 : SchedWriteRes<[SBPort1,SBPort015]> { 688 let Latency = 4; 689 let NumMicroOps = 2; 690 let ResourceCycles = [1,1]; 691} 692def: InstRW<[SBWriteResGroup29], (instrs MOV64sr)>; 693 694def SBWriteResGroup29_2 : SchedWriteRes<[SBPort5,SBPort015]> { 695 let Latency = 4; 696 let NumMicroOps = 4; 697 let ResourceCycles = [1,3]; 698} 699def: InstRW<[SBWriteResGroup29_2], (instrs PAUSE)>; 700 701def SBWriteResGroup31 : SchedWriteRes<[SBPort23]> { 702 let Latency = 5; 703 let NumMicroOps = 1; 704 let ResourceCycles = [1]; 705} 706def: InstRW<[SBWriteResGroup31], (instregex "MOVSX(16|32|64)rm(8|16|32)", 707 "MOVZX(16|32|64)rm(8|16)")>; 708 709def SBWriteResGroup76 : SchedWriteRes<[SBPort05]> { 710 let Latency = 5; 711 let NumMicroOps = 8; 712 let ResourceCycles = [8]; 713} 714def: InstRW<[SBWriteResGroup76], (instregex "RCL(8|16|32|64)r(i|CL)", 715 "RCR(8|16|32|64)r(i|CL)")>; 716 717def SBWriteResGroup33 : SchedWriteRes<[SBPort4,SBPort23]> { 718 let Latency = 5; 719 let NumMicroOps = 2; 720 let ResourceCycles = [1,1]; 721} 722def: InstRW<[SBWriteResGroup33], (instregex "PUSH(16r|32r|64r|64i8)")>; 723 724def SBWriteResGroup35 : SchedWriteRes<[SBPort1,SBPort5]> { 725 let Latency = 5; 726 let NumMicroOps = 3; 727 let ResourceCycles = [1,2]; 728} 729def: InstRW<[SBWriteResGroup35], (instrs CLI)>; 730 731def SBWriteResGroup35_2 : SchedWriteRes<[SBPort1,SBPort4,SBPort23]> { 732 let Latency = 5; 733 let NumMicroOps = 3; 734 let ResourceCycles = [1,1,1]; 735} 736def: InstRW<[SBWriteResGroup35_2], (instrs PUSHGS64)>; 737def: InstRW<[SBWriteResGroup35_2], (instregex "ISTT_FP(16|32|64)m")>; 738 739def SBWriteResGroup36 : SchedWriteRes<[SBPort4,SBPort5,SBPort23]> { 740 let Latency = 5; 741 let NumMicroOps = 3; 742 let ResourceCycles = [1,1,1]; 743} 744def: InstRW<[SBWriteResGroup36], (instrs CALL64pcrel32)>; 745def: InstRW<[SBWriteResGroup36], (instregex "CALL(16|32|64)r", 746 "(V?)EXTRACTPSmr")>; 747 748def SBWriteResGroup40 : SchedWriteRes<[SBPort4,SBPort23,SBPort015]> { 749 let Latency = 5; 750 let NumMicroOps = 3; 751 let ResourceCycles = [1,1,1]; 752} 753def: InstRW<[SBWriteResGroup40], (instrs STOSB, STOSL, STOSQ, STOSW)>; 754 755def SBWriteResGroup41 : SchedWriteRes<[SBPort5,SBPort015]> { 756 let Latency = 5; 757 let NumMicroOps = 4; 758 let ResourceCycles = [1,3]; 759} 760def: InstRW<[SBWriteResGroup41], (instrs FNINIT)>; 761 762def SBWriteResGroup45 : SchedWriteRes<[SBPort0,SBPort4,SBPort23,SBPort15]> { 763 let Latency = 5; 764 let NumMicroOps = 4; 765 let ResourceCycles = [1,1,1,1]; 766} 767def: InstRW<[SBWriteResGroup45], (instregex "(V?)PEXTR(D|Q)mr", 768 "PUSHF(16|64)")>; 769 770def SBWriteResGroup46 : SchedWriteRes<[SBPort4,SBPort5,SBPort01,SBPort23]> { 771 let Latency = 5; 772 let NumMicroOps = 4; 773 let ResourceCycles = [1,1,1,1]; 774} 775def: InstRW<[SBWriteResGroup46], (instregex "CLFLUSH")>; 776 777def SBWriteResGroup47 : SchedWriteRes<[SBPort4,SBPort5,SBPort01,SBPort23]> { 778 let Latency = 5; 779 let NumMicroOps = 5; 780 let ResourceCycles = [1,2,1,1]; 781} 782def: InstRW<[SBWriteResGroup47], (instregex "FXRSTOR")>; 783 784def SBWriteResGroup48 : SchedWriteRes<[SBPort23]> { 785 let Latency = 6; 786 let NumMicroOps = 1; 787 let ResourceCycles = [1]; 788} 789def: InstRW<[SBWriteResGroup48], (instrs MMX_MOVD64from64rm, 790 VBROADCASTSSrm)>; 791def: InstRW<[SBWriteResGroup48], (instregex "POP(16|32|64)r", 792 "(V?)MOV64toPQIrm", 793 "(V?)MOVDDUPrm", 794 "(V?)MOVDI2PDIrm", 795 "(V?)MOVQI2PQIrm", 796 "(V?)MOVSDrm", 797 "(V?)MOVSHDUPrm", 798 "(V?)MOVSLDUPrm", 799 "(V?)MOVSSrm")>; 800 801def SBWriteResGroup49 : SchedWriteRes<[SBPort5,SBPort23]> { 802 let Latency = 6; 803 let NumMicroOps = 2; 804 let ResourceCycles = [1,1]; 805} 806def: InstRW<[SBWriteResGroup49], (instrs MOV16sm)>; 807 808def SBWriteResGroup51 : SchedWriteRes<[SBPort23,SBPort15]> { 809 let Latency = 6; 810 let NumMicroOps = 2; 811 let ResourceCycles = [1,1]; 812} 813def: InstRW<[SBWriteResGroup51], (instrs MMX_PABSBrm, 814 MMX_PABSDrm, 815 MMX_PABSWrm, 816 MMX_PALIGNRrmi, 817 MMX_PSIGNBrm, 818 MMX_PSIGNDrm, 819 MMX_PSIGNWrm)>; 820 821def SBWriteResGroup52 : SchedWriteRes<[SBPort23,SBPort015]> { 822 let Latency = 6; 823 let NumMicroOps = 2; 824 let ResourceCycles = [1,1]; 825} 826def: InstRW<[SBWriteResGroup52], (instrs LODSL, LODSQ)>; 827 828def SBWriteResGroup53 : SchedWriteRes<[SBPort4,SBPort23]> { 829 let Latency = 6; 830 let NumMicroOps = 3; 831 let ResourceCycles = [1,2]; 832} 833def: InstRW<[SBWriteResGroup53], (instregex "ST_F(32|64)m", 834 "ST_FP(32|64|80)m")>; 835 836def SBWriteResGroup54 : SchedWriteRes<[SBPort23]> { 837 let Latency = 7; 838 let NumMicroOps = 1; 839 let ResourceCycles = [1]; 840} 841def: InstRW<[SBWriteResGroup54], (instrs VBROADCASTSDYrm, 842 VBROADCASTSSYrm, 843 VMOVDDUPYrm, 844 VMOVSHDUPYrm, 845 VMOVSLDUPYrm)>; 846 847def SBWriteResGroup58 : SchedWriteRes<[SBPort23,SBPort05]> { 848 let Latency = 7; 849 let NumMicroOps = 2; 850 let ResourceCycles = [1,1]; 851} 852def: InstRW<[SBWriteResGroup58], (instrs VINSERTF128rm)>; 853 854def SBWriteResGroup59 : SchedWriteRes<[SBPort23,SBPort15]> { 855 let Latency = 7; 856 let NumMicroOps = 2; 857 let ResourceCycles = [1,1]; 858} 859def: InstRW<[SBWriteResGroup59], (instrs MMX_PADDQirm)>; 860 861def SBWriteResGroup62 : SchedWriteRes<[SBPort5,SBPort23]> { 862 let Latency = 7; 863 let NumMicroOps = 3; 864 let ResourceCycles = [2,1]; 865} 866def: InstRW<[SBWriteResGroup62], (instrs VERRm, VERWm)>; 867 868def SBWriteResGroup63 : SchedWriteRes<[SBPort23,SBPort015]> { 869 let Latency = 7; 870 let NumMicroOps = 3; 871 let ResourceCycles = [1,2]; 872} 873def: InstRW<[SBWriteResGroup63], (instrs LODSB, LODSW)>; 874 875def SBWriteResGroup64 : SchedWriteRes<[SBPort5,SBPort01,SBPort23]> { 876 let Latency = 7; 877 let NumMicroOps = 3; 878 let ResourceCycles = [1,1,1]; 879} 880def: InstRW<[SBWriteResGroup64], (instrs FARJMP64)>; 881 882def SBWriteResGroup66 : SchedWriteRes<[SBPort0,SBPort4,SBPort23]> { 883 let Latency = 7; 884 let NumMicroOps = 4; 885 let ResourceCycles = [1,1,2]; 886} 887def: InstRW<[SBWriteResGroup66], (instrs FNSTSWm)>; 888 889def SBWriteResGroup67 : SchedWriteRes<[SBPort1,SBPort5,SBPort015]> { 890 let Latency = 7; 891 let NumMicroOps = 4; 892 let ResourceCycles = [1,2,1]; 893} 894def: InstRW<[SBWriteResGroup67], (instregex "SLDT(16|32|64)r", 895 "STR(16|32|64)r")>; 896 897def SBWriteResGroup68 : SchedWriteRes<[SBPort4,SBPort5,SBPort23]> { 898 let Latency = 7; 899 let NumMicroOps = 4; 900 let ResourceCycles = [1,1,2]; 901} 902def: InstRW<[SBWriteResGroup68], (instrs FNSTCW16m)>; 903def: InstRW<[SBWriteResGroup68], (instregex "CALL(16|32|64)m")>; 904 905def SBWriteResGroup69 : SchedWriteRes<[SBPort4,SBPort23,SBPort05]> { 906 let Latency = 7; 907 let NumMicroOps = 4; 908 let ResourceCycles = [1,2,1]; 909} 910def: InstRW<[SBWriteResGroup69], (instregex "SAR(8|16|32|64)m(1|i)", 911 "SHL(8|16|32|64)m(1|i)", 912 "SHR(8|16|32|64)m(1|i)")>; 913 914def SBWriteResGroup77 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> { 915 let Latency = 8; 916 let NumMicroOps = 3; 917 let ResourceCycles = [1,1,1]; 918} 919def: InstRW<[SBWriteResGroup77], (instregex "(V?)(U?)COMI(SD|SS)rm")>; 920 921def SBWriteResGroup81 : SchedWriteRes<[SBPort4, SBPort23, SBPort015]> { 922 let Latency = 6; 923 let NumMicroOps = 3; 924 let ResourceCycles = [1, 2, 1]; 925} 926def: InstRW<[SBWriteResGroup81], (instregex "CMPXCHG(8|16)B")>; 927 928def SBWriteResGroup83 : SchedWriteRes<[SBPort23,SBPort015]> { 929 let Latency = 8; 930 let NumMicroOps = 5; 931 let ResourceCycles = [2,3]; 932} 933def: InstRW<[SBWriteResGroup83], (instrs CMPSB, 934 CMPSL, 935 CMPSQ, 936 CMPSW)>; 937 938def SBWriteResGroup84 : SchedWriteRes<[SBPort4,SBPort5,SBPort23]> { 939 let Latency = 8; 940 let NumMicroOps = 5; 941 let ResourceCycles = [1,2,2]; 942} 943def: InstRW<[SBWriteResGroup84], (instrs FLDCW16m)>; 944 945def SBWriteResGroup85 : SchedWriteRes<[SBPort4,SBPort23,SBPort05]> { 946 let Latency = 8; 947 let NumMicroOps = 5; 948 let ResourceCycles = [1,2,2]; 949} 950def: InstRW<[SBWriteResGroup85], (instregex "ROL(8|16|32|64)m(1|i)", 951 "ROR(8|16|32|64)m(1|i)")>; 952 953def SBWriteResGroup86 : SchedWriteRes<[SBPort4,SBPort23,SBPort015]> { 954 let Latency = 8; 955 let NumMicroOps = 5; 956 let ResourceCycles = [1,2,2]; 957} 958def: InstRW<[SBWriteResGroup86], (instrs MOVSB, MOVSL, MOVSQ, MOVSW)>; 959def: InstRW<[SBWriteResGroup86], (instregex "XADD(8|16|32|64)rm")>; 960 961def SBWriteResGroup87 : SchedWriteRes<[SBPort4,SBPort5,SBPort01,SBPort23]> { 962 let Latency = 8; 963 let NumMicroOps = 5; 964 let ResourceCycles = [1,1,1,2]; 965} 966def: InstRW<[SBWriteResGroup87], (instrs FARCALL64)>; 967 968def SBWriteResGroup93 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> { 969 let Latency = 9; 970 let NumMicroOps = 3; 971 let ResourceCycles = [1,1,1]; 972} 973def: InstRW<[SBWriteResGroup93], (instregex "CVT(T?)(SD|SS)2SI(64)?rm")>; 974 975def SBWriteResGroup95 : SchedWriteRes<[SBPort5,SBPort01,SBPort23]> { 976 let Latency = 9; 977 let NumMicroOps = 3; 978 let ResourceCycles = [1,1,1]; 979} 980def: InstRW<[SBWriteResGroup95], (instregex "LD_F(32|64|80)m")>; 981 982def SBWriteResGroup97 : SchedWriteRes<[SBPort1,SBPort4,SBPort23]> { 983 let Latency = 9; 984 let NumMicroOps = 4; 985 let ResourceCycles = [1,1,2]; 986} 987def: InstRW<[SBWriteResGroup97], (instregex "IST_F(16|32)m", 988 "IST_FP(16|32|64)m")>; 989 990def SBWriteResGroup97_2 : SchedWriteRes<[SBPort4,SBPort23,SBPort05]> { 991 let Latency = 9; 992 let NumMicroOps = 6; 993 let ResourceCycles = [1,2,3]; 994} 995def: InstRW<[SBWriteResGroup97_2], (instregex "ROL(8|16|32|64)mCL", 996 "ROR(8|16|32|64)mCL", 997 "SAR(8|16|32|64)mCL", 998 "SHL(8|16|32|64)mCL", 999 "SHR(8|16|32|64)mCL")>; 1000 1001def SBWriteResGroup98 : SchedWriteRes<[SBPort4,SBPort23,SBPort015]> { 1002 let Latency = 9; 1003 let NumMicroOps = 6; 1004 let ResourceCycles = [1,2,3]; 1005} 1006def: SchedAlias<WriteADCRMW, SBWriteResGroup98>; 1007 1008def SBWriteResGroup99 : SchedWriteRes<[SBPort4,SBPort23,SBPort05,SBPort015]> { 1009 let Latency = 9; 1010 let NumMicroOps = 6; 1011 let ResourceCycles = [1,2,2,1]; 1012} 1013def: InstRW<[SBWriteResGroup99, ReadAfterLd], (instrs ADC8mr, ADC16mr, ADC32mr, ADC64mr, 1014 SBB8mr, SBB16mr, SBB32mr, SBB64mr)>; 1015 1016def SBWriteResGroup100 : SchedWriteRes<[SBPort4,SBPort5,SBPort23,SBPort05,SBPort015]> { 1017 let Latency = 9; 1018 let NumMicroOps = 6; 1019 let ResourceCycles = [1,1,2,1,1]; 1020} 1021def : SchedAlias<WriteBitTestRegLd, SBWriteResGroup100>; // TODO - this is incorrect - no RMW 1022 1023def SBWriteResGroup101 : SchedWriteRes<[SBPort1,SBPort23]> { 1024 let Latency = 10; 1025 let NumMicroOps = 2; 1026 let ResourceCycles = [1,1]; 1027} 1028def: InstRW<[SBWriteResGroup101], (instregex "(ADD|SUB|SUBR)_F(32|64)m", 1029 "ILD_F(16|32|64)m")>; 1030 1031def SBWriteResGroup104 : SchedWriteRes<[SBPort0,SBPort23]> { 1032 let Latency = 11; 1033 let NumMicroOps = 2; 1034 let ResourceCycles = [1,1]; 1035} 1036def: InstRW<[SBWriteResGroup104], (instregex "(V?)PCMPGTQrm")>; 1037 1038def SBWriteResGroup106 : SchedWriteRes<[SBPort1,SBPort23]> { 1039 let Latency = 11; 1040 let NumMicroOps = 3; 1041 let ResourceCycles = [2,1]; 1042} 1043def: InstRW<[SBWriteResGroup106], (instregex "FICOM(P?)(16|32)m")>; 1044 1045def SBWriteResGroup108 : SchedWriteRes<[SBPort05,SBPort23]> { 1046 let Latency = 11; 1047 let NumMicroOps = 11; 1048 let ResourceCycles = [7,4]; 1049} 1050def: InstRW<[SBWriteResGroup108], (instregex "RCL(8|16|32|64)m", 1051 "RCR(8|16|32|64)m")>; 1052 1053def SBWriteResGroup111 : SchedWriteRes<[SBPort0,SBPort23]> { 1054 let Latency = 12; 1055 let NumMicroOps = 2; 1056 let ResourceCycles = [1,1]; 1057} 1058def: InstRW<[SBWriteResGroup111], (instregex "MUL_F(32|64)m")>; 1059 1060def SBWriteResGroup114 : SchedWriteRes<[SBPort1,SBPort23]> { 1061 let Latency = 13; 1062 let NumMicroOps = 3; 1063 let ResourceCycles = [2,1]; 1064} 1065def: InstRW<[SBWriteResGroup114], (instregex "(ADD|SUB|SUBR)_FI(16|32)m")>; 1066 1067def SBWriteResGroup119 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> { 1068 let Latency = 15; 1069 let NumMicroOps = 3; 1070 let ResourceCycles = [1,1,1]; 1071} 1072def: InstRW<[SBWriteResGroup119], (instregex "MUL_FI(16|32)m")>; 1073 1074def SBWriteResGroup130 : SchedWriteRes<[SBPort0,SBPort23]> { 1075 let Latency = 31; 1076 let NumMicroOps = 2; 1077 let ResourceCycles = [1,1]; 1078} 1079def: InstRW<[SBWriteResGroup130], (instregex "DIV(R?)_F(32|64)m")>; 1080 1081def SBWriteResGroup131 : SchedWriteRes<[SBPort0,SBPort1,SBPort23]> { 1082 let Latency = 34; 1083 let NumMicroOps = 3; 1084 let ResourceCycles = [1,1,1]; 1085} 1086def: InstRW<[SBWriteResGroup131], (instregex "DIV(R?)_FI(16|32)m")>; 1087 1088def SBWriteResGroupVzeroall : SchedWriteRes<[SBPort5]> { 1089 let Latency = 9; 1090 let NumMicroOps = 20; 1091 let ResourceCycles = [2]; 1092} 1093def: InstRW<[SBWriteResGroupVzeroall], (instrs VZEROALL)>; 1094 1095def SBWriteResGroupVzeroupper : SchedWriteRes<[]> { 1096 let Latency = 1; 1097 let NumMicroOps = 4; 1098 let ResourceCycles = []; 1099} 1100def: InstRW<[SBWriteResGroupVzeroupper], (instrs VZEROUPPER)>; 1101 1102def: InstRW<[WriteZero], (instrs CLC)>; 1103 1104// Intruction variants handled by the renamer. These might not need execution 1105// ports in certain conditions. 1106// See Agner's Fog "The microarchitecture of Intel, AMD and VIA CPUs", 1107// section "Sandy Bridge and Ivy Bridge Pipeline" > "Register allocation and 1108// renaming". 1109// These can be investigated with llvm-exegesis, e.g. 1110// echo 'pxor %mm0, %mm0' | /tmp/llvm-exegesis -mode=uops -snippets-file=- 1111// echo 'vxorpd %xmm0, %xmm0, %xmm1' | /tmp/llvm-exegesis -mode=uops -snippets-file=- 1112 1113def SBWriteZeroLatency : SchedWriteRes<[]> { 1114 let Latency = 0; 1115} 1116 1117def SBWriteZeroIdiom : SchedWriteVariant<[ 1118 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SBWriteZeroLatency]>, 1119 SchedVar<NoSchedPred, [WriteALU]> 1120]>; 1121def : InstRW<[SBWriteZeroIdiom], (instrs SUB32rr, SUB64rr, 1122 XOR32rr, XOR64rr)>; 1123 1124def SBWriteFZeroIdiom : SchedWriteVariant<[ 1125 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SBWriteZeroLatency]>, 1126 SchedVar<NoSchedPred, [WriteFLogic]> 1127]>; 1128def : InstRW<[SBWriteFZeroIdiom], (instrs XORPSrr, VXORPSrr, XORPDrr, 1129 VXORPDrr)>; 1130 1131def SBWriteFZeroIdiomY : SchedWriteVariant<[ 1132 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SBWriteZeroLatency]>, 1133 SchedVar<NoSchedPred, [WriteFLogicY]> 1134]>; 1135def : InstRW<[SBWriteFZeroIdiomY], (instrs VXORPSYrr, VXORPDYrr)>; 1136 1137def SBWriteVZeroIdiomLogicX : SchedWriteVariant<[ 1138 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SBWriteZeroLatency]>, 1139 SchedVar<NoSchedPred, [WriteVecLogicX]> 1140]>; 1141def : InstRW<[SBWriteVZeroIdiomLogicX], (instrs PXORrr, VPXORrr)>; 1142 1143def SBWriteVZeroIdiomALUX : SchedWriteVariant<[ 1144 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SBWriteZeroLatency]>, 1145 SchedVar<NoSchedPred, [WriteVecALUX]> 1146]>; 1147def : InstRW<[SBWriteVZeroIdiomALUX], (instrs PSUBBrr, VPSUBBrr, 1148 PSUBDrr, VPSUBDrr, 1149 PSUBQrr, VPSUBQrr, 1150 PSUBWrr, VPSUBWrr, 1151 PCMPGTBrr, VPCMPGTBrr, 1152 PCMPGTDrr, VPCMPGTDrr, 1153 PCMPGTWrr, VPCMPGTWrr)>; 1154 1155def SBWritePCMPGTQ : SchedWriteRes<[SBPort0]> { 1156 let Latency = 5; 1157 let NumMicroOps = 1; 1158 let ResourceCycles = [1]; 1159} 1160 1161def SBWriteVZeroIdiomPCMPGTQ : SchedWriteVariant<[ 1162 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [SBWriteZeroLatency]>, 1163 SchedVar<NoSchedPred, [SBWritePCMPGTQ]> 1164]>; 1165def : InstRW<[SBWriteVZeroIdiomPCMPGTQ], (instrs PCMPGTQrr, VPCMPGTQrr)>; 1166 1167// CMOVs that use both Z and C flag require an extra uop. 1168def SBWriteCMOVA_CMOVBErr : SchedWriteRes<[SBPort05,SBPort015]> { 1169 let Latency = 3; 1170 let ResourceCycles = [2,1]; 1171 let NumMicroOps = 3; 1172} 1173 1174def SBWriteCMOVA_CMOVBErm : SchedWriteRes<[SBPort23,SBPort05,SBPort015]> { 1175 let Latency = 8; 1176 let ResourceCycles = [1,2,1]; 1177 let NumMicroOps = 4; 1178} 1179 1180def SBCMOVA_CMOVBErr : SchedWriteVariant<[ 1181 SchedVar<MCSchedPredicate<IsCMOVArr_Or_CMOVBErr>, [SBWriteCMOVA_CMOVBErr]>, 1182 SchedVar<NoSchedPred, [WriteCMOV]> 1183]>; 1184 1185def SBCMOVA_CMOVBErm : SchedWriteVariant<[ 1186 SchedVar<MCSchedPredicate<IsCMOVArm_Or_CMOVBErm>, [SBWriteCMOVA_CMOVBErm]>, 1187 SchedVar<NoSchedPred, [WriteCMOV.Folded]> 1188]>; 1189 1190def : InstRW<[SBCMOVA_CMOVBErr], (instrs CMOV16rr, CMOV32rr, CMOV64rr)>; 1191def : InstRW<[SBCMOVA_CMOVBErm], (instrs CMOV16rm, CMOV32rm, CMOV64rm)>; 1192 1193// SETCCs that use both Z and C flag require an extra uop. 1194def SBWriteSETA_SETBEr : SchedWriteRes<[SBPort05]> { 1195 let Latency = 2; 1196 let ResourceCycles = [2]; 1197 let NumMicroOps = 2; 1198} 1199 1200def SBWriteSETA_SETBEm : SchedWriteRes<[SBPort4,SBPort23,SBPort05]> { 1201 let Latency = 3; 1202 let ResourceCycles = [1,1,2]; 1203 let NumMicroOps = 4; 1204} 1205 1206def SBSETA_SETBErr : SchedWriteVariant<[ 1207 SchedVar<MCSchedPredicate<IsSETAr_Or_SETBEr>, [SBWriteSETA_SETBEr]>, 1208 SchedVar<NoSchedPred, [WriteSETCC]> 1209]>; 1210 1211def SBSETA_SETBErm : SchedWriteVariant<[ 1212 SchedVar<MCSchedPredicate<IsSETAm_Or_SETBEm>, [SBWriteSETA_SETBEm]>, 1213 SchedVar<NoSchedPred, [WriteSETCCStore]> 1214]>; 1215 1216def : InstRW<[SBSETA_SETBErr], (instrs SETCCr)>; 1217def : InstRW<[SBSETA_SETBErm], (instrs SETCCm)>; 1218 1219} // SchedModel 1220