1*0b57cec5SDimitry Andric//===-- X86SchedPredicates.td - X86 Scheduling Predicates --*- tablegen -*-===// 2*0b57cec5SDimitry Andric// 3*0b57cec5SDimitry Andric// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4*0b57cec5SDimitry Andric// See https://llvm.org/LICENSE.txt for license information. 5*0b57cec5SDimitry Andric// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6*0b57cec5SDimitry Andric// 7*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 8*0b57cec5SDimitry Andric// 9*0b57cec5SDimitry Andric// This file defines scheduling predicate definitions that are common to 10*0b57cec5SDimitry Andric// all X86 subtargets. 11*0b57cec5SDimitry Andric// 12*0b57cec5SDimitry Andric//===----------------------------------------------------------------------===// 13*0b57cec5SDimitry Andric 14*0b57cec5SDimitry Andric// A predicate used to identify dependency-breaking instructions that clear the 15*0b57cec5SDimitry Andric// content of the destination register. Note that this predicate only checks if 16*0b57cec5SDimitry Andric// input registers are the same. This predicate doesn't make any assumptions on 17*0b57cec5SDimitry Andric// the expected instruction opcodes, because different processors may implement 18*0b57cec5SDimitry Andric// different zero-idioms. 19*0b57cec5SDimitry Andricdef ZeroIdiomPredicate : CheckSameRegOperand<1, 2>; 20*0b57cec5SDimitry Andric 21*0b57cec5SDimitry Andric// A predicate used to identify VPERM that have bits 3 and 7 of their mask set. 22*0b57cec5SDimitry Andric// On some processors, these VPERM instructions are zero-idioms. 23*0b57cec5SDimitry Andricdef ZeroIdiomVPERMPredicate : CheckAll<[ 24*0b57cec5SDimitry Andric ZeroIdiomPredicate, 25*0b57cec5SDimitry Andric CheckImmOperand<3, 0x88> 26*0b57cec5SDimitry Andric]>; 27*0b57cec5SDimitry Andric 28*0b57cec5SDimitry Andric// A predicate used to check if a LEA instruction uses all three source 29*0b57cec5SDimitry Andric// operands: base, index, and offset. 30*0b57cec5SDimitry Andricdef IsThreeOperandsLEAPredicate: CheckAll<[ 31*0b57cec5SDimitry Andric // isRegOperand(Base) 32*0b57cec5SDimitry Andric CheckIsRegOperand<1>, 33*0b57cec5SDimitry Andric CheckNot<CheckInvalidRegOperand<1>>, 34*0b57cec5SDimitry Andric 35*0b57cec5SDimitry Andric // isRegOperand(Index) 36*0b57cec5SDimitry Andric CheckIsRegOperand<3>, 37*0b57cec5SDimitry Andric CheckNot<CheckInvalidRegOperand<3>>, 38*0b57cec5SDimitry Andric 39*0b57cec5SDimitry Andric // hasLEAOffset(Offset) 40*0b57cec5SDimitry Andric CheckAny<[ 41*0b57cec5SDimitry Andric CheckAll<[ 42*0b57cec5SDimitry Andric CheckIsImmOperand<4>, 43*0b57cec5SDimitry Andric CheckNot<CheckZeroOperand<4>> 44*0b57cec5SDimitry Andric ]>, 45*0b57cec5SDimitry Andric CheckNonPortable<"MI.getOperand(4).isGlobal()"> 46*0b57cec5SDimitry Andric ]> 47*0b57cec5SDimitry Andric]>; 48*0b57cec5SDimitry Andric 49*0b57cec5SDimitry Andricdef LEACases : MCOpcodeSwitchCase< 50*0b57cec5SDimitry Andric [LEA32r, LEA64r, LEA64_32r, LEA16r], 51*0b57cec5SDimitry Andric MCReturnStatement<IsThreeOperandsLEAPredicate> 52*0b57cec5SDimitry Andric>; 53*0b57cec5SDimitry Andric 54*0b57cec5SDimitry Andric// Used to generate the body of a TII member function. 55*0b57cec5SDimitry Andricdef IsThreeOperandsLEABody : 56*0b57cec5SDimitry Andric MCOpcodeSwitchStatement<[LEACases], MCReturnStatement<FalsePred>>; 57*0b57cec5SDimitry Andric 58*0b57cec5SDimitry Andric// This predicate evaluates to true only if the input machine instruction is a 59*0b57cec5SDimitry Andric// 3-operands LEA. Tablegen automatically generates a new method for it in 60*0b57cec5SDimitry Andric// X86GenInstrInfo. 61*0b57cec5SDimitry Andricdef IsThreeOperandsLEAFn : 62*0b57cec5SDimitry Andric TIIPredicate<"isThreeOperandsLEA", IsThreeOperandsLEABody>; 63*0b57cec5SDimitry Andric 64*0b57cec5SDimitry Andric// A predicate to check for COND_A and COND_BE CMOVs which have an extra uop 65*0b57cec5SDimitry Andric// on recent Intel CPUs. 66*0b57cec5SDimitry Andricdef IsCMOVArr_Or_CMOVBErr : CheckAny<[ 67*0b57cec5SDimitry Andric CheckImmOperand_s<3, "X86::COND_A">, 68*0b57cec5SDimitry Andric CheckImmOperand_s<3, "X86::COND_BE"> 69*0b57cec5SDimitry Andric]>; 70*0b57cec5SDimitry Andric 71*0b57cec5SDimitry Andricdef IsCMOVArm_Or_CMOVBErm : CheckAny<[ 72*0b57cec5SDimitry Andric CheckImmOperand_s<7, "X86::COND_A">, 73*0b57cec5SDimitry Andric CheckImmOperand_s<7, "X86::COND_BE"> 74*0b57cec5SDimitry Andric]>; 75*0b57cec5SDimitry Andric 76*0b57cec5SDimitry Andric// A predicate to check for COND_A and COND_BE SETCCs which have an extra uop 77*0b57cec5SDimitry Andric// on recent Intel CPUs. 78*0b57cec5SDimitry Andricdef IsSETAr_Or_SETBEr : CheckAny<[ 79*0b57cec5SDimitry Andric CheckImmOperand_s<1, "X86::COND_A">, 80*0b57cec5SDimitry Andric CheckImmOperand_s<1, "X86::COND_BE"> 81*0b57cec5SDimitry Andric]>; 82*0b57cec5SDimitry Andric 83*0b57cec5SDimitry Andricdef IsSETAm_Or_SETBEm : CheckAny<[ 84*0b57cec5SDimitry Andric CheckImmOperand_s<5, "X86::COND_A">, 85*0b57cec5SDimitry Andric CheckImmOperand_s<5, "X86::COND_BE"> 86*0b57cec5SDimitry Andric]>; 87