1//=- X86SchedIceLake.td - X86 Ice Lake Scheduling ------------*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the machine model for Ice Lake to support 10// instruction scheduling and other instruction cost heuristics. 11// 12// TODO: This is mainly a copy X86SchedSkylakeServer.td, but allows us to 13// iteratively improve scheduling handling toward better modelling the 14// Ice Lake (Sunny/Cypress Cove) microarchitecture. 15// 16//===----------------------------------------------------------------------===// 17 18def IceLakeModel : SchedMachineModel { 19 // All x86 instructions are modeled as a single micro-op, and Ice Lake can 20 // decode 6 instructions per cycle. 21 let IssueWidth = 6; 22 let MicroOpBufferSize = 224; // Based on the reorder buffer. 23 let LoadLatency = 5; 24 let MispredictPenalty = 14; 25 26 // Based on the LSD (loop-stream detector) queue size and benchmarking data. 27 let LoopMicroOpBufferSize = 50; 28 29 // This flag is set to allow the scheduler to assign a default model to 30 // unrecognized opcodes. 31 let CompleteModel = 0; 32} 33 34let SchedModel = IceLakeModel in { 35 36// Ice Lake can issue micro-ops to 8 different ports in one cycle. 37 38// Ports 0, 1, 5, and 6 handle all computation. 39// Ports 4 and 9 gets the data half of stores. Store data can be available later 40// than the store address, but since we don't model the latency of stores, we 41// can ignore that. 42// Ports 2 and 3 are identical. They handle loads and address calculations. 43// Ports 7 and 8 are identical. They handle stores address calculations. 44def ICXPort0 : ProcResource<1>; 45def ICXPort1 : ProcResource<1>; 46def ICXPort2 : ProcResource<1>; 47def ICXPort3 : ProcResource<1>; 48def ICXPort4 : ProcResource<1>; 49def ICXPort5 : ProcResource<1>; 50def ICXPort6 : ProcResource<1>; 51def ICXPort7 : ProcResource<1>; 52def ICXPort8 : ProcResource<1>; 53def ICXPort9 : ProcResource<1>; 54 55// Many micro-ops are capable of issuing on multiple ports. 56def ICXPort01 : ProcResGroup<[ICXPort0, ICXPort1]>; 57def ICXPort23 : ProcResGroup<[ICXPort2, ICXPort3]>; 58def ICXPort237 : ProcResGroup<[ICXPort2, ICXPort3, ICXPort7]>; 59def ICXPort04 : ProcResGroup<[ICXPort0, ICXPort4]>; 60def ICXPort05 : ProcResGroup<[ICXPort0, ICXPort5]>; 61def ICXPort06 : ProcResGroup<[ICXPort0, ICXPort6]>; 62def ICXPort15 : ProcResGroup<[ICXPort1, ICXPort5]>; 63def ICXPort16 : ProcResGroup<[ICXPort1, ICXPort6]>; 64def ICXPort49 : ProcResGroup<[ICXPort4, ICXPort9]>; 65def ICXPort56 : ProcResGroup<[ICXPort5, ICXPort6]>; 66def ICXPort78 : ProcResGroup<[ICXPort7, ICXPort8]>; 67def ICXPort015 : ProcResGroup<[ICXPort0, ICXPort1, ICXPort5]>; 68def ICXPort056 : ProcResGroup<[ICXPort0, ICXPort5, ICXPort6]>; 69def ICXPort0156: ProcResGroup<[ICXPort0, ICXPort1, ICXPort5, ICXPort6]>; 70 71def ICXDivider : ProcResource<1>; // Integer division issued on port 0. 72// FP division and sqrt on port 0. 73def ICXFPDivider : ProcResource<1>; 74 75// 60 Entry Unified Scheduler 76def ICXPortAny : ProcResGroup<[ICXPort0, ICXPort1, ICXPort2, ICXPort3, ICXPort4, 77 ICXPort5, ICXPort6, ICXPort7, ICXPort8, ICXPort9]> { 78 let BufferSize=60; 79} 80 81// Integer loads are 5 cycles, so ReadAfterLd registers needn't be available until 5 82// cycles after the memory operand. 83def : ReadAdvance<ReadAfterLd, 5>; 84 85// Vector loads are 5/6/7 cycles, so ReadAfterVec*Ld registers needn't be available 86// until 5/6/7 cycles after the memory operand. 87def : ReadAdvance<ReadAfterVecLd, 5>; 88def : ReadAdvance<ReadAfterVecXLd, 6>; 89def : ReadAdvance<ReadAfterVecYLd, 7>; 90 91def : ReadAdvance<ReadInt2Fpu, 0>; 92 93// Many SchedWrites are defined in pairs with and without a folded load. 94// Instructions with folded loads are usually micro-fused, so they only appear 95// as two micro-ops when queued in the reservation station. 96// This multiclass defines the resource usage for variants with and without 97// folded loads. 98multiclass ICXWriteResPair<X86FoldableSchedWrite SchedRW, 99 list<ProcResourceKind> ExePorts, 100 int Lat, list<int> Res = [1], int UOps = 1, 101 int LoadLat = 5> { 102 // Register variant is using a single cycle on ExePort. 103 def : WriteRes<SchedRW, ExePorts> { 104 let Latency = Lat; 105 let ResourceCycles = Res; 106 let NumMicroOps = UOps; 107 } 108 109 // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to 110 // the latency (default = 5). 111 def : WriteRes<SchedRW.Folded, !listconcat([ICXPort23], ExePorts)> { 112 let Latency = !add(Lat, LoadLat); 113 let ResourceCycles = !listconcat([1], Res); 114 let NumMicroOps = !add(UOps, 1); 115 } 116} 117 118// A folded store needs a cycle on port 4 for the store data, and an extra port 119// 2/3/7 cycle to recompute the address. 120def : WriteRes<WriteRMW, [ICXPort237,ICXPort4]>; 121 122// Arithmetic. 123defm : ICXWriteResPair<WriteALU, [ICXPort0156], 1>; // Simple integer ALU op. 124defm : ICXWriteResPair<WriteADC, [ICXPort06], 1>; // Integer ALU + flags op. 125 126// Integer multiplication. 127defm : ICXWriteResPair<WriteIMul8, [ICXPort1], 3>; 128defm : ICXWriteResPair<WriteIMul16, [ICXPort1,ICXPort06,ICXPort0156], 4, [1,1,2], 4>; 129defm : X86WriteRes<WriteIMul16Imm, [ICXPort1,ICXPort0156], 4, [1,1], 2>; 130defm : X86WriteRes<WriteIMul16ImmLd, [ICXPort1,ICXPort0156,ICXPort23], 8, [1,1,1], 3>; 131defm : X86WriteRes<WriteIMul16Reg, [ICXPort1], 3, [1], 1>; 132defm : X86WriteRes<WriteIMul16RegLd, [ICXPort1,ICXPort0156,ICXPort23], 8, [1,1,1], 3>; 133defm : ICXWriteResPair<WriteIMul32, [ICXPort1,ICXPort06,ICXPort0156], 4, [1,1,1], 3>; 134defm : ICXWriteResPair<WriteMULX32, [ICXPort1,ICXPort06,ICXPort0156], 3, [1,1,1], 3>; 135defm : ICXWriteResPair<WriteIMul32Imm, [ICXPort1], 3>; 136defm : ICXWriteResPair<WriteIMul32Reg, [ICXPort1], 3>; 137defm : ICXWriteResPair<WriteIMul64, [ICXPort1,ICXPort5], 4, [1,1], 2>; 138defm : ICXWriteResPair<WriteMULX64, [ICXPort1,ICXPort5], 3, [1,1], 2>; 139defm : ICXWriteResPair<WriteIMul64Imm, [ICXPort1], 3>; 140defm : ICXWriteResPair<WriteIMul64Reg, [ICXPort1], 3>; 141def ICXWriteIMulH : WriteRes<WriteIMulH, []> { let Latency = 4; } 142def : WriteRes<WriteIMulHLd, []> { 143 let Latency = !add(ICXWriteIMulH.Latency, SkylakeServerModel.LoadLatency); 144} 145 146defm : X86WriteRes<WriteBSWAP32, [ICXPort15], 1, [1], 1>; 147defm : X86WriteRes<WriteBSWAP64, [ICXPort06, ICXPort15], 2, [1,1], 2>; 148defm : X86WriteRes<WriteCMPXCHG,[ICXPort06, ICXPort0156], 5, [2,3], 5>; 149defm : X86WriteRes<WriteCMPXCHGRMW,[ICXPort23,ICXPort06,ICXPort0156,ICXPort237,ICXPort4], 8, [1,2,1,1,1], 6>; 150defm : X86WriteRes<WriteXCHG, [ICXPort0156], 2, [3], 3>; 151 152// TODO: Why isn't the ICXDivider used? 153defm : ICXWriteResPair<WriteDiv8, [ICXPort0, ICXDivider], 25, [1,10], 1, 4>; 154defm : X86WriteRes<WriteDiv16, [ICXPort0,ICXPort1,ICXPort5,ICXPort6,ICXPort05,ICXPort0156], 76, [7,2,8,3,1,11], 32>; 155defm : X86WriteRes<WriteDiv32, [ICXPort0,ICXPort1,ICXPort5,ICXPort6,ICXPort05,ICXPort0156], 76, [7,2,8,3,1,11], 32>; 156defm : X86WriteRes<WriteDiv64, [ICXPort0,ICXPort1,ICXPort5,ICXPort6,ICXPort05,ICXPort0156], 76, [7,2,8,3,1,11], 32>; 157defm : X86WriteRes<WriteDiv16Ld, [ICXPort0,ICXPort23,ICXDivider], 29, [1,1,10], 2>; 158defm : X86WriteRes<WriteDiv32Ld, [ICXPort0,ICXPort23,ICXDivider], 29, [1,1,10], 2>; 159defm : X86WriteRes<WriteDiv64Ld, [ICXPort0,ICXPort23,ICXDivider], 29, [1,1,10], 2>; 160 161defm : X86WriteRes<WriteIDiv8, [ICXPort0, ICXDivider], 25, [1,10], 1>; 162defm : X86WriteRes<WriteIDiv16, [ICXPort0,ICXPort1,ICXPort5,ICXPort6,ICXPort06,ICXPort0156], 102, [4,2,4,8,14,34], 66>; 163defm : X86WriteRes<WriteIDiv32, [ICXPort0,ICXPort1,ICXPort5,ICXPort6,ICXPort06,ICXPort0156], 102, [4,2,4,8,14,34], 66>; 164defm : X86WriteRes<WriteIDiv64, [ICXPort0,ICXPort1,ICXPort5,ICXPort6,ICXPort06,ICXPort0156], 102, [4,2,4,8,14,34], 66>; 165defm : X86WriteRes<WriteIDiv8Ld, [ICXPort0,ICXPort5,ICXPort23,ICXPort0156], 28, [2,4,1,1], 8>; 166defm : X86WriteRes<WriteIDiv16Ld, [ICXPort0,ICXPort5,ICXPort23,ICXPort0156], 28, [2,4,1,1], 8>; 167defm : X86WriteRes<WriteIDiv32Ld, [ICXPort0,ICXPort5,ICXPort23,ICXPort0156], 28, [2,4,1,1], 8>; 168defm : X86WriteRes<WriteIDiv64Ld, [ICXPort0,ICXPort5,ICXPort23,ICXPort0156], 28, [2,4,1,1], 8>; 169 170defm : ICXWriteResPair<WriteCRC32, [ICXPort1], 3>; 171 172def : WriteRes<WriteLEA, [ICXPort15]>; // LEA instructions can't fold loads. 173 174defm : ICXWriteResPair<WriteCMOV, [ICXPort06], 1, [1], 1>; // Conditional move. 175defm : X86WriteRes<WriteFCMOV, [ICXPort1], 3, [1], 1>; // x87 conditional move. 176def : WriteRes<WriteSETCC, [ICXPort06]>; // Setcc. 177def : WriteRes<WriteSETCCStore, [ICXPort06,ICXPort4,ICXPort237]> { 178 let Latency = 2; 179 let NumMicroOps = 3; 180} 181defm : X86WriteRes<WriteLAHFSAHF, [ICXPort06], 1, [1], 1>; 182defm : X86WriteRes<WriteBitTest, [ICXPort06], 1, [1], 1>; 183defm : X86WriteRes<WriteBitTestImmLd, [ICXPort06,ICXPort23], 6, [1,1], 2>; 184defm : X86WriteRes<WriteBitTestRegLd, [ICXPort0156,ICXPort23], 6, [1,1], 2>; 185defm : X86WriteRes<WriteBitTestSet, [ICXPort06], 1, [1], 1>; 186defm : X86WriteRes<WriteBitTestSetImmLd, [ICXPort06,ICXPort23], 5, [1,1], 3>; 187defm : X86WriteRes<WriteBitTestSetRegLd, [ICXPort0156,ICXPort23], 5, [1,1], 2>; 188 189// Integer shifts and rotates. 190defm : ICXWriteResPair<WriteShift, [ICXPort06], 1>; 191defm : ICXWriteResPair<WriteShiftCL, [ICXPort06], 3, [3], 3>; 192defm : ICXWriteResPair<WriteRotate, [ICXPort06], 1, [1], 1>; 193defm : ICXWriteResPair<WriteRotateCL, [ICXPort06], 3, [3], 3>; 194 195// SHLD/SHRD. 196defm : X86WriteRes<WriteSHDrri, [ICXPort1], 3, [1], 1>; 197defm : X86WriteRes<WriteSHDrrcl,[ICXPort1,ICXPort06,ICXPort0156], 6, [1, 2, 1], 4>; 198defm : X86WriteRes<WriteSHDmri, [ICXPort1,ICXPort23,ICXPort237,ICXPort0156], 9, [1, 1, 1, 1], 4>; 199defm : X86WriteRes<WriteSHDmrcl,[ICXPort1,ICXPort23,ICXPort237,ICXPort06,ICXPort0156], 11, [1, 1, 1, 2, 1], 6>; 200 201// Bit counts. 202defm : ICXWriteResPair<WriteBSF, [ICXPort1], 3>; 203defm : ICXWriteResPair<WriteBSR, [ICXPort1], 3>; 204defm : ICXWriteResPair<WriteLZCNT, [ICXPort1], 3>; 205defm : ICXWriteResPair<WriteTZCNT, [ICXPort1], 3>; 206defm : ICXWriteResPair<WritePOPCNT, [ICXPort1], 3>; 207 208// BMI1 BEXTR/BLS, BMI2 BZHI 209defm : ICXWriteResPair<WriteBEXTR, [ICXPort06,ICXPort15], 2, [1,1], 2>; 210defm : ICXWriteResPair<WriteBLS, [ICXPort15], 1>; 211defm : ICXWriteResPair<WriteBZHI, [ICXPort15], 1>; 212 213// Loads, stores, and moves, not folded with other operations. 214defm : X86WriteRes<WriteLoad, [ICXPort23], 5, [1], 1>; 215defm : X86WriteRes<WriteStore, [ICXPort237, ICXPort4], 1, [1,1], 1>; 216defm : X86WriteRes<WriteStoreNT, [ICXPort237, ICXPort4], 1, [1,1], 2>; 217defm : X86WriteRes<WriteMove, [ICXPort0156], 1, [1], 1>; 218 219// Model the effect of clobbering the read-write mask operand of the GATHER operation. 220// Does not cost anything by itself, only has latency, matching that of the WriteLoad, 221defm : X86WriteRes<WriteVecMaskedGatherWriteback, [], 5, [], 0>; 222 223// Idioms that clear a register, like xorps %xmm0, %xmm0. 224// These can often bypass execution ports completely. 225def : WriteRes<WriteZero, []>; 226 227// Branches don't produce values, so they have no latency, but they still 228// consume resources. Indirect branches can fold loads. 229defm : ICXWriteResPair<WriteJump, [ICXPort06], 1>; 230 231// Floating point. This covers both scalar and vector operations. 232defm : X86WriteRes<WriteFLD0, [ICXPort05], 1, [1], 1>; 233defm : X86WriteRes<WriteFLD1, [ICXPort05], 1, [2], 2>; 234defm : X86WriteRes<WriteFLDC, [ICXPort05], 1, [2], 2>; 235defm : X86WriteRes<WriteFLoad, [ICXPort23], 5, [1], 1>; 236defm : X86WriteRes<WriteFLoadX, [ICXPort23], 6, [1], 1>; 237defm : X86WriteRes<WriteFLoadY, [ICXPort23], 7, [1], 1>; 238defm : X86WriteRes<WriteFMaskedLoad, [ICXPort23,ICXPort015], 7, [1,1], 2>; 239defm : X86WriteRes<WriteFMaskedLoadY, [ICXPort23,ICXPort015], 8, [1,1], 2>; 240defm : X86WriteRes<WriteFStore, [ICXPort237,ICXPort4], 1, [1,1], 2>; 241defm : X86WriteRes<WriteFStoreX, [ICXPort237,ICXPort4], 1, [1,1], 2>; 242defm : X86WriteRes<WriteFStoreY, [ICXPort237,ICXPort4], 1, [1,1], 2>; 243defm : X86WriteRes<WriteFStoreNT, [ICXPort237,ICXPort4], 1, [1,1], 2>; 244defm : X86WriteRes<WriteFStoreNTX, [ICXPort237,ICXPort4], 1, [1,1], 2>; 245defm : X86WriteRes<WriteFStoreNTY, [ICXPort237,ICXPort4], 1, [1,1], 2>; 246 247defm : X86WriteRes<WriteFMaskedStore32, [ICXPort237,ICXPort0], 2, [1,1], 2>; 248defm : X86WriteRes<WriteFMaskedStore32Y, [ICXPort237,ICXPort0], 2, [1,1], 2>; 249defm : X86WriteRes<WriteFMaskedStore64, [ICXPort237,ICXPort0], 2, [1,1], 2>; 250defm : X86WriteRes<WriteFMaskedStore64Y, [ICXPort237,ICXPort0], 2, [1,1], 2>; 251 252defm : X86WriteRes<WriteFMove, [ICXPort015], 1, [1], 1>; 253defm : X86WriteRes<WriteFMoveX, [ICXPort015], 1, [1], 1>; 254defm : X86WriteRes<WriteFMoveY, [ICXPort015], 1, [1], 1>; 255defm : X86WriteRes<WriteFMoveZ, [ICXPort05], 1, [1], 1>; 256defm : X86WriteRes<WriteEMMS, [ICXPort05,ICXPort0156], 10, [9,1], 10>; 257 258defm : ICXWriteResPair<WriteFAdd, [ICXPort01], 4, [1], 1, 5>; // Floating point add/sub. 259defm : ICXWriteResPair<WriteFAddX, [ICXPort01], 4, [1], 1, 6>; 260defm : ICXWriteResPair<WriteFAddY, [ICXPort01], 4, [1], 1, 7>; 261defm : ICXWriteResPair<WriteFAddZ, [ICXPort05], 4, [1], 1, 7>; 262defm : ICXWriteResPair<WriteFAdd64, [ICXPort01], 4, [1], 1, 5>; // Floating point double add/sub. 263defm : ICXWriteResPair<WriteFAdd64X, [ICXPort01], 4, [1], 1, 6>; 264defm : ICXWriteResPair<WriteFAdd64Y, [ICXPort01], 4, [1], 1, 7>; 265defm : ICXWriteResPair<WriteFAdd64Z, [ICXPort05], 4, [1], 1, 7>; 266 267defm : ICXWriteResPair<WriteFCmp, [ICXPort01], 4, [1], 1, 5>; // Floating point compare. 268defm : ICXWriteResPair<WriteFCmpX, [ICXPort01], 4, [1], 1, 6>; 269defm : ICXWriteResPair<WriteFCmpY, [ICXPort01], 4, [1], 1, 7>; 270defm : ICXWriteResPair<WriteFCmpZ, [ICXPort05], 4, [1], 1, 7>; 271defm : ICXWriteResPair<WriteFCmp64, [ICXPort01], 4, [1], 1, 5>; // Floating point double compare. 272defm : ICXWriteResPair<WriteFCmp64X, [ICXPort01], 4, [1], 1, 6>; 273defm : ICXWriteResPair<WriteFCmp64Y, [ICXPort01], 4, [1], 1, 7>; 274defm : ICXWriteResPair<WriteFCmp64Z, [ICXPort05], 4, [1], 1, 7>; 275 276defm : ICXWriteResPair<WriteFCom, [ICXPort0], 2>; // Floating point compare to flags (X87). 277defm : ICXWriteResPair<WriteFComX, [ICXPort0], 2>; // Floating point compare to flags (SSE). 278 279defm : ICXWriteResPair<WriteFMul, [ICXPort01], 4, [1], 1, 5>; // Floating point multiplication. 280defm : ICXWriteResPair<WriteFMulX, [ICXPort01], 4, [1], 1, 6>; 281defm : ICXWriteResPair<WriteFMulY, [ICXPort01], 4, [1], 1, 7>; 282defm : ICXWriteResPair<WriteFMulZ, [ICXPort05], 4, [1], 1, 7>; 283defm : ICXWriteResPair<WriteFMul64, [ICXPort01], 4, [1], 1, 5>; // Floating point double multiplication. 284defm : ICXWriteResPair<WriteFMul64X, [ICXPort01], 4, [1], 1, 6>; 285defm : ICXWriteResPair<WriteFMul64Y, [ICXPort01], 4, [1], 1, 7>; 286defm : ICXWriteResPair<WriteFMul64Z, [ICXPort05], 4, [1], 1, 7>; 287 288defm : ICXWriteResPair<WriteFDiv, [ICXPort0,ICXFPDivider], 11, [1,3], 1, 5>; // 10-14 cycles. // Floating point division. 289//defm : ICXWriteResPair<WriteFDivX, [ICXPort0,ICXFPDivider], 11, [1,3], 1, 6>; // 10-14 cycles. 290defm : ICXWriteResPair<WriteFDivY, [ICXPort0,ICXFPDivider], 11, [1,5], 1, 7>; // 10-14 cycles. 291defm : ICXWriteResPair<WriteFDivZ, [ICXPort0,ICXPort5,ICXFPDivider], 18, [2,1,10], 3, 7>; // 10-14 cycles. 292//defm : ICXWriteResPair<WriteFDiv64, [ICXPort0,ICXFPDivider], 14, [1,3], 1, 5>; // 10-14 cycles. // Floating point division. 293//defm : ICXWriteResPair<WriteFDiv64X, [ICXPort0,ICXFPDivider], 14, [1,3], 1, 6>; // 10-14 cycles. 294//defm : ICXWriteResPair<WriteFDiv64Y, [ICXPort0,ICXFPDivider], 14, [1,5], 1, 7>; // 10-14 cycles. 295defm : ICXWriteResPair<WriteFDiv64Z, [ICXPort0,ICXPort5,ICXFPDivider], 23, [2,1,16], 3, 7>; // 10-14 cycles. 296 297defm : ICXWriteResPair<WriteFSqrt, [ICXPort0,ICXFPDivider], 12, [1,3], 1, 5>; // Floating point square root. 298defm : ICXWriteResPair<WriteFSqrtX, [ICXPort0,ICXFPDivider], 12, [1,3], 1, 6>; 299defm : ICXWriteResPair<WriteFSqrtY, [ICXPort0,ICXFPDivider], 12, [1,6], 1, 7>; 300defm : ICXWriteResPair<WriteFSqrtZ, [ICXPort0,ICXPort5,ICXFPDivider], 20, [2,1,12], 3, 7>; 301defm : ICXWriteResPair<WriteFSqrt64, [ICXPort0,ICXFPDivider], 18, [1,6], 1, 5>; // Floating point double square root. 302defm : ICXWriteResPair<WriteFSqrt64X, [ICXPort0,ICXFPDivider], 18, [1,6], 1, 6>; 303defm : ICXWriteResPair<WriteFSqrt64Y, [ICXPort0,ICXFPDivider], 18, [1,12],1, 7>; 304defm : ICXWriteResPair<WriteFSqrt64Z, [ICXPort0,ICXPort5,ICXFPDivider], 32, [2,1,24], 3, 7>; 305defm : ICXWriteResPair<WriteFSqrt80, [ICXPort0,ICXFPDivider], 21, [1,7]>; // Floating point long double square root. 306 307defm : ICXWriteResPair<WriteFRcp, [ICXPort0], 4, [1], 1, 5>; // Floating point reciprocal estimate. 308defm : ICXWriteResPair<WriteFRcpX, [ICXPort0], 4, [1], 1, 6>; 309defm : ICXWriteResPair<WriteFRcpY, [ICXPort0], 4, [1], 1, 7>; 310defm : ICXWriteResPair<WriteFRcpZ, [ICXPort0,ICXPort5], 4, [2,1], 3, 7>; 311 312defm : ICXWriteResPair<WriteFRsqrt, [ICXPort0], 4, [1], 1, 5>; // Floating point reciprocal square root estimate. 313defm : ICXWriteResPair<WriteFRsqrtX,[ICXPort0], 4, [1], 1, 6>; 314defm : ICXWriteResPair<WriteFRsqrtY,[ICXPort0], 4, [1], 1, 7>; 315defm : ICXWriteResPair<WriteFRsqrtZ,[ICXPort0,ICXPort5], 9, [2,1], 3, 7>; 316 317defm : ICXWriteResPair<WriteFMA, [ICXPort01], 4, [1], 1, 5>; // Fused Multiply Add. 318defm : ICXWriteResPair<WriteFMAX, [ICXPort01], 4, [1], 1, 6>; 319defm : ICXWriteResPair<WriteFMAY, [ICXPort01], 4, [1], 1, 7>; 320defm : ICXWriteResPair<WriteFMAZ, [ICXPort05], 4, [1], 1, 7>; 321defm : ICXWriteResPair<WriteDPPD, [ICXPort5,ICXPort015], 9, [1,2], 3, 6>; // Floating point double dot product. 322defm : ICXWriteResPair<WriteDPPS, [ICXPort5,ICXPort015], 13, [1,3], 4, 6>; 323defm : ICXWriteResPair<WriteDPPSY,[ICXPort5,ICXPort015], 13, [1,3], 4, 7>; 324defm : ICXWriteResPair<WriteDPPSZ,[ICXPort5,ICXPort015], 13, [1,3], 4, 7>; 325defm : ICXWriteResPair<WriteFSign, [ICXPort0], 1>; // Floating point fabs/fchs. 326defm : ICXWriteResPair<WriteFRnd, [ICXPort01], 8, [2], 2, 6>; // Floating point rounding. 327defm : ICXWriteResPair<WriteFRndY, [ICXPort01], 8, [2], 2, 7>; 328defm : ICXWriteResPair<WriteFRndZ, [ICXPort05], 8, [2], 2, 7>; 329defm : ICXWriteResPair<WriteFLogic, [ICXPort015], 1, [1], 1, 6>; // Floating point and/or/xor logicals. 330defm : ICXWriteResPair<WriteFLogicY, [ICXPort015], 1, [1], 1, 7>; 331defm : ICXWriteResPair<WriteFLogicZ, [ICXPort05], 1, [1], 1, 7>; 332defm : ICXWriteResPair<WriteFTest, [ICXPort0], 2, [1], 1, 6>; // Floating point TEST instructions. 333defm : ICXWriteResPair<WriteFTestY, [ICXPort0], 2, [1], 1, 7>; 334defm : ICXWriteResPair<WriteFTestZ, [ICXPort0], 2, [1], 1, 7>; 335defm : ICXWriteResPair<WriteFShuffle, [ICXPort15], 1, [1], 1, 6>; // Floating point vector shuffles. 336defm : ICXWriteResPair<WriteFShuffleY, [ICXPort15], 1, [1], 1, 7>; 337defm : ICXWriteResPair<WriteFShuffleZ, [ICXPort5], 1, [1], 1, 7>; 338defm : ICXWriteResPair<WriteFVarShuffle, [ICXPort15], 1, [1], 1, 6>; // Floating point vector variable shuffles. 339defm : ICXWriteResPair<WriteFVarShuffleY, [ICXPort15], 1, [1], 1, 7>; 340defm : ICXWriteResPair<WriteFVarShuffleZ, [ICXPort5], 1, [1], 1, 7>; 341defm : ICXWriteResPair<WriteFBlend, [ICXPort015], 1, [1], 1, 6>; // Floating point vector blends. 342defm : ICXWriteResPair<WriteFBlendY,[ICXPort015], 1, [1], 1, 7>; 343defm : ICXWriteResPair<WriteFBlendZ,[ICXPort015], 1, [1], 1, 7>; 344defm : ICXWriteResPair<WriteFVarBlend, [ICXPort015], 2, [2], 2, 6>; // Fp vector variable blends. 345defm : ICXWriteResPair<WriteFVarBlendY,[ICXPort015], 2, [2], 2, 7>; 346defm : ICXWriteResPair<WriteFVarBlendZ,[ICXPort015], 2, [2], 2, 7>; 347 348// FMA Scheduling helper class. 349// class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; } 350 351// Vector integer operations. 352defm : X86WriteRes<WriteVecLoad, [ICXPort23], 5, [1], 1>; 353defm : X86WriteRes<WriteVecLoadX, [ICXPort23], 6, [1], 1>; 354defm : X86WriteRes<WriteVecLoadY, [ICXPort23], 7, [1], 1>; 355defm : X86WriteRes<WriteVecLoadNT, [ICXPort23], 6, [1], 1>; 356defm : X86WriteRes<WriteVecLoadNTY, [ICXPort23], 7, [1], 1>; 357defm : X86WriteRes<WriteVecMaskedLoad, [ICXPort23,ICXPort015], 7, [1,1], 2>; 358defm : X86WriteRes<WriteVecMaskedLoadY, [ICXPort23,ICXPort015], 8, [1,1], 2>; 359defm : X86WriteRes<WriteVecStore, [ICXPort237,ICXPort4], 1, [1,1], 2>; 360defm : X86WriteRes<WriteVecStoreX, [ICXPort237,ICXPort4], 1, [1,1], 2>; 361defm : X86WriteRes<WriteVecStoreY, [ICXPort237,ICXPort4], 1, [1,1], 2>; 362defm : X86WriteRes<WriteVecStoreNT, [ICXPort237,ICXPort4], 1, [1,1], 2>; 363defm : X86WriteRes<WriteVecStoreNTY, [ICXPort237,ICXPort4], 1, [1,1], 2>; 364defm : X86WriteRes<WriteVecMaskedStore32, [ICXPort237,ICXPort0], 2, [1,1], 2>; 365defm : X86WriteRes<WriteVecMaskedStore32Y, [ICXPort237,ICXPort0], 2, [1,1], 2>; 366defm : X86WriteRes<WriteVecMaskedStore64, [ICXPort237,ICXPort0], 2, [1,1], 2>; 367defm : X86WriteRes<WriteVecMaskedStore64Y, [ICXPort237,ICXPort0], 2, [1,1], 2>; 368defm : X86WriteRes<WriteVecMove, [ICXPort05], 1, [1], 1>; 369defm : X86WriteRes<WriteVecMoveX, [ICXPort015], 1, [1], 1>; 370defm : X86WriteRes<WriteVecMoveY, [ICXPort015], 1, [1], 1>; 371defm : X86WriteRes<WriteVecMoveZ, [ICXPort05], 1, [1], 1>; 372defm : X86WriteRes<WriteVecMoveToGpr, [ICXPort0], 2, [1], 1>; 373defm : X86WriteRes<WriteVecMoveFromGpr, [ICXPort5], 1, [1], 1>; 374 375defm : ICXWriteResPair<WriteVecALU, [ICXPort05], 1, [1], 1, 5>; // Vector integer ALU op, no logicals. 376defm : ICXWriteResPair<WriteVecALUX, [ICXPort01], 1, [1], 1, 6>; 377defm : ICXWriteResPair<WriteVecALUY, [ICXPort01], 1, [1], 1, 7>; 378defm : ICXWriteResPair<WriteVecALUZ, [ICXPort0], 1, [1], 1, 7>; 379defm : ICXWriteResPair<WriteVecLogic, [ICXPort05], 1, [1], 1, 5>; // Vector integer and/or/xor. 380defm : ICXWriteResPair<WriteVecLogicX,[ICXPort015], 1, [1], 1, 6>; 381defm : ICXWriteResPair<WriteVecLogicY,[ICXPort015], 1, [1], 1, 7>; 382defm : ICXWriteResPair<WriteVecLogicZ,[ICXPort05], 1, [1], 1, 7>; 383defm : ICXWriteResPair<WriteVecTest, [ICXPort0,ICXPort5], 3, [1,1], 2, 6>; // Vector integer TEST instructions. 384defm : ICXWriteResPair<WriteVecTestY, [ICXPort0,ICXPort5], 3, [1,1], 2, 7>; 385defm : ICXWriteResPair<WriteVecTestZ, [ICXPort0,ICXPort5], 3, [1,1], 2, 7>; 386defm : ICXWriteResPair<WriteVecIMul, [ICXPort0], 5, [1], 1, 5>; // Vector integer multiply. 387defm : ICXWriteResPair<WriteVecIMulX, [ICXPort01], 5, [1], 1, 6>; 388defm : ICXWriteResPair<WriteVecIMulY, [ICXPort01], 5, [1], 1, 7>; 389defm : ICXWriteResPair<WriteVecIMulZ, [ICXPort05], 5, [1], 1, 7>; 390defm : ICXWriteResPair<WritePMULLD, [ICXPort01], 10, [2], 2, 6>; // Vector PMULLD. 391defm : ICXWriteResPair<WritePMULLDY, [ICXPort01], 10, [2], 2, 7>; 392defm : ICXWriteResPair<WritePMULLDZ, [ICXPort05], 10, [2], 2, 7>; 393defm : ICXWriteResPair<WriteShuffle, [ICXPort5], 1, [1], 1, 5>; // Vector shuffles. 394defm : ICXWriteResPair<WriteShuffleX, [ICXPort15], 1, [1], 1, 6>; 395defm : ICXWriteResPair<WriteShuffleY, [ICXPort15], 1, [1], 1, 7>; 396defm : ICXWriteResPair<WriteShuffleZ, [ICXPort5], 1, [1], 1, 7>; 397defm : ICXWriteResPair<WriteVarShuffle, [ICXPort5], 1, [1], 1, 5>; // Vector variable shuffles. 398defm : ICXWriteResPair<WriteVarShuffleX, [ICXPort15], 1, [1], 1, 6>; 399defm : ICXWriteResPair<WriteVarShuffleY, [ICXPort15], 1, [1], 1, 7>; 400defm : ICXWriteResPair<WriteVarShuffleZ, [ICXPort5], 1, [1], 1, 7>; 401defm : ICXWriteResPair<WriteBlend, [ICXPort5], 1, [1], 1, 6>; // Vector blends. 402defm : ICXWriteResPair<WriteBlendY,[ICXPort5], 1, [1], 1, 7>; 403defm : ICXWriteResPair<WriteBlendZ,[ICXPort5], 1, [1], 1, 7>; 404defm : ICXWriteResPair<WriteVarBlend, [ICXPort015], 2, [2], 2, 6>; // Vector variable blends. 405defm : ICXWriteResPair<WriteVarBlendY,[ICXPort015], 2, [2], 2, 6>; 406defm : ICXWriteResPair<WriteVarBlendZ,[ICXPort05], 2, [1], 1, 6>; 407defm : ICXWriteResPair<WriteMPSAD, [ICXPort5], 4, [2], 2, 6>; // Vector MPSAD. 408defm : ICXWriteResPair<WriteMPSADY, [ICXPort5], 4, [2], 2, 7>; 409defm : ICXWriteResPair<WriteMPSADZ, [ICXPort5], 4, [2], 2, 7>; 410defm : ICXWriteResPair<WritePSADBW, [ICXPort5], 3, [1], 1, 5>; // Vector PSADBW. 411defm : ICXWriteResPair<WritePSADBWX, [ICXPort5], 3, [1], 1, 6>; 412defm : ICXWriteResPair<WritePSADBWY, [ICXPort5], 3, [1], 1, 7>; 413defm : ICXWriteResPair<WritePSADBWZ, [ICXPort5], 3, [1], 1, 7>; 414defm : ICXWriteResPair<WritePHMINPOS, [ICXPort0], 4, [1], 1, 6>; // Vector PHMINPOS. 415 416// Vector integer shifts. 417defm : ICXWriteResPair<WriteVecShift, [ICXPort0], 1, [1], 1, 5>; 418defm : X86WriteRes<WriteVecShiftX, [ICXPort5,ICXPort01], 2, [1,1], 2>; 419defm : X86WriteRes<WriteVecShiftY, [ICXPort5,ICXPort01], 4, [1,1], 2>; 420defm : X86WriteRes<WriteVecShiftZ, [ICXPort5,ICXPort0], 4, [1,1], 2>; 421defm : X86WriteRes<WriteVecShiftXLd, [ICXPort01,ICXPort23], 7, [1,1], 2>; 422defm : X86WriteRes<WriteVecShiftYLd, [ICXPort01,ICXPort23], 8, [1,1], 2>; 423defm : X86WriteRes<WriteVecShiftZLd, [ICXPort0,ICXPort23], 8, [1,1], 2>; 424 425defm : ICXWriteResPair<WriteVecShiftImm, [ICXPort0], 1, [1], 1, 5>; 426defm : ICXWriteResPair<WriteVecShiftImmX, [ICXPort01], 1, [1], 1, 6>; // Vector integer immediate shifts. 427defm : ICXWriteResPair<WriteVecShiftImmY, [ICXPort01], 1, [1], 1, 7>; 428defm : ICXWriteResPair<WriteVecShiftImmZ, [ICXPort0], 1, [1], 1, 7>; 429defm : ICXWriteResPair<WriteVarVecShift, [ICXPort01], 1, [1], 1, 6>; // Variable vector shifts. 430defm : ICXWriteResPair<WriteVarVecShiftY, [ICXPort01], 1, [1], 1, 7>; 431defm : ICXWriteResPair<WriteVarVecShiftZ, [ICXPort0], 1, [1], 1, 7>; 432 433// Vector insert/extract operations. 434def : WriteRes<WriteVecInsert, [ICXPort5]> { 435 let Latency = 2; 436 let NumMicroOps = 2; 437 let ResourceCycles = [2]; 438} 439def : WriteRes<WriteVecInsertLd, [ICXPort5,ICXPort23]> { 440 let Latency = 6; 441 let NumMicroOps = 2; 442} 443def: InstRW<[WriteVecInsertLd], (instregex "(V?)MOV(H|L)(PD|PS)rm")>; 444 445def : WriteRes<WriteVecExtract, [ICXPort0,ICXPort5]> { 446 let Latency = 3; 447 let NumMicroOps = 2; 448} 449def : WriteRes<WriteVecExtractSt, [ICXPort4,ICXPort5,ICXPort237]> { 450 let Latency = 2; 451 let NumMicroOps = 3; 452} 453 454// Conversion between integer and float. 455defm : ICXWriteResPair<WriteCvtSS2I, [ICXPort01], 6, [2], 2>; // Needs more work: DD vs DQ. 456defm : ICXWriteResPair<WriteCvtPS2I, [ICXPort01], 3>; 457defm : ICXWriteResPair<WriteCvtPS2IY, [ICXPort01], 3>; 458defm : ICXWriteResPair<WriteCvtPS2IZ, [ICXPort05], 3>; 459defm : ICXWriteResPair<WriteCvtSD2I, [ICXPort01], 6, [2], 2>; 460defm : ICXWriteResPair<WriteCvtPD2I, [ICXPort01], 3>; 461defm : ICXWriteResPair<WriteCvtPD2IY, [ICXPort01], 3>; 462defm : ICXWriteResPair<WriteCvtPD2IZ, [ICXPort05], 3>; 463 464defm : ICXWriteResPair<WriteCvtI2SS, [ICXPort1], 4>; 465defm : ICXWriteResPair<WriteCvtI2PS, [ICXPort01], 4>; 466defm : ICXWriteResPair<WriteCvtI2PSY, [ICXPort01], 4>; 467defm : ICXWriteResPair<WriteCvtI2PSZ, [ICXPort05], 4>; // Needs more work: DD vs DQ. 468defm : ICXWriteResPair<WriteCvtI2SD, [ICXPort1], 4>; 469defm : ICXWriteResPair<WriteCvtI2PD, [ICXPort01], 4>; 470defm : ICXWriteResPair<WriteCvtI2PDY, [ICXPort01], 4>; 471defm : ICXWriteResPair<WriteCvtI2PDZ, [ICXPort05], 4>; 472 473defm : ICXWriteResPair<WriteCvtSS2SD, [ICXPort1], 3>; 474defm : ICXWriteResPair<WriteCvtPS2PD, [ICXPort1], 3>; 475defm : ICXWriteResPair<WriteCvtPS2PDY, [ICXPort5,ICXPort01], 3, [1,1], 2>; 476defm : ICXWriteResPair<WriteCvtPS2PDZ, [ICXPort05], 3, [2], 2>; 477defm : ICXWriteResPair<WriteCvtSD2SS, [ICXPort1], 3>; 478defm : ICXWriteResPair<WriteCvtPD2PS, [ICXPort1], 3>; 479defm : ICXWriteResPair<WriteCvtPD2PSY, [ICXPort5,ICXPort01], 3, [1,1], 2>; 480defm : ICXWriteResPair<WriteCvtPD2PSZ, [ICXPort05], 3, [2], 2>; 481 482defm : X86WriteRes<WriteCvtPH2PS, [ICXPort5,ICXPort01], 5, [1,1], 2>; 483defm : X86WriteRes<WriteCvtPH2PSY, [ICXPort5,ICXPort01], 7, [1,1], 2>; 484defm : X86WriteRes<WriteCvtPH2PSZ, [ICXPort5,ICXPort0], 7, [1,1], 2>; 485defm : X86WriteRes<WriteCvtPH2PSLd, [ICXPort23,ICXPort01], 9, [1,1], 2>; 486defm : X86WriteRes<WriteCvtPH2PSYLd, [ICXPort23,ICXPort01], 10, [1,1], 2>; 487defm : X86WriteRes<WriteCvtPH2PSZLd, [ICXPort23,ICXPort05], 10, [1,1], 2>; 488 489defm : X86WriteRes<WriteCvtPS2PH, [ICXPort5,ICXPort01], 5, [1,1], 2>; 490defm : X86WriteRes<WriteCvtPS2PHY, [ICXPort5,ICXPort01], 7, [1,1], 2>; 491defm : X86WriteRes<WriteCvtPS2PHZ, [ICXPort5,ICXPort05], 7, [1,1], 2>; 492defm : X86WriteRes<WriteCvtPS2PHSt, [ICXPort4,ICXPort5,ICXPort237,ICXPort01], 6, [1,1,1,1], 4>; 493defm : X86WriteRes<WriteCvtPS2PHYSt, [ICXPort4,ICXPort5,ICXPort237,ICXPort01], 8, [1,1,1,1], 4>; 494defm : X86WriteRes<WriteCvtPS2PHZSt, [ICXPort4,ICXPort5,ICXPort237,ICXPort05], 8, [1,1,1,1], 4>; 495 496// Strings instructions. 497 498// Packed Compare Implicit Length Strings, Return Mask 499def : WriteRes<WritePCmpIStrM, [ICXPort0]> { 500 let Latency = 10; 501 let NumMicroOps = 3; 502 let ResourceCycles = [3]; 503} 504def : WriteRes<WritePCmpIStrMLd, [ICXPort0, ICXPort23]> { 505 let Latency = 16; 506 let NumMicroOps = 4; 507 let ResourceCycles = [3,1]; 508} 509 510// Packed Compare Explicit Length Strings, Return Mask 511def : WriteRes<WritePCmpEStrM, [ICXPort0, ICXPort5, ICXPort015, ICXPort0156]> { 512 let Latency = 19; 513 let NumMicroOps = 9; 514 let ResourceCycles = [4,3,1,1]; 515} 516def : WriteRes<WritePCmpEStrMLd, [ICXPort0, ICXPort5, ICXPort23, ICXPort015, ICXPort0156]> { 517 let Latency = 25; 518 let NumMicroOps = 10; 519 let ResourceCycles = [4,3,1,1,1]; 520} 521 522// Packed Compare Implicit Length Strings, Return Index 523def : WriteRes<WritePCmpIStrI, [ICXPort0]> { 524 let Latency = 10; 525 let NumMicroOps = 3; 526 let ResourceCycles = [3]; 527} 528def : WriteRes<WritePCmpIStrILd, [ICXPort0, ICXPort23]> { 529 let Latency = 16; 530 let NumMicroOps = 4; 531 let ResourceCycles = [3,1]; 532} 533 534// Packed Compare Explicit Length Strings, Return Index 535def : WriteRes<WritePCmpEStrI, [ICXPort0,ICXPort5,ICXPort0156]> { 536 let Latency = 18; 537 let NumMicroOps = 8; 538 let ResourceCycles = [4,3,1]; 539} 540def : WriteRes<WritePCmpEStrILd, [ICXPort0, ICXPort5, ICXPort23, ICXPort0156]> { 541 let Latency = 24; 542 let NumMicroOps = 9; 543 let ResourceCycles = [4,3,1,1]; 544} 545 546// MOVMSK Instructions. 547def : WriteRes<WriteFMOVMSK, [ICXPort0]> { let Latency = 2; } 548def : WriteRes<WriteVecMOVMSK, [ICXPort0]> { let Latency = 2; } 549def : WriteRes<WriteVecMOVMSKY, [ICXPort0]> { let Latency = 2; } 550def : WriteRes<WriteMMXMOVMSK, [ICXPort0]> { let Latency = 2; } 551 552// AES instructions. 553def : WriteRes<WriteAESDecEnc, [ICXPort0]> { // Decryption, encryption. 554 let Latency = 4; 555 let NumMicroOps = 1; 556 let ResourceCycles = [1]; 557} 558def : WriteRes<WriteAESDecEncLd, [ICXPort0, ICXPort23]> { 559 let Latency = 10; 560 let NumMicroOps = 2; 561 let ResourceCycles = [1,1]; 562} 563 564def : WriteRes<WriteAESIMC, [ICXPort0]> { // InvMixColumn. 565 let Latency = 8; 566 let NumMicroOps = 2; 567 let ResourceCycles = [2]; 568} 569def : WriteRes<WriteAESIMCLd, [ICXPort0, ICXPort23]> { 570 let Latency = 14; 571 let NumMicroOps = 3; 572 let ResourceCycles = [2,1]; 573} 574 575def : WriteRes<WriteAESKeyGen, [ICXPort0,ICXPort5,ICXPort015]> { // Key Generation. 576 let Latency = 20; 577 let NumMicroOps = 11; 578 let ResourceCycles = [3,6,2]; 579} 580def : WriteRes<WriteAESKeyGenLd, [ICXPort0,ICXPort5,ICXPort23,ICXPort015]> { 581 let Latency = 25; 582 let NumMicroOps = 11; 583 let ResourceCycles = [3,6,1,1]; 584} 585 586// Carry-less multiplication instructions. 587def : WriteRes<WriteCLMul, [ICXPort5]> { 588 let Latency = 6; 589 let NumMicroOps = 1; 590 let ResourceCycles = [1]; 591} 592def : WriteRes<WriteCLMulLd, [ICXPort5, ICXPort23]> { 593 let Latency = 12; 594 let NumMicroOps = 2; 595 let ResourceCycles = [1,1]; 596} 597 598// Catch-all for expensive system instructions. 599def : WriteRes<WriteSystem, [ICXPort0156]> { let Latency = 100; } // def WriteSystem : SchedWrite; 600 601// AVX2. 602defm : ICXWriteResPair<WriteFShuffle256, [ICXPort5], 3, [1], 1, 7>; // Fp 256-bit width vector shuffles. 603defm : ICXWriteResPair<WriteFVarShuffle256, [ICXPort5], 3, [1], 1, 7>; // Fp 256-bit width vector variable shuffles. 604defm : ICXWriteResPair<WriteShuffle256, [ICXPort5], 3, [1], 1, 7>; // 256-bit width vector shuffles. 605defm : ICXWriteResPair<WriteVPMOV256, [ICXPort5], 3, [1], 1, 7>; // 256-bit width packed vector width-changing move. 606defm : ICXWriteResPair<WriteVarShuffle256, [ICXPort5], 3, [1], 1, 7>; // 256-bit width vector variable shuffles. 607 608// Old microcoded instructions that nobody use. 609def : WriteRes<WriteMicrocoded, [ICXPort0156]> { let Latency = 100; } // def WriteMicrocoded : SchedWrite; 610 611// Fence instructions. 612def : WriteRes<WriteFence, [ICXPort23, ICXPort4]>; 613 614// Load/store MXCSR. 615def : WriteRes<WriteLDMXCSR, [ICXPort0,ICXPort23,ICXPort0156]> { let Latency = 7; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } 616def : WriteRes<WriteSTMXCSR, [ICXPort4,ICXPort5,ICXPort237]> { let Latency = 2; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } 617 618// Nop, not very useful expect it provides a model for nops! 619def : WriteRes<WriteNop, []>; 620 621//////////////////////////////////////////////////////////////////////////////// 622// Horizontal add/sub instructions. 623//////////////////////////////////////////////////////////////////////////////// 624 625defm : ICXWriteResPair<WriteFHAdd, [ICXPort5,ICXPort015], 6, [2,1], 3, 6>; 626defm : ICXWriteResPair<WriteFHAddY, [ICXPort5,ICXPort015], 6, [2,1], 3, 7>; 627defm : ICXWriteResPair<WritePHAdd, [ICXPort5,ICXPort05], 3, [2,1], 3, 5>; 628defm : ICXWriteResPair<WritePHAddX, [ICXPort5,ICXPort015], 3, [2,1], 3, 6>; 629defm : ICXWriteResPair<WritePHAddY, [ICXPort5,ICXPort015], 3, [2,1], 3, 7>; 630 631// Remaining instrs. 632 633def ICXWriteResGroup1 : SchedWriteRes<[ICXPort0]> { 634 let Latency = 1; 635 let NumMicroOps = 1; 636 let ResourceCycles = [1]; 637} 638def: InstRW<[ICXWriteResGroup1], (instregex "KAND(B|D|Q|W)rr", 639 "KANDN(B|D|Q|W)rr", 640 "KMOV(B|D|Q|W)kk", 641 "KNOT(B|D|Q|W)rr", 642 "KOR(B|D|Q|W)rr", 643 "KXNOR(B|D|Q|W)rr", 644 "KXOR(B|D|Q|W)rr", 645 "KSET0(B|D|Q|W)", // Same as KXOR 646 "KSET1(B|D|Q|W)", // Same as KXNOR 647 "MMX_PADDS(B|W)rr", 648 "MMX_PADDUS(B|W)rr", 649 "MMX_PAVG(B|W)rr", 650 "MMX_PCMPEQ(B|D|W)rr", 651 "MMX_PCMPGT(B|D|W)rr", 652 "MMX_P(MAX|MIN)SWrr", 653 "MMX_P(MAX|MIN)UBrr", 654 "MMX_PSUBS(B|W)rr", 655 "MMX_PSUBUS(B|W)rr", 656 "VPMOVB2M(Z|Z128|Z256)rr", 657 "VPMOVD2M(Z|Z128|Z256)rr", 658 "VPMOVQ2M(Z|Z128|Z256)rr", 659 "VPMOVW2M(Z|Z128|Z256)rr")>; 660 661def ICXWriteResGroup3 : SchedWriteRes<[ICXPort5]> { 662 let Latency = 1; 663 let NumMicroOps = 1; 664 let ResourceCycles = [1]; 665} 666def: InstRW<[ICXWriteResGroup3], (instregex "COM(P?)_FST0r", 667 "KMOV(B|D|Q|W)kr", 668 "UCOM_F(P?)r", 669 "VPBROADCAST(D|Q)rr", 670 "(V?)INSERTPS(Z?)rr", 671 "(V?)MOV(HL|LH)PS(Z?)rr", 672 "(V?)MOVDDUP(Y|Z|Z128|Z256)?rr", 673 "(V?)PALIGNR(Y|Z|Z128|Z256)?rri", 674 "(V?)PERMIL(PD|PS)(Y|Z|Z128|Z256)?ri", 675 "(V?)PERMIL(PD|PS)(Y|Z|Z128|Z256)?rr", 676 "(V?)PACK(U|S)S(DW|WB)(Y|Z|Z128|Z256)?rr", 677 "(V?)UNPCK(L|H)(PD|PS)(Y|Z|Z128|Z256)?rr")>; 678 679def ICXWriteResGroup4 : SchedWriteRes<[ICXPort6]> { 680 let Latency = 1; 681 let NumMicroOps = 1; 682 let ResourceCycles = [1]; 683} 684def: InstRW<[ICXWriteResGroup4], (instregex "JMP(16|32|64)r")>; 685 686def ICXWriteResGroup6 : SchedWriteRes<[ICXPort05]> { 687 let Latency = 1; 688 let NumMicroOps = 1; 689 let ResourceCycles = [1]; 690} 691def: InstRW<[ICXWriteResGroup6], (instrs FINCSTP, FNOP)>; 692 693def ICXWriteResGroup7 : SchedWriteRes<[ICXPort06]> { 694 let Latency = 1; 695 let NumMicroOps = 1; 696 let ResourceCycles = [1]; 697} 698def: InstRW<[ICXWriteResGroup7], (instrs CDQ, CQO, CLAC, STAC)>; 699 700def ICXWriteResGroup8 : SchedWriteRes<[ICXPort15]> { 701 let Latency = 1; 702 let NumMicroOps = 1; 703 let ResourceCycles = [1]; 704} 705def: InstRW<[ICXWriteResGroup8], (instregex "ANDN(32|64)rr")>; 706 707def ICXWriteResGroup9 : SchedWriteRes<[ICXPort015]> { 708 let Latency = 1; 709 let NumMicroOps = 1; 710 let ResourceCycles = [1]; 711} 712def: InstRW<[ICXWriteResGroup9], (instregex "VBLENDMPD(Z128|Z256)rr", 713 "VBLENDMPS(Z128|Z256)rr", 714 "VPADD(B|D|Q|W)(Y|Z|Z128|Z256)rr", 715 "(V?)PADD(B|D|Q|W)rr", 716 "(V?)MOV(SD|SS)(Z?)rr", 717 "VPBLENDD(Y?)rri", 718 "VPBLENDMB(Z128|Z256)rr", 719 "VPBLENDMD(Z128|Z256)rr", 720 "VPBLENDMQ(Z128|Z256)rr", 721 "VPBLENDMW(Z128|Z256)rr", 722 "VPSUB(B|D|Q|W)(Y|Z|Z128|Z256)rrk", 723 "VPTERNLOGD(Z|Z128|Z256)rri", 724 "VPTERNLOGQ(Z|Z128|Z256)rri")>; 725 726def ICXWriteResGroup10 : SchedWriteRes<[ICXPort0156]> { 727 let Latency = 1; 728 let NumMicroOps = 1; 729 let ResourceCycles = [1]; 730} 731def: InstRW<[ICXWriteResGroup10], (instrs CBW, CWDE, CDQE, 732 CMC, STC, 733 SGDT64m, 734 SIDT64m, 735 SMSW16m, 736 STRm, 737 SYSCALL)>; 738 739def ICXWriteResGroup11 : SchedWriteRes<[ICXPort4,ICXPort237]> { 740 let Latency = 1; 741 let NumMicroOps = 2; 742 let ResourceCycles = [1,1]; 743} 744def: InstRW<[ICXWriteResGroup11], (instrs FBSTPm, VMPTRSTm)>; 745def: InstRW<[ICXWriteResGroup11], (instregex "KMOV(B|D|Q|W)mk", 746 "ST_FP(32|64|80)m")>; 747 748def ICXWriteResGroup13 : SchedWriteRes<[ICXPort5]> { 749 let Latency = 2; 750 let NumMicroOps = 2; 751 let ResourceCycles = [2]; 752} 753def: InstRW<[ICXWriteResGroup13], (instrs MMX_MOVQ2DQrr)>; 754 755def ICXWriteResGroup14 : SchedWriteRes<[ICXPort05]> { 756 let Latency = 2; 757 let NumMicroOps = 2; 758 let ResourceCycles = [2]; 759} 760def: InstRW<[ICXWriteResGroup14], (instrs FDECSTP, 761 MMX_MOVDQ2Qrr)>; 762 763def ICXWriteResGroup17 : SchedWriteRes<[ICXPort0156]> { 764 let Latency = 2; 765 let NumMicroOps = 2; 766 let ResourceCycles = [2]; 767} 768def: InstRW<[ICXWriteResGroup17], (instrs LFENCE, 769 WAIT, 770 XGETBV)>; 771 772def ICXWriteResGroup20 : SchedWriteRes<[ICXPort6,ICXPort0156]> { 773 let Latency = 2; 774 let NumMicroOps = 2; 775 let ResourceCycles = [1,1]; 776} 777def: InstRW<[ICXWriteResGroup20], (instregex "CLFLUSH")>; 778 779def ICXWriteResGroup21 : SchedWriteRes<[ICXPort237,ICXPort0156]> { 780 let Latency = 2; 781 let NumMicroOps = 2; 782 let ResourceCycles = [1,1]; 783} 784def: InstRW<[ICXWriteResGroup21], (instrs SFENCE)>; 785 786def ICXWriteResGroup23 : SchedWriteRes<[ICXPort06,ICXPort0156]> { 787 let Latency = 2; 788 let NumMicroOps = 2; 789 let ResourceCycles = [1,1]; 790} 791def: InstRW<[ICXWriteResGroup23], (instrs CWD, 792 JCXZ, JECXZ, JRCXZ, 793 ADC8i8, SBB8i8, 794 ADC16i16, SBB16i16, 795 ADC32i32, SBB32i32, 796 ADC64i32, SBB64i32)>; 797 798def ICXWriteResGroup25 : SchedWriteRes<[ICXPort4,ICXPort6,ICXPort237]> { 799 let Latency = 2; 800 let NumMicroOps = 3; 801 let ResourceCycles = [1,1,1]; 802} 803def: InstRW<[ICXWriteResGroup25], (instrs FNSTCW16m)>; 804 805def ICXWriteResGroup27 : SchedWriteRes<[ICXPort4,ICXPort237,ICXPort15]> { 806 let Latency = 2; 807 let NumMicroOps = 3; 808 let ResourceCycles = [1,1,1]; 809} 810def: InstRW<[ICXWriteResGroup27], (instregex "MOVBE(16|32|64)mr")>; 811 812def ICXWriteResGroup28 : SchedWriteRes<[ICXPort4,ICXPort237,ICXPort0156]> { 813 let Latency = 2; 814 let NumMicroOps = 3; 815 let ResourceCycles = [1,1,1]; 816} 817def: InstRW<[ICXWriteResGroup28], (instrs PUSH16r, PUSH32r, PUSH64r, PUSH64i8, 818 STOSB, STOSL, STOSQ, STOSW)>; 819def: InstRW<[ICXWriteResGroup28], (instregex "PUSH(16|32|64)rmr")>; 820 821def ICXWriteResGroup29 : SchedWriteRes<[ICXPort4,ICXPort237,ICXPort15]> { 822 let Latency = 2; 823 let NumMicroOps = 5; 824 let ResourceCycles = [2,2,1]; 825} 826def: InstRW<[ICXWriteResGroup29], (instregex "VMOVDQU8Zmr(b?)")>; 827 828def ICXWriteResGroup30 : SchedWriteRes<[ICXPort0]> { 829 let Latency = 3; 830 let NumMicroOps = 1; 831 let ResourceCycles = [1]; 832} 833def: InstRW<[ICXWriteResGroup30], (instregex "KMOV(B|D|Q|W)rk", 834 "KORTEST(B|D|Q|W)rr", 835 "KTEST(B|D|Q|W)rr")>; 836 837def ICXWriteResGroup31 : SchedWriteRes<[ICXPort1]> { 838 let Latency = 3; 839 let NumMicroOps = 1; 840 let ResourceCycles = [1]; 841} 842def: InstRW<[ICXWriteResGroup31], (instregex "PDEP(32|64)rr", 843 "PEXT(32|64)rr")>; 844 845def ICXWriteResGroup32 : SchedWriteRes<[ICXPort5]> { 846 let Latency = 3; 847 let NumMicroOps = 1; 848 let ResourceCycles = [1]; 849} 850def: InstRW<[ICXWriteResGroup32], (instrs VPSADBWZrr)>; // TODO: 512-bit ops require ports 0/1 to be joined. 851def: InstRW<[ICXWriteResGroup32], (instregex "(ADD|SUB|SUBR)_(FPrST0|FST0r|FrST0)", 852 "VALIGND(Z|Z128|Z256)rri", 853 "VALIGNQ(Z|Z128|Z256)rri", 854 "VDBPSADBWZrri", // TODO: 512-bit ops require ports 0/1 to be joined. 855 "VPBROADCAST(B|W)rr", 856 "VP(MAX|MIN)(S|U)Q(Z|Z128|Z256)rr")>; 857 858def ICXWriteResGroup33 : SchedWriteRes<[ICXPort5]> { 859 let Latency = 4; 860 let NumMicroOps = 1; 861 let ResourceCycles = [1]; 862} 863def: InstRW<[ICXWriteResGroup33], (instregex "KADD(B|D|Q|W)rr", 864 "KSHIFTL(B|D|Q|W)ri", 865 "KSHIFTR(B|D|Q|W)ri", 866 "KUNPCK(BW|DQ|WD)rr", 867 "VCMPPD(Z|Z128|Z256)rri", 868 "VCMPPS(Z|Z128|Z256)rri", 869 "VCMP(SD|SS)Zrr", 870 "VFPCLASS(PD|PS)(Z|Z128|Z256)rr", 871 "VFPCLASS(SD|SS)Zrr", 872 "VPCMPB(Z|Z128|Z256)rri", 873 "VPCMPD(Z|Z128|Z256)rri", 874 "VPCMPEQ(B|D|Q|W)(Z|Z128|Z256)rr", 875 "VPCMPGT(B|D|Q|W)(Z|Z128|Z256)rr", 876 "VPCMPQ(Z|Z128|Z256)rri", 877 "VPCMPU(B|D|Q|W)(Z|Z128|Z256)rri", 878 "VPCMPW(Z|Z128|Z256)rri", 879 "VPTEST(N?)M(B|D|Q|W)(Z|Z128|Z256)rr")>; 880 881def ICXWriteResGroup34 : SchedWriteRes<[ICXPort0,ICXPort0156]> { 882 let Latency = 3; 883 let NumMicroOps = 2; 884 let ResourceCycles = [1,1]; 885} 886def: InstRW<[ICXWriteResGroup34], (instrs FNSTSW16r)>; 887 888def ICXWriteResGroup37 : SchedWriteRes<[ICXPort0,ICXPort5]> { 889 let Latency = 3; 890 let NumMicroOps = 3; 891 let ResourceCycles = [1,2]; 892} 893def: InstRW<[ICXWriteResGroup37], (instregex "MMX_PH(ADD|SUB)SWrr")>; 894 895def ICXWriteResGroup38 : SchedWriteRes<[ICXPort5,ICXPort01]> { 896 let Latency = 3; 897 let NumMicroOps = 3; 898 let ResourceCycles = [2,1]; 899} 900def: InstRW<[ICXWriteResGroup38], (instregex "(V?)PH(ADD|SUB)SW(Y?)rr")>; 901 902def ICXWriteResGroup41 : SchedWriteRes<[ICXPort5,ICXPort0156]> { 903 let Latency = 3; 904 let NumMicroOps = 3; 905 let ResourceCycles = [2,1]; 906} 907def: InstRW<[ICXWriteResGroup41], (instrs MMX_PACKSSDWrr, 908 MMX_PACKSSWBrr, 909 MMX_PACKUSWBrr)>; 910 911def ICXWriteResGroup42 : SchedWriteRes<[ICXPort6,ICXPort0156]> { 912 let Latency = 3; 913 let NumMicroOps = 3; 914 let ResourceCycles = [1,2]; 915} 916def: InstRW<[ICXWriteResGroup42], (instregex "CLD")>; 917 918def ICXWriteResGroup43 : SchedWriteRes<[ICXPort237,ICXPort0156]> { 919 let Latency = 3; 920 let NumMicroOps = 3; 921 let ResourceCycles = [1,2]; 922} 923def: InstRW<[ICXWriteResGroup43], (instrs MFENCE)>; 924 925def ICXWriteResGroup44 : SchedWriteRes<[ICXPort06,ICXPort0156]> { 926 let Latency = 3; 927 let NumMicroOps = 3; 928 let ResourceCycles = [1,2]; 929} 930def: InstRW<[ICXWriteResGroup44], (instregex "RCL(8|16|32|64)r(1|i)", 931 "RCR(8|16|32|64)r(1|i)")>; 932 933def ICXWriteResGroup45 : SchedWriteRes<[ICXPort0,ICXPort4,ICXPort237]> { 934 let Latency = 3; 935 let NumMicroOps = 3; 936 let ResourceCycles = [1,1,1]; 937} 938def: InstRW<[ICXWriteResGroup45], (instrs FNSTSWm)>; 939 940def ICXWriteResGroup47 : SchedWriteRes<[ICXPort4,ICXPort6,ICXPort237,ICXPort0156]> { 941 let Latency = 3; 942 let NumMicroOps = 4; 943 let ResourceCycles = [1,1,1,1]; 944} 945def: InstRW<[ICXWriteResGroup47], (instregex "CALL(16|32|64)r")>; 946 947def ICXWriteResGroup48 : SchedWriteRes<[ICXPort4,ICXPort237,ICXPort06,ICXPort0156]> { 948 let Latency = 3; 949 let NumMicroOps = 4; 950 let ResourceCycles = [1,1,1,1]; 951} 952def: InstRW<[ICXWriteResGroup48], (instrs CALL64pcrel32)>; 953 954def ICXWriteResGroup49 : SchedWriteRes<[ICXPort0]> { 955 let Latency = 4; 956 let NumMicroOps = 1; 957 let ResourceCycles = [1]; 958} 959def: InstRW<[ICXWriteResGroup49], (instregex "MUL_(FPrST0|FST0r|FrST0)")>; 960 961def ICXWriteResGroup50 : SchedWriteRes<[ICXPort01]> { 962 let Latency = 4; 963 let NumMicroOps = 1; 964 let ResourceCycles = [1]; 965} 966def: InstRW<[ICXWriteResGroup50], (instregex "VCVTDQ2PS(Y|Z128|Z256)rr", 967 "(V?)CVTDQ2PSrr", 968 "VCVTPD2QQ(Z128|Z256)rr", 969 "VCVTPD2UQQ(Z128|Z256)rr", 970 "VCVTPS2DQ(Y|Z128|Z256)rr", 971 "(V?)CVTPS2DQrr", 972 "VCVTPS2UDQ(Z128|Z256)rr", 973 "VCVTQQ2PD(Z128|Z256)rr", 974 "VCVTTPD2QQ(Z128|Z256)rr", 975 "VCVTTPD2UQQ(Z128|Z256)rr", 976 "VCVTTPS2DQ(Z128|Z256)rr", 977 "(V?)CVTTPS2DQrr", 978 "VCVTTPS2UDQ(Z128|Z256)rr", 979 "VCVTUDQ2PS(Z128|Z256)rr", 980 "VCVTUQQ2PD(Z128|Z256)rr")>; 981 982def ICXWriteResGroup50z : SchedWriteRes<[ICXPort05]> { 983 let Latency = 4; 984 let NumMicroOps = 1; 985 let ResourceCycles = [1]; 986} 987def: InstRW<[ICXWriteResGroup50z], (instrs VCVTDQ2PSZrr, 988 VCVTPD2QQZrr, 989 VCVTPD2UQQZrr, 990 VCVTPS2DQZrr, 991 VCVTPS2UDQZrr, 992 VCVTQQ2PDZrr, 993 VCVTTPD2QQZrr, 994 VCVTTPD2UQQZrr, 995 VCVTTPS2DQZrr, 996 VCVTTPS2UDQZrr, 997 VCVTUDQ2PSZrr, 998 VCVTUQQ2PDZrr)>; 999 1000def ICXWriteResGroup51 : SchedWriteRes<[ICXPort5]> { 1001 let Latency = 4; 1002 let NumMicroOps = 2; 1003 let ResourceCycles = [2]; 1004} 1005def: InstRW<[ICXWriteResGroup51], (instregex "VEXPANDPD(Z|Z128|Z256)rr", 1006 "VEXPANDPS(Z|Z128|Z256)rr", 1007 "VPEXPANDD(Z|Z128|Z256)rr", 1008 "VPEXPANDQ(Z|Z128|Z256)rr", 1009 "VPMOVDB(Z|Z128|Z256)rr", 1010 "VPMOVDW(Z|Z128|Z256)rr", 1011 "VPMOVQB(Z|Z128|Z256)rr", 1012 "VPMOVQW(Z|Z128|Z256)rr", 1013 "VPMOVSDB(Z|Z128|Z256)rr", 1014 "VPMOVSDW(Z|Z128|Z256)rr", 1015 "VPMOVSQB(Z|Z128|Z256)rr", 1016 "VPMOVSQD(Z|Z128|Z256)rr", 1017 "VPMOVSQW(Z|Z128|Z256)rr", 1018 "VPMOVSWB(Z|Z128|Z256)rr", 1019 "VPMOVUSDB(Z|Z128|Z256)rr", 1020 "VPMOVUSDW(Z|Z128|Z256)rr", 1021 "VPMOVUSQB(Z|Z128|Z256)rr", 1022 "VPMOVUSQD(Z|Z128|Z256)rr", 1023 "VPMOVUSWB(Z|Z128|Z256)rr", 1024 "VPMOVWB(Z|Z128|Z256)rr")>; 1025 1026def ICXWriteResGroup54 : SchedWriteRes<[ICXPort4,ICXPort5,ICXPort237]> { 1027 let Latency = 4; 1028 let NumMicroOps = 3; 1029 let ResourceCycles = [1,1,1]; 1030} 1031def: InstRW<[ICXWriteResGroup54], (instregex "IST(T?)_FP(16|32|64)m", 1032 "IST_F(16|32)m", 1033 "VPMOVQD(Z|Z128|Z256)mr(b?)")>; 1034 1035def ICXWriteResGroup55 : SchedWriteRes<[ICXPort0156]> { 1036 let Latency = 4; 1037 let NumMicroOps = 4; 1038 let ResourceCycles = [4]; 1039} 1040def: InstRW<[ICXWriteResGroup55], (instrs FNCLEX)>; 1041 1042def ICXWriteResGroup56 : SchedWriteRes<[]> { 1043 let Latency = 0; 1044 let NumMicroOps = 4; 1045 let ResourceCycles = []; 1046} 1047def: InstRW<[ICXWriteResGroup56], (instrs VZEROUPPER)>; 1048 1049def ICXWriteResGroup57 : SchedWriteRes<[ICXPort1,ICXPort6,ICXPort0156]> { 1050 let Latency = 4; 1051 let NumMicroOps = 4; 1052 let ResourceCycles = [1,1,2]; 1053} 1054def: InstRW<[ICXWriteResGroup57], (instregex "LAR(16|32|64)rr")>; 1055 1056def ICXWriteResGroup58 : SchedWriteRes<[ICXPort23]> { 1057 let Latency = 5; 1058 let NumMicroOps = 1; 1059 let ResourceCycles = [1]; 1060} 1061def: InstRW<[ICXWriteResGroup58], (instregex "MOVSX(16|32|64)rm(8|16|32)", 1062 "MOVZX(16|32|64)rm(8|16)", 1063 "(V?)MOVDDUPrm")>; // TODO: Should this be ICXWriteResGroup71? 1064 1065def ICXWriteResGroup61 : SchedWriteRes<[ICXPort5,ICXPort015]> { 1066 let Latency = 5; 1067 let NumMicroOps = 2; 1068 let ResourceCycles = [1,1]; 1069} 1070def: InstRW<[ICXWriteResGroup61], (instregex "MMX_CVT(T?)PD2PIrr", 1071 "MMX_CVT(T?)PS2PIrr", 1072 "VCVTDQ2PDZ128rr", 1073 "VCVTPD2DQZ128rr", 1074 "(V?)CVT(T?)PD2DQrr", 1075 "VCVTPD2PSZ128rr", 1076 "(V?)CVTPD2PSrr", 1077 "VCVTPD2UDQZ128rr", 1078 "VCVTPS2PDZ128rr", 1079 "(V?)CVTPS2PDrr", 1080 "VCVTPS2QQZ128rr", 1081 "VCVTPS2UQQZ128rr", 1082 "VCVTQQ2PSZ128rr", 1083 "(V?)CVTSD2SS(Z?)rr", 1084 "(V?)CVTSI(64)?2SDrr", 1085 "VCVTSI2SSZrr", 1086 "(V?)CVTSI2SSrr", 1087 "VCVTSI(64)?2SDZrr", 1088 "VCVTSS2SDZrr", 1089 "(V?)CVTSS2SDrr", 1090 "VCVTTPD2DQZ128rr", 1091 "VCVTTPD2UDQZ128rr", 1092 "VCVTTPS2QQZ128rr", 1093 "VCVTTPS2UQQZ128rr", 1094 "VCVTUDQ2PDZ128rr", 1095 "VCVTUQQ2PSZ128rr", 1096 "VCVTUSI2SSZrr", 1097 "VCVTUSI(64)?2SDZrr")>; 1098 1099def ICXWriteResGroup62 : SchedWriteRes<[ICXPort5,ICXPort015]> { 1100 let Latency = 5; 1101 let NumMicroOps = 3; 1102 let ResourceCycles = [2,1]; 1103} 1104def: InstRW<[ICXWriteResGroup62], (instregex "VPCONFLICTQZ128rr")>; 1105 1106def ICXWriteResGroup63 : SchedWriteRes<[ICXPort1,ICXPort6,ICXPort06]> { 1107 let Latency = 5; 1108 let NumMicroOps = 3; 1109 let ResourceCycles = [1,1,1]; 1110} 1111def: InstRW<[ICXWriteResGroup63], (instregex "STR(16|32|64)r")>; 1112 1113def ICXWriteResGroup65 : SchedWriteRes<[ICXPort4,ICXPort237,ICXPort015]> { 1114 let Latency = 5; 1115 let NumMicroOps = 3; 1116 let ResourceCycles = [1,1,1]; 1117} 1118def: InstRW<[ICXWriteResGroup65], (instregex "VCVTPS2PHZ128mr(b?)", 1119 "VCVTPS2PHZ256mr(b?)", 1120 "VCVTPS2PHZmr(b?)")>; 1121 1122def ICXWriteResGroup66 : SchedWriteRes<[ICXPort4,ICXPort5,ICXPort237]> { 1123 let Latency = 5; 1124 let NumMicroOps = 4; 1125 let ResourceCycles = [1,2,1]; 1126} 1127def: InstRW<[ICXWriteResGroup66], (instregex "VPMOVDB(Z|Z128|Z256)mr(b?)", 1128 "VPMOVDW(Z|Z128|Z256)mr(b?)", 1129 "VPMOVQB(Z|Z128|Z256)mr(b?)", 1130 "VPMOVQW(Z|Z128|Z256)mr(b?)", 1131 "VPMOVSDB(Z|Z128|Z256)mr(b?)", 1132 "VPMOVSDW(Z|Z128|Z256)mr(b?)", 1133 "VPMOVSQB(Z|Z128|Z256)mr(b?)", 1134 "VPMOVSQD(Z|Z128|Z256)mr(b?)", 1135 "VPMOVSQW(Z|Z128|Z256)mr(b?)", 1136 "VPMOVSWB(Z|Z128|Z256)mr(b?)", 1137 "VPMOVUSDB(Z|Z128|Z256)mr(b?)", 1138 "VPMOVUSDW(Z|Z128|Z256)mr(b?)", 1139 "VPMOVUSQB(Z|Z128|Z256)mr(b?)", 1140 "VPMOVUSQD(Z|Z128|Z256)mr(b?)", 1141 "VPMOVUSQW(Z|Z128|Z256)mr(b?)", 1142 "VPMOVUSWB(Z|Z128|Z256)mr(b?)", 1143 "VPMOVWB(Z|Z128|Z256)mr(b?)")>; 1144 1145def ICXWriteResGroup67 : SchedWriteRes<[ICXPort06,ICXPort0156]> { 1146 let Latency = 5; 1147 let NumMicroOps = 5; 1148 let ResourceCycles = [1,4]; 1149} 1150def: InstRW<[ICXWriteResGroup67], (instrs XSETBV)>; 1151 1152def ICXWriteResGroup69 : SchedWriteRes<[ICXPort4,ICXPort237,ICXPort0156]> { 1153 let Latency = 5; 1154 let NumMicroOps = 6; 1155 let ResourceCycles = [1,1,4]; 1156} 1157def: InstRW<[ICXWriteResGroup69], (instregex "PUSHF(16|64)")>; 1158 1159def ICXWriteResGroup71 : SchedWriteRes<[ICXPort23]> { 1160 let Latency = 6; 1161 let NumMicroOps = 1; 1162 let ResourceCycles = [1]; 1163} 1164def: InstRW<[ICXWriteResGroup71], (instrs VBROADCASTSSrm, 1165 VPBROADCASTDrm, 1166 VPBROADCASTQrm, 1167 VMOVSHDUPrm, 1168 VMOVSLDUPrm, 1169 MOVSHDUPrm, 1170 MOVSLDUPrm)>; 1171 1172def ICXWriteResGroup72 : SchedWriteRes<[ICXPort5]> { 1173 let Latency = 6; 1174 let NumMicroOps = 2; 1175 let ResourceCycles = [2]; 1176} 1177def: InstRW<[ICXWriteResGroup72], (instrs MMX_CVTPI2PSrr)>; 1178def: InstRW<[ICXWriteResGroup72], (instregex "VCOMPRESSPD(Z|Z128|Z256)rr", 1179 "VCOMPRESSPS(Z|Z128|Z256)rr", 1180 "VPCOMPRESSD(Z|Z128|Z256)rr", 1181 "VPCOMPRESSQ(Z|Z128|Z256)rr", 1182 "VPERMW(Z|Z128|Z256)rr")>; 1183 1184def ICXWriteResGroup73 : SchedWriteRes<[ICXPort0,ICXPort23]> { 1185 let Latency = 6; 1186 let NumMicroOps = 2; 1187 let ResourceCycles = [1,1]; 1188} 1189def: InstRW<[ICXWriteResGroup73], (instrs MMX_PADDSBrm, 1190 MMX_PADDSWrm, 1191 MMX_PADDUSBrm, 1192 MMX_PADDUSWrm, 1193 MMX_PAVGBrm, 1194 MMX_PAVGWrm, 1195 MMX_PCMPEQBrm, 1196 MMX_PCMPEQDrm, 1197 MMX_PCMPEQWrm, 1198 MMX_PCMPGTBrm, 1199 MMX_PCMPGTDrm, 1200 MMX_PCMPGTWrm, 1201 MMX_PMAXSWrm, 1202 MMX_PMAXUBrm, 1203 MMX_PMINSWrm, 1204 MMX_PMINUBrm, 1205 MMX_PSUBSBrm, 1206 MMX_PSUBSWrm, 1207 MMX_PSUBUSBrm, 1208 MMX_PSUBUSWrm)>; 1209 1210def ICXWriteResGroup76 : SchedWriteRes<[ICXPort6,ICXPort23]> { 1211 let Latency = 6; 1212 let NumMicroOps = 2; 1213 let ResourceCycles = [1,1]; 1214} 1215def: InstRW<[ICXWriteResGroup76], (instrs FARJMP64m)>; 1216def: InstRW<[ICXWriteResGroup76], (instregex "JMP(16|32|64)m")>; 1217 1218def ICXWriteResGroup79 : SchedWriteRes<[ICXPort23,ICXPort15]> { 1219 let Latency = 6; 1220 let NumMicroOps = 2; 1221 let ResourceCycles = [1,1]; 1222} 1223def: InstRW<[ICXWriteResGroup79], (instregex "ANDN(32|64)rm", 1224 "MOVBE(16|32|64)rm")>; 1225 1226def ICXWriteResGroup80 : SchedWriteRes<[ICXPort23,ICXPort015]> { 1227 let Latency = 6; 1228 let NumMicroOps = 2; 1229 let ResourceCycles = [1,1]; 1230} 1231def: InstRW<[ICXWriteResGroup80], (instregex "VMOV(64to|QI2)PQIZrm(b?)")>; 1232def: InstRW<[ICXWriteResGroup80], (instrs VMOVDI2PDIZrm)>; 1233 1234def ICXWriteResGroup81 : SchedWriteRes<[ICXPort23,ICXPort0156]> { 1235 let Latency = 6; 1236 let NumMicroOps = 2; 1237 let ResourceCycles = [1,1]; 1238} 1239def: InstRW<[ICXWriteResGroup81], (instrs POP16r, POP32r, POP64r)>; 1240def: InstRW<[ICXWriteResGroup81], (instregex "POP(16|32|64)rmr")>; 1241 1242def ICXWriteResGroup82 : SchedWriteRes<[ICXPort5,ICXPort015]> { 1243 let Latency = 6; 1244 let NumMicroOps = 3; 1245 let ResourceCycles = [2,1]; 1246} 1247def: InstRW<[ICXWriteResGroup82], (instregex "(V?)CVTSI642SSrr", 1248 "VCVTSI642SSZrr", 1249 "VCVTUSI642SSZrr")>; 1250 1251def ICXWriteResGroup84 : SchedWriteRes<[ICXPort1,ICXPort6,ICXPort06,ICXPort0156]> { 1252 let Latency = 6; 1253 let NumMicroOps = 4; 1254 let ResourceCycles = [1,1,1,1]; 1255} 1256def: InstRW<[ICXWriteResGroup84], (instregex "SLDT(16|32|64)r")>; 1257 1258def ICXWriteResGroup86 : SchedWriteRes<[ICXPort4,ICXPort23,ICXPort237,ICXPort06]> { 1259 let Latency = 6; 1260 let NumMicroOps = 4; 1261 let ResourceCycles = [1,1,1,1]; 1262} 1263def: InstRW<[ICXWriteResGroup86], (instregex "SAR(8|16|32|64)m(1|i)", 1264 "SHL(8|16|32|64)m(1|i)", 1265 "SHR(8|16|32|64)m(1|i)")>; 1266 1267def ICXWriteResGroup87 : SchedWriteRes<[ICXPort4,ICXPort23,ICXPort237,ICXPort0156]> { 1268 let Latency = 6; 1269 let NumMicroOps = 4; 1270 let ResourceCycles = [1,1,1,1]; 1271} 1272def: InstRW<[ICXWriteResGroup87], (instregex "POP(16|32|64)rmm", 1273 "PUSH(16|32|64)rmm")>; 1274 1275def ICXWriteResGroup88 : SchedWriteRes<[ICXPort6,ICXPort0156]> { 1276 let Latency = 6; 1277 let NumMicroOps = 6; 1278 let ResourceCycles = [1,5]; 1279} 1280def: InstRW<[ICXWriteResGroup88], (instrs STD)>; 1281 1282def ICXWriteResGroup89 : SchedWriteRes<[ICXPort23]> { 1283 let Latency = 7; 1284 let NumMicroOps = 1; 1285 let ResourceCycles = [1]; 1286} 1287def: InstRW<[ICXWriteResGroup89], (instregex "LD_F(32|64|80)m")>; 1288def: InstRW<[ICXWriteResGroup89], (instrs VBROADCASTF128, 1289 VBROADCASTI128, 1290 VBROADCASTSDYrm, 1291 VBROADCASTSSYrm, 1292 VMOVDDUPYrm, 1293 VMOVSHDUPYrm, 1294 VMOVSLDUPYrm, 1295 VPBROADCASTDYrm, 1296 VPBROADCASTQYrm)>; 1297 1298def ICXWriteResGroup90 : SchedWriteRes<[ICXPort01,ICXPort5]> { 1299 let Latency = 7; 1300 let NumMicroOps = 2; 1301 let ResourceCycles = [1,1]; 1302} 1303def: InstRW<[ICXWriteResGroup90], (instrs VCVTDQ2PDYrr)>; 1304 1305def ICXWriteResGroup92 : SchedWriteRes<[ICXPort5,ICXPort23]> { 1306 let Latency = 7; 1307 let NumMicroOps = 2; 1308 let ResourceCycles = [1,1]; 1309} 1310def: InstRW<[ICXWriteResGroup92], (instregex "VMOV(SD|SS)Zrm(b?)", 1311 "VPBROADCAST(B|W)(Z128)?rm", 1312 "(V?)INSERTPS(Z?)rm", 1313 "(V?)PALIGNR(Z128)?rmi", 1314 "(V?)PERMIL(PD|PS)(Z128)?m(b?)i", 1315 "(V?)PERMIL(PD|PS)(Z128)?rm", 1316 "(V?)PACK(U|S)S(DW|WB)(Z128)?rm", 1317 "(V?)UNPCK(L|H)(PD|PS)(Z128)?rm")>; 1318 1319def ICXWriteResGroup93 : SchedWriteRes<[ICXPort5,ICXPort015]> { 1320 let Latency = 7; 1321 let NumMicroOps = 2; 1322 let ResourceCycles = [1,1]; 1323} 1324def: InstRW<[ICXWriteResGroup93], (instregex "VCVTDQ2PDZ256rr", 1325 "VCVTPD2DQ(Y|Z256)rr", 1326 "VCVTPD2PS(Y|Z256)rr", 1327 "VCVTPD2UDQZ256rr", 1328 "VCVTPS2PD(Y|Z256)rr", 1329 "VCVTPS2QQZ256rr", 1330 "VCVTPS2UQQZ256rr", 1331 "VCVTQQ2PSZ256rr", 1332 "VCVTTPD2DQ(Y|Z256)rr", 1333 "VCVTTPD2UDQZ256rr", 1334 "VCVTTPS2QQZ256rr", 1335 "VCVTTPS2UQQZ256rr", 1336 "VCVTUDQ2PDZ256rr", 1337 "VCVTUQQ2PSZ256rr")>; 1338 1339def ICXWriteResGroup93z : SchedWriteRes<[ICXPort5,ICXPort05]> { 1340 let Latency = 7; 1341 let NumMicroOps = 2; 1342 let ResourceCycles = [1,1]; 1343} 1344def: InstRW<[ICXWriteResGroup93z], (instrs VCVTDQ2PDZrr, 1345 VCVTPD2DQZrr, 1346 VCVTPD2PSZrr, 1347 VCVTPD2UDQZrr, 1348 VCVTPS2PDZrr, 1349 VCVTPS2QQZrr, 1350 VCVTPS2UQQZrr, 1351 VCVTQQ2PSZrr, 1352 VCVTTPD2DQZrr, 1353 VCVTTPD2UDQZrr, 1354 VCVTTPS2QQZrr, 1355 VCVTTPS2UQQZrr, 1356 VCVTUDQ2PDZrr, 1357 VCVTUQQ2PSZrr)>; 1358 1359def ICXWriteResGroup95 : SchedWriteRes<[ICXPort23,ICXPort015]> { 1360 let Latency = 7; 1361 let NumMicroOps = 2; 1362 let ResourceCycles = [1,1]; 1363} 1364def: InstRW<[ICXWriteResGroup95], (instrs VMOVNTDQAZ128rm, 1365 VPBLENDDrmi)>; 1366def: InstRW<[ICXWriteResGroup95, ReadAfterVecXLd], 1367 (instregex "VBLENDMPDZ128rm(b?)", 1368 "VBLENDMPSZ128rm(b?)", 1369 "VBROADCASTI32X2Z128rm(b?)", 1370 "VBROADCASTSSZ128rm(b?)", 1371 "VINSERT(F|I)128rm", 1372 "VMOVAPDZ128rm(b?)", 1373 "VMOVAPSZ128rm(b?)", 1374 "VMOVDDUPZ128rm(b?)", 1375 "VMOVDQA32Z128rm(b?)", 1376 "VMOVDQA64Z128rm(b?)", 1377 "VMOVDQU16Z128rm(b?)", 1378 "VMOVDQU32Z128rm(b?)", 1379 "VMOVDQU64Z128rm(b?)", 1380 "VMOVDQU8Z128rm(b?)", 1381 "VMOVSHDUPZ128rm(b?)", 1382 "VMOVSLDUPZ128rm(b?)", 1383 "VMOVUPDZ128rm(b?)", 1384 "VMOVUPSZ128rm(b?)", 1385 "VPADD(B|D|Q|W)Z128rm(b?)", 1386 "(V?)PADD(B|D|Q|W)rm", 1387 "VPBLENDM(B|D|Q|W)Z128rm(b?)", 1388 "VPBROADCASTDZ128rm(b?)", 1389 "VPBROADCASTQZ128rm(b?)", 1390 "VPSUB(B|D|Q|W)Z128rm(b?)", 1391 "(V?)PSUB(B|D|Q|W)rm", 1392 "VPTERNLOGDZ128rm(b?)i", 1393 "VPTERNLOGQZ128rm(b?)i")>; 1394 1395def ICXWriteResGroup96 : SchedWriteRes<[ICXPort5,ICXPort23]> { 1396 let Latency = 7; 1397 let NumMicroOps = 3; 1398 let ResourceCycles = [2,1]; 1399} 1400def: InstRW<[ICXWriteResGroup96], (instrs MMX_PACKSSDWrm, 1401 MMX_PACKSSWBrm, 1402 MMX_PACKUSWBrm)>; 1403 1404def ICXWriteResGroup97 : SchedWriteRes<[ICXPort5,ICXPort015]> { 1405 let Latency = 7; 1406 let NumMicroOps = 3; 1407 let ResourceCycles = [2,1]; 1408} 1409def: InstRW<[ICXWriteResGroup97], (instregex "VPERMI2W128rr", 1410 "VPERMI2W256rr", 1411 "VPERMI2Wrr", 1412 "VPERMT2W128rr", 1413 "VPERMT2W256rr", 1414 "VPERMT2Wrr")>; 1415 1416def ICXWriteResGroup99 : SchedWriteRes<[ICXPort23,ICXPort0156]> { 1417 let Latency = 7; 1418 let NumMicroOps = 3; 1419 let ResourceCycles = [1,2]; 1420} 1421def: InstRW<[ICXWriteResGroup99], (instrs LEAVE, LEAVE64, 1422 SCASB, SCASL, SCASQ, SCASW)>; 1423 1424def ICXWriteResGroup100 : SchedWriteRes<[ICXPort0,ICXPort5,ICXPort015]> { 1425 let Latency = 7; 1426 let NumMicroOps = 3; 1427 let ResourceCycles = [1,1,1]; 1428} 1429def: InstRW<[ICXWriteResGroup100], (instregex "VCVTSS2USI64Zrr", 1430 "(V?)CVTSS2SI64(Z?)rr", 1431 "(V?)CVTTSS2SI64(Z?)rr", 1432 "VCVTTSS2USI64Zrr")>; 1433 1434def ICXWriteResGroup101 : SchedWriteRes<[ICXPort0,ICXPort23,ICXPort05]> { 1435 let Latency = 7; 1436 let NumMicroOps = 3; 1437 let ResourceCycles = [1,1,1]; 1438} 1439def: InstRW<[ICXWriteResGroup101], (instrs FLDCW16m)>; 1440 1441def ICXWriteResGroup103 : SchedWriteRes<[ICXPort5,ICXPort23,ICXPort0156]> { 1442 let Latency = 7; 1443 let NumMicroOps = 3; 1444 let ResourceCycles = [1,1,1]; 1445} 1446def: InstRW<[ICXWriteResGroup103], (instregex "KMOV(B|D|Q|W)km")>; 1447 1448def ICXWriteResGroup104 : SchedWriteRes<[ICXPort6,ICXPort23,ICXPort0156]> { 1449 let Latency = 7; 1450 let NumMicroOps = 3; 1451 let ResourceCycles = [1,1,1]; 1452} 1453def: InstRW<[ICXWriteResGroup104], (instrs LRET64, RET64)>; 1454 1455def ICXWriteResGroup106 : SchedWriteRes<[ICXPort4,ICXPort5,ICXPort237]> { 1456 let Latency = 7; 1457 let NumMicroOps = 4; 1458 let ResourceCycles = [1,2,1]; 1459} 1460def: InstRW<[ICXWriteResGroup106], (instregex "VCOMPRESSPD(Z|Z128|Z256)mr(b?)", 1461 "VCOMPRESSPS(Z|Z128|Z256)mr(b?)", 1462 "VPCOMPRESSD(Z|Z128|Z256)mr(b?)", 1463 "VPCOMPRESSQ(Z|Z128|Z256)mr(b?)")>; 1464 1465def ICXWriteResGroup107 : SchedWriteRes<[ICXPort4,ICXPort23,ICXPort237,ICXPort06]> { 1466 let Latency = 7; 1467 let NumMicroOps = 5; 1468 let ResourceCycles = [1,1,1,2]; 1469} 1470def: InstRW<[ICXWriteResGroup107], (instregex "ROL(8|16|32|64)m(1|i)", 1471 "ROR(8|16|32|64)m(1|i)")>; 1472 1473def ICXWriteResGroup107_1 : SchedWriteRes<[ICXPort06]> { 1474 let Latency = 2; 1475 let NumMicroOps = 2; 1476 let ResourceCycles = [2]; 1477} 1478def: InstRW<[ICXWriteResGroup107_1], (instrs ROL8r1, ROL16r1, ROL32r1, ROL64r1, 1479 ROR8r1, ROR16r1, ROR32r1, ROR64r1)>; 1480 1481def ICXWriteResGroup108 : SchedWriteRes<[ICXPort4,ICXPort23,ICXPort237,ICXPort0156]> { 1482 let Latency = 7; 1483 let NumMicroOps = 5; 1484 let ResourceCycles = [1,1,1,2]; 1485} 1486def: InstRW<[ICXWriteResGroup108], (instregex "XADD(8|16|32|64)rm")>; 1487 1488def ICXWriteResGroup109 : SchedWriteRes<[ICXPort4,ICXPort6,ICXPort23,ICXPort237,ICXPort0156]> { 1489 let Latency = 7; 1490 let NumMicroOps = 5; 1491 let ResourceCycles = [1,1,1,1,1]; 1492} 1493def: InstRW<[ICXWriteResGroup109], (instregex "CALL(16|32|64)m")>; 1494def: InstRW<[ICXWriteResGroup109], (instrs FARCALL64m)>; 1495 1496def ICXWriteResGroup110 : SchedWriteRes<[ICXPort0,ICXPort4,ICXPort237,ICXPort0156]> { 1497 let Latency = 7; 1498 let NumMicroOps = 7; 1499 let ResourceCycles = [1,2,2,2]; 1500} 1501def: InstRW<[ICXWriteResGroup110], (instrs VPSCATTERDQZ128mr, 1502 VPSCATTERQQZ128mr, 1503 VSCATTERDPDZ128mr, 1504 VSCATTERQPDZ128mr)>; 1505 1506def ICXWriteResGroup111 : SchedWriteRes<[ICXPort6,ICXPort06,ICXPort15,ICXPort0156]> { 1507 let Latency = 7; 1508 let NumMicroOps = 7; 1509 let ResourceCycles = [1,3,1,2]; 1510} 1511def: InstRW<[ICXWriteResGroup111], (instrs LOOP)>; 1512 1513def ICXWriteResGroup112 : SchedWriteRes<[ICXPort0,ICXPort4,ICXPort237,ICXPort0156]> { 1514 let Latency = 7; 1515 let NumMicroOps = 11; 1516 let ResourceCycles = [1,4,4,2]; 1517} 1518def: InstRW<[ICXWriteResGroup112], (instrs VPSCATTERDQZ256mr, 1519 VPSCATTERQQZ256mr, 1520 VSCATTERDPDZ256mr, 1521 VSCATTERQPDZ256mr)>; 1522 1523def ICXWriteResGroup113 : SchedWriteRes<[ICXPort0,ICXPort4,ICXPort237,ICXPort0156]> { 1524 let Latency = 7; 1525 let NumMicroOps = 19; 1526 let ResourceCycles = [1,8,8,2]; 1527} 1528def: InstRW<[ICXWriteResGroup113], (instrs VPSCATTERDQZmr, 1529 VPSCATTERQQZmr, 1530 VSCATTERDPDZmr, 1531 VSCATTERQPDZmr)>; 1532 1533def ICXWriteResGroup114 : SchedWriteRes<[ICXPort0,ICXPort4,ICXPort5,ICXPort237,ICXPort0156]> { 1534 let Latency = 7; 1535 let NumMicroOps = 36; 1536 let ResourceCycles = [1,16,1,16,2]; 1537} 1538def: InstRW<[ICXWriteResGroup114], (instrs VSCATTERDPSZmr)>; 1539 1540def ICXWriteResGroup118 : SchedWriteRes<[ICXPort1,ICXPort23]> { 1541 let Latency = 8; 1542 let NumMicroOps = 2; 1543 let ResourceCycles = [1,1]; 1544} 1545def: InstRW<[ICXWriteResGroup118], (instregex "PDEP(32|64)rm", 1546 "PEXT(32|64)rm")>; 1547 1548def ICXWriteResGroup119 : SchedWriteRes<[ICXPort5,ICXPort23]> { 1549 let Latency = 8; 1550 let NumMicroOps = 2; 1551 let ResourceCycles = [1,1]; 1552} 1553def: InstRW<[ICXWriteResGroup119], (instregex "FCOM(P?)(32|64)m", 1554 "VPBROADCASTB(Z|Z256)rm(b?)", 1555 "VPBROADCASTW(Z|Z256)rm(b?)", 1556 "(V?)PALIGNR(Y|Z|Z256)rmi", 1557 "(V?)PERMIL(PD|PS)(Y|Z|Z256)m(b?)i", 1558 "(V?)PERMIL(PD|PS)(Y|Z|Z256)rm", 1559 "(V?)PACK(U|S)S(DW|WB)(Y|Z|Z256)rm", 1560 "(V?)UNPCK(L|H)(PD|PS)(Y|Z|Z256)rm")>; 1561def: InstRW<[ICXWriteResGroup119], (instrs VPBROADCASTBYrm, 1562 VPBROADCASTWYrm, 1563 VPMOVSXBDYrm, 1564 VPMOVSXBQYrm, 1565 VPMOVSXWQYrm)>; 1566 1567def ICXWriteResGroup121 : SchedWriteRes<[ICXPort23,ICXPort015]> { 1568 let Latency = 8; 1569 let NumMicroOps = 2; 1570 let ResourceCycles = [1,1]; 1571} 1572def: InstRW<[ICXWriteResGroup121], (instrs VMOVNTDQAZ256rm, 1573 VPBLENDDYrmi)>; 1574def: InstRW<[ICXWriteResGroup121, ReadAfterVecYLd], 1575 (instregex "VBLENDMPD(Z|Z256)rm(b?)", 1576 "VBLENDMPS(Z|Z256)rm(b?)", 1577 "VBROADCASTF32X2Z256rm(b?)", 1578 "VBROADCASTF32X2Zrm(b?)", 1579 "VBROADCASTF32X4Z256rm(b?)", 1580 "VBROADCASTF32X4rm(b?)", 1581 "VBROADCASTF32X8rm(b?)", 1582 "VBROADCASTF64X2Z128rm(b?)", 1583 "VBROADCASTF64X2rm(b?)", 1584 "VBROADCASTF64X4rm(b?)", 1585 "VBROADCASTI32X2Z256rm(b?)", 1586 "VBROADCASTI32X2Zrm(b?)", 1587 "VBROADCASTI32X4Z256rm(b?)", 1588 "VBROADCASTI32X4rm(b?)", 1589 "VBROADCASTI32X8rm(b?)", 1590 "VBROADCASTI64X2Z128rm(b?)", 1591 "VBROADCASTI64X2rm(b?)", 1592 "VBROADCASTI64X4rm(b?)", 1593 "VBROADCASTSD(Z|Z256)rm(b?)", 1594 "VBROADCASTSS(Z|Z256)rm(b?)", 1595 "VINSERTF32x4(Z|Z256)rm(b?)", 1596 "VINSERTF32x8Zrm(b?)", 1597 "VINSERTF64x2(Z|Z256)rm(b?)", 1598 "VINSERTF64x4Zrm(b?)", 1599 "VINSERTI32x4(Z|Z256)rm(b?)", 1600 "VINSERTI32x8Zrm(b?)", 1601 "VINSERTI64x2(Z|Z256)rm(b?)", 1602 "VINSERTI64x4Zrm(b?)", 1603 "VMOVAPD(Z|Z256)rm(b?)", 1604 "VMOVAPS(Z|Z256)rm(b?)", 1605 "VMOVDDUP(Z|Z256)rm(b?)", 1606 "VMOVDQA32(Z|Z256)rm(b?)", 1607 "VMOVDQA64(Z|Z256)rm(b?)", 1608 "VMOVDQU16(Z|Z256)rm(b?)", 1609 "VMOVDQU32(Z|Z256)rm(b?)", 1610 "VMOVDQU64(Z|Z256)rm(b?)", 1611 "VMOVDQU8(Z|Z256)rm(b?)", 1612 "VMOVSHDUP(Z|Z256)rm(b?)", 1613 "VMOVSLDUP(Z|Z256)rm(b?)", 1614 "VMOVUPD(Z|Z256)rm(b?)", 1615 "VMOVUPS(Z|Z256)rm(b?)", 1616 "VPADD(B|D|Q|W)Yrm", 1617 "VPADD(B|D|Q|W)(Z|Z256)rm(b?)", 1618 "VPBLENDM(B|D|Q|W)(Z|Z256)rm(b?)", 1619 "VPBROADCASTD(Z|Z256)rm(b?)", 1620 "VPBROADCASTQ(Z|Z256)rm(b?)", 1621 "VPSUB(B|D|Q|W)Yrm", 1622 "VPSUB(B|D|Q|W)(Z|Z256)rm(b?)", 1623 "VPTERNLOGD(Z|Z256)rm(b?)i", 1624 "VPTERNLOGQ(Z|Z256)rm(b?)i")>; 1625 1626def ICXWriteResGroup123 : SchedWriteRes<[ICXPort0,ICXPort5,ICXPort23]> { 1627 let Latency = 8; 1628 let NumMicroOps = 4; 1629 let ResourceCycles = [1,2,1]; 1630} 1631def: InstRW<[ICXWriteResGroup123], (instregex "MMX_PH(ADD|SUB)SWrm")>; 1632 1633def ICXWriteResGroup127 : SchedWriteRes<[ICXPort23,ICXPort237,ICXPort06,ICXPort0156]> { 1634 let Latency = 8; 1635 let NumMicroOps = 5; 1636 let ResourceCycles = [1,1,1,2]; 1637} 1638def: InstRW<[ICXWriteResGroup127], (instregex "RCL(8|16|32|64)m(1|i)", 1639 "RCR(8|16|32|64)m(1|i)")>; 1640 1641def ICXWriteResGroup128 : SchedWriteRes<[ICXPort4,ICXPort23,ICXPort237,ICXPort06]> { 1642 let Latency = 8; 1643 let NumMicroOps = 6; 1644 let ResourceCycles = [1,1,1,3]; 1645} 1646def: InstRW<[ICXWriteResGroup128], (instregex "ROL(8|16|32|64)mCL", 1647 "ROR(8|16|32|64)mCL", 1648 "SAR(8|16|32|64)mCL", 1649 "SHL(8|16|32|64)mCL", 1650 "SHR(8|16|32|64)mCL")>; 1651 1652def ICXWriteResGroup130 : SchedWriteRes<[ICXPort4,ICXPort23,ICXPort237,ICXPort06,ICXPort0156]> { 1653 let Latency = 8; 1654 let NumMicroOps = 6; 1655 let ResourceCycles = [1,1,1,2,1]; 1656} 1657def: SchedAlias<WriteADCRMW, ICXWriteResGroup130>; 1658 1659def ICXWriteResGroup131 : SchedWriteRes<[ICXPort0,ICXPort4,ICXPort5,ICXPort237,ICXPort0156]> { 1660 let Latency = 8; 1661 let NumMicroOps = 8; 1662 let ResourceCycles = [1,2,1,2,2]; 1663} 1664def: InstRW<[ICXWriteResGroup131], (instrs VPSCATTERQDZ128mr, 1665 VPSCATTERQDZ256mr, 1666 VSCATTERQPSZ128mr, 1667 VSCATTERQPSZ256mr)>; 1668 1669def ICXWriteResGroup132 : SchedWriteRes<[ICXPort0,ICXPort4,ICXPort5,ICXPort237,ICXPort0156]> { 1670 let Latency = 8; 1671 let NumMicroOps = 12; 1672 let ResourceCycles = [1,4,1,4,2]; 1673} 1674def: InstRW<[ICXWriteResGroup132], (instrs VPSCATTERDDZ128mr, 1675 VSCATTERDPSZ128mr)>; 1676 1677def ICXWriteResGroup133 : SchedWriteRes<[ICXPort0,ICXPort4,ICXPort5,ICXPort237,ICXPort0156]> { 1678 let Latency = 8; 1679 let NumMicroOps = 20; 1680 let ResourceCycles = [1,8,1,8,2]; 1681} 1682def: InstRW<[ICXWriteResGroup133], (instrs VPSCATTERDDZ256mr, 1683 VSCATTERDPSZ256mr)>; 1684 1685def ICXWriteResGroup134 : SchedWriteRes<[ICXPort0,ICXPort4,ICXPort5,ICXPort237,ICXPort0156]> { 1686 let Latency = 8; 1687 let NumMicroOps = 36; 1688 let ResourceCycles = [1,16,1,16,2]; 1689} 1690def: InstRW<[ICXWriteResGroup134], (instrs VPSCATTERDDZmr)>; 1691 1692def ICXWriteResGroup135 : SchedWriteRes<[ICXPort0,ICXPort23]> { 1693 let Latency = 9; 1694 let NumMicroOps = 2; 1695 let ResourceCycles = [1,1]; 1696} 1697def: InstRW<[ICXWriteResGroup135], (instrs MMX_CVTPI2PSrm)>; 1698 1699def ICXWriteResGroup136 : SchedWriteRes<[ICXPort5,ICXPort23]> { 1700 let Latency = 9; 1701 let NumMicroOps = 2; 1702 let ResourceCycles = [1,1]; 1703} 1704def: InstRW<[ICXWriteResGroup136], (instrs VPMOVSXBWYrm, 1705 VPMOVSXDQYrm, 1706 VPMOVSXWDYrm, 1707 VPMOVZXWDYrm)>; 1708def: InstRW<[ICXWriteResGroup136], (instregex "VALIGN(D|Q)Z128rm(b?)i", 1709 "VFPCLASSSDZrm(b?)", 1710 "VFPCLASSSSZrm(b?)", 1711 "(V?)PCMPGTQrm", 1712 "VPERMI2D128rm(b?)", 1713 "VPERMI2PD128rm(b?)", 1714 "VPERMI2PS128rm(b?)", 1715 "VPERMI2Q128rm(b?)", 1716 "VPERMT2D128rm(b?)", 1717 "VPERMT2PD128rm(b?)", 1718 "VPERMT2PS128rm(b?)", 1719 "VPERMT2Q128rm(b?)", 1720 "VPMAXSQZ128rm(b?)", 1721 "VPMAXUQZ128rm(b?)", 1722 "VPMINSQZ128rm(b?)", 1723 "VPMINUQZ128rm(b?)")>; 1724 1725def ICXWriteResGroup136_2 : SchedWriteRes<[ICXPort5,ICXPort23]> { 1726 let Latency = 10; 1727 let NumMicroOps = 2; 1728 let ResourceCycles = [1,1]; 1729} 1730def: InstRW<[ICXWriteResGroup136_2], (instregex "VCMP(PD|PS)Z128rm(b?)i", 1731 "VCMP(SD|SS)Zrm", 1732 "VFPCLASSPDZ128rm(b?)", 1733 "VFPCLASSPSZ128rm(b?)", 1734 "VPCMPBZ128rmi(b?)", 1735 "VPCMPDZ128rmi(b?)", 1736 "VPCMPEQ(B|D|Q|W)Z128rm(b?)", 1737 "VPCMPGT(B|D|Q|W)Z128rm(b?)", 1738 "VPCMPQZ128rmi(b?)", 1739 "VPCMPU(B|D|Q|W)Z128rmi(b?)", 1740 "VPCMPWZ128rmi(b?)", 1741 "VPTESTMBZ128rm(b?)", 1742 "VPTESTMDZ128rm(b?)", 1743 "VPTESTMQZ128rm(b?)", 1744 "VPTESTMWZ128rm(b?)", 1745 "VPTESTNMBZ128rm(b?)", 1746 "VPTESTNMDZ128rm(b?)", 1747 "VPTESTNMQZ128rm(b?)", 1748 "VPTESTNMWZ128rm(b?)")>; 1749 1750def ICXWriteResGroup137 : SchedWriteRes<[ICXPort23,ICXPort015]> { 1751 let Latency = 9; 1752 let NumMicroOps = 2; 1753 let ResourceCycles = [1,1]; 1754} 1755def: InstRW<[ICXWriteResGroup137], (instregex "MMX_CVT(T?)PS2PIrm", 1756 "(V?)CVTPS2PDrm")>; 1757 1758def ICXWriteResGroup143 : SchedWriteRes<[ICXPort5,ICXPort01,ICXPort23]> { 1759 let Latency = 9; 1760 let NumMicroOps = 4; 1761 let ResourceCycles = [2,1,1]; 1762} 1763def: InstRW<[ICXWriteResGroup143], (instregex "(V?)PHADDSWrm", 1764 "(V?)PHSUBSWrm")>; 1765 1766def ICXWriteResGroup146 : SchedWriteRes<[ICXPort1,ICXPort6,ICXPort23,ICXPort0156]> { 1767 let Latency = 9; 1768 let NumMicroOps = 5; 1769 let ResourceCycles = [1,2,1,1]; 1770} 1771def: InstRW<[ICXWriteResGroup146], (instregex "LAR(16|32|64)rm", 1772 "LSL(16|32|64)rm")>; 1773 1774def ICXWriteResGroup148 : SchedWriteRes<[ICXPort5,ICXPort23]> { 1775 let Latency = 10; 1776 let NumMicroOps = 2; 1777 let ResourceCycles = [1,1]; 1778} 1779def: InstRW<[ICXWriteResGroup148], (instrs VPCMPGTQYrm)>; 1780def: InstRW<[ICXWriteResGroup148], (instregex "(ADD|SUB|SUBR)_F(32|64)m", 1781 "ILD_F(16|32|64)m", 1782 "VALIGND(Z|Z256)rm(b?)i", 1783 "VALIGNQ(Z|Z256)rm(b?)i", 1784 "VPMAXSQ(Z|Z256)rm(b?)", 1785 "VPMAXUQ(Z|Z256)rm(b?)", 1786 "VPMINSQ(Z|Z256)rm(b?)", 1787 "VPMINUQ(Z|Z256)rm(b?)")>; 1788 1789def ICXWriteResGroup148_2 : SchedWriteRes<[ICXPort5,ICXPort23]> { 1790 let Latency = 11; 1791 let NumMicroOps = 2; 1792 let ResourceCycles = [1,1]; 1793} 1794def: InstRW<[ICXWriteResGroup148_2], (instregex "VCMPPD(Z|Z256)rm(b?)i", 1795 "VCMPPS(Z|Z256)rm(b?)i", 1796 "VFPCLASSPD(Z|Z256)rm(b?)", 1797 "VFPCLASSPS(Z|Z256)rm(b?)", 1798 "VPCMPB(Z|Z256)rmi(b?)", 1799 "VPCMPD(Z|Z256)rmi(b?)", 1800 "VPCMPEQB(Z|Z256)rm(b?)", 1801 "VPCMPEQD(Z|Z256)rm(b?)", 1802 "VPCMPEQQ(Z|Z256)rm(b?)", 1803 "VPCMPEQW(Z|Z256)rm(b?)", 1804 "VPCMPGTB(Z|Z256)rm(b?)", 1805 "VPCMPGTD(Z|Z256)rm(b?)", 1806 "VPCMPGTQ(Z|Z256)rm(b?)", 1807 "VPCMPGTW(Z|Z256)rm(b?)", 1808 "VPCMPQ(Z|Z256)rmi(b?)", 1809 "VPCMPU(B|D|Q|W)Z256rmi(b?)", 1810 "VPCMPU(B|D|Q|W)Zrmi(b?)", 1811 "VPCMPW(Z|Z256)rmi(b?)", 1812 "VPTESTM(B|D|Q|W)Z256rm(b?)", 1813 "VPTESTM(B|D|Q|W)Zrm(b?)", 1814 "VPTESTNM(B|D|Q|W)Z256rm(b?)", 1815 "VPTESTNM(B|D|Q|W)Zrm(b?)")>; 1816 1817def ICXWriteResGroup149 : SchedWriteRes<[ICXPort23,ICXPort015]> { 1818 let Latency = 10; 1819 let NumMicroOps = 2; 1820 let ResourceCycles = [1,1]; 1821} 1822def: InstRW<[ICXWriteResGroup149], (instregex "VCVTDQ2PDZ128rm(b?)", 1823 "VCVTDQ2PSZ128rm(b?)", 1824 "(V?)CVTDQ2PSrm", 1825 "VCVTPD2QQZ128rm(b?)", 1826 "VCVTPD2UQQZ128rm(b?)", 1827 "VCVTPH2PSZ128rm(b?)", 1828 "VCVTPS2DQZ128rm(b?)", 1829 "(V?)CVTPS2DQrm", 1830 "VCVTPS2PDZ128rm(b?)", 1831 "VCVTPS2QQZ128rm(b?)", 1832 "VCVTPS2UDQZ128rm(b?)", 1833 "VCVTPS2UQQZ128rm(b?)", 1834 "VCVTQQ2PDZ128rm(b?)", 1835 "VCVTQQ2PSZ128rm(b?)", 1836 "VCVTSS2SDZrm", 1837 "(V?)CVTSS2SDrm", 1838 "VCVTTPD2QQZ128rm(b?)", 1839 "VCVTTPD2UQQZ128rm(b?)", 1840 "VCVTTPS2DQZ128rm(b?)", 1841 "(V?)CVTTPS2DQrm", 1842 "VCVTTPS2QQZ128rm(b?)", 1843 "VCVTTPS2UDQZ128rm(b?)", 1844 "VCVTTPS2UQQZ128rm(b?)", 1845 "VCVTUDQ2PDZ128rm(b?)", 1846 "VCVTUDQ2PSZ128rm(b?)", 1847 "VCVTUQQ2PDZ128rm(b?)", 1848 "VCVTUQQ2PSZ128rm(b?)")>; 1849 1850def ICXWriteResGroup151 : SchedWriteRes<[ICXPort5,ICXPort23]> { 1851 let Latency = 10; 1852 let NumMicroOps = 3; 1853 let ResourceCycles = [2,1]; 1854} 1855def: InstRW<[ICXWriteResGroup151], (instregex "VEXPANDPDZ128rm(b?)", 1856 "VEXPANDPSZ128rm(b?)", 1857 "VPEXPANDDZ128rm(b?)", 1858 "VPEXPANDQZ128rm(b?)")>; 1859 1860def ICXWriteResGroup153 : SchedWriteRes<[ICXPort5,ICXPort23,ICXPort015]> { 1861 let Latency = 10; 1862 let NumMicroOps = 3; 1863 let ResourceCycles = [1,1,1]; 1864} 1865def: InstRW<[ICXWriteResGroup153], (instregex "(V?)CVTSD2SSrm")>; 1866 1867def ICXWriteResGroup154 : SchedWriteRes<[ICXPort5,ICXPort01,ICXPort23]> { 1868 let Latency = 10; 1869 let NumMicroOps = 4; 1870 let ResourceCycles = [2,1,1]; 1871} 1872def: InstRW<[ICXWriteResGroup154], (instrs VPHADDSWYrm, 1873 VPHSUBSWYrm)>; 1874 1875def ICXWriteResGroup157 : SchedWriteRes<[ICXPort4,ICXPort6,ICXPort23,ICXPort237,ICXPort06,ICXPort0156]> { 1876 let Latency = 10; 1877 let NumMicroOps = 8; 1878 let ResourceCycles = [1,1,1,1,1,3]; 1879} 1880def: InstRW<[ICXWriteResGroup157], (instregex "XCHG(8|16|32|64)rm")>; 1881 1882def ICXWriteResGroup159 : SchedWriteRes<[ICXPort0,ICXFPDivider]> { 1883 let Latency = 11; 1884 let NumMicroOps = 1; 1885 let ResourceCycles = [1,3]; 1886} 1887def : SchedAlias<WriteFDivX, ICXWriteResGroup159>; // TODO - convert to ZnWriteResFpuPair 1888 1889def ICXWriteResGroup160 : SchedWriteRes<[ICXPort0,ICXPort23]> { 1890 let Latency = 11; 1891 let NumMicroOps = 2; 1892 let ResourceCycles = [1,1]; 1893} 1894def: InstRW<[ICXWriteResGroup160], (instregex "MUL_F(32|64)m")>; 1895 1896def ICXWriteResGroup161 : SchedWriteRes<[ICXPort23,ICXPort015]> { 1897 let Latency = 11; 1898 let NumMicroOps = 2; 1899 let ResourceCycles = [1,1]; 1900} 1901def: InstRW<[ICXWriteResGroup161], (instrs VCVTDQ2PSYrm, 1902 VCVTPS2PDYrm)>; 1903def: InstRW<[ICXWriteResGroup161], (instregex "VCVTDQ2(PD|PS)(Z|Z256)rm(b?)", 1904 "VCVTPH2PS(Z|Z256)rm(b?)", 1905 "VCVTPS2PD(Z|Z256)rm(b?)", 1906 "VCVTQQ2PD(Z|Z256)rm(b?)", 1907 "VCVTQQ2PSZ256rm(b?)", 1908 "VCVT(T?)PD2QQ(Z|Z256)rm(b?)", 1909 "VCVT(T?)PD2UQQ(Z|Z256)rm(b?)", 1910 "VCVT(T?)PS2DQYrm", 1911 "VCVT(T?)PS2DQ(Z|Z256)rm(b?)", 1912 "VCVT(T?)PS2QQZ256rm(b?)", 1913 "VCVT(T?)PS2UDQ(Z|Z256)rm(b?)", 1914 "VCVT(T?)PS2UQQZ256rm(b?)", 1915 "VCVTUDQ2(PD|PS)(Z|Z256)rm(b?)", 1916 "VCVTUQQ2PD(Z|Z256)rm(b?)", 1917 "VCVTUQQ2PSZ256rm(b?)")>; 1918 1919def ICXWriteResGroup162 : SchedWriteRes<[ICXPort5,ICXPort23]> { 1920 let Latency = 11; 1921 let NumMicroOps = 3; 1922 let ResourceCycles = [2,1]; 1923} 1924def: InstRW<[ICXWriteResGroup162], (instregex "FICOM(P?)(16|32)m", 1925 "VEXPANDPD(Z|Z256)rm(b?)", 1926 "VEXPANDPS(Z|Z256)rm(b?)", 1927 "VPEXPANDD(Z|Z256)rm(b?)", 1928 "VPEXPANDQ(Z|Z256)rm(b?)")>; 1929 1930def ICXWriteResGroup163 : SchedWriteRes<[ICXPort23,ICXPort015]> { 1931 let Latency = 11; 1932 let NumMicroOps = 3; 1933 let ResourceCycles = [1,2]; 1934} 1935def: InstRW<[ICXWriteResGroup163], (instregex "VCVTSD2SSZrm")>; 1936 1937def ICXWriteResGroup164 : SchedWriteRes<[ICXPort0,ICXPort5,ICXPort23]> { 1938 let Latency = 11; 1939 let NumMicroOps = 3; 1940 let ResourceCycles = [1,1,1]; 1941} 1942def: InstRW<[ICXWriteResGroup164], (instregex "(V?)CVTDQ2PDrm")>; 1943 1944def ICXWriteResGroup166 : SchedWriteRes<[ICXPort5,ICXPort23,ICXPort015]> { 1945 let Latency = 11; 1946 let NumMicroOps = 3; 1947 let ResourceCycles = [1,1,1]; 1948} 1949def: InstRW<[ICXWriteResGroup166], (instrs CVTPD2PSrm, 1950 CVTPD2DQrm, 1951 CVTTPD2DQrm, 1952 MMX_CVTPD2PIrm, 1953 MMX_CVTTPD2PIrm)>; 1954 1955def ICXWriteResGroup167 : SchedWriteRes<[ICXPort5,ICXPort23,ICXPort015]> { 1956 let Latency = 11; 1957 let NumMicroOps = 4; 1958 let ResourceCycles = [2,1,1]; 1959} 1960def: InstRW<[ICXWriteResGroup167], (instregex "VPCONFLICTQZ128rm(b?)")>; 1961 1962def ICXWriteResGroup169 : SchedWriteRes<[ICXPort1,ICXPort06,ICXPort0156]> { 1963 let Latency = 11; 1964 let NumMicroOps = 7; 1965 let ResourceCycles = [2,3,2]; 1966} 1967def: InstRW<[ICXWriteResGroup169], (instregex "RCL(16|32|64)rCL", 1968 "RCR(16|32|64)rCL")>; 1969 1970def ICXWriteResGroup170 : SchedWriteRes<[ICXPort1,ICXPort06,ICXPort15,ICXPort0156]> { 1971 let Latency = 11; 1972 let NumMicroOps = 9; 1973 let ResourceCycles = [1,5,1,2]; 1974} 1975def: InstRW<[ICXWriteResGroup170], (instrs RCL8rCL)>; 1976 1977def ICXWriteResGroup171 : SchedWriteRes<[ICXPort06,ICXPort0156]> { 1978 let Latency = 11; 1979 let NumMicroOps = 11; 1980 let ResourceCycles = [2,9]; 1981} 1982def: InstRW<[ICXWriteResGroup171], (instrs LOOPE, LOOPNE)>; 1983 1984def ICXWriteResGroup174 : SchedWriteRes<[ICXPort01]> { 1985 let Latency = 15; 1986 let NumMicroOps = 3; 1987 let ResourceCycles = [3]; 1988} 1989def: InstRW<[ICXWriteResGroup174], (instregex "VPMULLQ(Z128|Z256)rr")>; 1990 1991def ICXWriteResGroup174z : SchedWriteRes<[ICXPort05]> { 1992 let Latency = 15; 1993 let NumMicroOps = 3; 1994 let ResourceCycles = [3]; 1995} 1996def: InstRW<[ICXWriteResGroup174z], (instregex "VPMULLQZrr")>; 1997 1998def ICXWriteResGroup175 : SchedWriteRes<[ICXPort5,ICXPort23]> { 1999 let Latency = 12; 2000 let NumMicroOps = 3; 2001 let ResourceCycles = [2,1]; 2002} 2003def: InstRW<[ICXWriteResGroup175], (instregex "VPERMWZ128rm(b?)")>; 2004 2005def ICXWriteResGroup176 : SchedWriteRes<[ICXPort0,ICXPort23,ICXPort015]> { 2006 let Latency = 12; 2007 let NumMicroOps = 3; 2008 let ResourceCycles = [1,1,1]; 2009} 2010def: InstRW<[ICXWriteResGroup176], (instregex "VCVT(T?)SD2USIZrm(b?)", 2011 "VCVT(T?)SS2USI64Zrm(b?)")>; 2012 2013def ICXWriteResGroup177 : SchedWriteRes<[ICXPort5,ICXPort23,ICXPort015]> { 2014 let Latency = 12; 2015 let NumMicroOps = 3; 2016 let ResourceCycles = [1,1,1]; 2017} 2018def: InstRW<[ICXWriteResGroup177], (instregex "VCVT(T?)PS2QQZrm(b?)", 2019 "VCVT(T?)PS2UQQZrm(b?)")>; 2020 2021def ICXWriteResGroup179 : SchedWriteRes<[ICXPort0,ICXPort5,ICXPort23,ICXPort015]> { 2022 let Latency = 12; 2023 let NumMicroOps = 4; 2024 let ResourceCycles = [1,1,1,1]; 2025} 2026def: InstRW<[ICXWriteResGroup179], (instregex "CVTTSS2SI64rm")>; 2027 2028def ICXWriteResGroup180 : SchedWriteRes<[ICXPort5,ICXPort23]> { 2029 let Latency = 13; 2030 let NumMicroOps = 3; 2031 let ResourceCycles = [2,1]; 2032} 2033def: InstRW<[ICXWriteResGroup180], (instregex "(ADD|SUB|SUBR)_FI(16|32)m", 2034 "VPERMWZ256rm(b?)", 2035 "VPERMWZrm(b?)")>; 2036 2037def ICXWriteResGroup181 : SchedWriteRes<[ICXPort0,ICXPort5,ICXPort23]> { 2038 let Latency = 13; 2039 let NumMicroOps = 3; 2040 let ResourceCycles = [1,1,1]; 2041} 2042def: InstRW<[ICXWriteResGroup181], (instrs VCVTDQ2PDYrm)>; 2043 2044def ICXWriteResGroup183 : SchedWriteRes<[ICXPort5,ICXPort23,ICXPort015]> { 2045 let Latency = 13; 2046 let NumMicroOps = 4; 2047 let ResourceCycles = [2,1,1]; 2048} 2049def: InstRW<[ICXWriteResGroup183], (instregex "VPERMI2W128rm(b?)", 2050 "VPERMT2W128rm(b?)")>; 2051 2052def ICXWriteResGroup184 : SchedWriteRes<[ICXPort0,ICXFPDivider]> { 2053 let Latency = 14; 2054 let NumMicroOps = 1; 2055 let ResourceCycles = [1,3]; 2056} 2057def : SchedAlias<WriteFDiv64, ICXWriteResGroup184>; // TODO - convert to ZnWriteResFpuPair 2058def : SchedAlias<WriteFDiv64X, ICXWriteResGroup184>; // TODO - convert to ZnWriteResFpuPair 2059 2060def ICXWriteResGroup184_1 : SchedWriteRes<[ICXPort0,ICXFPDivider]> { 2061 let Latency = 14; 2062 let NumMicroOps = 1; 2063 let ResourceCycles = [1,5]; 2064} 2065def : SchedAlias<WriteFDiv64Y, ICXWriteResGroup184_1>; // TODO - convert to ZnWriteResFpuPair 2066 2067def ICXWriteResGroup187 : SchedWriteRes<[ICXPort0,ICXPort5,ICXPort23]> { 2068 let Latency = 14; 2069 let NumMicroOps = 3; 2070 let ResourceCycles = [1,1,1]; 2071} 2072def: InstRW<[ICXWriteResGroup187], (instregex "MUL_FI(16|32)m")>; 2073 2074def ICXWriteResGroup188 : SchedWriteRes<[ICXPort5,ICXPort23,ICXPort015]> { 2075 let Latency = 14; 2076 let NumMicroOps = 3; 2077 let ResourceCycles = [1,1,1]; 2078} 2079def: InstRW<[ICXWriteResGroup188], (instregex "VCVTPD2DQZrm(b?)", 2080 "VCVTPD2PSZrm(b?)", 2081 "VCVTPD2UDQZrm(b?)", 2082 "VCVTQQ2PSZrm(b?)", 2083 "VCVTTPD2DQZrm(b?)", 2084 "VCVTTPD2UDQZrm(b?)", 2085 "VCVTUQQ2PSZrm(b?)")>; 2086 2087def ICXWriteResGroup189 : SchedWriteRes<[ICXPort5,ICXPort23,ICXPort015]> { 2088 let Latency = 14; 2089 let NumMicroOps = 4; 2090 let ResourceCycles = [2,1,1]; 2091} 2092def: InstRW<[ICXWriteResGroup189], (instregex "VPERMI2W256rm(b?)", 2093 "VPERMI2Wrm(b?)", 2094 "VPERMT2W256rm(b?)", 2095 "VPERMT2Wrm(b?)")>; 2096 2097def ICXWriteResGroup190 : SchedWriteRes<[ICXPort1,ICXPort06,ICXPort15,ICXPort0156]> { 2098 let Latency = 14; 2099 let NumMicroOps = 10; 2100 let ResourceCycles = [2,4,1,3]; 2101} 2102def: InstRW<[ICXWriteResGroup190], (instrs RCR8rCL)>; 2103 2104def ICXWriteResGroup191 : SchedWriteRes<[ICXPort0]> { 2105 let Latency = 15; 2106 let NumMicroOps = 1; 2107 let ResourceCycles = [1]; 2108} 2109def: InstRW<[ICXWriteResGroup191], (instregex "DIVR_(FPrST0|FST0r|FrST0)")>; 2110 2111def ICXWriteResGroup194 : SchedWriteRes<[ICXPort1,ICXPort5,ICXPort01,ICXPort23,ICXPort015]> { 2112 let Latency = 15; 2113 let NumMicroOps = 8; 2114 let ResourceCycles = [1,2,2,1,2]; 2115} 2116def: InstRW<[ICXWriteResGroup194], (instregex "VPCONFLICTDZ128rm(b?)")>; 2117 2118def ICXWriteResGroup195 : SchedWriteRes<[ICXPort1,ICXPort23,ICXPort237,ICXPort06,ICXPort15,ICXPort0156]> { 2119 let Latency = 15; 2120 let NumMicroOps = 10; 2121 let ResourceCycles = [1,1,1,5,1,1]; 2122} 2123def: InstRW<[ICXWriteResGroup195], (instregex "RCL(8|16|32|64)mCL")>; 2124 2125def ICXWriteResGroup199 : SchedWriteRes<[ICXPort4,ICXPort23,ICXPort237,ICXPort06,ICXPort15,ICXPort0156]> { 2126 let Latency = 16; 2127 let NumMicroOps = 14; 2128 let ResourceCycles = [1,1,1,4,2,5]; 2129} 2130def: InstRW<[ICXWriteResGroup199], (instrs CMPXCHG8B)>; 2131 2132def ICXWriteResGroup200 : SchedWriteRes<[ICXPort1, ICXPort05, ICXPort6]> { 2133 let Latency = 12; 2134 let NumMicroOps = 34; 2135 let ResourceCycles = [1, 4, 5]; 2136} 2137def: InstRW<[ICXWriteResGroup200], (instrs VZEROALL)>; 2138 2139def ICXWriteResGroup201 : SchedWriteRes<[ICXPort0,ICXPort23,ICXFPDivider]> { 2140 let Latency = 17; 2141 let NumMicroOps = 2; 2142 let ResourceCycles = [1,1,5]; 2143} 2144def : SchedAlias<WriteFDivXLd, ICXWriteResGroup201>; // TODO - convert to ZnWriteResFpuPair 2145 2146def ICXWriteResGroup202 : SchedWriteRes<[ICXPort0,ICXPort1,ICXPort5,ICXPort6,ICXPort05,ICXPort0156]> { 2147 let Latency = 17; 2148 let NumMicroOps = 15; 2149 let ResourceCycles = [2,1,2,4,2,4]; 2150} 2151def: InstRW<[ICXWriteResGroup202], (instrs XCH_F)>; 2152 2153def ICXWriteResGroup205 : SchedWriteRes<[ICXPort23,ICXPort01]> { 2154 let Latency = 21; 2155 let NumMicroOps = 4; 2156 let ResourceCycles = [1,3]; 2157} 2158def: InstRW<[ICXWriteResGroup205], (instregex "VPMULLQZ128rm(b?)")>; 2159 2160def ICXWriteResGroup207 : SchedWriteRes<[ICXPort5,ICXPort6,ICXPort06,ICXPort0156]> { 2161 let Latency = 18; 2162 let NumMicroOps = 8; 2163 let ResourceCycles = [1,1,1,5]; 2164} 2165def: InstRW<[ICXWriteResGroup207], (instrs CPUID, RDTSC)>; 2166 2167def ICXWriteResGroup208 : SchedWriteRes<[ICXPort1,ICXPort23,ICXPort237,ICXPort06,ICXPort15,ICXPort0156]> { 2168 let Latency = 18; 2169 let NumMicroOps = 11; 2170 let ResourceCycles = [2,1,1,4,1,2]; 2171} 2172def: InstRW<[ICXWriteResGroup208], (instregex "RCR(8|16|32|64)mCL")>; 2173 2174def ICXWriteResGroup209 : SchedWriteRes<[ICXPort0,ICXPort23,ICXFPDivider]> { 2175 let Latency = 19; 2176 let NumMicroOps = 2; 2177 let ResourceCycles = [1,1,4]; 2178} 2179def : SchedAlias<WriteFDiv64Ld, ICXWriteResGroup209>; // TODO - convert to ZnWriteResFpuPair 2180 2181def ICXWriteResGroup211 : SchedWriteRes<[ICXPort23,ICXPort01]> { 2182 let Latency = 22; 2183 let NumMicroOps = 4; 2184 let ResourceCycles = [1,3]; 2185} 2186def: InstRW<[ICXWriteResGroup211], (instregex "VPMULLQZ256rm(b?)")>; 2187 2188def ICXWriteResGroup211_1 : SchedWriteRes<[ICXPort23,ICXPort05]> { 2189 let Latency = 22; 2190 let NumMicroOps = 4; 2191 let ResourceCycles = [1,3]; 2192} 2193def: InstRW<[ICXWriteResGroup211_1], (instregex "VPMULLQZrm(b?)")>; 2194 2195def ICXWriteResGroup215 : SchedWriteRes<[ICXPort0]> { 2196 let Latency = 20; 2197 let NumMicroOps = 1; 2198 let ResourceCycles = [1]; 2199} 2200def: InstRW<[ICXWriteResGroup215], (instregex "DIV_(FPrST0|FST0r|FrST0)")>; 2201 2202def ICXWriteResGroup216 : SchedWriteRes<[ICXPort0,ICXPort23,ICXFPDivider]> { 2203 let Latency = 20; 2204 let NumMicroOps = 2; 2205 let ResourceCycles = [1,1,4]; 2206} 2207def : SchedAlias<WriteFDiv64XLd, ICXWriteResGroup216>; // TODO - convert to ZnWriteResFpuPair 2208 2209def ICXWriteGatherEVEX2 : SchedWriteRes<[ICXPort0,ICXPort23,ICXPort015,ICXPort0156]> { 2210 let Latency = 17; 2211 let NumMicroOps = 5; // 2 uops perform multiple loads 2212 let ResourceCycles = [1,2,1,1]; 2213} 2214def: InstRW<[ICXWriteGatherEVEX2], (instrs VGATHERQPSZ128rm, VPGATHERQDZ128rm, 2215 VGATHERDPDZ128rm, VPGATHERDQZ128rm, 2216 VGATHERQPDZ128rm, VPGATHERQQZ128rm)>; 2217 2218def ICXWriteGatherEVEX4 : SchedWriteRes<[ICXPort0,ICXPort23,ICXPort015,ICXPort0156]> { 2219 let Latency = 19; 2220 let NumMicroOps = 5; // 2 uops perform multiple loads 2221 let ResourceCycles = [1,4,1,1]; 2222} 2223def: InstRW<[ICXWriteGatherEVEX4], (instrs VGATHERQPSZ256rm, VPGATHERQDZ256rm, 2224 VGATHERQPDZ256rm, VPGATHERQQZ256rm, 2225 VGATHERDPSZ128rm, VPGATHERDDZ128rm, 2226 VGATHERDPDZ256rm, VPGATHERDQZ256rm)>; 2227 2228def ICXWriteGatherEVEX8 : SchedWriteRes<[ICXPort0,ICXPort23,ICXPort015,ICXPort0156]> { 2229 let Latency = 21; 2230 let NumMicroOps = 5; // 2 uops perform multiple loads 2231 let ResourceCycles = [1,8,1,1]; 2232} 2233def: InstRW<[ICXWriteGatherEVEX8], (instrs VGATHERDPSZ256rm, VPGATHERDDZ256rm, 2234 VGATHERDPDZrm, VPGATHERDQZrm, 2235 VGATHERQPDZrm, VPGATHERQQZrm, 2236 VGATHERQPSZrm, VPGATHERQDZrm)>; 2237 2238def ICXWriteGatherEVEX16 : SchedWriteRes<[ICXPort0,ICXPort23,ICXPort015,ICXPort0156]> { 2239 let Latency = 25; 2240 let NumMicroOps = 5; // 2 uops perform multiple loads 2241 let ResourceCycles = [1,16,1,1]; 2242} 2243def: InstRW<[ICXWriteGatherEVEX16], (instrs VGATHERDPSZrm, VPGATHERDDZrm)>; 2244 2245def ICXWriteResGroup219 : SchedWriteRes<[ICXPort4,ICXPort5,ICXPort6,ICXPort23,ICXPort237,ICXPort06,ICXPort0156]> { 2246 let Latency = 20; 2247 let NumMicroOps = 8; 2248 let ResourceCycles = [1,1,1,1,1,1,2]; 2249} 2250def: InstRW<[ICXWriteResGroup219], (instrs INSB, INSL, INSW)>; 2251 2252def ICXWriteResGroup220 : SchedWriteRes<[ICXPort5,ICXPort6,ICXPort0156]> { 2253 let Latency = 20; 2254 let NumMicroOps = 10; 2255 let ResourceCycles = [1,2,7]; 2256} 2257def: InstRW<[ICXWriteResGroup220], (instrs MWAITrr)>; 2258 2259def ICXWriteResGroup222 : SchedWriteRes<[ICXPort0,ICXPort23,ICXFPDivider]> { 2260 let Latency = 21; 2261 let NumMicroOps = 2; 2262 let ResourceCycles = [1,1,8]; 2263} 2264def : SchedAlias<WriteFDiv64YLd, ICXWriteResGroup222>; // TODO - convert to ZnWriteResFpuPair 2265 2266def ICXWriteResGroup223 : SchedWriteRes<[ICXPort0,ICXPort23]> { 2267 let Latency = 22; 2268 let NumMicroOps = 2; 2269 let ResourceCycles = [1,1]; 2270} 2271def: InstRW<[ICXWriteResGroup223], (instregex "DIV_F(32|64)m")>; 2272 2273def ICXWriteResGroupVEX2 : SchedWriteRes<[ICXPort0, ICXPort23, ICXPort5, ICXPort015]> { 2274 let Latency = 18; 2275 let NumMicroOps = 5; // 2 uops perform multiple loads 2276 let ResourceCycles = [1,2,1,1]; 2277} 2278def: InstRW<[ICXWriteResGroupVEX2], (instrs VGATHERDPDrm, VPGATHERDQrm, 2279 VGATHERQPDrm, VPGATHERQQrm, 2280 VGATHERQPSrm, VPGATHERQDrm)>; 2281 2282def ICXWriteResGroupVEX4 : SchedWriteRes<[ICXPort0, ICXPort23, ICXPort5, ICXPort015]> { 2283 let Latency = 20; 2284 let NumMicroOps = 5; // 2 uops peform multiple loads 2285 let ResourceCycles = [1,4,1,1]; 2286} 2287def: InstRW<[ICXWriteResGroupVEX4], (instrs VGATHERDPDYrm, VPGATHERDQYrm, 2288 VGATHERDPSrm, VPGATHERDDrm, 2289 VGATHERQPDYrm, VPGATHERQQYrm, 2290 VGATHERQPSYrm, VPGATHERQDYrm)>; 2291 2292def ICXWriteResGroupVEX8 : SchedWriteRes<[ICXPort0, ICXPort23, ICXPort5, ICXPort015]> { 2293 let Latency = 22; 2294 let NumMicroOps = 5; // 2 uops perform multiple loads 2295 let ResourceCycles = [1,8,1,1]; 2296} 2297def: InstRW<[ICXWriteResGroupVEX8], (instrs VGATHERDPSYrm, VPGATHERDDYrm)>; 2298 2299def ICXWriteResGroup225 : SchedWriteRes<[ICXPort5,ICXPort01,ICXPort015]> { 2300 let Latency = 22; 2301 let NumMicroOps = 14; 2302 let ResourceCycles = [5,5,4]; 2303} 2304def: InstRW<[ICXWriteResGroup225], (instregex "VPCONFLICTDZ128rr", 2305 "VPCONFLICTQZ256rr")>; 2306 2307def ICXWriteResGroup228 : SchedWriteRes<[ICXPort0,ICXPort4,ICXPort5,ICXPort23,ICXPort237,ICXPort06,ICXPort0156]> { 2308 let Latency = 23; 2309 let NumMicroOps = 19; 2310 let ResourceCycles = [2,1,4,1,1,4,6]; 2311} 2312def: InstRW<[ICXWriteResGroup228], (instrs CMPXCHG16B)>; 2313 2314def ICXWriteResGroup233 : SchedWriteRes<[ICXPort0,ICXPort5,ICXPort23]> { 2315 let Latency = 25; 2316 let NumMicroOps = 3; 2317 let ResourceCycles = [1,1,1]; 2318} 2319def: InstRW<[ICXWriteResGroup233], (instregex "DIV_FI(16|32)m")>; 2320 2321def ICXWriteResGroup239 : SchedWriteRes<[ICXPort0,ICXPort23]> { 2322 let Latency = 27; 2323 let NumMicroOps = 2; 2324 let ResourceCycles = [1,1]; 2325} 2326def: InstRW<[ICXWriteResGroup239], (instregex "DIVR_F(32|64)m")>; 2327 2328def ICXWriteResGroup242 : SchedWriteRes<[ICXPort5,ICXPort01,ICXPort23,ICXPort015]> { 2329 let Latency = 29; 2330 let NumMicroOps = 15; 2331 let ResourceCycles = [5,5,1,4]; 2332} 2333def: InstRW<[ICXWriteResGroup242], (instregex "VPCONFLICTQZ256rm(b?)")>; 2334 2335def ICXWriteResGroup243 : SchedWriteRes<[ICXPort0,ICXPort5,ICXPort23]> { 2336 let Latency = 30; 2337 let NumMicroOps = 3; 2338 let ResourceCycles = [1,1,1]; 2339} 2340def: InstRW<[ICXWriteResGroup243], (instregex "DIVR_FI(16|32)m")>; 2341 2342def ICXWriteResGroup247 : SchedWriteRes<[ICXPort5,ICXPort6,ICXPort23,ICXPort06,ICXPort0156]> { 2343 let Latency = 35; 2344 let NumMicroOps = 23; 2345 let ResourceCycles = [1,5,3,4,10]; 2346} 2347def: InstRW<[ICXWriteResGroup247], (instregex "IN(8|16|32)ri", 2348 "IN(8|16|32)rr")>; 2349 2350def ICXWriteResGroup248 : SchedWriteRes<[ICXPort5,ICXPort6,ICXPort23,ICXPort237,ICXPort06,ICXPort0156]> { 2351 let Latency = 35; 2352 let NumMicroOps = 23; 2353 let ResourceCycles = [1,5,2,1,4,10]; 2354} 2355def: InstRW<[ICXWriteResGroup248], (instregex "OUT(8|16|32)ir", 2356 "OUT(8|16|32)rr")>; 2357 2358def ICXWriteResGroup249 : SchedWriteRes<[ICXPort5,ICXPort01,ICXPort015]> { 2359 let Latency = 37; 2360 let NumMicroOps = 21; 2361 let ResourceCycles = [9,7,5]; 2362} 2363def: InstRW<[ICXWriteResGroup249], (instregex "VPCONFLICTDZ256rr", 2364 "VPCONFLICTQZrr")>; 2365 2366def ICXWriteResGroup250 : SchedWriteRes<[ICXPort1,ICXPort6,ICXPort23,ICXPort0156]> { 2367 let Latency = 37; 2368 let NumMicroOps = 31; 2369 let ResourceCycles = [1,8,1,21]; 2370} 2371def: InstRW<[ICXWriteResGroup250], (instregex "XRSTOR(64)?")>; 2372 2373def ICXWriteResGroup252 : SchedWriteRes<[ICXPort1,ICXPort4,ICXPort5,ICXPort6,ICXPort23,ICXPort237,ICXPort15,ICXPort0156]> { 2374 let Latency = 40; 2375 let NumMicroOps = 18; 2376 let ResourceCycles = [1,1,2,3,1,1,1,8]; 2377} 2378def: InstRW<[ICXWriteResGroup252], (instrs VMCLEARm)>; 2379 2380def ICXWriteResGroup253 : SchedWriteRes<[ICXPort4,ICXPort6,ICXPort23,ICXPort237,ICXPort0156]> { 2381 let Latency = 41; 2382 let NumMicroOps = 39; 2383 let ResourceCycles = [1,10,1,1,26]; 2384} 2385def: InstRW<[ICXWriteResGroup253], (instrs XSAVE64)>; 2386 2387def ICXWriteResGroup254 : SchedWriteRes<[ICXPort5,ICXPort0156]> { 2388 let Latency = 42; 2389 let NumMicroOps = 22; 2390 let ResourceCycles = [2,20]; 2391} 2392def: InstRW<[ICXWriteResGroup254], (instrs RDTSCP)>; 2393 2394def ICXWriteResGroup255 : SchedWriteRes<[ICXPort4,ICXPort6,ICXPort23,ICXPort237,ICXPort0156]> { 2395 let Latency = 42; 2396 let NumMicroOps = 40; 2397 let ResourceCycles = [1,11,1,1,26]; 2398} 2399def: InstRW<[ICXWriteResGroup255], (instrs XSAVE)>; 2400def: InstRW<[ICXWriteResGroup255], (instregex "XSAVEC", "XSAVES", "XSAVEOPT")>; 2401 2402def ICXWriteResGroup256 : SchedWriteRes<[ICXPort5,ICXPort01,ICXPort23,ICXPort015]> { 2403 let Latency = 44; 2404 let NumMicroOps = 22; 2405 let ResourceCycles = [9,7,1,5]; 2406} 2407def: InstRW<[ICXWriteResGroup256], (instregex "VPCONFLICTDZ256rm(b?)", 2408 "VPCONFLICTQZrm(b?)")>; 2409 2410def ICXWriteResGroup258 : SchedWriteRes<[ICXPort0,ICXPort23,ICXPort05,ICXPort06,ICXPort0156]> { 2411 let Latency = 62; 2412 let NumMicroOps = 64; 2413 let ResourceCycles = [2,8,5,10,39]; 2414} 2415def: InstRW<[ICXWriteResGroup258], (instrs FLDENVm)>; 2416 2417def ICXWriteResGroup259 : SchedWriteRes<[ICXPort0,ICXPort6,ICXPort23,ICXPort05,ICXPort06,ICXPort15,ICXPort0156]> { 2418 let Latency = 63; 2419 let NumMicroOps = 88; 2420 let ResourceCycles = [4,4,31,1,2,1,45]; 2421} 2422def: InstRW<[ICXWriteResGroup259], (instrs FXRSTOR64)>; 2423 2424def ICXWriteResGroup260 : SchedWriteRes<[ICXPort0,ICXPort6,ICXPort23,ICXPort05,ICXPort06,ICXPort15,ICXPort0156]> { 2425 let Latency = 63; 2426 let NumMicroOps = 90; 2427 let ResourceCycles = [4,2,33,1,2,1,47]; 2428} 2429def: InstRW<[ICXWriteResGroup260], (instrs FXRSTOR)>; 2430 2431def ICXWriteResGroup261 : SchedWriteRes<[ICXPort5,ICXPort01,ICXPort015]> { 2432 let Latency = 67; 2433 let NumMicroOps = 35; 2434 let ResourceCycles = [17,11,7]; 2435} 2436def: InstRW<[ICXWriteResGroup261], (instregex "VPCONFLICTDZrr")>; 2437 2438def ICXWriteResGroup262 : SchedWriteRes<[ICXPort5,ICXPort01,ICXPort23,ICXPort015]> { 2439 let Latency = 74; 2440 let NumMicroOps = 36; 2441 let ResourceCycles = [17,11,1,7]; 2442} 2443def: InstRW<[ICXWriteResGroup262], (instregex "VPCONFLICTDZrm(b?)")>; 2444 2445def ICXWriteResGroup263 : SchedWriteRes<[ICXPort5,ICXPort05,ICXPort0156]> { 2446 let Latency = 75; 2447 let NumMicroOps = 15; 2448 let ResourceCycles = [6,3,6]; 2449} 2450def: InstRW<[ICXWriteResGroup263], (instrs FNINIT)>; 2451 2452def ICXWriteResGroup266 : SchedWriteRes<[ICXPort0,ICXPort1,ICXPort4,ICXPort5,ICXPort6,ICXPort237,ICXPort06,ICXPort0156]> { 2453 let Latency = 106; 2454 let NumMicroOps = 100; 2455 let ResourceCycles = [9,1,11,16,1,11,21,30]; 2456} 2457def: InstRW<[ICXWriteResGroup266], (instrs FSTENVm)>; 2458 2459def ICXWriteResGroup267 : SchedWriteRes<[ICXPort6,ICXPort0156]> { 2460 let Latency = 140; 2461 let NumMicroOps = 4; 2462 let ResourceCycles = [1,3]; 2463} 2464def: InstRW<[ICXWriteResGroup267], (instrs PAUSE)>; 2465 2466def: InstRW<[WriteZero], (instrs CLC)>; 2467 2468 2469// Instruction variants handled by the renamer. These might not need execution 2470// ports in certain conditions. 2471// See Agner's Fog "The microarchitecture of Intel, AMD and VIA CPUs", 2472// section "Skylake Pipeline" > "Register allocation and renaming". 2473// These can be investigated with llvm-exegesis, e.g. 2474// echo 'pxor %mm0, %mm0' | /tmp/llvm-exegesis -mode=uops -snippets-file=- 2475// echo 'vxorpd %xmm0, %xmm0, %xmm1' | /tmp/llvm-exegesis -mode=uops -snippets-file=- 2476 2477def ICXWriteZeroLatency : SchedWriteRes<[]> { 2478 let Latency = 0; 2479} 2480 2481def ICXWriteZeroIdiom : SchedWriteVariant<[ 2482 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [ICXWriteZeroLatency]>, 2483 SchedVar<NoSchedPred, [WriteALU]> 2484]>; 2485def : InstRW<[ICXWriteZeroIdiom], (instrs SUB32rr, SUB64rr, 2486 XOR32rr, XOR64rr)>; 2487 2488def ICXWriteFZeroIdiom : SchedWriteVariant<[ 2489 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [ICXWriteZeroLatency]>, 2490 SchedVar<NoSchedPred, [WriteFLogic]> 2491]>; 2492def : InstRW<[ICXWriteFZeroIdiom], (instrs XORPSrr, VXORPSrr, 2493 XORPDrr, VXORPDrr, 2494 VXORPSZ128rr, 2495 VXORPDZ128rr)>; 2496 2497def ICXWriteFZeroIdiomY : SchedWriteVariant<[ 2498 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [ICXWriteZeroLatency]>, 2499 SchedVar<NoSchedPred, [WriteFLogicY]> 2500]>; 2501def : InstRW<[ICXWriteFZeroIdiomY], (instrs VXORPSYrr, VXORPDYrr, 2502 VXORPSZ256rr, VXORPDZ256rr)>; 2503 2504def ICXWriteFZeroIdiomZ : SchedWriteVariant<[ 2505 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [ICXWriteZeroLatency]>, 2506 SchedVar<NoSchedPred, [WriteFLogicZ]> 2507]>; 2508def : InstRW<[ICXWriteFZeroIdiomZ], (instrs VXORPSZrr, VXORPDZrr)>; 2509 2510def ICXWriteVZeroIdiomLogicX : SchedWriteVariant<[ 2511 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [ICXWriteZeroLatency]>, 2512 SchedVar<NoSchedPred, [WriteVecLogicX]> 2513]>; 2514def : InstRW<[ICXWriteVZeroIdiomLogicX], (instrs PXORrr, VPXORrr, 2515 VPXORDZ128rr, VPXORQZ128rr)>; 2516 2517def ICXWriteVZeroIdiomLogicY : SchedWriteVariant<[ 2518 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [ICXWriteZeroLatency]>, 2519 SchedVar<NoSchedPred, [WriteVecLogicY]> 2520]>; 2521def : InstRW<[ICXWriteVZeroIdiomLogicY], (instrs VPXORYrr, 2522 VPXORDZ256rr, VPXORQZ256rr)>; 2523 2524def ICXWriteVZeroIdiomLogicZ : SchedWriteVariant<[ 2525 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [ICXWriteZeroLatency]>, 2526 SchedVar<NoSchedPred, [WriteVecLogicZ]> 2527]>; 2528def : InstRW<[ICXWriteVZeroIdiomLogicZ], (instrs VPXORDZrr, VPXORQZrr)>; 2529 2530def ICXWriteVZeroIdiomALUX : SchedWriteVariant<[ 2531 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [ICXWriteZeroLatency]>, 2532 SchedVar<NoSchedPred, [WriteVecALUX]> 2533]>; 2534def : InstRW<[ICXWriteVZeroIdiomALUX], (instrs PCMPGTBrr, VPCMPGTBrr, 2535 PCMPGTDrr, VPCMPGTDrr, 2536 PCMPGTWrr, VPCMPGTWrr)>; 2537 2538def ICXWriteVZeroIdiomALUY : SchedWriteVariant<[ 2539 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [ICXWriteZeroLatency]>, 2540 SchedVar<NoSchedPred, [WriteVecALUY]> 2541]>; 2542def : InstRW<[ICXWriteVZeroIdiomALUY], (instrs VPCMPGTBYrr, 2543 VPCMPGTDYrr, 2544 VPCMPGTWYrr)>; 2545 2546def ICXWritePSUB : SchedWriteRes<[ICXPort015]> { 2547 let Latency = 1; 2548 let NumMicroOps = 1; 2549 let ResourceCycles = [1]; 2550} 2551 2552def ICXWriteVZeroIdiomPSUB : SchedWriteVariant<[ 2553 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [ICXWriteZeroLatency]>, 2554 SchedVar<NoSchedPred, [ICXWritePSUB]> 2555]>; 2556 2557def : InstRW<[ICXWriteVZeroIdiomPSUB], (instrs PSUBBrr, VPSUBBrr, VPSUBBZ128rr, 2558 PSUBDrr, VPSUBDrr, VPSUBDZ128rr, 2559 PSUBQrr, VPSUBQrr, VPSUBQZ128rr, 2560 PSUBWrr, VPSUBWrr, VPSUBWZ128rr, 2561 VPSUBBYrr, VPSUBBZ256rr, 2562 VPSUBDYrr, VPSUBDZ256rr, 2563 VPSUBQYrr, VPSUBQZ256rr, 2564 VPSUBWYrr, VPSUBWZ256rr, 2565 VPSUBBZrr, 2566 VPSUBDZrr, 2567 VPSUBQZrr, 2568 VPSUBWZrr)>; 2569def ICXWritePCMPGTQ : SchedWriteRes<[ICXPort5]> { 2570 let Latency = 3; 2571 let NumMicroOps = 1; 2572 let ResourceCycles = [1]; 2573} 2574 2575def ICXWriteVZeroIdiomPCMPGTQ : SchedWriteVariant<[ 2576 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [ICXWriteZeroLatency]>, 2577 SchedVar<NoSchedPred, [ICXWritePCMPGTQ]> 2578]>; 2579def : InstRW<[ICXWriteVZeroIdiomPCMPGTQ], (instrs PCMPGTQrr, VPCMPGTQrr, 2580 VPCMPGTQYrr)>; 2581 2582 2583// CMOVs that use both Z and C flag require an extra uop. 2584def ICXWriteCMOVA_CMOVBErr : SchedWriteRes<[ICXPort06]> { 2585 let Latency = 2; 2586 let ResourceCycles = [2]; 2587 let NumMicroOps = 2; 2588} 2589 2590def ICXWriteCMOVA_CMOVBErm : SchedWriteRes<[ICXPort23,ICXPort06]> { 2591 let Latency = 7; 2592 let ResourceCycles = [1,2]; 2593 let NumMicroOps = 3; 2594} 2595 2596def ICXCMOVA_CMOVBErr : SchedWriteVariant<[ 2597 SchedVar<MCSchedPredicate<IsCMOVArr_Or_CMOVBErr>, [ICXWriteCMOVA_CMOVBErr]>, 2598 SchedVar<NoSchedPred, [WriteCMOV]> 2599]>; 2600 2601def ICXCMOVA_CMOVBErm : SchedWriteVariant<[ 2602 SchedVar<MCSchedPredicate<IsCMOVArm_Or_CMOVBErm>, [ICXWriteCMOVA_CMOVBErm]>, 2603 SchedVar<NoSchedPred, [WriteCMOV.Folded]> 2604]>; 2605 2606def : InstRW<[ICXCMOVA_CMOVBErr], (instrs CMOV16rr, CMOV32rr, CMOV64rr)>; 2607def : InstRW<[ICXCMOVA_CMOVBErm], (instrs CMOV16rm, CMOV32rm, CMOV64rm)>; 2608 2609// SETCCs that use both Z and C flag require an extra uop. 2610def ICXWriteSETA_SETBEr : SchedWriteRes<[ICXPort06]> { 2611 let Latency = 2; 2612 let ResourceCycles = [2]; 2613 let NumMicroOps = 2; 2614} 2615 2616def ICXWriteSETA_SETBEm : SchedWriteRes<[ICXPort4,ICXPort237,ICXPort06]> { 2617 let Latency = 3; 2618 let ResourceCycles = [1,1,2]; 2619 let NumMicroOps = 4; 2620} 2621 2622def ICXSETA_SETBErr : SchedWriteVariant<[ 2623 SchedVar<MCSchedPredicate<IsSETAr_Or_SETBEr>, [ICXWriteSETA_SETBEr]>, 2624 SchedVar<NoSchedPred, [WriteSETCC]> 2625]>; 2626 2627def ICXSETA_SETBErm : SchedWriteVariant<[ 2628 SchedVar<MCSchedPredicate<IsSETAm_Or_SETBEm>, [ICXWriteSETA_SETBEm]>, 2629 SchedVar<NoSchedPred, [WriteSETCCStore]> 2630]>; 2631 2632def : InstRW<[ICXSETA_SETBErr], (instrs SETCCr)>; 2633def : InstRW<[ICXSETA_SETBErm], (instrs SETCCm)>; 2634 2635/////////////////////////////////////////////////////////////////////////////// 2636// Dependency breaking instructions. 2637/////////////////////////////////////////////////////////////////////////////// 2638 2639def : IsZeroIdiomFunction<[ 2640 // GPR Zero-idioms. 2641 DepBreakingClass<[ SUB32rr, SUB64rr, XOR32rr, XOR64rr ], ZeroIdiomPredicate>, 2642 2643 // SSE Zero-idioms. 2644 DepBreakingClass<[ 2645 // fp variants. 2646 XORPSrr, XORPDrr, 2647 2648 // int variants. 2649 PXORrr, 2650 PSUBBrr, PSUBWrr, PSUBDrr, PSUBQrr, 2651 PCMPGTBrr, PCMPGTDrr, PCMPGTQrr, PCMPGTWrr 2652 ], ZeroIdiomPredicate>, 2653 2654 // AVX Zero-idioms. 2655 DepBreakingClass<[ 2656 // xmm fp variants. 2657 VXORPSrr, VXORPDrr, 2658 2659 // xmm int variants. 2660 VPXORrr, 2661 VPSUBBrr, VPSUBWrr, VPSUBDrr, VPSUBQrr, 2662 VPCMPGTBrr, VPCMPGTWrr, VPCMPGTDrr, VPCMPGTQrr, 2663 2664 // ymm variants. 2665 VXORPSYrr, VXORPDYrr, VPXORYrr, 2666 VPSUBBYrr, VPSUBWYrr, VPSUBDYrr, VPSUBQYrr, 2667 VPCMPGTBYrr, VPCMPGTWYrr, VPCMPGTDYrr, VPCMPGTQYrr, 2668 2669 // zmm variants. 2670 VXORPSZrr, VXORPDZrr, VPXORDZrr, VPXORQZrr, 2671 VXORPSZ128rr, VXORPDZ128rr, VPXORDZ128rr, VPXORQZ128rr, 2672 VXORPSZ256rr, VXORPDZ256rr, VPXORDZ256rr, VPXORQZ256rr, 2673 VPSUBBZrr, VPSUBWZrr, VPSUBDZrr, VPSUBQZrr, 2674 VPSUBBZ128rr, VPSUBWZ128rr, VPSUBDZ128rr, VPSUBQZ128rr, 2675 VPSUBBZ256rr, VPSUBWZ256rr, VPSUBDZ256rr, VPSUBQZ256rr, 2676 ], ZeroIdiomPredicate>, 2677]>; 2678 2679} // SchedModel 2680