1//=- X86SchedIceLake.td - X86 Ice Lake Scheduling ------------*- tablegen -*-=// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8// 9// This file defines the machine model for Ice Lake to support 10// instruction scheduling and other instruction cost heuristics. 11// 12// TODO: This is mainly a copy X86SchedSkylakeServer.td, but allows us to 13// iteratively improve scheduling handling toward better modelling the 14// Ice Lake (Sunny/Cypress Cove) microarchitecture. 15// 16//===----------------------------------------------------------------------===// 17 18def IceLakeModel : SchedMachineModel { 19 // All x86 instructions are modeled as a single micro-op, and Ice Lake can 20 // decode 6 instructions per cycle. 21 let IssueWidth = 6; 22 let MicroOpBufferSize = 224; // Based on the reorder buffer. 23 let LoadLatency = 5; 24 let MispredictPenalty = 14; 25 26 // Based on the LSD (loop-stream detector) queue size and benchmarking data. 27 let LoopMicroOpBufferSize = 50; 28 29 // This flag is set to allow the scheduler to assign a default model to 30 // unrecognized opcodes. 31 let CompleteModel = 0; 32} 33 34let SchedModel = IceLakeModel in { 35 36// Ice Lake can issue micro-ops to 8 different ports in one cycle. 37 38// Ports 0, 1, 5, and 6 handle all computation. 39// Ports 4 and 9 gets the data half of stores. Store data can be available later 40// than the store address, but since we don't model the latency of stores, we 41// can ignore that. 42// Ports 2 and 3 are identical. They handle loads and address calculations. 43// Ports 7 and 8 are identical. They handle stores address calculations. 44def ICXPort0 : ProcResource<1>; 45def ICXPort1 : ProcResource<1>; 46def ICXPort2 : ProcResource<1>; 47def ICXPort3 : ProcResource<1>; 48def ICXPort4 : ProcResource<1>; 49def ICXPort5 : ProcResource<1>; 50def ICXPort6 : ProcResource<1>; 51def ICXPort7 : ProcResource<1>; 52def ICXPort8 : ProcResource<1>; 53def ICXPort9 : ProcResource<1>; 54 55// Many micro-ops are capable of issuing on multiple ports. 56def ICXPort01 : ProcResGroup<[ICXPort0, ICXPort1]>; 57def ICXPort23 : ProcResGroup<[ICXPort2, ICXPort3]>; 58def ICXPort237 : ProcResGroup<[ICXPort2, ICXPort3, ICXPort7]>; 59def ICXPort04 : ProcResGroup<[ICXPort0, ICXPort4]>; 60def ICXPort05 : ProcResGroup<[ICXPort0, ICXPort5]>; 61def ICXPort06 : ProcResGroup<[ICXPort0, ICXPort6]>; 62def ICXPort15 : ProcResGroup<[ICXPort1, ICXPort5]>; 63def ICXPort16 : ProcResGroup<[ICXPort1, ICXPort6]>; 64def ICXPort49 : ProcResGroup<[ICXPort4, ICXPort9]>; 65def ICXPort56 : ProcResGroup<[ICXPort5, ICXPort6]>; 66def ICXPort78 : ProcResGroup<[ICXPort7, ICXPort8]>; 67def ICXPort015 : ProcResGroup<[ICXPort0, ICXPort1, ICXPort5]>; 68def ICXPort056 : ProcResGroup<[ICXPort0, ICXPort5, ICXPort6]>; 69def ICXPort0156: ProcResGroup<[ICXPort0, ICXPort1, ICXPort5, ICXPort6]>; 70 71def ICXDivider : ProcResource<1>; // Integer division issued on port 0. 72// FP division and sqrt on port 0. 73def ICXFPDivider : ProcResource<1>; 74 75// 60 Entry Unified Scheduler 76def ICXPortAny : ProcResGroup<[ICXPort0, ICXPort1, ICXPort2, ICXPort3, ICXPort4, 77 ICXPort5, ICXPort6, ICXPort7, ICXPort8, ICXPort9]> { 78 let BufferSize=60; 79} 80 81// Integer loads are 5 cycles, so ReadAfterLd registers needn't be available until 5 82// cycles after the memory operand. 83def : ReadAdvance<ReadAfterLd, 5>; 84 85// Vector loads are 5/6/7 cycles, so ReadAfterVec*Ld registers needn't be available 86// until 5/6/7 cycles after the memory operand. 87def : ReadAdvance<ReadAfterVecLd, 5>; 88def : ReadAdvance<ReadAfterVecXLd, 6>; 89def : ReadAdvance<ReadAfterVecYLd, 7>; 90 91def : ReadAdvance<ReadInt2Fpu, 0>; 92 93// Many SchedWrites are defined in pairs with and without a folded load. 94// Instructions with folded loads are usually micro-fused, so they only appear 95// as two micro-ops when queued in the reservation station. 96// This multiclass defines the resource usage for variants with and without 97// folded loads. 98multiclass ICXWriteResPair<X86FoldableSchedWrite SchedRW, 99 list<ProcResourceKind> ExePorts, 100 int Lat, list<int> Res = [1], int UOps = 1, 101 int LoadLat = 5, int LoadUOps = 1> { 102 // Register variant is using a single cycle on ExePort. 103 def : WriteRes<SchedRW, ExePorts> { 104 let Latency = Lat; 105 let ResourceCycles = Res; 106 let NumMicroOps = UOps; 107 } 108 109 // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to 110 // the latency (default = 5). 111 def : WriteRes<SchedRW.Folded, !listconcat([ICXPort23], ExePorts)> { 112 let Latency = !add(Lat, LoadLat); 113 let ResourceCycles = !listconcat([1], Res); 114 let NumMicroOps = !add(UOps, LoadUOps); 115 } 116} 117 118// A folded store needs a cycle on port 4 for the store data, and an extra port 119// 2/3/7 cycle to recompute the address. 120def : WriteRes<WriteRMW, [ICXPort237,ICXPort4]>; 121 122// Arithmetic. 123defm : ICXWriteResPair<WriteALU, [ICXPort0156], 1>; // Simple integer ALU op. 124defm : ICXWriteResPair<WriteADC, [ICXPort06], 1>; // Integer ALU + flags op. 125 126// Integer multiplication. 127defm : ICXWriteResPair<WriteIMul8, [ICXPort1], 3>; 128defm : ICXWriteResPair<WriteIMul16, [ICXPort1,ICXPort06,ICXPort0156], 4, [1,1,2], 4>; 129defm : X86WriteRes<WriteIMul16Imm, [ICXPort1,ICXPort0156], 4, [1,1], 2>; 130defm : X86WriteRes<WriteIMul16ImmLd, [ICXPort1,ICXPort0156,ICXPort23], 8, [1,1,1], 3>; 131defm : X86WriteRes<WriteIMul16Reg, [ICXPort1], 3, [1], 1>; 132defm : X86WriteRes<WriteIMul16RegLd, [ICXPort1,ICXPort0156,ICXPort23], 8, [1,1,1], 3>; 133defm : ICXWriteResPair<WriteIMul32, [ICXPort1,ICXPort06,ICXPort0156], 4, [1,1,1], 3>; 134defm : ICXWriteResPair<WriteMULX32, [ICXPort1,ICXPort06,ICXPort0156], 3, [1,1,1], 3>; 135defm : ICXWriteResPair<WriteIMul32Imm, [ICXPort1], 3>; 136defm : ICXWriteResPair<WriteIMul32Reg, [ICXPort1], 3>; 137defm : ICXWriteResPair<WriteIMul64, [ICXPort1,ICXPort5], 4, [1,1], 2>; 138defm : ICXWriteResPair<WriteMULX64, [ICXPort1,ICXPort5], 3, [1,1], 2>; 139defm : ICXWriteResPair<WriteIMul64Imm, [ICXPort1], 3>; 140defm : ICXWriteResPair<WriteIMul64Reg, [ICXPort1], 3>; 141def ICXWriteIMulH : WriteRes<WriteIMulH, []> { let Latency = 4; } 142def : WriteRes<WriteIMulHLd, []> { 143 let Latency = !add(ICXWriteIMulH.Latency, SkylakeServerModel.LoadLatency); 144} 145 146defm : X86WriteRes<WriteBSWAP32, [ICXPort15], 1, [1], 1>; 147defm : X86WriteRes<WriteBSWAP64, [ICXPort06, ICXPort15], 2, [1,1], 2>; 148defm : X86WriteRes<WriteCMPXCHG,[ICXPort06, ICXPort0156], 5, [2,3], 5>; 149defm : X86WriteRes<WriteCMPXCHGRMW,[ICXPort23,ICXPort06,ICXPort0156,ICXPort237,ICXPort4], 8, [1,2,1,1,1], 6>; 150defm : X86WriteRes<WriteXCHG, [ICXPort0156], 2, [3], 3>; 151 152// TODO: Why isn't the ICXDivider used? 153defm : ICXWriteResPair<WriteDiv8, [ICXPort0, ICXDivider], 25, [1,10], 1, 4>; 154defm : X86WriteRes<WriteDiv16, [ICXPort0,ICXPort1,ICXPort5,ICXPort6,ICXPort05,ICXPort0156], 76, [7,2,8,3,1,11], 32>; 155defm : X86WriteRes<WriteDiv32, [ICXPort0,ICXPort1,ICXPort5,ICXPort6,ICXPort05,ICXPort0156], 76, [7,2,8,3,1,11], 32>; 156defm : X86WriteRes<WriteDiv64, [ICXPort0,ICXPort1,ICXPort5,ICXPort6,ICXPort05,ICXPort0156], 76, [7,2,8,3,1,11], 32>; 157defm : X86WriteRes<WriteDiv16Ld, [ICXPort0,ICXPort23,ICXDivider], 29, [1,1,10], 2>; 158defm : X86WriteRes<WriteDiv32Ld, [ICXPort0,ICXPort23,ICXDivider], 29, [1,1,10], 2>; 159defm : X86WriteRes<WriteDiv64Ld, [ICXPort0,ICXPort23,ICXDivider], 29, [1,1,10], 2>; 160 161defm : X86WriteRes<WriteIDiv8, [ICXPort0, ICXDivider], 25, [1,10], 1>; 162defm : X86WriteRes<WriteIDiv16, [ICXPort0,ICXPort1,ICXPort5,ICXPort6,ICXPort06,ICXPort0156], 102, [4,2,4,8,14,34], 66>; 163defm : X86WriteRes<WriteIDiv32, [ICXPort0,ICXPort1,ICXPort5,ICXPort6,ICXPort06,ICXPort0156], 102, [4,2,4,8,14,34], 66>; 164defm : X86WriteRes<WriteIDiv64, [ICXPort0,ICXPort1,ICXPort5,ICXPort6,ICXPort06,ICXPort0156], 102, [4,2,4,8,14,34], 66>; 165defm : X86WriteRes<WriteIDiv8Ld, [ICXPort0,ICXPort5,ICXPort23,ICXPort0156], 28, [2,4,1,1], 8>; 166defm : X86WriteRes<WriteIDiv16Ld, [ICXPort0,ICXPort5,ICXPort23,ICXPort0156], 28, [2,4,1,1], 8>; 167defm : X86WriteRes<WriteIDiv32Ld, [ICXPort0,ICXPort5,ICXPort23,ICXPort0156], 28, [2,4,1,1], 8>; 168defm : X86WriteRes<WriteIDiv64Ld, [ICXPort0,ICXPort5,ICXPort23,ICXPort0156], 28, [2,4,1,1], 8>; 169 170defm : ICXWriteResPair<WriteCRC32, [ICXPort1], 3>; 171 172def : WriteRes<WriteLEA, [ICXPort15]>; // LEA instructions can't fold loads. 173 174defm : ICXWriteResPair<WriteCMOV, [ICXPort06], 1, [1], 1>; // Conditional move. 175defm : X86WriteRes<WriteFCMOV, [ICXPort1], 3, [1], 1>; // x87 conditional move. 176def : WriteRes<WriteSETCC, [ICXPort06]>; // Setcc. 177def : WriteRes<WriteSETCCStore, [ICXPort06,ICXPort4,ICXPort237]> { 178 let Latency = 2; 179 let NumMicroOps = 3; 180} 181defm : X86WriteRes<WriteLAHFSAHF, [ICXPort06], 1, [1], 1>; 182defm : X86WriteRes<WriteBitTest, [ICXPort06], 1, [1], 1>; 183defm : X86WriteRes<WriteBitTestImmLd, [ICXPort06,ICXPort23], 6, [1,1], 2>; 184defm : X86WriteRes<WriteBitTestRegLd, [ICXPort0156,ICXPort23], 6, [1,1], 2>; 185defm : X86WriteRes<WriteBitTestSet, [ICXPort06], 1, [1], 1>; 186defm : X86WriteRes<WriteBitTestSetImmLd, [ICXPort06,ICXPort23], 5, [1,1], 3>; 187defm : X86WriteRes<WriteBitTestSetRegLd, [ICXPort0156,ICXPort23], 5, [1,1], 2>; 188 189// Integer shifts and rotates. 190defm : ICXWriteResPair<WriteShift, [ICXPort06], 1>; 191defm : ICXWriteResPair<WriteShiftCL, [ICXPort06], 3, [3], 3>; 192defm : ICXWriteResPair<WriteRotate, [ICXPort06], 1, [1], 1>; 193defm : ICXWriteResPair<WriteRotateCL, [ICXPort06], 3, [3], 3>; 194 195// SHLD/SHRD. 196defm : X86WriteRes<WriteSHDrri, [ICXPort1], 3, [1], 1>; 197defm : X86WriteRes<WriteSHDrrcl,[ICXPort1,ICXPort06,ICXPort0156], 6, [1, 2, 1], 4>; 198defm : X86WriteRes<WriteSHDmri, [ICXPort1,ICXPort23,ICXPort237,ICXPort0156], 9, [1, 1, 1, 1], 4>; 199defm : X86WriteRes<WriteSHDmrcl,[ICXPort1,ICXPort23,ICXPort237,ICXPort06,ICXPort0156], 11, [1, 1, 1, 2, 1], 6>; 200 201// Bit counts. 202defm : ICXWriteResPair<WriteBSF, [ICXPort1], 3>; 203defm : ICXWriteResPair<WriteBSR, [ICXPort1], 3>; 204defm : ICXWriteResPair<WriteLZCNT, [ICXPort1], 3>; 205defm : ICXWriteResPair<WriteTZCNT, [ICXPort1], 3>; 206defm : ICXWriteResPair<WritePOPCNT, [ICXPort1], 3>; 207 208// BMI1 BEXTR/BLS, BMI2 BZHI 209defm : ICXWriteResPair<WriteBEXTR, [ICXPort06,ICXPort15], 2, [1,1], 2>; 210defm : ICXWriteResPair<WriteBLS, [ICXPort15], 1>; 211defm : ICXWriteResPair<WriteBZHI, [ICXPort15], 1>; 212 213// Loads, stores, and moves, not folded with other operations. 214defm : X86WriteRes<WriteLoad, [ICXPort23], 5, [1], 1>; 215defm : X86WriteRes<WriteStore, [ICXPort237, ICXPort4], 1, [1,1], 1>; 216defm : X86WriteRes<WriteStoreNT, [ICXPort237, ICXPort4], 1, [1,1], 2>; 217defm : X86WriteRes<WriteMove, [ICXPort0156], 1, [1], 1>; 218 219// Model the effect of clobbering the read-write mask operand of the GATHER operation. 220// Does not cost anything by itself, only has latency, matching that of the WriteLoad, 221defm : X86WriteRes<WriteVecMaskedGatherWriteback, [], 5, [], 0>; 222 223// Idioms that clear a register, like xorps %xmm0, %xmm0. 224// These can often bypass execution ports completely. 225def : WriteRes<WriteZero, []>; 226 227// Branches don't produce values, so they have no latency, but they still 228// consume resources. Indirect branches can fold loads. 229defm : ICXWriteResPair<WriteJump, [ICXPort06], 1>; 230 231// Floating point. This covers both scalar and vector operations. 232defm : X86WriteRes<WriteFLD0, [ICXPort05], 1, [1], 1>; 233defm : X86WriteRes<WriteFLD1, [ICXPort05], 1, [2], 2>; 234defm : X86WriteRes<WriteFLDC, [ICXPort05], 1, [2], 2>; 235defm : X86WriteRes<WriteFLoad, [ICXPort23], 5, [1], 1>; 236defm : X86WriteRes<WriteFLoadX, [ICXPort23], 6, [1], 1>; 237defm : X86WriteRes<WriteFLoadY, [ICXPort23], 7, [1], 1>; 238defm : X86WriteRes<WriteFMaskedLoad, [ICXPort23,ICXPort015], 7, [1,1], 2>; 239defm : X86WriteRes<WriteFMaskedLoadY, [ICXPort23,ICXPort015], 8, [1,1], 2>; 240defm : X86WriteRes<WriteFStore, [ICXPort237,ICXPort4], 1, [1,1], 2>; 241defm : X86WriteRes<WriteFStoreX, [ICXPort237,ICXPort4], 1, [1,1], 2>; 242defm : X86WriteRes<WriteFStoreY, [ICXPort237,ICXPort4], 1, [1,1], 2>; 243defm : X86WriteRes<WriteFStoreNT, [ICXPort237,ICXPort4], 1, [1,1], 2>; 244defm : X86WriteRes<WriteFStoreNTX, [ICXPort237,ICXPort4], 1, [1,1], 2>; 245defm : X86WriteRes<WriteFStoreNTY, [ICXPort237,ICXPort4], 1, [1,1], 2>; 246 247defm : X86WriteRes<WriteFMaskedStore32, [ICXPort237,ICXPort0], 2, [1,1], 2>; 248defm : X86WriteRes<WriteFMaskedStore32Y, [ICXPort237,ICXPort0], 2, [1,1], 2>; 249defm : X86WriteRes<WriteFMaskedStore64, [ICXPort237,ICXPort0], 2, [1,1], 2>; 250defm : X86WriteRes<WriteFMaskedStore64Y, [ICXPort237,ICXPort0], 2, [1,1], 2>; 251 252defm : X86WriteRes<WriteFMove, [ICXPort015], 1, [1], 1>; 253defm : X86WriteRes<WriteFMoveX, [ICXPort015], 1, [1], 1>; 254defm : X86WriteRes<WriteFMoveY, [ICXPort015], 1, [1], 1>; 255defm : X86WriteRes<WriteFMoveZ, [ICXPort05], 1, [1], 1>; 256defm : X86WriteRes<WriteEMMS, [ICXPort05,ICXPort0156], 10, [9,1], 10>; 257 258defm : ICXWriteResPair<WriteFAdd, [ICXPort01], 4, [1], 1, 5>; // Floating point add/sub. 259defm : ICXWriteResPair<WriteFAddX, [ICXPort01], 4, [1], 1, 6>; 260defm : ICXWriteResPair<WriteFAddY, [ICXPort01], 4, [1], 1, 7>; 261defm : ICXWriteResPair<WriteFAddZ, [ICXPort05], 4, [1], 1, 7>; 262defm : ICXWriteResPair<WriteFAdd64, [ICXPort01], 4, [1], 1, 5>; // Floating point double add/sub. 263defm : ICXWriteResPair<WriteFAdd64X, [ICXPort01], 4, [1], 1, 6>; 264defm : ICXWriteResPair<WriteFAdd64Y, [ICXPort01], 4, [1], 1, 7>; 265defm : ICXWriteResPair<WriteFAdd64Z, [ICXPort05], 4, [1], 1, 7>; 266 267defm : ICXWriteResPair<WriteFCmp, [ICXPort01], 4, [1], 1, 5>; // Floating point compare. 268defm : ICXWriteResPair<WriteFCmpX, [ICXPort01], 4, [1], 1, 6>; 269defm : ICXWriteResPair<WriteFCmpY, [ICXPort01], 4, [1], 1, 7>; 270defm : ICXWriteResPair<WriteFCmpZ, [ICXPort05], 4, [1], 1, 7>; 271defm : ICXWriteResPair<WriteFCmp64, [ICXPort01], 4, [1], 1, 5>; // Floating point double compare. 272defm : ICXWriteResPair<WriteFCmp64X, [ICXPort01], 4, [1], 1, 6>; 273defm : ICXWriteResPair<WriteFCmp64Y, [ICXPort01], 4, [1], 1, 7>; 274defm : ICXWriteResPair<WriteFCmp64Z, [ICXPort05], 4, [1], 1, 7>; 275 276defm : ICXWriteResPair<WriteFCom, [ICXPort0], 2>; // Floating point compare to flags (X87). 277defm : ICXWriteResPair<WriteFComX, [ICXPort0], 2>; // Floating point compare to flags (SSE). 278 279defm : ICXWriteResPair<WriteFMul, [ICXPort01], 4, [1], 1, 5>; // Floating point multiplication. 280defm : ICXWriteResPair<WriteFMulX, [ICXPort01], 4, [1], 1, 6>; 281defm : ICXWriteResPair<WriteFMulY, [ICXPort01], 4, [1], 1, 7>; 282defm : ICXWriteResPair<WriteFMulZ, [ICXPort05], 4, [1], 1, 7>; 283defm : ICXWriteResPair<WriteFMul64, [ICXPort01], 4, [1], 1, 5>; // Floating point double multiplication. 284defm : ICXWriteResPair<WriteFMul64X, [ICXPort01], 4, [1], 1, 6>; 285defm : ICXWriteResPair<WriteFMul64Y, [ICXPort01], 4, [1], 1, 7>; 286defm : ICXWriteResPair<WriteFMul64Z, [ICXPort05], 4, [1], 1, 7>; 287 288defm : ICXWriteResPair<WriteFDiv, [ICXPort0,ICXFPDivider], 11, [1,3], 1, 5>; // 10-14 cycles. // Floating point division. 289defm : ICXWriteResPair<WriteFDivX, [ICXPort0,ICXFPDivider], 11, [1,3], 1, 6>; // 10-14 cycles. 290defm : ICXWriteResPair<WriteFDivY, [ICXPort0,ICXFPDivider], 11, [1,5], 1, 7>; // 10-14 cycles. 291defm : ICXWriteResPair<WriteFDivZ, [ICXPort0,ICXPort5,ICXFPDivider], 18, [2,1,10], 3, 7>; // 10-14 cycles. 292defm : ICXWriteResPair<WriteFDiv64, [ICXPort0,ICXFPDivider], 14, [1,4], 1, 5>; // 10-14 cycles. // Floating point division. 293defm : ICXWriteResPair<WriteFDiv64X, [ICXPort0,ICXFPDivider], 14, [1,4], 1, 6>; // 10-14 cycles. 294defm : ICXWriteResPair<WriteFDiv64Y, [ICXPort0,ICXFPDivider], 14, [1,8], 1, 7>; // 10-14 cycles. 295defm : ICXWriteResPair<WriteFDiv64Z, [ICXPort0,ICXPort5,ICXFPDivider], 23, [2,1,16], 3, 7>; // 10-14 cycles. 296 297defm : ICXWriteResPair<WriteFSqrt, [ICXPort0,ICXFPDivider], 12, [1,3], 1, 5>; // Floating point square root. 298defm : ICXWriteResPair<WriteFSqrtX, [ICXPort0,ICXFPDivider], 12, [1,3], 1, 6>; 299defm : ICXWriteResPair<WriteFSqrtY, [ICXPort0,ICXFPDivider], 12, [1,6], 1, 7>; 300defm : ICXWriteResPair<WriteFSqrtZ, [ICXPort0,ICXPort5,ICXFPDivider], 20, [2,1,12], 3, 7>; 301defm : ICXWriteResPair<WriteFSqrt64, [ICXPort0,ICXFPDivider], 18, [1,6], 1, 5>; // Floating point double square root. 302defm : ICXWriteResPair<WriteFSqrt64X, [ICXPort0,ICXFPDivider], 18, [1,6], 1, 6>; 303defm : ICXWriteResPair<WriteFSqrt64Y, [ICXPort0,ICXFPDivider], 18, [1,12],1, 7>; 304defm : ICXWriteResPair<WriteFSqrt64Z, [ICXPort0,ICXPort5,ICXFPDivider], 32, [2,1,24], 3, 7>; 305defm : ICXWriteResPair<WriteFSqrt80, [ICXPort0,ICXFPDivider], 21, [1,7]>; // Floating point long double square root. 306 307defm : ICXWriteResPair<WriteFRcp, [ICXPort0], 4, [1], 1, 5>; // Floating point reciprocal estimate. 308defm : ICXWriteResPair<WriteFRcpX, [ICXPort0], 4, [1], 1, 6>; 309defm : ICXWriteResPair<WriteFRcpY, [ICXPort0], 4, [1], 1, 7>; 310defm : ICXWriteResPair<WriteFRcpZ, [ICXPort0,ICXPort5], 4, [2,1], 3, 7>; 311 312defm : ICXWriteResPair<WriteFRsqrt, [ICXPort0], 4, [1], 1, 5>; // Floating point reciprocal square root estimate. 313defm : ICXWriteResPair<WriteFRsqrtX,[ICXPort0], 4, [1], 1, 6>; 314defm : ICXWriteResPair<WriteFRsqrtY,[ICXPort0], 4, [1], 1, 7>; 315defm : ICXWriteResPair<WriteFRsqrtZ,[ICXPort0,ICXPort5], 9, [2,1], 3, 7>; 316 317defm : ICXWriteResPair<WriteFMA, [ICXPort01], 4, [1], 1, 5>; // Fused Multiply Add. 318defm : ICXWriteResPair<WriteFMAX, [ICXPort01], 4, [1], 1, 6>; 319defm : ICXWriteResPair<WriteFMAY, [ICXPort01], 4, [1], 1, 7>; 320defm : ICXWriteResPair<WriteFMAZ, [ICXPort05], 4, [1], 1, 7>; 321defm : ICXWriteResPair<WriteDPPD, [ICXPort5,ICXPort015], 9, [1,2], 3, 6>; // Floating point double dot product. 322defm : ICXWriteResPair<WriteDPPS, [ICXPort5,ICXPort015], 13, [1,3], 4, 6>; 323defm : ICXWriteResPair<WriteDPPSY,[ICXPort5,ICXPort015], 13, [1,3], 4, 7>; 324defm : ICXWriteResPair<WriteFSign, [ICXPort0], 1>; // Floating point fabs/fchs. 325defm : ICXWriteResPair<WriteFRnd, [ICXPort01], 8, [2], 2, 6>; // Floating point rounding. 326defm : ICXWriteResPair<WriteFRndY, [ICXPort01], 8, [2], 2, 7>; 327defm : ICXWriteResPair<WriteFRndZ, [ICXPort05], 8, [2], 2, 7>; 328defm : ICXWriteResPair<WriteFLogic, [ICXPort015], 1, [1], 1, 6>; // Floating point and/or/xor logicals. 329defm : ICXWriteResPair<WriteFLogicY, [ICXPort015], 1, [1], 1, 7>; 330defm : ICXWriteResPair<WriteFLogicZ, [ICXPort05], 1, [1], 1, 7>; 331defm : ICXWriteResPair<WriteFTest, [ICXPort0], 2, [1], 1, 6>; // Floating point TEST instructions. 332defm : ICXWriteResPair<WriteFTestY, [ICXPort0], 2, [1], 1, 7>; 333defm : ICXWriteResPair<WriteFTestZ, [ICXPort0], 2, [1], 1, 7>; 334defm : ICXWriteResPair<WriteFShuffle, [ICXPort15], 1, [1], 1, 6>; // Floating point vector shuffles. 335defm : ICXWriteResPair<WriteFShuffleY, [ICXPort15], 1, [1], 1, 7>; 336defm : ICXWriteResPair<WriteFShuffleZ, [ICXPort5], 1, [1], 1, 7>; 337defm : ICXWriteResPair<WriteFVarShuffle, [ICXPort15], 1, [1], 1, 6>; // Floating point vector variable shuffles. 338defm : ICXWriteResPair<WriteFVarShuffleY, [ICXPort15], 1, [1], 1, 7>; 339defm : ICXWriteResPair<WriteFVarShuffleZ, [ICXPort5], 1, [1], 1, 7>; 340defm : ICXWriteResPair<WriteFBlend, [ICXPort015], 1, [1], 1, 6>; // Floating point vector blends. 341defm : ICXWriteResPair<WriteFBlendY,[ICXPort015], 1, [1], 1, 7>; 342defm : ICXWriteResPair<WriteFBlendZ,[ICXPort015], 1, [1], 1, 7>; 343defm : ICXWriteResPair<WriteFVarBlend, [ICXPort015], 2, [2], 2, 6>; // Fp vector variable blends. 344defm : ICXWriteResPair<WriteFVarBlendY,[ICXPort015], 2, [2], 2, 7>; 345defm : ICXWriteResPair<WriteFVarBlendZ,[ICXPort015], 2, [2], 2, 7>; 346 347// FMA Scheduling helper class. 348// class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; } 349 350// Vector integer operations. 351defm : X86WriteRes<WriteVecLoad, [ICXPort23], 5, [1], 1>; 352defm : X86WriteRes<WriteVecLoadX, [ICXPort23], 6, [1], 1>; 353defm : X86WriteRes<WriteVecLoadY, [ICXPort23], 7, [1], 1>; 354defm : X86WriteRes<WriteVecLoadNT, [ICXPort23], 6, [1], 1>; 355defm : X86WriteRes<WriteVecLoadNTY, [ICXPort23], 7, [1], 1>; 356defm : X86WriteRes<WriteVecMaskedLoad, [ICXPort23,ICXPort015], 7, [1,1], 2>; 357defm : X86WriteRes<WriteVecMaskedLoadY, [ICXPort23,ICXPort015], 8, [1,1], 2>; 358defm : X86WriteRes<WriteVecStore, [ICXPort237,ICXPort4], 1, [1,1], 2>; 359defm : X86WriteRes<WriteVecStoreX, [ICXPort237,ICXPort4], 1, [1,1], 2>; 360defm : X86WriteRes<WriteVecStoreY, [ICXPort237,ICXPort4], 1, [1,1], 2>; 361defm : X86WriteRes<WriteVecStoreNT, [ICXPort237,ICXPort4], 1, [1,1], 2>; 362defm : X86WriteRes<WriteVecStoreNTY, [ICXPort237,ICXPort4], 1, [1,1], 2>; 363defm : X86WriteRes<WriteVecMaskedStore32, [ICXPort237,ICXPort0], 2, [1,1], 2>; 364defm : X86WriteRes<WriteVecMaskedStore32Y, [ICXPort237,ICXPort0], 2, [1,1], 2>; 365defm : X86WriteRes<WriteVecMaskedStore64, [ICXPort237,ICXPort0], 2, [1,1], 2>; 366defm : X86WriteRes<WriteVecMaskedStore64Y, [ICXPort237,ICXPort0], 2, [1,1], 2>; 367defm : X86WriteRes<WriteVecMove, [ICXPort05], 1, [1], 1>; 368defm : X86WriteRes<WriteVecMoveX, [ICXPort015], 1, [1], 1>; 369defm : X86WriteRes<WriteVecMoveY, [ICXPort015], 1, [1], 1>; 370defm : X86WriteRes<WriteVecMoveZ, [ICXPort05], 1, [1], 1>; 371defm : X86WriteRes<WriteVecMoveToGpr, [ICXPort0], 2, [1], 1>; 372defm : X86WriteRes<WriteVecMoveFromGpr, [ICXPort5], 1, [1], 1>; 373 374defm : ICXWriteResPair<WriteVecALU, [ICXPort05], 1, [1], 1, 5>; // Vector integer ALU op, no logicals. 375defm : ICXWriteResPair<WriteVecALUX, [ICXPort01], 1, [1], 1, 6>; 376defm : ICXWriteResPair<WriteVecALUY, [ICXPort01], 1, [1], 1, 7>; 377defm : ICXWriteResPair<WriteVecALUZ, [ICXPort0], 1, [1], 1, 7>; 378defm : ICXWriteResPair<WriteVecLogic, [ICXPort05], 1, [1], 1, 5>; // Vector integer and/or/xor. 379defm : ICXWriteResPair<WriteVecLogicX,[ICXPort015], 1, [1], 1, 6>; 380defm : ICXWriteResPair<WriteVecLogicY,[ICXPort015], 1, [1], 1, 7>; 381defm : ICXWriteResPair<WriteVecLogicZ,[ICXPort05], 1, [1], 1, 7>; 382defm : ICXWriteResPair<WriteVecTest, [ICXPort0,ICXPort5], 3, [1,1], 2, 6>; // Vector integer TEST instructions. 383defm : ICXWriteResPair<WriteVecTestY, [ICXPort0,ICXPort5], 3, [1,1], 2, 7>; 384defm : ICXWriteResPair<WriteVecTestZ, [ICXPort0,ICXPort5], 3, [1,1], 2, 7>; 385defm : ICXWriteResPair<WriteVecIMul, [ICXPort0], 5, [1], 1, 5>; // Vector integer multiply. 386defm : ICXWriteResPair<WriteVecIMulX, [ICXPort01], 5, [1], 1, 6>; 387defm : ICXWriteResPair<WriteVecIMulY, [ICXPort01], 5, [1], 1, 7>; 388defm : ICXWriteResPair<WriteVecIMulZ, [ICXPort05], 5, [1], 1, 7>; 389defm : ICXWriteResPair<WritePMULLD, [ICXPort01], 10, [2], 2, 6>; // Vector PMULLD. 390defm : ICXWriteResPair<WritePMULLDY, [ICXPort01], 10, [2], 2, 7>; 391defm : ICXWriteResPair<WritePMULLDZ, [ICXPort05], 10, [2], 2, 7>; 392defm : ICXWriteResPair<WriteShuffle, [ICXPort5], 1, [1], 1, 5>; // Vector shuffles. 393defm : ICXWriteResPair<WriteShuffleX, [ICXPort15], 1, [1], 1, 6>; 394defm : ICXWriteResPair<WriteShuffleY, [ICXPort15], 1, [1], 1, 7>; 395defm : ICXWriteResPair<WriteShuffleZ, [ICXPort5], 1, [1], 1, 7>; 396defm : ICXWriteResPair<WriteVarShuffle, [ICXPort5], 1, [1], 1, 5>; // Vector variable shuffles. 397defm : ICXWriteResPair<WriteVarShuffleX, [ICXPort15], 1, [1], 1, 6>; 398defm : ICXWriteResPair<WriteVarShuffleY, [ICXPort15], 1, [1], 1, 7>; 399defm : ICXWriteResPair<WriteVarShuffleZ, [ICXPort5], 1, [1], 1, 7>; 400defm : ICXWriteResPair<WriteBlend, [ICXPort5], 1, [1], 1, 6>; // Vector blends. 401defm : ICXWriteResPair<WriteBlendY,[ICXPort5], 1, [1], 1, 7>; 402defm : ICXWriteResPair<WriteBlendZ,[ICXPort5], 1, [1], 1, 7>; 403defm : ICXWriteResPair<WriteVarBlend, [ICXPort015], 2, [2], 2, 6>; // Vector variable blends. 404defm : ICXWriteResPair<WriteVarBlendY,[ICXPort015], 2, [2], 2, 6>; 405defm : ICXWriteResPair<WriteVarBlendZ,[ICXPort05], 2, [1], 1, 6>; 406defm : ICXWriteResPair<WriteMPSAD, [ICXPort5], 4, [2], 2, 6>; // Vector MPSAD. 407defm : ICXWriteResPair<WriteMPSADY, [ICXPort5], 4, [2], 2, 7>; 408defm : ICXWriteResPair<WriteMPSADZ, [ICXPort5], 4, [2], 2, 7>; 409defm : ICXWriteResPair<WritePSADBW, [ICXPort5], 3, [1], 1, 5>; // Vector PSADBW. 410defm : ICXWriteResPair<WritePSADBWX, [ICXPort5], 3, [1], 1, 6>; 411defm : ICXWriteResPair<WritePSADBWY, [ICXPort5], 3, [1], 1, 7>; 412defm : ICXWriteResPair<WritePSADBWZ, [ICXPort5], 3, [1], 1, 7>; // TODO: 512-bit ops require ports 0/1 to be joined. 413defm : ICXWriteResPair<WritePHMINPOS, [ICXPort0], 4, [1], 1, 6>; // Vector PHMINPOS. 414 415// Vector integer shifts. 416defm : ICXWriteResPair<WriteVecShift, [ICXPort0], 1, [1], 1, 5>; 417defm : X86WriteRes<WriteVecShiftX, [ICXPort5,ICXPort01], 2, [1,1], 2>; 418defm : X86WriteRes<WriteVecShiftY, [ICXPort5,ICXPort01], 4, [1,1], 2>; 419defm : X86WriteRes<WriteVecShiftZ, [ICXPort5,ICXPort0], 4, [1,1], 2>; 420defm : X86WriteRes<WriteVecShiftXLd, [ICXPort01,ICXPort23], 7, [1,1], 2>; 421defm : X86WriteRes<WriteVecShiftYLd, [ICXPort01,ICXPort23], 8, [1,1], 2>; 422defm : X86WriteRes<WriteVecShiftZLd, [ICXPort0,ICXPort23], 8, [1,1], 2>; 423 424defm : ICXWriteResPair<WriteVecShiftImm, [ICXPort0], 1, [1], 1, 5>; 425defm : ICXWriteResPair<WriteVecShiftImmX, [ICXPort01], 1, [1], 1, 6>; // Vector integer immediate shifts. 426defm : ICXWriteResPair<WriteVecShiftImmY, [ICXPort01], 1, [1], 1, 7>; 427defm : ICXWriteResPair<WriteVecShiftImmZ, [ICXPort0], 1, [1], 1, 7>; 428defm : ICXWriteResPair<WriteVarVecShift, [ICXPort01], 1, [1], 1, 6>; // Variable vector shifts. 429defm : ICXWriteResPair<WriteVarVecShiftY, [ICXPort01], 1, [1], 1, 7>; 430defm : ICXWriteResPair<WriteVarVecShiftZ, [ICXPort0], 1, [1], 1, 7>; 431 432// Vector insert/extract operations. 433def : WriteRes<WriteVecInsert, [ICXPort5]> { 434 let Latency = 2; 435 let NumMicroOps = 2; 436 let ResourceCycles = [2]; 437} 438def : WriteRes<WriteVecInsertLd, [ICXPort5,ICXPort23]> { 439 let Latency = 6; 440 let NumMicroOps = 2; 441} 442def: InstRW<[WriteVecInsertLd], (instregex "(V?)MOV(H|L)(PD|PS)rm")>; 443 444def : WriteRes<WriteVecExtract, [ICXPort0,ICXPort5]> { 445 let Latency = 3; 446 let NumMicroOps = 2; 447} 448def : WriteRes<WriteVecExtractSt, [ICXPort4,ICXPort5,ICXPort237]> { 449 let Latency = 2; 450 let NumMicroOps = 3; 451} 452 453// Conversion between integer and float. 454defm : ICXWriteResPair<WriteCvtSS2I, [ICXPort01], 6, [2], 2>; // Needs more work: DD vs DQ. 455defm : ICXWriteResPair<WriteCvtPS2I, [ICXPort01], 3>; 456defm : ICXWriteResPair<WriteCvtPS2IY, [ICXPort01], 3>; 457defm : ICXWriteResPair<WriteCvtPS2IZ, [ICXPort05], 3>; 458defm : ICXWriteResPair<WriteCvtSD2I, [ICXPort01], 6, [2], 2>; 459defm : ICXWriteResPair<WriteCvtPD2I, [ICXPort01], 3>; 460defm : ICXWriteResPair<WriteCvtPD2IY, [ICXPort01], 3>; 461defm : ICXWriteResPair<WriteCvtPD2IZ, [ICXPort05], 3>; 462 463defm : ICXWriteResPair<WriteCvtI2SS, [ICXPort1], 4>; 464defm : ICXWriteResPair<WriteCvtI2PS, [ICXPort01], 4>; 465defm : ICXWriteResPair<WriteCvtI2PSY, [ICXPort01], 4>; 466defm : ICXWriteResPair<WriteCvtI2PSZ, [ICXPort05], 4>; // Needs more work: DD vs DQ. 467defm : ICXWriteResPair<WriteCvtI2SD, [ICXPort1], 4>; 468defm : ICXWriteResPair<WriteCvtI2PD, [ICXPort01], 4>; 469defm : ICXWriteResPair<WriteCvtI2PDY, [ICXPort01], 4>; 470defm : ICXWriteResPair<WriteCvtI2PDZ, [ICXPort05], 4>; 471 472defm : ICXWriteResPair<WriteCvtSS2SD, [ICXPort1], 3>; 473defm : ICXWriteResPair<WriteCvtPS2PD, [ICXPort1], 3>; 474defm : ICXWriteResPair<WriteCvtPS2PDY, [ICXPort5,ICXPort01], 3, [1,1], 2>; 475defm : ICXWriteResPair<WriteCvtPS2PDZ, [ICXPort05], 3, [2], 2>; 476defm : ICXWriteResPair<WriteCvtSD2SS, [ICXPort5,ICXPort01], 5, [1,1], 2, 5>; 477defm : ICXWriteResPair<WriteCvtPD2PS, [ICXPort5,ICXPort01], 5, [1,1], 2, 6>; 478defm : ICXWriteResPair<WriteCvtPD2PSY, [ICXPort5,ICXPort01], 7, [1,1], 2, 7>; 479defm : ICXWriteResPair<WriteCvtPD2PSZ, [ICXPort5,ICXPort0], 7, [1,1], 2, 7>; 480 481defm : X86WriteRes<WriteCvtPH2PS, [ICXPort5,ICXPort01], 5, [1,1], 2>; 482defm : X86WriteRes<WriteCvtPH2PSY, [ICXPort5,ICXPort01], 7, [1,1], 2>; 483defm : X86WriteRes<WriteCvtPH2PSZ, [ICXPort5,ICXPort0], 7, [1,1], 2>; 484defm : X86WriteRes<WriteCvtPH2PSLd, [ICXPort23,ICXPort01], 9, [1,1], 2>; 485defm : X86WriteRes<WriteCvtPH2PSYLd, [ICXPort23,ICXPort01], 10, [1,1], 2>; 486defm : X86WriteRes<WriteCvtPH2PSZLd, [ICXPort23,ICXPort05], 10, [1,1], 2>; 487 488defm : X86WriteRes<WriteCvtPS2PH, [ICXPort5,ICXPort01], 5, [1,1], 2>; 489defm : X86WriteRes<WriteCvtPS2PHY, [ICXPort5,ICXPort01], 7, [1,1], 2>; 490defm : X86WriteRes<WriteCvtPS2PHZ, [ICXPort5,ICXPort05], 7, [1,1], 2>; 491defm : X86WriteRes<WriteCvtPS2PHSt, [ICXPort4,ICXPort5,ICXPort237,ICXPort01], 6, [1,1,1,1], 4>; 492defm : X86WriteRes<WriteCvtPS2PHYSt, [ICXPort4,ICXPort5,ICXPort237,ICXPort01], 8, [1,1,1,1], 4>; 493defm : X86WriteRes<WriteCvtPS2PHZSt, [ICXPort4,ICXPort5,ICXPort237,ICXPort05], 8, [1,1,1,1], 4>; 494 495// Strings instructions. 496 497// Packed Compare Implicit Length Strings, Return Mask 498def : WriteRes<WritePCmpIStrM, [ICXPort0]> { 499 let Latency = 10; 500 let NumMicroOps = 3; 501 let ResourceCycles = [3]; 502} 503def : WriteRes<WritePCmpIStrMLd, [ICXPort0, ICXPort23]> { 504 let Latency = 16; 505 let NumMicroOps = 4; 506 let ResourceCycles = [3,1]; 507} 508 509// Packed Compare Explicit Length Strings, Return Mask 510def : WriteRes<WritePCmpEStrM, [ICXPort0, ICXPort5, ICXPort015, ICXPort0156]> { 511 let Latency = 19; 512 let NumMicroOps = 9; 513 let ResourceCycles = [4,3,1,1]; 514} 515def : WriteRes<WritePCmpEStrMLd, [ICXPort0, ICXPort5, ICXPort23, ICXPort015, ICXPort0156]> { 516 let Latency = 25; 517 let NumMicroOps = 10; 518 let ResourceCycles = [4,3,1,1,1]; 519} 520 521// Packed Compare Implicit Length Strings, Return Index 522def : WriteRes<WritePCmpIStrI, [ICXPort0]> { 523 let Latency = 10; 524 let NumMicroOps = 3; 525 let ResourceCycles = [3]; 526} 527def : WriteRes<WritePCmpIStrILd, [ICXPort0, ICXPort23]> { 528 let Latency = 16; 529 let NumMicroOps = 4; 530 let ResourceCycles = [3,1]; 531} 532 533// Packed Compare Explicit Length Strings, Return Index 534def : WriteRes<WritePCmpEStrI, [ICXPort0,ICXPort5,ICXPort0156]> { 535 let Latency = 18; 536 let NumMicroOps = 8; 537 let ResourceCycles = [4,3,1]; 538} 539def : WriteRes<WritePCmpEStrILd, [ICXPort0, ICXPort5, ICXPort23, ICXPort0156]> { 540 let Latency = 24; 541 let NumMicroOps = 9; 542 let ResourceCycles = [4,3,1,1]; 543} 544 545// MOVMSK Instructions. 546def : WriteRes<WriteFMOVMSK, [ICXPort0]> { let Latency = 2; } 547def : WriteRes<WriteVecMOVMSK, [ICXPort0]> { let Latency = 2; } 548def : WriteRes<WriteVecMOVMSKY, [ICXPort0]> { let Latency = 2; } 549def : WriteRes<WriteMMXMOVMSK, [ICXPort0]> { let Latency = 2; } 550 551// AES instructions. 552def : WriteRes<WriteAESDecEnc, [ICXPort0]> { // Decryption, encryption. 553 let Latency = 4; 554 let NumMicroOps = 1; 555 let ResourceCycles = [1]; 556} 557def : WriteRes<WriteAESDecEncLd, [ICXPort0, ICXPort23]> { 558 let Latency = 10; 559 let NumMicroOps = 2; 560 let ResourceCycles = [1,1]; 561} 562 563def : WriteRes<WriteAESIMC, [ICXPort0]> { // InvMixColumn. 564 let Latency = 8; 565 let NumMicroOps = 2; 566 let ResourceCycles = [2]; 567} 568def : WriteRes<WriteAESIMCLd, [ICXPort0, ICXPort23]> { 569 let Latency = 14; 570 let NumMicroOps = 3; 571 let ResourceCycles = [2,1]; 572} 573 574def : WriteRes<WriteAESKeyGen, [ICXPort0,ICXPort5,ICXPort015]> { // Key Generation. 575 let Latency = 20; 576 let NumMicroOps = 11; 577 let ResourceCycles = [3,6,2]; 578} 579def : WriteRes<WriteAESKeyGenLd, [ICXPort0,ICXPort5,ICXPort23,ICXPort015]> { 580 let Latency = 25; 581 let NumMicroOps = 11; 582 let ResourceCycles = [3,6,1,1]; 583} 584 585// Carry-less multiplication instructions. 586def : WriteRes<WriteCLMul, [ICXPort5]> { 587 let Latency = 6; 588 let NumMicroOps = 1; 589 let ResourceCycles = [1]; 590} 591def : WriteRes<WriteCLMulLd, [ICXPort5, ICXPort23]> { 592 let Latency = 12; 593 let NumMicroOps = 2; 594 let ResourceCycles = [1,1]; 595} 596 597// Catch-all for expensive system instructions. 598def : WriteRes<WriteSystem, [ICXPort0156]> { let Latency = 100; } // def WriteSystem : SchedWrite; 599 600// AVX2. 601defm : ICXWriteResPair<WriteFShuffle256, [ICXPort5], 3, [1], 1, 7>; // Fp 256-bit width vector shuffles. 602defm : ICXWriteResPair<WriteFVarShuffle256, [ICXPort5], 3, [1], 1, 7>; // Fp 256-bit width vector variable shuffles. 603defm : ICXWriteResPair<WriteShuffle256, [ICXPort5], 3, [1], 1, 7>; // 256-bit width vector shuffles. 604defm : ICXWriteResPair<WriteVPMOV256, [ICXPort5], 3, [1], 1, 7>; // 256-bit width packed vector width-changing move. 605defm : ICXWriteResPair<WriteVarShuffle256, [ICXPort5], 3, [1], 1, 7>; // 256-bit width vector variable shuffles. 606 607// Old microcoded instructions that nobody use. 608def : WriteRes<WriteMicrocoded, [ICXPort0156]> { let Latency = 100; } // def WriteMicrocoded : SchedWrite; 609 610// Fence instructions. 611def : WriteRes<WriteFence, [ICXPort23, ICXPort4]>; 612 613// Load/store MXCSR. 614def : WriteRes<WriteLDMXCSR, [ICXPort0,ICXPort23,ICXPort0156]> { let Latency = 7; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } 615def : WriteRes<WriteSTMXCSR, [ICXPort4,ICXPort5,ICXPort237]> { let Latency = 2; let NumMicroOps = 3; let ResourceCycles = [1,1,1]; } 616 617// Nop, not very useful expect it provides a model for nops! 618def : WriteRes<WriteNop, []>; 619 620//////////////////////////////////////////////////////////////////////////////// 621// Horizontal add/sub instructions. 622//////////////////////////////////////////////////////////////////////////////// 623 624defm : ICXWriteResPair<WriteFHAdd, [ICXPort5,ICXPort015], 6, [2,1], 3, 6>; 625defm : ICXWriteResPair<WriteFHAddY, [ICXPort5,ICXPort015], 6, [2,1], 3, 7>; 626defm : ICXWriteResPair<WritePHAdd, [ICXPort5,ICXPort05], 3, [2,1], 3, 5>; 627defm : ICXWriteResPair<WritePHAddX, [ICXPort5,ICXPort015], 3, [2,1], 3, 6>; 628defm : ICXWriteResPair<WritePHAddY, [ICXPort5,ICXPort015], 3, [2,1], 3, 7>; 629 630// Remaining instrs. 631 632def ICXWriteResGroup1 : SchedWriteRes<[ICXPort0]> { 633 let Latency = 1; 634 let NumMicroOps = 1; 635 let ResourceCycles = [1]; 636} 637def: InstRW<[ICXWriteResGroup1], (instregex "KAND(B|D|Q|W)rr", 638 "KANDN(B|D|Q|W)rr", 639 "KMOV(B|D|Q|W)kk", 640 "KNOT(B|D|Q|W)rr", 641 "KOR(B|D|Q|W)rr", 642 "KXNOR(B|D|Q|W)rr", 643 "KXOR(B|D|Q|W)rr", 644 "KSET0(B|D|Q|W)", // Same as KXOR 645 "KSET1(B|D|Q|W)", // Same as KXNOR 646 "MMX_PADDS(B|W)rr", 647 "MMX_PADDUS(B|W)rr", 648 "MMX_PAVG(B|W)rr", 649 "MMX_PCMPEQ(B|D|W)rr", 650 "MMX_PCMPGT(B|D|W)rr", 651 "MMX_P(MAX|MIN)SWrr", 652 "MMX_P(MAX|MIN)UBrr", 653 "MMX_PSUBS(B|W)rr", 654 "MMX_PSUBUS(B|W)rr", 655 "VPMOVB2M(Z|Z128|Z256)rr", 656 "VPMOVD2M(Z|Z128|Z256)rr", 657 "VPMOVQ2M(Z|Z128|Z256)rr", 658 "VPMOVW2M(Z|Z128|Z256)rr")>; 659 660def ICXWriteResGroup3 : SchedWriteRes<[ICXPort5]> { 661 let Latency = 1; 662 let NumMicroOps = 1; 663 let ResourceCycles = [1]; 664} 665def: InstRW<[ICXWriteResGroup3], (instregex "COM(P?)_FST0r", 666 "KMOV(B|D|Q|W)kr", 667 "UCOM_F(P?)r", 668 "VPBROADCAST(D|Q)rr", 669 "(V?)INSERTPS(Z?)rr", 670 "(V?)MOV(HL|LH)PS(Z?)rr", 671 "(V?)MOVDDUP(Y|Z128|Z256)?rr", 672 "(V?)PALIGNR(Y|Z128|Z256)?rri", 673 "(V?)PERMIL(PD|PS)(Y|Z128|Z256)?ri", 674 "(V?)PERMIL(PD|PS)(Y|Z128|Z256)?rr", 675 "(V?)UNPCK(L|H)(PD|PS)(Y|Z128|Z256)?rr")>; 676 677def ICXWriteResGroup4 : SchedWriteRes<[ICXPort6]> { 678 let Latency = 1; 679 let NumMicroOps = 1; 680 let ResourceCycles = [1]; 681} 682def: InstRW<[ICXWriteResGroup4], (instregex "JMP(16|32|64)r")>; 683 684def ICXWriteResGroup6 : SchedWriteRes<[ICXPort05]> { 685 let Latency = 1; 686 let NumMicroOps = 1; 687 let ResourceCycles = [1]; 688} 689def: InstRW<[ICXWriteResGroup6], (instrs FINCSTP, FNOP)>; 690 691def ICXWriteResGroup7 : SchedWriteRes<[ICXPort06]> { 692 let Latency = 1; 693 let NumMicroOps = 1; 694 let ResourceCycles = [1]; 695} 696def: InstRW<[ICXWriteResGroup7], (instrs CDQ, CQO, CLAC, STAC)>; 697 698def ICXWriteResGroup8 : SchedWriteRes<[ICXPort15]> { 699 let Latency = 1; 700 let NumMicroOps = 1; 701 let ResourceCycles = [1]; 702} 703def: InstRW<[ICXWriteResGroup8], (instregex "ANDN(32|64)rr")>; 704 705def ICXWriteResGroup9 : SchedWriteRes<[ICXPort015]> { 706 let Latency = 1; 707 let NumMicroOps = 1; 708 let ResourceCycles = [1]; 709} 710def: InstRW<[ICXWriteResGroup9], (instregex "VBLENDMPD(Z128|Z256)rr", 711 "VBLENDMPS(Z128|Z256)rr", 712 "VPADD(B|D|Q|W)(Y|Z|Z128|Z256)rr", 713 "(V?)PADD(B|D|Q|W)rr", 714 "(V?)MOV(SD|SS)(Z?)rr", 715 "VPBLENDD(Y?)rri", 716 "VPBLENDMB(Z128|Z256)rr", 717 "VPBLENDMD(Z128|Z256)rr", 718 "VPBLENDMQ(Z128|Z256)rr", 719 "VPBLENDMW(Z128|Z256)rr", 720 "VPSUB(B|D|Q|W)(Y|Z|Z128|Z256)rrk", 721 "VPTERNLOGD(Z|Z128|Z256)rri", 722 "VPTERNLOGQ(Z|Z128|Z256)rri")>; 723 724def ICXWriteResGroup10 : SchedWriteRes<[ICXPort0156]> { 725 let Latency = 1; 726 let NumMicroOps = 1; 727 let ResourceCycles = [1]; 728} 729def: InstRW<[ICXWriteResGroup10], (instrs SGDT64m, 730 SIDT64m, 731 SMSW16m, 732 STRm, 733 SYSCALL)>; 734 735def ICXWriteResGroup11 : SchedWriteRes<[ICXPort4,ICXPort237]> { 736 let Latency = 1; 737 let NumMicroOps = 2; 738 let ResourceCycles = [1,1]; 739} 740def: InstRW<[ICXWriteResGroup11], (instrs FBSTPm, VMPTRSTm)>; 741def: InstRW<[ICXWriteResGroup11], (instregex "KMOV(B|D|Q|W)mk", 742 "ST_FP(32|64|80)m")>; 743 744def ICXWriteResGroup13 : SchedWriteRes<[ICXPort5]> { 745 let Latency = 2; 746 let NumMicroOps = 2; 747 let ResourceCycles = [2]; 748} 749def: InstRW<[ICXWriteResGroup13], (instrs MMX_MOVQ2DQrr)>; 750 751def ICXWriteResGroup14 : SchedWriteRes<[ICXPort05]> { 752 let Latency = 2; 753 let NumMicroOps = 2; 754 let ResourceCycles = [2]; 755} 756def: InstRW<[ICXWriteResGroup14], (instrs FDECSTP, 757 MMX_MOVDQ2Qrr)>; 758 759def ICXWriteResGroup17 : SchedWriteRes<[ICXPort0156]> { 760 let Latency = 2; 761 let NumMicroOps = 2; 762 let ResourceCycles = [2]; 763} 764def: InstRW<[ICXWriteResGroup17], (instrs LFENCE, 765 WAIT, 766 XGETBV)>; 767 768def ICXWriteResGroup20 : SchedWriteRes<[ICXPort6,ICXPort0156]> { 769 let Latency = 2; 770 let NumMicroOps = 2; 771 let ResourceCycles = [1,1]; 772} 773def: InstRW<[ICXWriteResGroup20], (instregex "CLFLUSH")>; 774 775def ICXWriteResGroup21 : SchedWriteRes<[ICXPort237,ICXPort0156]> { 776 let Latency = 2; 777 let NumMicroOps = 2; 778 let ResourceCycles = [1,1]; 779} 780def: InstRW<[ICXWriteResGroup21], (instrs SFENCE)>; 781 782def ICXWriteResGroup23 : SchedWriteRes<[ICXPort06,ICXPort0156]> { 783 let Latency = 2; 784 let NumMicroOps = 2; 785 let ResourceCycles = [1,1]; 786} 787def: InstRW<[ICXWriteResGroup23], (instrs CWD, 788 JCXZ, JECXZ, JRCXZ, 789 ADC8i8, SBB8i8, 790 ADC16i16, SBB16i16, 791 ADC32i32, SBB32i32, 792 ADC64i32, SBB64i32)>; 793 794def ICXWriteResGroup25 : SchedWriteRes<[ICXPort4,ICXPort6,ICXPort237]> { 795 let Latency = 2; 796 let NumMicroOps = 3; 797 let ResourceCycles = [1,1,1]; 798} 799def: InstRW<[ICXWriteResGroup25], (instrs FNSTCW16m)>; 800 801def ICXWriteResGroup27 : SchedWriteRes<[ICXPort4,ICXPort237,ICXPort15]> { 802 let Latency = 2; 803 let NumMicroOps = 3; 804 let ResourceCycles = [1,1,1]; 805} 806def: InstRW<[ICXWriteResGroup27], (instregex "MOVBE(16|32|64)mr")>; 807 808def ICXWriteResGroup28 : SchedWriteRes<[ICXPort4,ICXPort237,ICXPort0156]> { 809 let Latency = 2; 810 let NumMicroOps = 3; 811 let ResourceCycles = [1,1,1]; 812} 813def: InstRW<[ICXWriteResGroup28], (instrs PUSH16r, PUSH32r, PUSH64r, PUSH64i8, 814 STOSB, STOSL, STOSQ, STOSW)>; 815def: InstRW<[ICXWriteResGroup28], (instregex "PUSH(16|32|64)rmr")>; 816 817def ICXWriteResGroup29 : SchedWriteRes<[ICXPort4,ICXPort237,ICXPort15]> { 818 let Latency = 2; 819 let NumMicroOps = 5; 820 let ResourceCycles = [2,2,1]; 821} 822def: InstRW<[ICXWriteResGroup29], (instregex "VMOVDQU8Zmr(b?)")>; 823 824def ICXWriteResGroup30 : SchedWriteRes<[ICXPort0]> { 825 let Latency = 3; 826 let NumMicroOps = 1; 827 let ResourceCycles = [1]; 828} 829def: InstRW<[ICXWriteResGroup30], (instregex "KMOV(B|D|Q|W)rk", 830 "KORTEST(B|D|Q|W)rr", 831 "KTEST(B|D|Q|W)rr")>; 832 833def ICXWriteResGroup31 : SchedWriteRes<[ICXPort1]> { 834 let Latency = 3; 835 let NumMicroOps = 1; 836 let ResourceCycles = [1]; 837} 838def: InstRW<[ICXWriteResGroup31], (instregex "PDEP(32|64)rr", 839 "PEXT(32|64)rr")>; 840 841def ICXWriteResGroup32 : SchedWriteRes<[ICXPort5]> { 842 let Latency = 3; 843 let NumMicroOps = 1; 844 let ResourceCycles = [1]; 845} 846def: InstRW<[ICXWriteResGroup32], (instregex "(ADD|SUB|SUBR)_(FPrST0|FST0r|FrST0)", 847 "VALIGND(Z|Z128|Z256)rri", 848 "VALIGNQ(Z|Z128|Z256)rri", 849 "VPBROADCAST(B|W)rr", 850 "(V?)PACK(U|S)S(DW|WB)(Y|Z|Z128|Z256)?rr", 851 "VP(MAX|MIN)(S|U)Q(Z|Z128|Z256)rr")>; 852 853def ICXWriteResGroup33 : SchedWriteRes<[ICXPort5]> { 854 let Latency = 4; 855 let NumMicroOps = 1; 856 let ResourceCycles = [1]; 857} 858def: InstRW<[ICXWriteResGroup33], (instregex "KADD(B|D|Q|W)rr", 859 "KSHIFTL(B|D|Q|W)ri", 860 "KSHIFTR(B|D|Q|W)ri", 861 "KUNPCK(BW|DQ|WD)rr", 862 "VCMPPD(Z|Z128|Z256)rri", 863 "VCMPPS(Z|Z128|Z256)rri", 864 "VCMP(SD|SS)Zrr", 865 "VFPCLASS(PD|PS)(Z|Z128|Z256)rr", 866 "VFPCLASS(SD|SS)Zrr", 867 "VPCMPB(Z|Z128|Z256)rri", 868 "VPCMPD(Z|Z128|Z256)rri", 869 "VPCMPEQ(B|D|Q|W)(Z|Z128|Z256)rr", 870 "VPCMPGT(B|D|Q|W)(Z|Z128|Z256)rr", 871 "VPCMPQ(Z|Z128|Z256)rri", 872 "VPCMPU(B|D|Q|W)(Z|Z128|Z256)rri", 873 "VPCMPW(Z|Z128|Z256)rri", 874 "VPTEST(N?)M(B|D|Q|W)(Z|Z128|Z256)rr")>; 875 876def ICXWriteResGroup34 : SchedWriteRes<[ICXPort0,ICXPort0156]> { 877 let Latency = 3; 878 let NumMicroOps = 2; 879 let ResourceCycles = [1,1]; 880} 881def: InstRW<[ICXWriteResGroup34], (instrs FNSTSW16r)>; 882 883def ICXWriteResGroup37 : SchedWriteRes<[ICXPort0,ICXPort5]> { 884 let Latency = 3; 885 let NumMicroOps = 3; 886 let ResourceCycles = [1,2]; 887} 888def: InstRW<[ICXWriteResGroup37], (instregex "MMX_PH(ADD|SUB)SWrr")>; 889 890def ICXWriteResGroup38 : SchedWriteRes<[ICXPort5,ICXPort01]> { 891 let Latency = 3; 892 let NumMicroOps = 3; 893 let ResourceCycles = [2,1]; 894} 895def: InstRW<[ICXWriteResGroup38], (instregex "(V?)PH(ADD|SUB)SW(Y?)rr")>; 896 897def ICXWriteResGroup41 : SchedWriteRes<[ICXPort5,ICXPort0156]> { 898 let Latency = 3; 899 let NumMicroOps = 3; 900 let ResourceCycles = [2,1]; 901} 902def: InstRW<[ICXWriteResGroup41], (instrs MMX_PACKSSDWrr, 903 MMX_PACKSSWBrr, 904 MMX_PACKUSWBrr)>; 905 906def ICXWriteResGroup42 : SchedWriteRes<[ICXPort6,ICXPort0156]> { 907 let Latency = 3; 908 let NumMicroOps = 3; 909 let ResourceCycles = [1,2]; 910} 911def: InstRW<[ICXWriteResGroup42], (instregex "CLD")>; 912 913def ICXWriteResGroup43 : SchedWriteRes<[ICXPort237,ICXPort0156]> { 914 let Latency = 3; 915 let NumMicroOps = 3; 916 let ResourceCycles = [1,2]; 917} 918def: InstRW<[ICXWriteResGroup43], (instrs MFENCE)>; 919 920def ICXWriteResGroup44 : SchedWriteRes<[ICXPort06,ICXPort0156]> { 921 let Latency = 2; 922 let NumMicroOps = 3; 923 let ResourceCycles = [1,2]; 924} 925def: InstRW<[ICXWriteResGroup44], (instrs RCL8r1, RCL16r1, RCL32r1, RCL64r1, 926 RCR8r1, RCR16r1, RCR32r1, RCR64r1)>; 927 928def ICXWriteResGroup44b : SchedWriteRes<[ICXPort1,ICXPort06,ICXPort0156]> { 929 let Latency = 5; 930 let NumMicroOps = 7; 931 let ResourceCycles = [2,3,2]; 932} 933def: InstRW<[ICXWriteResGroup44b], (instrs RCR8ri, RCR16ri, RCR32ri, RCR64ri)>; 934 935def ICXWriteResGroup44c : SchedWriteRes<[ICXPort1,ICXPort06,ICXPort0156]> { 936 let Latency = 6; 937 let NumMicroOps = 7; 938 let ResourceCycles = [2,3,2]; 939} 940def: InstRW<[ICXWriteResGroup44c], (instrs RCL8ri, RCL16ri, RCL32ri, RCL64ri)>; 941 942def ICXWriteResGroup45 : SchedWriteRes<[ICXPort0,ICXPort4,ICXPort237]> { 943 let Latency = 3; 944 let NumMicroOps = 3; 945 let ResourceCycles = [1,1,1]; 946} 947def: InstRW<[ICXWriteResGroup45], (instrs FNSTSWm)>; 948 949def ICXWriteResGroup47 : SchedWriteRes<[ICXPort4,ICXPort6,ICXPort237,ICXPort0156]> { 950 let Latency = 3; 951 let NumMicroOps = 4; 952 let ResourceCycles = [1,1,1,1]; 953} 954def: InstRW<[ICXWriteResGroup47], (instregex "CALL(16|32|64)r")>; 955 956def ICXWriteResGroup48 : SchedWriteRes<[ICXPort4,ICXPort237,ICXPort06,ICXPort0156]> { 957 let Latency = 3; 958 let NumMicroOps = 4; 959 let ResourceCycles = [1,1,1,1]; 960} 961def: InstRW<[ICXWriteResGroup48], (instrs CALL64pcrel32)>; 962 963def ICXWriteResGroup49 : SchedWriteRes<[ICXPort0]> { 964 let Latency = 4; 965 let NumMicroOps = 1; 966 let ResourceCycles = [1]; 967} 968def: InstRW<[ICXWriteResGroup49], (instregex "MUL_(FPrST0|FST0r|FrST0)")>; 969 970def ICXWriteResGroup50 : SchedWriteRes<[ICXPort01]> { 971 let Latency = 4; 972 let NumMicroOps = 1; 973 let ResourceCycles = [1]; 974} 975def: InstRW<[ICXWriteResGroup50], (instregex "VCVTPD2QQ(Z128|Z256)rr", 976 "VCVTPD2UQQ(Z128|Z256)rr", 977 "VCVTPS2DQ(Y|Z128|Z256)rr", 978 "(V?)CVTPS2DQrr", 979 "VCVTPS2UDQ(Z128|Z256)rr", 980 "VCVTTPD2QQ(Z128|Z256)rr", 981 "VCVTTPD2UQQ(Z128|Z256)rr", 982 "VCVTTPS2DQ(Z128|Z256)rr", 983 "(V?)CVTTPS2DQrr", 984 "VCVTTPS2UDQ(Z128|Z256)rr")>; 985 986def ICXWriteResGroup50z : SchedWriteRes<[ICXPort05]> { 987 let Latency = 4; 988 let NumMicroOps = 1; 989 let ResourceCycles = [1]; 990} 991def: InstRW<[ICXWriteResGroup50z], (instrs VCVTPD2QQZrr, 992 VCVTPD2UQQZrr, 993 VCVTPS2DQZrr, 994 VCVTPS2UDQZrr, 995 VCVTTPD2QQZrr, 996 VCVTTPD2UQQZrr, 997 VCVTTPS2DQZrr, 998 VCVTTPS2UDQZrr)>; 999 1000def ICXWriteResGroup51 : SchedWriteRes<[ICXPort5]> { 1001 let Latency = 4; 1002 let NumMicroOps = 2; 1003 let ResourceCycles = [2]; 1004} 1005def: InstRW<[ICXWriteResGroup51], (instregex "VEXPANDPD(Z|Z128|Z256)rr", 1006 "VEXPANDPS(Z|Z128|Z256)rr", 1007 "VPEXPANDD(Z|Z128|Z256)rr", 1008 "VPEXPANDQ(Z|Z128|Z256)rr", 1009 "VPMOVDB(Z|Z128|Z256)rr", 1010 "VPMOVDW(Z|Z128|Z256)rr", 1011 "VPMOVQB(Z|Z128|Z256)rr", 1012 "VPMOVQW(Z|Z128|Z256)rr", 1013 "VPMOVSDB(Z|Z128|Z256)rr", 1014 "VPMOVSDW(Z|Z128|Z256)rr", 1015 "VPMOVSQB(Z|Z128|Z256)rr", 1016 "VPMOVSQD(Z|Z128|Z256)rr", 1017 "VPMOVSQW(Z|Z128|Z256)rr", 1018 "VPMOVSWB(Z|Z128|Z256)rr", 1019 "VPMOVUSDB(Z|Z128|Z256)rr", 1020 "VPMOVUSDW(Z|Z128|Z256)rr", 1021 "VPMOVUSQB(Z|Z128|Z256)rr", 1022 "VPMOVUSQD(Z|Z128|Z256)rr", 1023 "VPMOVUSWB(Z|Z128|Z256)rr", 1024 "VPMOVWB(Z|Z128|Z256)rr")>; 1025 1026def ICXWriteResGroup54 : SchedWriteRes<[ICXPort4,ICXPort5,ICXPort237]> { 1027 let Latency = 4; 1028 let NumMicroOps = 3; 1029 let ResourceCycles = [1,1,1]; 1030} 1031def: InstRW<[ICXWriteResGroup54], (instregex "IST(T?)_FP(16|32|64)m", 1032 "IST_F(16|32)m", 1033 "VPMOVQD(Z|Z128|Z256)mr(b?)")>; 1034 1035def ICXWriteResGroup55 : SchedWriteRes<[ICXPort0156]> { 1036 let Latency = 4; 1037 let NumMicroOps = 4; 1038 let ResourceCycles = [4]; 1039} 1040def: InstRW<[ICXWriteResGroup55], (instrs FNCLEX)>; 1041 1042def ICXWriteResGroup56 : SchedWriteRes<[]> { 1043 let Latency = 0; 1044 let NumMicroOps = 4; 1045 let ResourceCycles = []; 1046} 1047def: InstRW<[ICXWriteResGroup56], (instrs VZEROUPPER)>; 1048 1049def ICXWriteResGroup57 : SchedWriteRes<[ICXPort1,ICXPort6,ICXPort0156]> { 1050 let Latency = 4; 1051 let NumMicroOps = 4; 1052 let ResourceCycles = [1,1,2]; 1053} 1054def: InstRW<[ICXWriteResGroup57], (instregex "LAR(16|32|64)rr")>; 1055 1056def ICXWriteResGroup61 : SchedWriteRes<[ICXPort5,ICXPort01]> { 1057 let Latency = 5; 1058 let NumMicroOps = 2; 1059 let ResourceCycles = [1,1]; 1060} 1061def: InstRW<[ICXWriteResGroup61], (instregex "MMX_CVT(T?)PD2PIrr", 1062 "MMX_CVT(T?)PS2PIrr", 1063 "VCVTDQ2PDZ128rr", 1064 "VCVTPD2DQZ128rr", 1065 "(V?)CVT(T?)PD2DQrr", 1066 "VCVTPD2UDQZ128rr", 1067 "VCVTPS2PDZ128rr", 1068 "(V?)CVTPS2PDrr", 1069 "VCVTPS2QQZ128rr", 1070 "VCVTPS2UQQZ128rr", 1071 "VCVTQQ2PSZ128rr", 1072 "(V?)CVTSI(64)?2SDrr", 1073 "VCVTSI2SSZrr", 1074 "(V?)CVTSI2SSrr", 1075 "VCVTSI(64)?2SDZrr", 1076 "VCVTSS2SDZrr", 1077 "(V?)CVTSS2SDrr", 1078 "VCVTTPD2DQZ128rr", 1079 "VCVTTPD2UDQZ128rr", 1080 "VCVTTPS2QQZ128rr", 1081 "VCVTTPS2UQQZ128rr", 1082 "VCVTUDQ2PDZ128rr", 1083 "VCVTUQQ2PSZ128rr", 1084 "VCVTUSI2SSZrr", 1085 "VCVTUSI(64)?2SDZrr")>; 1086 1087def ICXWriteResGroup62 : SchedWriteRes<[ICXPort5,ICXPort015]> { 1088 let Latency = 5; 1089 let NumMicroOps = 3; 1090 let ResourceCycles = [2,1]; 1091} 1092def: InstRW<[ICXWriteResGroup62], (instregex "VPCONFLICTQZ128rr")>; 1093 1094def ICXWriteResGroup63 : SchedWriteRes<[ICXPort1,ICXPort6,ICXPort06]> { 1095 let Latency = 5; 1096 let NumMicroOps = 3; 1097 let ResourceCycles = [1,1,1]; 1098} 1099def: InstRW<[ICXWriteResGroup63], (instregex "STR(16|32|64)r")>; 1100 1101def ICXWriteResGroup65 : SchedWriteRes<[ICXPort4,ICXPort237,ICXPort01]> { 1102 let Latency = 5; 1103 let NumMicroOps = 3; 1104 let ResourceCycles = [1,1,1]; 1105} 1106def: InstRW<[ICXWriteResGroup65], (instregex "VCVTPS2PHZ128mr(b?)", 1107 "VCVTPS2PHZ256mr(b?)", 1108 "VCVTPS2PHZmr(b?)")>; 1109 1110def ICXWriteResGroup66 : SchedWriteRes<[ICXPort4,ICXPort5,ICXPort237]> { 1111 let Latency = 5; 1112 let NumMicroOps = 4; 1113 let ResourceCycles = [1,2,1]; 1114} 1115def: InstRW<[ICXWriteResGroup66], (instregex "VPMOVDB(Z|Z128|Z256)mr(b?)", 1116 "VPMOVDW(Z|Z128|Z256)mr(b?)", 1117 "VPMOVQB(Z|Z128|Z256)mr(b?)", 1118 "VPMOVQW(Z|Z128|Z256)mr(b?)", 1119 "VPMOVSDB(Z|Z128|Z256)mr(b?)", 1120 "VPMOVSDW(Z|Z128|Z256)mr(b?)", 1121 "VPMOVSQB(Z|Z128|Z256)mr(b?)", 1122 "VPMOVSQD(Z|Z128|Z256)mr(b?)", 1123 "VPMOVSQW(Z|Z128|Z256)mr(b?)", 1124 "VPMOVSWB(Z|Z128|Z256)mr(b?)", 1125 "VPMOVUSDB(Z|Z128|Z256)mr(b?)", 1126 "VPMOVUSDW(Z|Z128|Z256)mr(b?)", 1127 "VPMOVUSQB(Z|Z128|Z256)mr(b?)", 1128 "VPMOVUSQD(Z|Z128|Z256)mr(b?)", 1129 "VPMOVUSQW(Z|Z128|Z256)mr(b?)", 1130 "VPMOVUSWB(Z|Z128|Z256)mr(b?)", 1131 "VPMOVWB(Z|Z128|Z256)mr(b?)")>; 1132 1133def ICXWriteResGroup67 : SchedWriteRes<[ICXPort06,ICXPort0156]> { 1134 let Latency = 5; 1135 let NumMicroOps = 5; 1136 let ResourceCycles = [1,4]; 1137} 1138def: InstRW<[ICXWriteResGroup67], (instrs XSETBV)>; 1139 1140def ICXWriteResGroup69 : SchedWriteRes<[ICXPort4,ICXPort237,ICXPort0156]> { 1141 let Latency = 5; 1142 let NumMicroOps = 6; 1143 let ResourceCycles = [1,1,4]; 1144} 1145def: InstRW<[ICXWriteResGroup69], (instregex "PUSHF(16|64)")>; 1146 1147def ICXWriteResGroup71 : SchedWriteRes<[ICXPort23]> { 1148 let Latency = 6; 1149 let NumMicroOps = 1; 1150 let ResourceCycles = [1]; 1151} 1152def: InstRW<[ICXWriteResGroup71], (instrs VBROADCASTSSrm, 1153 VPBROADCASTDrm, 1154 VPBROADCASTQrm, 1155 VMOVSHDUPrm, 1156 VMOVSLDUPrm, 1157 VMOVDDUPrm, 1158 MOVSHDUPrm, 1159 MOVSLDUPrm, 1160 MOVDDUPrm)>; 1161 1162def ICXWriteResGroup72 : SchedWriteRes<[ICXPort5]> { 1163 let Latency = 6; 1164 let NumMicroOps = 2; 1165 let ResourceCycles = [2]; 1166} 1167def: InstRW<[ICXWriteResGroup72], (instrs MMX_CVTPI2PSrr)>; 1168def: InstRW<[ICXWriteResGroup72], (instregex "VCOMPRESSPD(Z|Z128|Z256)rr", 1169 "VCOMPRESSPS(Z|Z128|Z256)rr", 1170 "VPCOMPRESSD(Z|Z128|Z256)rr", 1171 "VPCOMPRESSQ(Z|Z128|Z256)rr", 1172 "VPERMW(Z|Z128|Z256)rr")>; 1173 1174def ICXWriteResGroup73 : SchedWriteRes<[ICXPort0,ICXPort23]> { 1175 let Latency = 6; 1176 let NumMicroOps = 2; 1177 let ResourceCycles = [1,1]; 1178} 1179def: InstRW<[ICXWriteResGroup73], (instrs MMX_PADDSBrm, 1180 MMX_PADDSWrm, 1181 MMX_PADDUSBrm, 1182 MMX_PADDUSWrm, 1183 MMX_PAVGBrm, 1184 MMX_PAVGWrm, 1185 MMX_PCMPEQBrm, 1186 MMX_PCMPEQDrm, 1187 MMX_PCMPEQWrm, 1188 MMX_PCMPGTBrm, 1189 MMX_PCMPGTDrm, 1190 MMX_PCMPGTWrm, 1191 MMX_PMAXSWrm, 1192 MMX_PMAXUBrm, 1193 MMX_PMINSWrm, 1194 MMX_PMINUBrm, 1195 MMX_PSUBSBrm, 1196 MMX_PSUBSWrm, 1197 MMX_PSUBUSBrm, 1198 MMX_PSUBUSWrm)>; 1199 1200def ICXWriteResGroup76 : SchedWriteRes<[ICXPort6,ICXPort23]> { 1201 let Latency = 6; 1202 let NumMicroOps = 2; 1203 let ResourceCycles = [1,1]; 1204} 1205def: InstRW<[ICXWriteResGroup76], (instrs FARJMP64m)>; 1206def: InstRW<[ICXWriteResGroup76], (instregex "JMP(16|32|64)m")>; 1207 1208def ICXWriteResGroup79 : SchedWriteRes<[ICXPort23,ICXPort15]> { 1209 let Latency = 6; 1210 let NumMicroOps = 2; 1211 let ResourceCycles = [1,1]; 1212} 1213def: InstRW<[ICXWriteResGroup79], (instregex "ANDN(32|64)rm", 1214 "MOVBE(16|32|64)rm")>; 1215 1216def ICXWriteResGroup80 : SchedWriteRes<[ICXPort23,ICXPort015]> { 1217 let Latency = 6; 1218 let NumMicroOps = 2; 1219 let ResourceCycles = [1,1]; 1220} 1221def: InstRW<[ICXWriteResGroup80], (instregex "VMOV(64to|QI2)PQIZrm(b?)")>; 1222def: InstRW<[ICXWriteResGroup80], (instrs VMOVDI2PDIZrm)>; 1223 1224def ICXWriteResGroup81 : SchedWriteRes<[ICXPort23,ICXPort0156]> { 1225 let Latency = 6; 1226 let NumMicroOps = 2; 1227 let ResourceCycles = [1,1]; 1228} 1229def: InstRW<[ICXWriteResGroup81], (instrs POP16r, POP32r, POP64r)>; 1230def: InstRW<[ICXWriteResGroup81], (instregex "POP(16|32|64)rmr")>; 1231 1232def ICXWriteResGroup82 : SchedWriteRes<[ICXPort5,ICXPort01]> { 1233 let Latency = 6; 1234 let NumMicroOps = 3; 1235 let ResourceCycles = [2,1]; 1236} 1237def: InstRW<[ICXWriteResGroup82], (instregex "(V?)CVTSI642SSrr", 1238 "VCVTSI642SSZrr", 1239 "VCVTUSI642SSZrr")>; 1240 1241def ICXWriteResGroup84 : SchedWriteRes<[ICXPort1,ICXPort6,ICXPort06,ICXPort0156]> { 1242 let Latency = 6; 1243 let NumMicroOps = 4; 1244 let ResourceCycles = [1,1,1,1]; 1245} 1246def: InstRW<[ICXWriteResGroup84], (instregex "SLDT(16|32|64)r")>; 1247 1248def ICXWriteResGroup86 : SchedWriteRes<[ICXPort4,ICXPort23,ICXPort237,ICXPort06]> { 1249 let Latency = 6; 1250 let NumMicroOps = 4; 1251 let ResourceCycles = [1,1,1,1]; 1252} 1253def: InstRW<[ICXWriteResGroup86], (instregex "SAR(8|16|32|64)m(1|i)", 1254 "SHL(8|16|32|64)m(1|i)", 1255 "SHR(8|16|32|64)m(1|i)")>; 1256 1257def ICXWriteResGroup87 : SchedWriteRes<[ICXPort4,ICXPort23,ICXPort237,ICXPort0156]> { 1258 let Latency = 6; 1259 let NumMicroOps = 4; 1260 let ResourceCycles = [1,1,1,1]; 1261} 1262def: InstRW<[ICXWriteResGroup87], (instregex "POP(16|32|64)rmm", 1263 "PUSH(16|32|64)rmm")>; 1264 1265def ICXWriteResGroup88 : SchedWriteRes<[ICXPort6,ICXPort0156]> { 1266 let Latency = 6; 1267 let NumMicroOps = 6; 1268 let ResourceCycles = [1,5]; 1269} 1270def: InstRW<[ICXWriteResGroup88], (instrs STD)>; 1271 1272def ICXWriteResGroup89 : SchedWriteRes<[ICXPort23]> { 1273 let Latency = 7; 1274 let NumMicroOps = 1; 1275 let ResourceCycles = [1]; 1276} 1277def: InstRW<[ICXWriteResGroup89], (instregex "LD_F(32|64|80)m")>; 1278def: InstRW<[ICXWriteResGroup89], (instrs VBROADCASTF128, 1279 VBROADCASTI128, 1280 VBROADCASTSDYrm, 1281 VBROADCASTSSYrm, 1282 VMOVDDUPYrm, 1283 VMOVSHDUPYrm, 1284 VMOVSLDUPYrm, 1285 VPBROADCASTDYrm, 1286 VPBROADCASTQYrm)>; 1287 1288def ICXWriteResGroup90 : SchedWriteRes<[ICXPort01,ICXPort5]> { 1289 let Latency = 7; 1290 let NumMicroOps = 2; 1291 let ResourceCycles = [1,1]; 1292} 1293def: InstRW<[ICXWriteResGroup90], (instrs VCVTDQ2PDYrr)>; 1294 1295def ICXWriteResGroup92 : SchedWriteRes<[ICXPort5,ICXPort23]> { 1296 let Latency = 7; 1297 let NumMicroOps = 2; 1298 let ResourceCycles = [1,1]; 1299} 1300def: InstRW<[ICXWriteResGroup92], (instregex "VMOV(SD|SS)Zrm(b?)", 1301 "VPBROADCAST(B|W)(Z128)?rm", 1302 "(V?)INSERTPS(Z?)rm", 1303 "(V?)PALIGNR(Z128)?rmi", 1304 "(V?)PERMIL(PD|PS)(Z128)?m(b?)i", 1305 "(V?)PERMIL(PD|PS)(Z128)?rm", 1306 "(V?)UNPCK(L|H)(PD|PS)(Z128)?rm")>; 1307 1308def ICXWriteResGroup93 : SchedWriteRes<[ICXPort5,ICXPort01]> { 1309 let Latency = 7; 1310 let NumMicroOps = 2; 1311 let ResourceCycles = [1,1]; 1312} 1313def: InstRW<[ICXWriteResGroup93], (instregex "VCVTDQ2PDZ256rr", 1314 "VCVTPD2DQ(Y|Z256)rr", 1315 "VCVTPD2UDQZ256rr", 1316 "VCVTPS2PD(Y|Z256)rr", 1317 "VCVTPS2QQZ256rr", 1318 "VCVTPS2UQQZ256rr", 1319 "VCVTQQ2PSZ256rr", 1320 "VCVTTPD2DQ(Y|Z256)rr", 1321 "VCVTTPD2UDQZ256rr", 1322 "VCVTTPS2QQZ256rr", 1323 "VCVTTPS2UQQZ256rr", 1324 "VCVTUDQ2PDZ256rr", 1325 "VCVTUQQ2PSZ256rr")>; 1326 1327def ICXWriteResGroup93z : SchedWriteRes<[ICXPort5,ICXPort05]> { 1328 let Latency = 7; 1329 let NumMicroOps = 2; 1330 let ResourceCycles = [1,1]; 1331} 1332def: InstRW<[ICXWriteResGroup93z], (instrs VCVTDQ2PDZrr, 1333 VCVTPD2DQZrr, 1334 VCVTPD2UDQZrr, 1335 VCVTPS2PDZrr, 1336 VCVTPS2QQZrr, 1337 VCVTPS2UQQZrr, 1338 VCVTQQ2PSZrr, 1339 VCVTTPD2DQZrr, 1340 VCVTTPD2UDQZrr, 1341 VCVTTPS2QQZrr, 1342 VCVTTPS2UQQZrr, 1343 VCVTUDQ2PDZrr, 1344 VCVTUQQ2PSZrr)>; 1345 1346def ICXWriteResGroup95 : SchedWriteRes<[ICXPort23,ICXPort015]> { 1347 let Latency = 7; 1348 let NumMicroOps = 2; 1349 let ResourceCycles = [1,1]; 1350} 1351def: InstRW<[ICXWriteResGroup95], (instrs VMOVNTDQAZ128rm, 1352 VPBLENDDrmi)>; 1353def: InstRW<[ICXWriteResGroup95, ReadAfterVecXLd], 1354 (instregex "VBLENDMPDZ128rm(b?)", 1355 "VBLENDMPSZ128rm(b?)", 1356 "VBROADCASTI32X2Z128rm(b?)", 1357 "VBROADCASTSSZ128rm(b?)", 1358 "VINSERT(F|I)128rm", 1359 "VMOVAPDZ128rm(b?)", 1360 "VMOVAPSZ128rm(b?)", 1361 "VMOVDDUPZ128rm(b?)", 1362 "VMOVDQA32Z128rm(b?)", 1363 "VMOVDQA64Z128rm(b?)", 1364 "VMOVDQU16Z128rm(b?)", 1365 "VMOVDQU32Z128rm(b?)", 1366 "VMOVDQU64Z128rm(b?)", 1367 "VMOVDQU8Z128rm(b?)", 1368 "VMOVSHDUPZ128rm(b?)", 1369 "VMOVSLDUPZ128rm(b?)", 1370 "VMOVUPDZ128rm(b?)", 1371 "VMOVUPSZ128rm(b?)", 1372 "VPADD(B|D|Q|W)Z128rm(b?)", 1373 "(V?)PADD(B|D|Q|W)rm", 1374 "VPBLENDM(B|D|Q|W)Z128rm(b?)", 1375 "VPBROADCASTDZ128rm(b?)", 1376 "VPBROADCASTQZ128rm(b?)", 1377 "VPSUB(B|D|Q|W)Z128rm(b?)", 1378 "(V?)PSUB(B|D|Q|W)rm", 1379 "VPTERNLOGDZ128rm(b?)i", 1380 "VPTERNLOGQZ128rm(b?)i")>; 1381 1382def ICXWriteResGroup96 : SchedWriteRes<[ICXPort5,ICXPort23]> { 1383 let Latency = 7; 1384 let NumMicroOps = 3; 1385 let ResourceCycles = [2,1]; 1386} 1387def: InstRW<[ICXWriteResGroup96], (instrs MMX_PACKSSDWrm, 1388 MMX_PACKSSWBrm, 1389 MMX_PACKUSWBrm)>; 1390 1391def ICXWriteResGroup97 : SchedWriteRes<[ICXPort5,ICXPort015]> { 1392 let Latency = 7; 1393 let NumMicroOps = 3; 1394 let ResourceCycles = [2,1]; 1395} 1396def: InstRW<[ICXWriteResGroup97], (instregex "VPERMI2W128rr", 1397 "VPERMI2W256rr", 1398 "VPERMI2Wrr", 1399 "VPERMT2W128rr", 1400 "VPERMT2W256rr", 1401 "VPERMT2Wrr")>; 1402 1403def ICXWriteResGroup99 : SchedWriteRes<[ICXPort23,ICXPort0156]> { 1404 let Latency = 7; 1405 let NumMicroOps = 3; 1406 let ResourceCycles = [1,2]; 1407} 1408def: InstRW<[ICXWriteResGroup99], (instrs LEAVE, LEAVE64, 1409 SCASB, SCASL, SCASQ, SCASW)>; 1410 1411def ICXWriteResGroup100 : SchedWriteRes<[ICXPort0,ICXPort5,ICXPort01]> { 1412 let Latency = 7; 1413 let NumMicroOps = 3; 1414 let ResourceCycles = [1,1,1]; 1415} 1416def: InstRW<[ICXWriteResGroup100], (instregex "(V?)CVT(T?)SS2SI64(Z?)rr", 1417 "VCVT(T?)SS2USI64Zrr")>; 1418 1419def ICXWriteResGroup101 : SchedWriteRes<[ICXPort0,ICXPort23,ICXPort05]> { 1420 let Latency = 7; 1421 let NumMicroOps = 3; 1422 let ResourceCycles = [1,1,1]; 1423} 1424def: InstRW<[ICXWriteResGroup101], (instrs FLDCW16m)>; 1425 1426def ICXWriteResGroup103 : SchedWriteRes<[ICXPort5,ICXPort23,ICXPort0156]> { 1427 let Latency = 7; 1428 let NumMicroOps = 3; 1429 let ResourceCycles = [1,1,1]; 1430} 1431def: InstRW<[ICXWriteResGroup103], (instregex "KMOV(B|D|Q|W)km")>; 1432 1433def ICXWriteResGroup104 : SchedWriteRes<[ICXPort6,ICXPort23,ICXPort0156]> { 1434 let Latency = 7; 1435 let NumMicroOps = 3; 1436 let ResourceCycles = [1,1,1]; 1437} 1438def: InstRW<[ICXWriteResGroup104], (instrs LRET64, RET64)>; 1439 1440def ICXWriteResGroup106 : SchedWriteRes<[ICXPort4,ICXPort5,ICXPort237]> { 1441 let Latency = 7; 1442 let NumMicroOps = 4; 1443 let ResourceCycles = [1,2,1]; 1444} 1445def: InstRW<[ICXWriteResGroup106], (instregex "VCOMPRESSPD(Z|Z128|Z256)mr(b?)", 1446 "VCOMPRESSPS(Z|Z128|Z256)mr(b?)", 1447 "VPCOMPRESSD(Z|Z128|Z256)mr(b?)", 1448 "VPCOMPRESSQ(Z|Z128|Z256)mr(b?)")>; 1449 1450def ICXWriteResGroup107 : SchedWriteRes<[ICXPort4,ICXPort23,ICXPort237,ICXPort06]> { 1451 let Latency = 7; 1452 let NumMicroOps = 5; 1453 let ResourceCycles = [1,1,1,2]; 1454} 1455def: InstRW<[ICXWriteResGroup107], (instregex "ROL(8|16|32|64)m(1|i)", 1456 "ROR(8|16|32|64)m(1|i)")>; 1457 1458def ICXWriteResGroup107_1 : SchedWriteRes<[ICXPort06]> { 1459 let Latency = 2; 1460 let NumMicroOps = 2; 1461 let ResourceCycles = [2]; 1462} 1463def: InstRW<[ICXWriteResGroup107_1], (instrs ROL8r1, ROL16r1, ROL32r1, ROL64r1, 1464 ROR8r1, ROR16r1, ROR32r1, ROR64r1)>; 1465 1466def ICXWriteResGroup108 : SchedWriteRes<[ICXPort4,ICXPort23,ICXPort237,ICXPort0156]> { 1467 let Latency = 7; 1468 let NumMicroOps = 5; 1469 let ResourceCycles = [1,1,1,2]; 1470} 1471def: InstRW<[ICXWriteResGroup108], (instregex "XADD(8|16|32|64)rm")>; 1472 1473def ICXWriteResGroup109 : SchedWriteRes<[ICXPort4,ICXPort6,ICXPort23,ICXPort237,ICXPort0156]> { 1474 let Latency = 7; 1475 let NumMicroOps = 5; 1476 let ResourceCycles = [1,1,1,1,1]; 1477} 1478def: InstRW<[ICXWriteResGroup109], (instregex "CALL(16|32|64)m")>; 1479def: InstRW<[ICXWriteResGroup109], (instrs FARCALL64m)>; 1480 1481def ICXWriteResGroup110 : SchedWriteRes<[ICXPort0,ICXPort4,ICXPort237,ICXPort0156]> { 1482 let Latency = 7; 1483 let NumMicroOps = 7; 1484 let ResourceCycles = [1,2,2,2]; 1485} 1486def: InstRW<[ICXWriteResGroup110], (instrs VPSCATTERDQZ128mr, 1487 VPSCATTERQQZ128mr, 1488 VSCATTERDPDZ128mr, 1489 VSCATTERQPDZ128mr)>; 1490 1491def ICXWriteResGroup111 : SchedWriteRes<[ICXPort6,ICXPort06,ICXPort15,ICXPort0156]> { 1492 let Latency = 7; 1493 let NumMicroOps = 7; 1494 let ResourceCycles = [1,3,1,2]; 1495} 1496def: InstRW<[ICXWriteResGroup111], (instrs LOOP)>; 1497 1498def ICXWriteResGroup112 : SchedWriteRes<[ICXPort0,ICXPort4,ICXPort237,ICXPort0156]> { 1499 let Latency = 7; 1500 let NumMicroOps = 11; 1501 let ResourceCycles = [1,4,4,2]; 1502} 1503def: InstRW<[ICXWriteResGroup112], (instrs VPSCATTERDQZ256mr, 1504 VPSCATTERQQZ256mr, 1505 VSCATTERDPDZ256mr, 1506 VSCATTERQPDZ256mr)>; 1507 1508def ICXWriteResGroup113 : SchedWriteRes<[ICXPort0,ICXPort4,ICXPort237,ICXPort0156]> { 1509 let Latency = 7; 1510 let NumMicroOps = 19; 1511 let ResourceCycles = [1,8,8,2]; 1512} 1513def: InstRW<[ICXWriteResGroup113], (instrs VPSCATTERDQZmr, 1514 VPSCATTERQQZmr, 1515 VSCATTERDPDZmr, 1516 VSCATTERQPDZmr)>; 1517 1518def ICXWriteResGroup114 : SchedWriteRes<[ICXPort0,ICXPort4,ICXPort5,ICXPort237,ICXPort0156]> { 1519 let Latency = 7; 1520 let NumMicroOps = 36; 1521 let ResourceCycles = [1,16,1,16,2]; 1522} 1523def: InstRW<[ICXWriteResGroup114], (instrs VSCATTERDPSZmr)>; 1524 1525def ICXWriteResGroup118 : SchedWriteRes<[ICXPort1,ICXPort23]> { 1526 let Latency = 8; 1527 let NumMicroOps = 2; 1528 let ResourceCycles = [1,1]; 1529} 1530def: InstRW<[ICXWriteResGroup118], (instregex "PDEP(32|64)rm", 1531 "PEXT(32|64)rm")>; 1532 1533def ICXWriteResGroup119 : SchedWriteRes<[ICXPort5,ICXPort23]> { 1534 let Latency = 8; 1535 let NumMicroOps = 2; 1536 let ResourceCycles = [1,1]; 1537} 1538def: InstRW<[ICXWriteResGroup119], (instregex "FCOM(P?)(32|64)m", 1539 "VPBROADCASTB(Z|Z256)rm(b?)", 1540 "VPBROADCASTW(Z|Z256)rm(b?)", 1541 "(V?)PALIGNR(Y|Z256)rmi", 1542 "(V?)PERMIL(PD|PS)(Y|Z256)m(b?)i", 1543 "(V?)PERMIL(PD|PS)(Y|Z256)rm", 1544 "(V?)UNPCK(L|H)(PD|PS)(Y|Z256)rm")>; 1545def: InstRW<[ICXWriteResGroup119], (instrs VPBROADCASTBYrm, 1546 VPBROADCASTWYrm, 1547 VPMOVSXBDYrm, 1548 VPMOVSXBQYrm, 1549 VPMOVSXWQYrm)>; 1550 1551def ICXWriteResGroup121 : SchedWriteRes<[ICXPort23,ICXPort015]> { 1552 let Latency = 8; 1553 let NumMicroOps = 2; 1554 let ResourceCycles = [1,1]; 1555} 1556def: InstRW<[ICXWriteResGroup121], (instrs VMOVNTDQAZ256rm, 1557 VPBLENDDYrmi)>; 1558def: InstRW<[ICXWriteResGroup121, ReadAfterVecYLd], 1559 (instregex "VBLENDMPD(Z|Z256)rm(b?)", 1560 "VBLENDMPS(Z|Z256)rm(b?)", 1561 "VBROADCASTF32X2Z256rm(b?)", 1562 "VBROADCASTF32X2Zrm(b?)", 1563 "VBROADCASTF32X4Z256rm(b?)", 1564 "VBROADCASTF32X4rm(b?)", 1565 "VBROADCASTF32X8rm(b?)", 1566 "VBROADCASTF64X2Z128rm(b?)", 1567 "VBROADCASTF64X2rm(b?)", 1568 "VBROADCASTF64X4rm(b?)", 1569 "VBROADCASTI32X2Z256rm(b?)", 1570 "VBROADCASTI32X2Zrm(b?)", 1571 "VBROADCASTI32X4Z256rm(b?)", 1572 "VBROADCASTI32X4rm(b?)", 1573 "VBROADCASTI32X8rm(b?)", 1574 "VBROADCASTI64X2Z128rm(b?)", 1575 "VBROADCASTI64X2rm(b?)", 1576 "VBROADCASTI64X4rm(b?)", 1577 "VBROADCASTSD(Z|Z256)rm(b?)", 1578 "VBROADCASTSS(Z|Z256)rm(b?)", 1579 "VINSERTF32x4(Z|Z256)rm(b?)", 1580 "VINSERTF32x8Zrm(b?)", 1581 "VINSERTF64x2(Z|Z256)rm(b?)", 1582 "VINSERTF64x4Zrm(b?)", 1583 "VINSERTI32x4(Z|Z256)rm(b?)", 1584 "VINSERTI32x8Zrm(b?)", 1585 "VINSERTI64x2(Z|Z256)rm(b?)", 1586 "VINSERTI64x4Zrm(b?)", 1587 "VMOVAPD(Z|Z256)rm(b?)", 1588 "VMOVAPS(Z|Z256)rm(b?)", 1589 "VMOVDDUP(Z|Z256)rm(b?)", 1590 "VMOVDQA32(Z|Z256)rm(b?)", 1591 "VMOVDQA64(Z|Z256)rm(b?)", 1592 "VMOVDQU16(Z|Z256)rm(b?)", 1593 "VMOVDQU32(Z|Z256)rm(b?)", 1594 "VMOVDQU64(Z|Z256)rm(b?)", 1595 "VMOVDQU8(Z|Z256)rm(b?)", 1596 "VMOVSHDUP(Z|Z256)rm(b?)", 1597 "VMOVSLDUP(Z|Z256)rm(b?)", 1598 "VMOVUPD(Z|Z256)rm(b?)", 1599 "VMOVUPS(Z|Z256)rm(b?)", 1600 "VPADD(B|D|Q|W)Yrm", 1601 "VPADD(B|D|Q|W)(Z|Z256)rm(b?)", 1602 "VPBLENDM(B|D|Q|W)(Z|Z256)rm(b?)", 1603 "VPBROADCASTD(Z|Z256)rm(b?)", 1604 "VPBROADCASTQ(Z|Z256)rm(b?)", 1605 "VPSUB(B|D|Q|W)Yrm", 1606 "VPSUB(B|D|Q|W)(Z|Z256)rm(b?)", 1607 "VPTERNLOGD(Z|Z256)rm(b?)i", 1608 "VPTERNLOGQ(Z|Z256)rm(b?)i")>; 1609 1610def ICXWriteResGroup123 : SchedWriteRes<[ICXPort0,ICXPort5,ICXPort23]> { 1611 let Latency = 8; 1612 let NumMicroOps = 4; 1613 let ResourceCycles = [1,2,1]; 1614} 1615def: InstRW<[ICXWriteResGroup123], (instregex "MMX_PH(ADD|SUB)SWrm")>; 1616 1617def ICXWriteResGroup127 : SchedWriteRes<[ICXPort23,ICXPort237,ICXPort06,ICXPort0156]> { 1618 let Latency = 8; 1619 let NumMicroOps = 5; 1620 let ResourceCycles = [1,1,1,2]; 1621} 1622def: InstRW<[ICXWriteResGroup127], (instregex "RCL(8|16|32|64)m(1|i)", 1623 "RCR(8|16|32|64)m(1|i)")>; 1624 1625def ICXWriteResGroup128 : SchedWriteRes<[ICXPort4,ICXPort23,ICXPort237,ICXPort06]> { 1626 let Latency = 8; 1627 let NumMicroOps = 6; 1628 let ResourceCycles = [1,1,1,3]; 1629} 1630def: InstRW<[ICXWriteResGroup128], (instregex "ROL(8|16|32|64)mCL", 1631 "ROR(8|16|32|64)mCL", 1632 "SAR(8|16|32|64)mCL", 1633 "SHL(8|16|32|64)mCL", 1634 "SHR(8|16|32|64)mCL")>; 1635 1636def ICXWriteResGroup130 : SchedWriteRes<[ICXPort4,ICXPort23,ICXPort237,ICXPort06,ICXPort0156]> { 1637 let Latency = 8; 1638 let NumMicroOps = 6; 1639 let ResourceCycles = [1,1,1,2,1]; 1640} 1641def: SchedAlias<WriteADCRMW, ICXWriteResGroup130>; 1642 1643def ICXWriteResGroup131 : SchedWriteRes<[ICXPort0,ICXPort4,ICXPort5,ICXPort237,ICXPort0156]> { 1644 let Latency = 8; 1645 let NumMicroOps = 8; 1646 let ResourceCycles = [1,2,1,2,2]; 1647} 1648def: InstRW<[ICXWriteResGroup131], (instrs VPSCATTERQDZ128mr, 1649 VPSCATTERQDZ256mr, 1650 VSCATTERQPSZ128mr, 1651 VSCATTERQPSZ256mr)>; 1652 1653def ICXWriteResGroup132 : SchedWriteRes<[ICXPort0,ICXPort4,ICXPort5,ICXPort237,ICXPort0156]> { 1654 let Latency = 8; 1655 let NumMicroOps = 12; 1656 let ResourceCycles = [1,4,1,4,2]; 1657} 1658def: InstRW<[ICXWriteResGroup132], (instrs VPSCATTERDDZ128mr, 1659 VSCATTERDPSZ128mr)>; 1660 1661def ICXWriteResGroup133 : SchedWriteRes<[ICXPort0,ICXPort4,ICXPort5,ICXPort237,ICXPort0156]> { 1662 let Latency = 8; 1663 let NumMicroOps = 20; 1664 let ResourceCycles = [1,8,1,8,2]; 1665} 1666def: InstRW<[ICXWriteResGroup133], (instrs VPSCATTERDDZ256mr, 1667 VSCATTERDPSZ256mr)>; 1668 1669def ICXWriteResGroup134 : SchedWriteRes<[ICXPort0,ICXPort4,ICXPort5,ICXPort237,ICXPort0156]> { 1670 let Latency = 8; 1671 let NumMicroOps = 36; 1672 let ResourceCycles = [1,16,1,16,2]; 1673} 1674def: InstRW<[ICXWriteResGroup134], (instrs VPSCATTERDDZmr)>; 1675 1676def ICXWriteResGroup135 : SchedWriteRes<[ICXPort0,ICXPort23]> { 1677 let Latency = 9; 1678 let NumMicroOps = 2; 1679 let ResourceCycles = [1,1]; 1680} 1681def: InstRW<[ICXWriteResGroup135], (instrs MMX_CVTPI2PSrm)>; 1682 1683def ICXWriteResGroup136 : SchedWriteRes<[ICXPort5,ICXPort23]> { 1684 let Latency = 9; 1685 let NumMicroOps = 2; 1686 let ResourceCycles = [1,1]; 1687} 1688def: InstRW<[ICXWriteResGroup136], (instrs VPMOVSXBWYrm, 1689 VPMOVSXDQYrm, 1690 VPMOVSXWDYrm, 1691 VPMOVZXWDYrm)>; 1692def: InstRW<[ICXWriteResGroup136], (instregex "VALIGN(D|Q)Z128rm(b?)i", 1693 "VFPCLASSSDZrm(b?)", 1694 "VFPCLASSSSZrm(b?)", 1695 "(V?)PCMPGTQrm", 1696 "VPERMI2D128rm(b?)", 1697 "VPERMI2PD128rm(b?)", 1698 "VPERMI2PS128rm(b?)", 1699 "VPERMI2Q128rm(b?)", 1700 "VPERMT2D128rm(b?)", 1701 "VPERMT2PD128rm(b?)", 1702 "VPERMT2PS128rm(b?)", 1703 "VPERMT2Q128rm(b?)", 1704 "VPMAXSQZ128rm(b?)", 1705 "VPMAXUQZ128rm(b?)", 1706 "VPMINSQZ128rm(b?)", 1707 "VPMINUQZ128rm(b?)")>; 1708 1709def ICXWriteResGroup136_2 : SchedWriteRes<[ICXPort5,ICXPort23]> { 1710 let Latency = 10; 1711 let NumMicroOps = 2; 1712 let ResourceCycles = [1,1]; 1713} 1714def: InstRW<[ICXWriteResGroup136_2], (instregex "VCMP(PD|PS)Z128rm(b?)i", 1715 "VCMP(SD|SS)Zrm", 1716 "VFPCLASSPDZ128rm(b?)", 1717 "VFPCLASSPSZ128rm(b?)", 1718 "VPCMPBZ128rmi(b?)", 1719 "VPCMPDZ128rmi(b?)", 1720 "VPCMPEQ(B|D|Q|W)Z128rm(b?)", 1721 "VPCMPGT(B|D|Q|W)Z128rm(b?)", 1722 "VPCMPQZ128rmi(b?)", 1723 "VPCMPU(B|D|Q|W)Z128rmi(b?)", 1724 "VPCMPWZ128rmi(b?)", 1725 "(V?)PACK(U|S)S(DW|WB)(Z128)?rm", 1726 "VPTESTMBZ128rm(b?)", 1727 "VPTESTMDZ128rm(b?)", 1728 "VPTESTMQZ128rm(b?)", 1729 "VPTESTMWZ128rm(b?)", 1730 "VPTESTNMBZ128rm(b?)", 1731 "VPTESTNMDZ128rm(b?)", 1732 "VPTESTNMQZ128rm(b?)", 1733 "VPTESTNMWZ128rm(b?)")>; 1734 1735def ICXWriteResGroup137 : SchedWriteRes<[ICXPort23,ICXPort01]> { 1736 let Latency = 9; 1737 let NumMicroOps = 2; 1738 let ResourceCycles = [1,1]; 1739} 1740def: InstRW<[ICXWriteResGroup137], (instregex "MMX_CVT(T?)PS2PIrm", 1741 "(V?)CVTPS2PDrm")>; 1742 1743def ICXWriteResGroup143 : SchedWriteRes<[ICXPort5,ICXPort01,ICXPort23]> { 1744 let Latency = 9; 1745 let NumMicroOps = 4; 1746 let ResourceCycles = [2,1,1]; 1747} 1748def: InstRW<[ICXWriteResGroup143], (instregex "(V?)PHADDSWrm", 1749 "(V?)PHSUBSWrm")>; 1750 1751def ICXWriteResGroup146 : SchedWriteRes<[ICXPort1,ICXPort6,ICXPort23,ICXPort0156]> { 1752 let Latency = 9; 1753 let NumMicroOps = 5; 1754 let ResourceCycles = [1,2,1,1]; 1755} 1756def: InstRW<[ICXWriteResGroup146], (instregex "LAR(16|32|64)rm", 1757 "LSL(16|32|64)rm")>; 1758 1759def ICXWriteResGroup148 : SchedWriteRes<[ICXPort5,ICXPort23]> { 1760 let Latency = 10; 1761 let NumMicroOps = 2; 1762 let ResourceCycles = [1,1]; 1763} 1764def: InstRW<[ICXWriteResGroup148], (instrs VPCMPGTQYrm)>; 1765def: InstRW<[ICXWriteResGroup148], (instregex "(ADD|SUB|SUBR)_F(32|64)m", 1766 "ILD_F(16|32|64)m", 1767 "VALIGND(Z|Z256)rm(b?)i", 1768 "VALIGNQ(Z|Z256)rm(b?)i", 1769 "VPMAXSQ(Z|Z256)rm(b?)", 1770 "VPMAXUQ(Z|Z256)rm(b?)", 1771 "VPMINSQ(Z|Z256)rm(b?)", 1772 "VPMINUQ(Z|Z256)rm(b?)")>; 1773 1774def ICXWriteResGroup148_2 : SchedWriteRes<[ICXPort5,ICXPort23]> { 1775 let Latency = 11; 1776 let NumMicroOps = 2; 1777 let ResourceCycles = [1,1]; 1778} 1779def: InstRW<[ICXWriteResGroup148_2], (instregex "VCMPPD(Z|Z256)rm(b?)i", 1780 "VCMPPS(Z|Z256)rm(b?)i", 1781 "VFPCLASSPD(Z|Z256)rm(b?)", 1782 "VFPCLASSPS(Z|Z256)rm(b?)", 1783 "VPCMPB(Z|Z256)rmi(b?)", 1784 "VPCMPD(Z|Z256)rmi(b?)", 1785 "VPCMPEQB(Z|Z256)rm(b?)", 1786 "VPCMPEQD(Z|Z256)rm(b?)", 1787 "VPCMPEQQ(Z|Z256)rm(b?)", 1788 "VPCMPEQW(Z|Z256)rm(b?)", 1789 "VPCMPGTB(Z|Z256)rm(b?)", 1790 "VPCMPGTD(Z|Z256)rm(b?)", 1791 "VPCMPGTQ(Z|Z256)rm(b?)", 1792 "VPCMPGTW(Z|Z256)rm(b?)", 1793 "VPCMPQ(Z|Z256)rmi(b?)", 1794 "VPCMPU(B|D|Q|W)Z256rmi(b?)", 1795 "VPCMPU(B|D|Q|W)Zrmi(b?)", 1796 "VPCMPW(Z|Z256)rmi(b?)", 1797 "(V?)PACK(U|S)S(DW|WB)(Y|Z|Z256)rm", 1798 "VPTESTM(B|D|Q|W)Z256rm(b?)", 1799 "VPTESTM(B|D|Q|W)Zrm(b?)", 1800 "VPTESTNM(B|D|Q|W)Z256rm(b?)", 1801 "VPTESTNM(B|D|Q|W)Zrm(b?)")>; 1802 1803def ICXWriteResGroup149 : SchedWriteRes<[ICXPort23,ICXPort01]> { 1804 let Latency = 10; 1805 let NumMicroOps = 2; 1806 let ResourceCycles = [1,1]; 1807} 1808def: InstRW<[ICXWriteResGroup149], (instregex "VCVTDQ2PDZ128rm(b?)", 1809 "VCVTDQ2PSZ128rm(b?)", 1810 "(V?)CVTDQ2PSrm", 1811 "VCVTPD2QQZ128rm(b?)", 1812 "VCVTPD2UQQZ128rm(b?)", 1813 "VCVTPH2PSZ128rm(b?)", 1814 "VCVTPS2DQZ128rm(b?)", 1815 "(V?)CVTPS2DQrm", 1816 "VCVTPS2PDZ128rm(b?)", 1817 "VCVTPS2QQZ128rm(b?)", 1818 "VCVTPS2UDQZ128rm(b?)", 1819 "VCVTPS2UQQZ128rm(b?)", 1820 "VCVTQQ2PDZ128rm(b?)", 1821 "VCVTQQ2PSZ128rm(b?)", 1822 "VCVTSS2SDZrm", 1823 "(V?)CVTSS2SDrm", 1824 "VCVTTPD2QQZ128rm(b?)", 1825 "VCVTTPD2UQQZ128rm(b?)", 1826 "VCVTTPS2DQZ128rm(b?)", 1827 "(V?)CVTTPS2DQrm", 1828 "VCVTTPS2QQZ128rm(b?)", 1829 "VCVTTPS2UDQZ128rm(b?)", 1830 "VCVTTPS2UQQZ128rm(b?)", 1831 "VCVTUDQ2PDZ128rm(b?)", 1832 "VCVTUDQ2PSZ128rm(b?)", 1833 "VCVTUQQ2PDZ128rm(b?)", 1834 "VCVTUQQ2PSZ128rm(b?)")>; 1835 1836def ICXWriteResGroup151 : SchedWriteRes<[ICXPort5,ICXPort23]> { 1837 let Latency = 10; 1838 let NumMicroOps = 3; 1839 let ResourceCycles = [2,1]; 1840} 1841def: InstRW<[ICXWriteResGroup151], (instregex "VEXPANDPDZ128rm(b?)", 1842 "VEXPANDPSZ128rm(b?)", 1843 "VPEXPANDDZ128rm(b?)", 1844 "VPEXPANDQZ128rm(b?)")>; 1845 1846def ICXWriteResGroup154 : SchedWriteRes<[ICXPort5,ICXPort01,ICXPort23]> { 1847 let Latency = 10; 1848 let NumMicroOps = 4; 1849 let ResourceCycles = [2,1,1]; 1850} 1851def: InstRW<[ICXWriteResGroup154], (instrs VPHADDSWYrm, 1852 VPHSUBSWYrm)>; 1853 1854def ICXWriteResGroup157 : SchedWriteRes<[ICXPort4,ICXPort6,ICXPort23,ICXPort237,ICXPort06,ICXPort0156]> { 1855 let Latency = 10; 1856 let NumMicroOps = 8; 1857 let ResourceCycles = [1,1,1,1,1,3]; 1858} 1859def: InstRW<[ICXWriteResGroup157], (instregex "XCHG(8|16|32|64)rm")>; 1860 1861def ICXWriteResGroup160 : SchedWriteRes<[ICXPort0,ICXPort23]> { 1862 let Latency = 11; 1863 let NumMicroOps = 2; 1864 let ResourceCycles = [1,1]; 1865} 1866def: InstRW<[ICXWriteResGroup160], (instregex "MUL_F(32|64)m")>; 1867 1868def ICXWriteResGroup161 : SchedWriteRes<[ICXPort23,ICXPort01]> { 1869 let Latency = 11; 1870 let NumMicroOps = 2; 1871 let ResourceCycles = [1,1]; 1872} 1873def: InstRW<[ICXWriteResGroup161], (instrs VCVTDQ2PSYrm, 1874 VCVTPS2PDYrm)>; 1875def: InstRW<[ICXWriteResGroup161], (instregex "VCVTDQ2(PD|PS)(Z|Z256)rm(b?)", 1876 "VCVTPH2PS(Z|Z256)rm(b?)", 1877 "VCVTPS2PD(Z|Z256)rm(b?)", 1878 "VCVTQQ2PD(Z|Z256)rm(b?)", 1879 "VCVTQQ2PSZ256rm(b?)", 1880 "VCVT(T?)PD2QQ(Z|Z256)rm(b?)", 1881 "VCVT(T?)PD2UQQ(Z|Z256)rm(b?)", 1882 "VCVT(T?)PS2DQYrm", 1883 "VCVT(T?)PS2DQ(Z|Z256)rm(b?)", 1884 "VCVT(T?)PS2QQZ256rm(b?)", 1885 "VCVT(T?)PS2UDQ(Z|Z256)rm(b?)", 1886 "VCVT(T?)PS2UQQZ256rm(b?)", 1887 "VCVTUDQ2(PD|PS)(Z|Z256)rm(b?)", 1888 "VCVTUQQ2PD(Z|Z256)rm(b?)", 1889 "VCVTUQQ2PSZ256rm(b?)")>; 1890 1891def ICXWriteResGroup162 : SchedWriteRes<[ICXPort5,ICXPort23]> { 1892 let Latency = 11; 1893 let NumMicroOps = 3; 1894 let ResourceCycles = [2,1]; 1895} 1896def: InstRW<[ICXWriteResGroup162], (instregex "FICOM(P?)(16|32)m", 1897 "VEXPANDPD(Z|Z256)rm(b?)", 1898 "VEXPANDPS(Z|Z256)rm(b?)", 1899 "VPEXPANDD(Z|Z256)rm(b?)", 1900 "VPEXPANDQ(Z|Z256)rm(b?)")>; 1901 1902def ICXWriteResGroup164 : SchedWriteRes<[ICXPort0,ICXPort5,ICXPort23]> { 1903 let Latency = 11; 1904 let NumMicroOps = 3; 1905 let ResourceCycles = [1,1,1]; 1906} 1907def: InstRW<[ICXWriteResGroup164], (instregex "(V?)CVTDQ2PDrm")>; 1908 1909def ICXWriteResGroup166 : SchedWriteRes<[ICXPort5,ICXPort23,ICXPort01]> { 1910 let Latency = 11; 1911 let NumMicroOps = 3; 1912 let ResourceCycles = [1,1,1]; 1913} 1914def: InstRW<[ICXWriteResGroup166], (instrs CVTPD2DQrm, 1915 CVTTPD2DQrm, 1916 MMX_CVTPD2PIrm, 1917 MMX_CVTTPD2PIrm)>; 1918 1919def ICXWriteResGroup167 : SchedWriteRes<[ICXPort5,ICXPort23,ICXPort015]> { 1920 let Latency = 11; 1921 let NumMicroOps = 4; 1922 let ResourceCycles = [2,1,1]; 1923} 1924def: InstRW<[ICXWriteResGroup167], (instregex "VPCONFLICTQZ128rm(b?)")>; 1925 1926def ICXWriteResGroup169 : SchedWriteRes<[ICXPort1,ICXPort06,ICXPort0156]> { 1927 let Latency = 11; 1928 let NumMicroOps = 7; 1929 let ResourceCycles = [2,3,2]; 1930} 1931def: InstRW<[ICXWriteResGroup169], (instregex "RCL(16|32|64)rCL", 1932 "RCR(16|32|64)rCL")>; 1933 1934def ICXWriteResGroup170 : SchedWriteRes<[ICXPort1,ICXPort06,ICXPort15,ICXPort0156]> { 1935 let Latency = 11; 1936 let NumMicroOps = 9; 1937 let ResourceCycles = [1,5,1,2]; 1938} 1939def: InstRW<[ICXWriteResGroup170], (instrs RCL8rCL)>; 1940 1941def ICXWriteResGroup171 : SchedWriteRes<[ICXPort06,ICXPort0156]> { 1942 let Latency = 11; 1943 let NumMicroOps = 11; 1944 let ResourceCycles = [2,9]; 1945} 1946def: InstRW<[ICXWriteResGroup171], (instrs LOOPE, LOOPNE)>; 1947 1948def ICXWriteResGroup174 : SchedWriteRes<[ICXPort01]> { 1949 let Latency = 15; 1950 let NumMicroOps = 3; 1951 let ResourceCycles = [3]; 1952} 1953def: InstRW<[ICXWriteResGroup174], (instregex "VPMULLQ(Z128|Z256)rr")>; 1954 1955def ICXWriteResGroup174z : SchedWriteRes<[ICXPort0]> { 1956 let Latency = 15; 1957 let NumMicroOps = 3; 1958 let ResourceCycles = [3]; 1959} 1960def: InstRW<[ICXWriteResGroup174z], (instregex "VPMULLQZrr")>; 1961 1962def ICXWriteResGroup175 : SchedWriteRes<[ICXPort5,ICXPort23]> { 1963 let Latency = 12; 1964 let NumMicroOps = 3; 1965 let ResourceCycles = [2,1]; 1966} 1967def: InstRW<[ICXWriteResGroup175], (instregex "VPERMWZ128rm(b?)")>; 1968 1969def ICXWriteResGroup176 : SchedWriteRes<[ICXPort0,ICXPort23,ICXPort01]> { 1970 let Latency = 12; 1971 let NumMicroOps = 3; 1972 let ResourceCycles = [1,1,1]; 1973} 1974def: InstRW<[ICXWriteResGroup176], (instregex "VCVT(T?)SD2USIZrm(b?)", 1975 "VCVT(T?)SS2USI64Zrm(b?)")>; 1976 1977def ICXWriteResGroup177 : SchedWriteRes<[ICXPort5,ICXPort23,ICXPort01]> { 1978 let Latency = 12; 1979 let NumMicroOps = 3; 1980 let ResourceCycles = [1,1,1]; 1981} 1982def: InstRW<[ICXWriteResGroup177], (instregex "VCVT(T?)PS2QQZrm(b?)", 1983 "VCVT(T?)PS2UQQZrm(b?)")>; 1984 1985def ICXWriteResGroup180 : SchedWriteRes<[ICXPort5,ICXPort23]> { 1986 let Latency = 13; 1987 let NumMicroOps = 3; 1988 let ResourceCycles = [2,1]; 1989} 1990def: InstRW<[ICXWriteResGroup180], (instregex "(ADD|SUB|SUBR)_FI(16|32)m", 1991 "VPERMWZ256rm(b?)", 1992 "VPERMWZrm(b?)")>; 1993 1994def ICXWriteResGroup181 : SchedWriteRes<[ICXPort0,ICXPort5,ICXPort23]> { 1995 let Latency = 13; 1996 let NumMicroOps = 3; 1997 let ResourceCycles = [1,1,1]; 1998} 1999def: InstRW<[ICXWriteResGroup181], (instrs VCVTDQ2PDYrm)>; 2000 2001def ICXWriteResGroup183 : SchedWriteRes<[ICXPort5,ICXPort23,ICXPort015]> { 2002 let Latency = 13; 2003 let NumMicroOps = 4; 2004 let ResourceCycles = [2,1,1]; 2005} 2006def: InstRW<[ICXWriteResGroup183], (instregex "VPERMI2W128rm(b?)", 2007 "VPERMT2W128rm(b?)")>; 2008 2009def ICXWriteResGroup187 : SchedWriteRes<[ICXPort0,ICXPort5,ICXPort23]> { 2010 let Latency = 14; 2011 let NumMicroOps = 3; 2012 let ResourceCycles = [1,1,1]; 2013} 2014def: InstRW<[ICXWriteResGroup187], (instregex "MUL_FI(16|32)m")>; 2015 2016def ICXWriteResGroup188 : SchedWriteRes<[ICXPort5,ICXPort23,ICXPort01]> { 2017 let Latency = 14; 2018 let NumMicroOps = 3; 2019 let ResourceCycles = [1,1,1]; 2020} 2021def: InstRW<[ICXWriteResGroup188], (instregex "VCVTPD2DQZrm(b?)", 2022 "VCVTPD2UDQZrm(b?)", 2023 "VCVTQQ2PSZrm(b?)", 2024 "VCVTTPD2DQZrm(b?)", 2025 "VCVTTPD2UDQZrm(b?)", 2026 "VCVTUQQ2PSZrm(b?)")>; 2027 2028def ICXWriteResGroup189 : SchedWriteRes<[ICXPort5,ICXPort23,ICXPort015]> { 2029 let Latency = 14; 2030 let NumMicroOps = 4; 2031 let ResourceCycles = [2,1,1]; 2032} 2033def: InstRW<[ICXWriteResGroup189], (instregex "VPERMI2W256rm(b?)", 2034 "VPERMI2Wrm(b?)", 2035 "VPERMT2W256rm(b?)", 2036 "VPERMT2Wrm(b?)")>; 2037 2038def ICXWriteResGroup190 : SchedWriteRes<[ICXPort1,ICXPort06,ICXPort15,ICXPort0156]> { 2039 let Latency = 14; 2040 let NumMicroOps = 10; 2041 let ResourceCycles = [2,4,1,3]; 2042} 2043def: InstRW<[ICXWriteResGroup190], (instrs RCR8rCL)>; 2044 2045def ICXWriteResGroup191 : SchedWriteRes<[ICXPort0]> { 2046 let Latency = 15; 2047 let NumMicroOps = 1; 2048 let ResourceCycles = [1]; 2049} 2050def: InstRW<[ICXWriteResGroup191], (instregex "DIVR_(FPrST0|FST0r|FrST0)")>; 2051 2052def ICXWriteResGroup194 : SchedWriteRes<[ICXPort1,ICXPort5,ICXPort01,ICXPort23,ICXPort015]> { 2053 let Latency = 15; 2054 let NumMicroOps = 8; 2055 let ResourceCycles = [1,2,2,1,2]; 2056} 2057def: InstRW<[ICXWriteResGroup194], (instregex "VPCONFLICTDZ128rm(b?)")>; 2058 2059def ICXWriteResGroup195 : SchedWriteRes<[ICXPort1,ICXPort23,ICXPort237,ICXPort06,ICXPort15,ICXPort0156]> { 2060 let Latency = 15; 2061 let NumMicroOps = 10; 2062 let ResourceCycles = [1,1,1,5,1,1]; 2063} 2064def: InstRW<[ICXWriteResGroup195], (instregex "RCL(8|16|32|64)mCL")>; 2065 2066def ICXWriteResGroup199 : SchedWriteRes<[ICXPort4,ICXPort23,ICXPort237,ICXPort06,ICXPort15,ICXPort0156]> { 2067 let Latency = 16; 2068 let NumMicroOps = 14; 2069 let ResourceCycles = [1,1,1,4,2,5]; 2070} 2071def: InstRW<[ICXWriteResGroup199], (instrs CMPXCHG8B)>; 2072 2073def ICXWriteResGroup200 : SchedWriteRes<[ICXPort1, ICXPort05, ICXPort6]> { 2074 let Latency = 12; 2075 let NumMicroOps = 34; 2076 let ResourceCycles = [1, 4, 5]; 2077} 2078def: InstRW<[ICXWriteResGroup200], (instrs VZEROALL)>; 2079 2080def ICXWriteResGroup202 : SchedWriteRes<[ICXPort0,ICXPort1,ICXPort5,ICXPort6,ICXPort05,ICXPort0156]> { 2081 let Latency = 17; 2082 let NumMicroOps = 15; 2083 let ResourceCycles = [2,1,2,4,2,4]; 2084} 2085def: InstRW<[ICXWriteResGroup202], (instrs XCH_F)>; 2086 2087def ICXWriteResGroup205 : SchedWriteRes<[ICXPort23,ICXPort01]> { 2088 let Latency = 21; 2089 let NumMicroOps = 4; 2090 let ResourceCycles = [1,3]; 2091} 2092def: InstRW<[ICXWriteResGroup205], (instregex "VPMULLQZ128rm(b?)")>; 2093 2094def ICXWriteResGroup207 : SchedWriteRes<[ICXPort5,ICXPort6,ICXPort06,ICXPort0156]> { 2095 let Latency = 18; 2096 let NumMicroOps = 8; 2097 let ResourceCycles = [1,1,1,5]; 2098} 2099def: InstRW<[ICXWriteResGroup207], (instrs CPUID, RDTSC)>; 2100 2101def ICXWriteResGroup208 : SchedWriteRes<[ICXPort1,ICXPort23,ICXPort237,ICXPort06,ICXPort15,ICXPort0156]> { 2102 let Latency = 18; 2103 let NumMicroOps = 11; 2104 let ResourceCycles = [2,1,1,4,1,2]; 2105} 2106def: InstRW<[ICXWriteResGroup208], (instregex "RCR(8|16|32|64)mCL")>; 2107 2108def ICXWriteResGroup211 : SchedWriteRes<[ICXPort23,ICXPort01]> { 2109 let Latency = 22; 2110 let NumMicroOps = 4; 2111 let ResourceCycles = [1,3]; 2112} 2113def: InstRW<[ICXWriteResGroup211], (instregex "VPMULLQZ256rm(b?)")>; 2114 2115def ICXWriteResGroup211_1 : SchedWriteRes<[ICXPort23,ICXPort0]> { 2116 let Latency = 22; 2117 let NumMicroOps = 4; 2118 let ResourceCycles = [1,3]; 2119} 2120def: InstRW<[ICXWriteResGroup211_1], (instregex "VPMULLQZrm(b?)")>; 2121 2122def ICXWriteResGroup215 : SchedWriteRes<[ICXPort0]> { 2123 let Latency = 20; 2124 let NumMicroOps = 1; 2125 let ResourceCycles = [1]; 2126} 2127def: InstRW<[ICXWriteResGroup215], (instregex "DIV_(FPrST0|FST0r|FrST0)")>; 2128 2129def ICXWriteGatherEVEX2 : SchedWriteRes<[ICXPort0,ICXPort23,ICXPort015,ICXPort0156]> { 2130 let Latency = 17; 2131 let NumMicroOps = 5; // 2 uops perform multiple loads 2132 let ResourceCycles = [1,2,1,1]; 2133} 2134def: InstRW<[ICXWriteGatherEVEX2], (instrs VGATHERQPSZ128rm, VPGATHERQDZ128rm, 2135 VGATHERDPDZ128rm, VPGATHERDQZ128rm, 2136 VGATHERQPDZ128rm, VPGATHERQQZ128rm)>; 2137 2138def ICXWriteGatherEVEX4 : SchedWriteRes<[ICXPort0,ICXPort23,ICXPort015,ICXPort0156]> { 2139 let Latency = 19; 2140 let NumMicroOps = 5; // 2 uops perform multiple loads 2141 let ResourceCycles = [1,4,1,1]; 2142} 2143def: InstRW<[ICXWriteGatherEVEX4], (instrs VGATHERQPSZ256rm, VPGATHERQDZ256rm, 2144 VGATHERQPDZ256rm, VPGATHERQQZ256rm, 2145 VGATHERDPSZ128rm, VPGATHERDDZ128rm, 2146 VGATHERDPDZ256rm, VPGATHERDQZ256rm)>; 2147 2148def ICXWriteGatherEVEX8 : SchedWriteRes<[ICXPort0,ICXPort23,ICXPort015,ICXPort0156]> { 2149 let Latency = 21; 2150 let NumMicroOps = 5; // 2 uops perform multiple loads 2151 let ResourceCycles = [1,8,1,1]; 2152} 2153def: InstRW<[ICXWriteGatherEVEX8], (instrs VGATHERDPSZ256rm, VPGATHERDDZ256rm, 2154 VGATHERDPDZrm, VPGATHERDQZrm, 2155 VGATHERQPDZrm, VPGATHERQQZrm, 2156 VGATHERQPSZrm, VPGATHERQDZrm)>; 2157 2158def ICXWriteGatherEVEX16 : SchedWriteRes<[ICXPort0,ICXPort23,ICXPort015,ICXPort0156]> { 2159 let Latency = 25; 2160 let NumMicroOps = 5; // 2 uops perform multiple loads 2161 let ResourceCycles = [1,16,1,1]; 2162} 2163def: InstRW<[ICXWriteGatherEVEX16], (instrs VGATHERDPSZrm, VPGATHERDDZrm)>; 2164 2165def ICXWriteResGroup219 : SchedWriteRes<[ICXPort4,ICXPort5,ICXPort6,ICXPort23,ICXPort237,ICXPort06,ICXPort0156]> { 2166 let Latency = 20; 2167 let NumMicroOps = 8; 2168 let ResourceCycles = [1,1,1,1,1,1,2]; 2169} 2170def: InstRW<[ICXWriteResGroup219], (instrs INSB, INSL, INSW)>; 2171 2172def ICXWriteResGroup220 : SchedWriteRes<[ICXPort5,ICXPort6,ICXPort0156]> { 2173 let Latency = 20; 2174 let NumMicroOps = 10; 2175 let ResourceCycles = [1,2,7]; 2176} 2177def: InstRW<[ICXWriteResGroup220], (instrs MWAITrr)>; 2178 2179def ICXWriteResGroup223 : SchedWriteRes<[ICXPort0,ICXPort23]> { 2180 let Latency = 22; 2181 let NumMicroOps = 2; 2182 let ResourceCycles = [1,1]; 2183} 2184def: InstRW<[ICXWriteResGroup223], (instregex "DIV_F(32|64)m")>; 2185 2186def ICXWriteResGroupVEX2 : SchedWriteRes<[ICXPort0, ICXPort23, ICXPort5, ICXPort015]> { 2187 let Latency = 18; 2188 let NumMicroOps = 5; // 2 uops perform multiple loads 2189 let ResourceCycles = [1,2,1,1]; 2190} 2191def: InstRW<[ICXWriteResGroupVEX2], (instrs VGATHERDPDrm, VPGATHERDQrm, 2192 VGATHERQPDrm, VPGATHERQQrm, 2193 VGATHERQPSrm, VPGATHERQDrm)>; 2194 2195def ICXWriteResGroupVEX4 : SchedWriteRes<[ICXPort0, ICXPort23, ICXPort5, ICXPort015]> { 2196 let Latency = 20; 2197 let NumMicroOps = 5; // 2 uops peform multiple loads 2198 let ResourceCycles = [1,4,1,1]; 2199} 2200def: InstRW<[ICXWriteResGroupVEX4], (instrs VGATHERDPDYrm, VPGATHERDQYrm, 2201 VGATHERDPSrm, VPGATHERDDrm, 2202 VGATHERQPDYrm, VPGATHERQQYrm, 2203 VGATHERQPSYrm, VPGATHERQDYrm)>; 2204 2205def ICXWriteResGroupVEX8 : SchedWriteRes<[ICXPort0, ICXPort23, ICXPort5, ICXPort015]> { 2206 let Latency = 22; 2207 let NumMicroOps = 5; // 2 uops perform multiple loads 2208 let ResourceCycles = [1,8,1,1]; 2209} 2210def: InstRW<[ICXWriteResGroupVEX8], (instrs VGATHERDPSYrm, VPGATHERDDYrm)>; 2211 2212def ICXWriteResGroup225 : SchedWriteRes<[ICXPort5,ICXPort01,ICXPort015]> { 2213 let Latency = 22; 2214 let NumMicroOps = 14; 2215 let ResourceCycles = [5,5,4]; 2216} 2217def: InstRW<[ICXWriteResGroup225], (instregex "VPCONFLICTDZ128rr", 2218 "VPCONFLICTQZ256rr")>; 2219 2220def ICXWriteResGroup228 : SchedWriteRes<[ICXPort0,ICXPort4,ICXPort5,ICXPort23,ICXPort237,ICXPort06,ICXPort0156]> { 2221 let Latency = 23; 2222 let NumMicroOps = 19; 2223 let ResourceCycles = [2,1,4,1,1,4,6]; 2224} 2225def: InstRW<[ICXWriteResGroup228], (instrs CMPXCHG16B)>; 2226 2227def ICXWriteResGroup233 : SchedWriteRes<[ICXPort0,ICXPort5,ICXPort23]> { 2228 let Latency = 25; 2229 let NumMicroOps = 3; 2230 let ResourceCycles = [1,1,1]; 2231} 2232def: InstRW<[ICXWriteResGroup233], (instregex "DIV_FI(16|32)m")>; 2233 2234def ICXWriteResGroup239 : SchedWriteRes<[ICXPort0,ICXPort23]> { 2235 let Latency = 27; 2236 let NumMicroOps = 2; 2237 let ResourceCycles = [1,1]; 2238} 2239def: InstRW<[ICXWriteResGroup239], (instregex "DIVR_F(32|64)m")>; 2240 2241def ICXWriteResGroup242 : SchedWriteRes<[ICXPort5,ICXPort01,ICXPort23,ICXPort015]> { 2242 let Latency = 29; 2243 let NumMicroOps = 15; 2244 let ResourceCycles = [5,5,1,4]; 2245} 2246def: InstRW<[ICXWriteResGroup242], (instregex "VPCONFLICTQZ256rm(b?)")>; 2247 2248def ICXWriteResGroup243 : SchedWriteRes<[ICXPort0,ICXPort5,ICXPort23]> { 2249 let Latency = 30; 2250 let NumMicroOps = 3; 2251 let ResourceCycles = [1,1,1]; 2252} 2253def: InstRW<[ICXWriteResGroup243], (instregex "DIVR_FI(16|32)m")>; 2254 2255def ICXWriteResGroup247 : SchedWriteRes<[ICXPort5,ICXPort6,ICXPort23,ICXPort06,ICXPort0156]> { 2256 let Latency = 35; 2257 let NumMicroOps = 23; 2258 let ResourceCycles = [1,5,3,4,10]; 2259} 2260def: InstRW<[ICXWriteResGroup247], (instregex "IN(8|16|32)ri", 2261 "IN(8|16|32)rr")>; 2262 2263def ICXWriteResGroup248 : SchedWriteRes<[ICXPort5,ICXPort6,ICXPort23,ICXPort237,ICXPort06,ICXPort0156]> { 2264 let Latency = 35; 2265 let NumMicroOps = 23; 2266 let ResourceCycles = [1,5,2,1,4,10]; 2267} 2268def: InstRW<[ICXWriteResGroup248], (instregex "OUT(8|16|32)ir", 2269 "OUT(8|16|32)rr")>; 2270 2271def ICXWriteResGroup249 : SchedWriteRes<[ICXPort5,ICXPort01,ICXPort015]> { 2272 let Latency = 37; 2273 let NumMicroOps = 21; 2274 let ResourceCycles = [9,7,5]; 2275} 2276def: InstRW<[ICXWriteResGroup249], (instregex "VPCONFLICTDZ256rr", 2277 "VPCONFLICTQZrr")>; 2278 2279def ICXWriteResGroup250 : SchedWriteRes<[ICXPort1,ICXPort6,ICXPort23,ICXPort0156]> { 2280 let Latency = 37; 2281 let NumMicroOps = 31; 2282 let ResourceCycles = [1,8,1,21]; 2283} 2284def: InstRW<[ICXWriteResGroup250], (instregex "XRSTOR(64)?")>; 2285 2286def ICXWriteResGroup252 : SchedWriteRes<[ICXPort1,ICXPort4,ICXPort5,ICXPort6,ICXPort23,ICXPort237,ICXPort15,ICXPort0156]> { 2287 let Latency = 40; 2288 let NumMicroOps = 18; 2289 let ResourceCycles = [1,1,2,3,1,1,1,8]; 2290} 2291def: InstRW<[ICXWriteResGroup252], (instrs VMCLEARm)>; 2292 2293def ICXWriteResGroup253 : SchedWriteRes<[ICXPort4,ICXPort6,ICXPort23,ICXPort237,ICXPort0156]> { 2294 let Latency = 41; 2295 let NumMicroOps = 39; 2296 let ResourceCycles = [1,10,1,1,26]; 2297} 2298def: InstRW<[ICXWriteResGroup253], (instrs XSAVE64)>; 2299 2300def ICXWriteResGroup254 : SchedWriteRes<[ICXPort5,ICXPort0156]> { 2301 let Latency = 42; 2302 let NumMicroOps = 22; 2303 let ResourceCycles = [2,20]; 2304} 2305def: InstRW<[ICXWriteResGroup254], (instrs RDTSCP)>; 2306 2307def ICXWriteResGroup255 : SchedWriteRes<[ICXPort4,ICXPort6,ICXPort23,ICXPort237,ICXPort0156]> { 2308 let Latency = 42; 2309 let NumMicroOps = 40; 2310 let ResourceCycles = [1,11,1,1,26]; 2311} 2312def: InstRW<[ICXWriteResGroup255], (instrs XSAVE)>; 2313def: InstRW<[ICXWriteResGroup255], (instregex "XSAVEC", "XSAVES", "XSAVEOPT")>; 2314 2315def ICXWriteResGroup256 : SchedWriteRes<[ICXPort5,ICXPort01,ICXPort23,ICXPort015]> { 2316 let Latency = 44; 2317 let NumMicroOps = 22; 2318 let ResourceCycles = [9,7,1,5]; 2319} 2320def: InstRW<[ICXWriteResGroup256], (instregex "VPCONFLICTDZ256rm(b?)", 2321 "VPCONFLICTQZrm(b?)")>; 2322 2323def ICXWriteResGroup258 : SchedWriteRes<[ICXPort0,ICXPort23,ICXPort05,ICXPort06,ICXPort0156]> { 2324 let Latency = 62; 2325 let NumMicroOps = 64; 2326 let ResourceCycles = [2,8,5,10,39]; 2327} 2328def: InstRW<[ICXWriteResGroup258], (instrs FLDENVm)>; 2329 2330def ICXWriteResGroup259 : SchedWriteRes<[ICXPort0,ICXPort6,ICXPort23,ICXPort05,ICXPort06,ICXPort15,ICXPort0156]> { 2331 let Latency = 63; 2332 let NumMicroOps = 88; 2333 let ResourceCycles = [4,4,31,1,2,1,45]; 2334} 2335def: InstRW<[ICXWriteResGroup259], (instrs FXRSTOR64)>; 2336 2337def ICXWriteResGroup260 : SchedWriteRes<[ICXPort0,ICXPort6,ICXPort23,ICXPort05,ICXPort06,ICXPort15,ICXPort0156]> { 2338 let Latency = 63; 2339 let NumMicroOps = 90; 2340 let ResourceCycles = [4,2,33,1,2,1,47]; 2341} 2342def: InstRW<[ICXWriteResGroup260], (instrs FXRSTOR)>; 2343 2344def ICXWriteResGroup261 : SchedWriteRes<[ICXPort5,ICXPort01,ICXPort015]> { 2345 let Latency = 67; 2346 let NumMicroOps = 35; 2347 let ResourceCycles = [17,11,7]; 2348} 2349def: InstRW<[ICXWriteResGroup261], (instregex "VPCONFLICTDZrr")>; 2350 2351def ICXWriteResGroup262 : SchedWriteRes<[ICXPort5,ICXPort01,ICXPort23,ICXPort015]> { 2352 let Latency = 74; 2353 let NumMicroOps = 36; 2354 let ResourceCycles = [17,11,1,7]; 2355} 2356def: InstRW<[ICXWriteResGroup262], (instregex "VPCONFLICTDZrm(b?)")>; 2357 2358def ICXWriteResGroup263 : SchedWriteRes<[ICXPort5,ICXPort05,ICXPort0156]> { 2359 let Latency = 75; 2360 let NumMicroOps = 15; 2361 let ResourceCycles = [6,3,6]; 2362} 2363def: InstRW<[ICXWriteResGroup263], (instrs FNINIT)>; 2364 2365def ICXWriteResGroup266 : SchedWriteRes<[ICXPort0,ICXPort1,ICXPort4,ICXPort5,ICXPort6,ICXPort237,ICXPort06,ICXPort0156]> { 2366 let Latency = 106; 2367 let NumMicroOps = 100; 2368 let ResourceCycles = [9,1,11,16,1,11,21,30]; 2369} 2370def: InstRW<[ICXWriteResGroup266], (instrs FSTENVm)>; 2371 2372def ICXWriteResGroup267 : SchedWriteRes<[ICXPort6,ICXPort0156]> { 2373 let Latency = 140; 2374 let NumMicroOps = 4; 2375 let ResourceCycles = [1,3]; 2376} 2377def: InstRW<[ICXWriteResGroup267], (instrs PAUSE)>; 2378 2379def: InstRW<[WriteZero], (instrs CLC)>; 2380 2381 2382// Instruction variants handled by the renamer. These might not need execution 2383// ports in certain conditions. 2384// See Agner's Fog "The microarchitecture of Intel, AMD and VIA CPUs", 2385// section "Skylake Pipeline" > "Register allocation and renaming". 2386// These can be investigated with llvm-exegesis, e.g. 2387// echo 'pxor %mm0, %mm0' | /tmp/llvm-exegesis -mode=uops -snippets-file=- 2388// echo 'vxorpd %xmm0, %xmm0, %xmm1' | /tmp/llvm-exegesis -mode=uops -snippets-file=- 2389 2390def ICXWriteZeroLatency : SchedWriteRes<[]> { 2391 let Latency = 0; 2392} 2393 2394def ICXWriteZeroIdiom : SchedWriteVariant<[ 2395 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [ICXWriteZeroLatency]>, 2396 SchedVar<NoSchedPred, [WriteALU]> 2397]>; 2398def : InstRW<[ICXWriteZeroIdiom], (instrs SUB32rr, SUB64rr, 2399 XOR32rr, XOR64rr)>; 2400 2401def ICXWriteFZeroIdiom : SchedWriteVariant<[ 2402 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [ICXWriteZeroLatency]>, 2403 SchedVar<NoSchedPred, [WriteFLogic]> 2404]>; 2405def : InstRW<[ICXWriteFZeroIdiom], (instrs XORPSrr, VXORPSrr, 2406 XORPDrr, VXORPDrr, 2407 VXORPSZ128rr, 2408 VXORPDZ128rr)>; 2409 2410def ICXWriteFZeroIdiomY : SchedWriteVariant<[ 2411 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [ICXWriteZeroLatency]>, 2412 SchedVar<NoSchedPred, [WriteFLogicY]> 2413]>; 2414def : InstRW<[ICXWriteFZeroIdiomY], (instrs VXORPSYrr, VXORPDYrr, 2415 VXORPSZ256rr, VXORPDZ256rr)>; 2416 2417def ICXWriteFZeroIdiomZ : SchedWriteVariant<[ 2418 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [ICXWriteZeroLatency]>, 2419 SchedVar<NoSchedPred, [WriteFLogicZ]> 2420]>; 2421def : InstRW<[ICXWriteFZeroIdiomZ], (instrs VXORPSZrr, VXORPDZrr)>; 2422 2423def ICXWriteVZeroIdiomLogicX : SchedWriteVariant<[ 2424 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [ICXWriteZeroLatency]>, 2425 SchedVar<NoSchedPred, [WriteVecLogicX]> 2426]>; 2427def : InstRW<[ICXWriteVZeroIdiomLogicX], (instrs PXORrr, VPXORrr, 2428 VPXORDZ128rr, VPXORQZ128rr)>; 2429 2430def ICXWriteVZeroIdiomLogicY : SchedWriteVariant<[ 2431 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [ICXWriteZeroLatency]>, 2432 SchedVar<NoSchedPred, [WriteVecLogicY]> 2433]>; 2434def : InstRW<[ICXWriteVZeroIdiomLogicY], (instrs VPXORYrr, 2435 VPXORDZ256rr, VPXORQZ256rr)>; 2436 2437def ICXWriteVZeroIdiomLogicZ : SchedWriteVariant<[ 2438 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [ICXWriteZeroLatency]>, 2439 SchedVar<NoSchedPred, [WriteVecLogicZ]> 2440]>; 2441def : InstRW<[ICXWriteVZeroIdiomLogicZ], (instrs VPXORDZrr, VPXORQZrr)>; 2442 2443def ICXWriteVZeroIdiomALUX : SchedWriteVariant<[ 2444 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [ICXWriteZeroLatency]>, 2445 SchedVar<NoSchedPred, [WriteVecALUX]> 2446]>; 2447def : InstRW<[ICXWriteVZeroIdiomALUX], (instrs PCMPGTBrr, VPCMPGTBrr, 2448 PCMPGTDrr, VPCMPGTDrr, 2449 PCMPGTWrr, VPCMPGTWrr)>; 2450 2451def ICXWriteVZeroIdiomALUY : SchedWriteVariant<[ 2452 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [ICXWriteZeroLatency]>, 2453 SchedVar<NoSchedPred, [WriteVecALUY]> 2454]>; 2455def : InstRW<[ICXWriteVZeroIdiomALUY], (instrs VPCMPGTBYrr, 2456 VPCMPGTDYrr, 2457 VPCMPGTWYrr)>; 2458 2459def ICXWritePSUB : SchedWriteRes<[ICXPort015]> { 2460 let Latency = 1; 2461 let NumMicroOps = 1; 2462 let ResourceCycles = [1]; 2463} 2464 2465def ICXWriteVZeroIdiomPSUB : SchedWriteVariant<[ 2466 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [ICXWriteZeroLatency]>, 2467 SchedVar<NoSchedPred, [ICXWritePSUB]> 2468]>; 2469 2470def : InstRW<[ICXWriteVZeroIdiomPSUB], (instrs PSUBBrr, VPSUBBrr, VPSUBBZ128rr, 2471 PSUBDrr, VPSUBDrr, VPSUBDZ128rr, 2472 PSUBQrr, VPSUBQrr, VPSUBQZ128rr, 2473 PSUBWrr, VPSUBWrr, VPSUBWZ128rr, 2474 VPSUBBYrr, VPSUBBZ256rr, 2475 VPSUBDYrr, VPSUBDZ256rr, 2476 VPSUBQYrr, VPSUBQZ256rr, 2477 VPSUBWYrr, VPSUBWZ256rr, 2478 VPSUBBZrr, 2479 VPSUBDZrr, 2480 VPSUBQZrr, 2481 VPSUBWZrr)>; 2482def ICXWritePCMPGTQ : SchedWriteRes<[ICXPort5]> { 2483 let Latency = 3; 2484 let NumMicroOps = 1; 2485 let ResourceCycles = [1]; 2486} 2487 2488def ICXWriteVZeroIdiomPCMPGTQ : SchedWriteVariant<[ 2489 SchedVar<MCSchedPredicate<ZeroIdiomPredicate>, [ICXWriteZeroLatency]>, 2490 SchedVar<NoSchedPred, [ICXWritePCMPGTQ]> 2491]>; 2492def : InstRW<[ICXWriteVZeroIdiomPCMPGTQ], (instrs PCMPGTQrr, VPCMPGTQrr, 2493 VPCMPGTQYrr)>; 2494 2495 2496// CMOVs that use both Z and C flag require an extra uop. 2497def ICXWriteCMOVA_CMOVBErr : SchedWriteRes<[ICXPort06]> { 2498 let Latency = 2; 2499 let ResourceCycles = [2]; 2500 let NumMicroOps = 2; 2501} 2502 2503def ICXWriteCMOVA_CMOVBErm : SchedWriteRes<[ICXPort23,ICXPort06]> { 2504 let Latency = 7; 2505 let ResourceCycles = [1,2]; 2506 let NumMicroOps = 3; 2507} 2508 2509def ICXCMOVA_CMOVBErr : SchedWriteVariant<[ 2510 SchedVar<MCSchedPredicate<IsCMOVArr_Or_CMOVBErr>, [ICXWriteCMOVA_CMOVBErr]>, 2511 SchedVar<NoSchedPred, [WriteCMOV]> 2512]>; 2513 2514def ICXCMOVA_CMOVBErm : SchedWriteVariant<[ 2515 SchedVar<MCSchedPredicate<IsCMOVArm_Or_CMOVBErm>, [ICXWriteCMOVA_CMOVBErm]>, 2516 SchedVar<NoSchedPred, [WriteCMOV.Folded]> 2517]>; 2518 2519def : InstRW<[ICXCMOVA_CMOVBErr], (instrs CMOV16rr, CMOV32rr, CMOV64rr)>; 2520def : InstRW<[ICXCMOVA_CMOVBErm], (instrs CMOV16rm, CMOV32rm, CMOV64rm)>; 2521 2522// SETCCs that use both Z and C flag require an extra uop. 2523def ICXWriteSETA_SETBEr : SchedWriteRes<[ICXPort06]> { 2524 let Latency = 2; 2525 let ResourceCycles = [2]; 2526 let NumMicroOps = 2; 2527} 2528 2529def ICXWriteSETA_SETBEm : SchedWriteRes<[ICXPort4,ICXPort237,ICXPort06]> { 2530 let Latency = 3; 2531 let ResourceCycles = [1,1,2]; 2532 let NumMicroOps = 4; 2533} 2534 2535def ICXSETA_SETBErr : SchedWriteVariant<[ 2536 SchedVar<MCSchedPredicate<IsSETAr_Or_SETBEr>, [ICXWriteSETA_SETBEr]>, 2537 SchedVar<NoSchedPred, [WriteSETCC]> 2538]>; 2539 2540def ICXSETA_SETBErm : SchedWriteVariant<[ 2541 SchedVar<MCSchedPredicate<IsSETAm_Or_SETBEm>, [ICXWriteSETA_SETBEm]>, 2542 SchedVar<NoSchedPred, [WriteSETCCStore]> 2543]>; 2544 2545def : InstRW<[ICXSETA_SETBErr], (instrs SETCCr)>; 2546def : InstRW<[ICXSETA_SETBErm], (instrs SETCCm)>; 2547 2548/////////////////////////////////////////////////////////////////////////////// 2549// Dependency breaking instructions. 2550/////////////////////////////////////////////////////////////////////////////// 2551 2552def : IsZeroIdiomFunction<[ 2553 // GPR Zero-idioms. 2554 DepBreakingClass<[ SUB32rr, SUB64rr, XOR32rr, XOR64rr ], ZeroIdiomPredicate>, 2555 2556 // SSE Zero-idioms. 2557 DepBreakingClass<[ 2558 // fp variants. 2559 XORPSrr, XORPDrr, 2560 2561 // int variants. 2562 PXORrr, 2563 PSUBBrr, PSUBWrr, PSUBDrr, PSUBQrr, 2564 PCMPGTBrr, PCMPGTDrr, PCMPGTQrr, PCMPGTWrr 2565 ], ZeroIdiomPredicate>, 2566 2567 // AVX Zero-idioms. 2568 DepBreakingClass<[ 2569 // xmm fp variants. 2570 VXORPSrr, VXORPDrr, 2571 2572 // xmm int variants. 2573 VPXORrr, 2574 VPSUBBrr, VPSUBWrr, VPSUBDrr, VPSUBQrr, 2575 VPCMPGTBrr, VPCMPGTWrr, VPCMPGTDrr, VPCMPGTQrr, 2576 2577 // ymm variants. 2578 VXORPSYrr, VXORPDYrr, VPXORYrr, 2579 VPSUBBYrr, VPSUBWYrr, VPSUBDYrr, VPSUBQYrr, 2580 VPCMPGTBYrr, VPCMPGTWYrr, VPCMPGTDYrr, VPCMPGTQYrr, 2581 2582 // zmm variants. 2583 VXORPSZrr, VXORPDZrr, VPXORDZrr, VPXORQZrr, 2584 VXORPSZ128rr, VXORPDZ128rr, VPXORDZ128rr, VPXORQZ128rr, 2585 VXORPSZ256rr, VXORPDZ256rr, VPXORDZ256rr, VPXORQZ256rr, 2586 VPSUBBZrr, VPSUBWZrr, VPSUBDZrr, VPSUBQZrr, 2587 VPSUBBZ128rr, VPSUBWZ128rr, VPSUBDZ128rr, VPSUBQZ128rr, 2588 VPSUBBZ256rr, VPSUBWZ256rr, VPSUBDZ256rr, VPSUBQZ256rr, 2589 ], ZeroIdiomPredicate>, 2590]>; 2591 2592} // SchedModel 2593